1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * IPQ5332 device tree source 4 * 5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,apss-ipq.h> 9#include <dt-bindings/clock/qcom,ipq5332-gcc.h> 10#include <dt-bindings/interconnect/qcom,ipq5332.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 }; 23 24 xo_board: xo-board-clk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 }; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a53"; 37 reg = <0x0>; 38 enable-method = "psci"; 39 next-level-cache = <&l2_0>; 40 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 41 operating-points-v2 = <&cpu_opp_table>; 42 }; 43 44 cpu1: cpu@1 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x1>; 48 enable-method = "psci"; 49 next-level-cache = <&l2_0>; 50 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 51 operating-points-v2 = <&cpu_opp_table>; 52 }; 53 54 cpu2: cpu@2 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a53"; 57 reg = <0x2>; 58 enable-method = "psci"; 59 next-level-cache = <&l2_0>; 60 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 61 operating-points-v2 = <&cpu_opp_table>; 62 }; 63 64 cpu3: cpu@3 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x3>; 68 enable-method = "psci"; 69 next-level-cache = <&l2_0>; 70 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 71 operating-points-v2 = <&cpu_opp_table>; 72 }; 73 74 l2_0: l2-cache { 75 compatible = "cache"; 76 cache-level = <2>; 77 cache-unified; 78 }; 79 }; 80 81 firmware { 82 scm { 83 compatible = "qcom,scm-ipq5332", "qcom,scm"; 84 qcom,dload-mode = <&tcsr 0x6100>; 85 }; 86 }; 87 88 memory@40000000 { 89 device_type = "memory"; 90 /* We expect the bootloader to fill in the size */ 91 reg = <0x0 0x40000000 0x0 0x0>; 92 }; 93 94 cpu_opp_table: opp-table-cpu { 95 compatible = "operating-points-v2-kryo-cpu"; 96 opp-shared; 97 nvmem-cells = <&cpu_speed_bin>; 98 99 opp-1100000000 { 100 opp-hz = /bits/ 64 <1100000000>; 101 opp-supported-hw = <0x7>; 102 clock-latency-ns = <200000>; 103 }; 104 105 opp-1500000000 { 106 opp-hz = /bits/ 64 <1500000000>; 107 opp-supported-hw = <0x3>; 108 clock-latency-ns = <200000>; 109 }; 110 }; 111 112 pmu { 113 compatible = "arm,cortex-a53-pmu"; 114 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 115 }; 116 117 psci { 118 compatible = "arm,psci-1.0"; 119 method = "smc"; 120 }; 121 122 reserved-memory { 123 #address-cells = <2>; 124 #size-cells = <2>; 125 ranges; 126 127 bootloader@4a100000 { 128 reg = <0x0 0x4a100000 0x0 0x400000>; 129 no-map; 130 }; 131 132 sbl@4a500000 { 133 reg = <0x0 0x4a500000 0x0 0x100000>; 134 no-map; 135 }; 136 137 tz_mem: tz@4a600000 { 138 reg = <0x0 0x4a600000 0x0 0x200000>; 139 no-map; 140 }; 141 142 smem@4a800000 { 143 compatible = "qcom,smem"; 144 reg = <0x0 0x4a800000 0x0 0x100000>; 145 no-map; 146 147 hwlocks = <&tcsr_mutex 3>; 148 }; 149 }; 150 151 soc@0 { 152 compatible = "simple-bus"; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 ranges = <0 0 0 0xffffffff>; 156 157 usbphy0: phy@7b000 { 158 compatible = "qcom,ipq5332-usb-hsphy"; 159 reg = <0x0007b000 0x12c>; 160 161 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; 162 163 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 164 165 #phy-cells = <0>; 166 167 status = "disabled"; 168 }; 169 170 qfprom: efuse@a4000 { 171 compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; 172 reg = <0x000a4000 0x721>; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 176 cpu_speed_bin: cpu-speed-bin@1d { 177 reg = <0x1d 0x2>; 178 bits = <7 2>; 179 }; 180 181 tsens_sens11_off: s11@3a5 { 182 reg = <0x3a5 0x1>; 183 bits = <4 4>; 184 }; 185 186 tsens_sens12_off: s12@3a6 { 187 reg = <0x3a6 0x1>; 188 bits = <0 4>; 189 }; 190 191 tsens_sens13_off: s13@3a6 { 192 reg = <0x3a6 0x1>; 193 bits = <4 4>; 194 }; 195 196 tsens_sens14_off: s14@3ad { 197 reg = <0x3ad 0x2>; 198 bits = <7 4>; 199 }; 200 201 tsens_sens15_off: s15@3ae { 202 reg = <0x3ae 0x1>; 203 bits = <3 4>; 204 }; 205 206 tsens_mode: mode@3e1 { 207 reg = <0x3e1 0x1>; 208 bits = <0 3>; 209 }; 210 211 tsens_base0: base0@3e1 { 212 reg = <0x3e1 0x2>; 213 bits = <3 10>; 214 }; 215 216 tsens_base1: base1@3e2 { 217 reg = <0x3e2 0x2>; 218 bits = <5 10>; 219 }; 220 }; 221 222 rng: rng@e3000 { 223 compatible = "qcom,ipq5332-trng", "qcom,trng"; 224 reg = <0x000e3000 0x1000>; 225 clocks = <&gcc GCC_PRNG_AHB_CLK>; 226 clock-names = "core"; 227 }; 228 229 tsens: thermal-sensor@4a9000 { 230 compatible = "qcom,ipq5332-tsens"; 231 reg = <0x004a9000 0x1000>, 232 <0x004a8000 0x1000>; 233 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; 234 interrupt-names = "combined"; 235 nvmem-cells = <&tsens_mode>, 236 <&tsens_base0>, 237 <&tsens_base1>, 238 <&tsens_sens11_off>, 239 <&tsens_sens12_off>, 240 <&tsens_sens13_off>, 241 <&tsens_sens14_off>, 242 <&tsens_sens15_off>; 243 nvmem-cell-names = "mode", 244 "base0", 245 "base1", 246 "tsens_sens11_off", 247 "tsens_sens12_off", 248 "tsens_sens13_off", 249 "tsens_sens14_off", 250 "tsens_sens15_off"; 251 #qcom,sensors = <5>; 252 #thermal-sensor-cells = <1>; 253 }; 254 255 pcie0_phy: phy@4b0000 { 256 compatible = "qcom,ipq5332-uniphy-pcie-phy"; 257 reg = <0x004b0000 0x800>; 258 259 clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>, 260 <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; 261 262 resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>, 263 <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>, 264 <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>; 265 266 #clock-cells = <0>; 267 268 #phy-cells = <0>; 269 270 num-lanes = <1>; 271 272 status = "disabled"; 273 }; 274 275 pcie1_phy: phy@4b1000 { 276 compatible = "qcom,ipq5332-uniphy-pcie-phy"; 277 reg = <0x004b1000 0x1000>; 278 279 clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>, 280 <&gcc GCC_PCIE3X2_PHY_AHB_CLK>; 281 282 resets = <&gcc GCC_PCIE3X2_PHY_BCR>, 283 <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>, 284 <&gcc GCC_PCIE3X2PHY_PHY_BCR>; 285 286 #clock-cells = <0>; 287 288 #phy-cells = <0>; 289 290 num-lanes = <2>; 291 292 status = "disabled"; 293 }; 294 295 tlmm: pinctrl@1000000 { 296 compatible = "qcom,ipq5332-tlmm"; 297 reg = <0x01000000 0x300000>; 298 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 299 gpio-controller; 300 #gpio-cells = <2>; 301 gpio-ranges = <&tlmm 0 0 53>; 302 interrupt-controller; 303 #interrupt-cells = <2>; 304 305 serial_0_pins: serial0-state { 306 pins = "gpio18", "gpio19"; 307 function = "blsp0_uart0"; 308 drive-strength = <8>; 309 bias-pull-up; 310 }; 311 }; 312 313 gcc: clock-controller@1800000 { 314 compatible = "qcom,ipq5332-gcc"; 315 reg = <0x01800000 0x80000>; 316 #clock-cells = <1>; 317 #reset-cells = <1>; 318 #interconnect-cells = <1>; 319 clocks = <&xo_board>, 320 <&sleep_clk>, 321 <&pcie1_phy>, 322 <&pcie0_phy>, 323 <0>; 324 }; 325 326 tcsr_mutex: hwlock@1905000 { 327 compatible = "qcom,tcsr-mutex"; 328 reg = <0x01905000 0x20000>; 329 #hwlock-cells = <1>; 330 }; 331 332 tcsr: syscon@1937000 { 333 compatible = "qcom,tcsr-ipq5332", "syscon"; 334 reg = <0x01937000 0x21000>; 335 }; 336 337 sdhc: mmc@7804000 { 338 compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; 339 reg = <0x07804000 0x1000>, <0x07805000 0x1000>; 340 341 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 343 interrupt-names = "hc_irq", "pwr_irq"; 344 345 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 346 <&gcc GCC_SDCC1_APPS_CLK>, 347 <&xo_board>; 348 clock-names = "iface", "core", "xo"; 349 status = "disabled"; 350 }; 351 352 blsp_dma: dma-controller@7884000 { 353 compatible = "qcom,bam-v1.7.0"; 354 reg = <0x07884000 0x1d000>; 355 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 357 clock-names = "bam_clk"; 358 #dma-cells = <1>; 359 qcom,ee = <0>; 360 }; 361 362 blsp1_uart0: serial@78af000 { 363 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 364 reg = <0x078af000 0x200>; 365 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 367 <&gcc GCC_BLSP1_AHB_CLK>; 368 clock-names = "core", "iface"; 369 status = "disabled"; 370 }; 371 372 blsp1_uart1: serial@78b0000 { 373 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 374 reg = <0x078b0000 0x200>; 375 interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 377 <&gcc GCC_BLSP1_AHB_CLK>; 378 clock-names = "core", "iface"; 379 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 380 dma-names = "tx", "rx"; 381 status = "disabled"; 382 }; 383 384 blsp1_spi0: spi@78b5000 { 385 compatible = "qcom,spi-qup-v2.2.1"; 386 reg = <0x078b5000 0x600>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 391 <&gcc GCC_BLSP1_AHB_CLK>; 392 clock-names = "core", "iface"; 393 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 394 dma-names = "tx", "rx"; 395 status = "disabled"; 396 }; 397 398 blsp1_i2c1: i2c@78b6000 { 399 compatible = "qcom,i2c-qup-v2.2.1"; 400 reg = <0x078b6000 0x600>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 405 <&gcc GCC_BLSP1_AHB_CLK>; 406 clock-names = "core", "iface"; 407 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 408 dma-names = "tx", "rx"; 409 status = "disabled"; 410 }; 411 412 blsp1_spi2: spi@78b7000 { 413 compatible = "qcom,spi-qup-v2.2.1"; 414 reg = <0x078b7000 0x600>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 419 <&gcc GCC_BLSP1_AHB_CLK>; 420 clock-names = "core", "iface"; 421 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 422 dma-names = "tx", "rx"; 423 status = "disabled"; 424 }; 425 426 qpic_bam: dma-controller@7984000 { 427 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 428 reg = <0x07984000 0x1c000>; 429 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&gcc GCC_QPIC_AHB_CLK>; 431 clock-names = "bam_clk"; 432 #dma-cells = <1>; 433 qcom,ee = <0>; 434 status = "disabled"; 435 }; 436 437 qpic_nand: spi@79b0000 { 438 compatible = "qcom,ipq5332-snand", "qcom,ipq9574-snand"; 439 reg = <0x079b0000 0x10000>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 clocks = <&gcc GCC_QPIC_CLK>, 443 <&gcc GCC_QPIC_AHB_CLK>, 444 <&gcc GCC_QPIC_IO_MACRO_CLK>; 445 clock-names = "core", 446 "aon", 447 "iom"; 448 449 dmas = <&qpic_bam 0>, 450 <&qpic_bam 1>, 451 <&qpic_bam 2>; 452 dma-names = "tx", 453 "rx", 454 "cmd"; 455 456 status = "disabled"; 457 }; 458 459 usb: usb@8af8800 { 460 compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; 461 reg = <0x08af8800 0x400>; 462 463 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 466 interrupt-names = "pwr_event", 467 "dp_hs_phy_irq", 468 "dm_hs_phy_irq"; 469 470 clocks = <&gcc GCC_USB0_MASTER_CLK>, 471 <&gcc GCC_USB0_SLEEP_CLK>, 472 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 473 clock-names = "core", 474 "sleep", 475 "mock_utmi"; 476 477 resets = <&gcc GCC_USB_BCR>; 478 479 qcom,select-utmi-as-pipe-clk; 480 481 #address-cells = <1>; 482 #size-cells = <1>; 483 ranges; 484 interconnects = <&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>, 485 <&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>; 486 interconnect-names = "usb-ddr", "apps-usb"; 487 488 status = "disabled"; 489 490 usb_dwc: usb@8a00000 { 491 compatible = "snps,dwc3"; 492 reg = <0x08a00000 0xe000>; 493 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 494 clock-names = "ref"; 495 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 496 phy-names = "usb2-phy"; 497 phys = <&usbphy0>; 498 tx-fifo-resize; 499 snps,is-utmi-l1-suspend; 500 snps,hird-threshold = /bits/ 8 <0x0>; 501 snps,dis_u2_susphy_quirk; 502 snps,dis_u3_susphy_quirk; 503 }; 504 }; 505 506 intc: interrupt-controller@b000000 { 507 compatible = "qcom,msm-qgic2"; 508 reg = <0x0b000000 0x1000>, /* GICD */ 509 <0x0b002000 0x1000>, /* GICC */ 510 <0x0b001000 0x1000>, /* GICH */ 511 <0x0b004000 0x1000>; /* GICV */ 512 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 513 interrupt-controller; 514 #interrupt-cells = <3>; 515 #address-cells = <1>; 516 #size-cells = <1>; 517 ranges = <0 0x0b00c000 0x3000>; 518 519 v2m0: v2m@0 { 520 compatible = "arm,gic-v2m-frame"; 521 reg = <0x00000000 0xffd>; 522 msi-controller; 523 }; 524 525 v2m1: v2m@1000 { 526 compatible = "arm,gic-v2m-frame"; 527 reg = <0x00001000 0xffd>; 528 msi-controller; 529 }; 530 531 v2m2: v2m@2000 { 532 compatible = "arm,gic-v2m-frame"; 533 reg = <0x00002000 0xffd>; 534 msi-controller; 535 }; 536 }; 537 538 watchdog: watchdog@b017000 { 539 compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt"; 540 reg = <0x0b017000 0x1000>; 541 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 542 clocks = <&sleep_clk>; 543 timeout-sec = <30>; 544 }; 545 546 apcs_glb: mailbox@b111000 { 547 compatible = "qcom,ipq5332-apcs-apps-global", 548 "qcom,ipq6018-apcs-apps-global"; 549 reg = <0x0b111000 0x1000>; 550 #clock-cells = <1>; 551 clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>; 552 clock-names = "pll", "xo", "gpll0"; 553 #mbox-cells = <1>; 554 }; 555 556 a53pll: clock@b116000 { 557 compatible = "qcom,ipq5332-a53pll"; 558 reg = <0x0b116000 0x40>; 559 #clock-cells = <0>; 560 clocks = <&xo_board>; 561 clock-names = "xo"; 562 }; 563 564 timer@b120000 { 565 compatible = "arm,armv7-timer-mem"; 566 reg = <0x0b120000 0x1000>; 567 #address-cells = <1>; 568 #size-cells = <1>; 569 ranges; 570 571 frame@b120000 { 572 reg = <0x0b121000 0x1000>, 573 <0x0b122000 0x1000>; 574 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 576 frame-number = <0>; 577 }; 578 579 frame@b123000 { 580 reg = <0x0b123000 0x1000>; 581 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 582 frame-number = <1>; 583 status = "disabled"; 584 }; 585 586 frame@b124000 { 587 reg = <0x0b124000 0x1000>; 588 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 589 frame-number = <2>; 590 status = "disabled"; 591 }; 592 593 frame@b125000 { 594 reg = <0x0b125000 0x1000>; 595 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 596 frame-number = <3>; 597 status = "disabled"; 598 }; 599 600 frame@b126000 { 601 reg = <0x0b126000 0x1000>; 602 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 603 frame-number = <4>; 604 status = "disabled"; 605 }; 606 607 frame@b127000 { 608 reg = <0x0b127000 0x1000>; 609 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 610 frame-number = <5>; 611 status = "disabled"; 612 }; 613 614 frame@b128000 { 615 reg = <0x0b128000 0x1000>; 616 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 617 frame-number = <6>; 618 status = "disabled"; 619 }; 620 }; 621 622 pcie1: pcie@18000000 { 623 compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574"; 624 reg = <0x18000000 0xf1c>, 625 <0x18000f20 0xa8>, 626 <0x18001000 0x1000>, 627 <0x00088000 0x3000>, 628 <0x18100000 0x1000>, 629 <0x0008b000 0x1000>; 630 reg-names = "dbi", 631 "elbi", 632 "atu", 633 "parf", 634 "config", 635 "mhi"; 636 device_type = "pci"; 637 linux,pci-domain = <1>; 638 num-lanes = <2>; 639 #address-cells = <3>; 640 #size-cells = <2>; 641 642 ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x00100000>, 643 <0x02000000 0x0 0x18300000 0x18300000 0x0 0x07d00000>; 644 645 msi-map = <0x0 &v2m0 0x0 0xffd>; 646 647 interrupts = <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>; 656 interrupt-names = "msi0", 657 "msi1", 658 "msi2", 659 "msi3", 660 "msi4", 661 "msi5", 662 "msi6", 663 "msi7", 664 "global"; 665 666 #interrupt-cells = <1>; 667 interrupt-map-mask = <0 0 0 0x7>; 668 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 669 <0 0 0 2 &intc 0 GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 670 <0 0 0 3 &intc 0 GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 671 <0 0 0 4 &intc 0 GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>; 672 673 clocks = <&gcc GCC_PCIE3X2_AXI_M_CLK>, 674 <&gcc GCC_PCIE3X2_AXI_S_CLK>, 675 <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>, 676 <&gcc GCC_PCIE3X2_RCHG_CLK>, 677 <&gcc GCC_PCIE3X2_AHB_CLK>, 678 <&gcc GCC_PCIE3X2_AUX_CLK>; 679 clock-names = "axi_m", 680 "axi_s", 681 "axi_bridge", 682 "rchng", 683 "ahb", 684 "aux"; 685 686 assigned-clocks = <&gcc GCC_PCIE3X2_AUX_CLK>; 687 688 assigned-clock-rates = <2000000>; 689 690 resets = <&gcc GCC_PCIE3X2_PIPE_ARES>, 691 <&gcc GCC_PCIE3X2_CORE_STICKY_ARES>, 692 <&gcc GCC_PCIE3X2_AXI_S_STICKY_ARES>, 693 <&gcc GCC_PCIE3X2_AXI_S_CLK_ARES>, 694 <&gcc GCC_PCIE3X2_AXI_M_STICKY_ARES>, 695 <&gcc GCC_PCIE3X2_AXI_M_CLK_ARES>, 696 <&gcc GCC_PCIE3X2_AUX_CLK_ARES>, 697 <&gcc GCC_PCIE3X2_AHB_CLK_ARES>; 698 reset-names = "pipe", 699 "sticky", 700 "axi_s_sticky", 701 "axi_s", 702 "axi_m_sticky", 703 "axi_m", 704 "aux", 705 "ahb"; 706 707 phys = <&pcie1_phy>; 708 phy-names = "pciephy"; 709 710 interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>, 711 <&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>; 712 interconnect-names = "pcie-mem", "cpu-pcie"; 713 714 status = "disabled"; 715 716 pcie@0 { 717 device_type = "pci"; 718 reg = <0x0 0x0 0x0 0x0 0x0>; 719 720 #address-cells = <3>; 721 #size-cells = <2>; 722 ranges; 723 }; 724 }; 725 726 pcie0: pcie@20000000 { 727 compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574"; 728 reg = <0x20000000 0xf1c>, 729 <0x20000f20 0xa8>, 730 <0x20001000 0x1000>, 731 <0x00080000 0x3000>, 732 <0x20100000 0x1000>, 733 <0x00083000 0x1000>; 734 reg-names = "dbi", 735 "elbi", 736 "atu", 737 "parf", 738 "config", 739 "mhi"; 740 device_type = "pci"; 741 linux,pci-domain = <0>; 742 num-lanes = <1>; 743 #address-cells = <3>; 744 #size-cells = <2>; 745 746 ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x00100000>, 747 <0x02000000 0x0 0x20300000 0x20300000 0x0 0x0fd00000>; 748 749 msi-map = <0x0 &v2m0 0x0 0xffd>; 750 751 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 760 interrupt-names = "msi0", 761 "msi1", 762 "msi2", 763 "msi3", 764 "msi4", 765 "msi5", 766 "msi6", 767 "msi7", 768 "global"; 769 770 #interrupt-cells = <1>; 771 interrupt-map-mask = <0 0 0 0x7>; 772 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 773 <0 0 0 2 &intc 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 774 <0 0 0 3 &intc 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 775 <0 0 0 4 &intc 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 776 777 clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>, 778 <&gcc GCC_PCIE3X1_0_AXI_S_CLK>, 779 <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>, 780 <&gcc GCC_PCIE3X1_0_RCHG_CLK>, 781 <&gcc GCC_PCIE3X1_0_AHB_CLK>, 782 <&gcc GCC_PCIE3X1_0_AUX_CLK>; 783 clock-names = "axi_m", 784 "axi_s", 785 "axi_bridge", 786 "rchng", 787 "ahb", 788 "aux"; 789 790 assigned-clocks = <&gcc GCC_PCIE3X1_0_AUX_CLK>; 791 792 assigned-clock-rates = <2000000>; 793 794 resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>, 795 <&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>, 796 <&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>, 797 <&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>, 798 <&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>, 799 <&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>, 800 <&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>, 801 <&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>; 802 reset-names = "pipe", 803 "sticky", 804 "axi_s_sticky", 805 "axi_s", 806 "axi_m_sticky", 807 "axi_m", 808 "aux", 809 "ahb"; 810 811 phys = <&pcie0_phy>; 812 phy-names = "pciephy"; 813 814 interconnects = <&gcc MASTER_SNOC_PCIE3_1_M &gcc SLAVE_SNOC_PCIE3_1_M>, 815 <&gcc MASTER_ANOC_PCIE3_1_S &gcc SLAVE_ANOC_PCIE3_1_S>; 816 interconnect-names = "pcie-mem", "cpu-pcie"; 817 818 status = "disabled"; 819 820 pcie@0 { 821 device_type = "pci"; 822 reg = <0x0 0x0 0x0 0x0 0x0>; 823 824 #address-cells = <3>; 825 #size-cells = <2>; 826 ranges; 827 }; 828 }; 829 }; 830 831 thermal-zones { 832 rfa-0-thermal { 833 thermal-sensors = <&tsens 11>; 834 835 trips { 836 rfa-0-critical { 837 temperature = <125000>; 838 hysteresis = <1000>; 839 type = "critical"; 840 }; 841 }; 842 }; 843 844 rfa-1-thermal { 845 thermal-sensors = <&tsens 12>; 846 847 trips { 848 rfa-1-critical { 849 temperature = <125000>; 850 hysteresis = <1000>; 851 type = "critical"; 852 }; 853 }; 854 }; 855 856 misc-thermal { 857 thermal-sensors = <&tsens 13>; 858 859 trips { 860 misc-critical { 861 temperature = <125000>; 862 hysteresis = <1000>; 863 type = "critical"; 864 }; 865 }; 866 }; 867 868 cpu-top-thermal { 869 polling-delay-passive = <100>; 870 thermal-sensors = <&tsens 14>; 871 872 trips { 873 cpu-top-critical { 874 temperature = <115000>; 875 hysteresis = <1000>; 876 type = "critical"; 877 }; 878 879 cpu-passive { 880 temperature = <105000>; 881 hysteresis = <1000>; 882 type = "passive"; 883 }; 884 }; 885 }; 886 887 top-glue-thermal { 888 thermal-sensors = <&tsens 15>; 889 890 trips { 891 top-glue-critical { 892 temperature = <125000>; 893 hysteresis = <1000>; 894 type = "critical"; 895 }; 896 }; 897 }; 898 }; 899 900 timer { 901 compatible = "arm,armv8-timer"; 902 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 903 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 904 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 905 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 906 }; 907}; 908