1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * IPQ5332 device tree source 4 * 5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,apss-ipq.h> 9#include <dt-bindings/clock/qcom,ipq5332-gcc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 clocks { 18 sleep_clk: sleep-clk { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 }; 22 23 xo_board: xo-board-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 CPU0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0x0>; 37 enable-method = "psci"; 38 next-level-cache = <&L2_0>; 39 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 40 operating-points-v2 = <&cpu_opp_table>; 41 }; 42 43 CPU1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 reg = <0x1>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 50 operating-points-v2 = <&cpu_opp_table>; 51 }; 52 53 CPU2: cpu@2 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x2>; 57 enable-method = "psci"; 58 next-level-cache = <&L2_0>; 59 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 60 operating-points-v2 = <&cpu_opp_table>; 61 }; 62 63 CPU3: cpu@3 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53"; 66 reg = <0x3>; 67 enable-method = "psci"; 68 next-level-cache = <&L2_0>; 69 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 70 operating-points-v2 = <&cpu_opp_table>; 71 }; 72 73 L2_0: l2-cache { 74 compatible = "cache"; 75 cache-level = <2>; 76 cache-unified; 77 }; 78 }; 79 80 firmware { 81 scm { 82 compatible = "qcom,scm-ipq5332", "qcom,scm"; 83 qcom,dload-mode = <&tcsr 0x6100>; 84 }; 85 }; 86 87 memory@40000000 { 88 device_type = "memory"; 89 /* We expect the bootloader to fill in the size */ 90 reg = <0x0 0x40000000 0x0 0x0>; 91 }; 92 93 cpu_opp_table: opp-table-cpu { 94 compatible = "operating-points-v2-kryo-cpu"; 95 opp-shared; 96 nvmem-cells = <&cpu_speed_bin>; 97 98 opp-1100000000 { 99 opp-hz = /bits/ 64 <1100000000>; 100 opp-supported-hw = <0x7>; 101 clock-latency-ns = <200000>; 102 }; 103 104 opp-1500000000 { 105 opp-hz = /bits/ 64 <1500000000>; 106 opp-supported-hw = <0x3>; 107 clock-latency-ns = <200000>; 108 }; 109 }; 110 111 pmu { 112 compatible = "arm,cortex-a53-pmu"; 113 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 114 }; 115 116 psci { 117 compatible = "arm,psci-1.0"; 118 method = "smc"; 119 }; 120 121 reserved-memory { 122 #address-cells = <2>; 123 #size-cells = <2>; 124 ranges; 125 126 bootloader@4a100000 { 127 reg = <0x0 0x4a100000 0x0 0x400000>; 128 no-map; 129 }; 130 131 sbl@4a500000 { 132 reg = <0x0 0x4a500000 0x0 0x100000>; 133 no-map; 134 }; 135 136 tz_mem: tz@4a600000 { 137 reg = <0x0 0x4a600000 0x0 0x200000>; 138 no-map; 139 }; 140 141 smem@4a800000 { 142 compatible = "qcom,smem"; 143 reg = <0x0 0x4a800000 0x0 0x100000>; 144 no-map; 145 146 hwlocks = <&tcsr_mutex 3>; 147 }; 148 }; 149 150 soc@0 { 151 compatible = "simple-bus"; 152 #address-cells = <1>; 153 #size-cells = <1>; 154 ranges = <0 0 0 0xffffffff>; 155 156 usbphy0: phy@7b000 { 157 compatible = "qcom,ipq5332-usb-hsphy"; 158 reg = <0x0007b000 0x12c>; 159 160 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; 161 162 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 163 164 #phy-cells = <0>; 165 166 status = "disabled"; 167 }; 168 169 qfprom: efuse@a4000 { 170 compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; 171 reg = <0x000a4000 0x721>; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 175 cpu_speed_bin: cpu-speed-bin@1d { 176 reg = <0x1d 0x2>; 177 bits = <7 2>; 178 }; 179 }; 180 181 rng: rng@e3000 { 182 compatible = "qcom,prng-ee"; 183 reg = <0x000e3000 0x1000>; 184 clocks = <&gcc GCC_PRNG_AHB_CLK>; 185 clock-names = "core"; 186 }; 187 188 tlmm: pinctrl@1000000 { 189 compatible = "qcom,ipq5332-tlmm"; 190 reg = <0x01000000 0x300000>; 191 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 192 gpio-controller; 193 #gpio-cells = <2>; 194 gpio-ranges = <&tlmm 0 0 53>; 195 interrupt-controller; 196 #interrupt-cells = <2>; 197 198 serial_0_pins: serial0-state { 199 pins = "gpio18", "gpio19"; 200 function = "blsp0_uart0"; 201 drive-strength = <8>; 202 bias-pull-up; 203 }; 204 }; 205 206 gcc: clock-controller@1800000 { 207 compatible = "qcom,ipq5332-gcc"; 208 reg = <0x01800000 0x80000>; 209 #clock-cells = <1>; 210 #reset-cells = <1>; 211 #power-domain-cells = <1>; 212 clocks = <&xo_board>, 213 <&sleep_clk>, 214 <0>, 215 <0>, 216 <0>; 217 }; 218 219 tcsr_mutex: hwlock@1905000 { 220 compatible = "qcom,tcsr-mutex"; 221 reg = <0x01905000 0x20000>; 222 #hwlock-cells = <1>; 223 }; 224 225 tcsr: syscon@1937000 { 226 compatible = "qcom,tcsr-ipq5332", "syscon"; 227 reg = <0x01937000 0x21000>; 228 }; 229 230 sdhc: mmc@7804000 { 231 compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; 232 reg = <0x07804000 0x1000>, <0x07805000 0x1000>; 233 234 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 236 interrupt-names = "hc_irq", "pwr_irq"; 237 238 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 239 <&gcc GCC_SDCC1_APPS_CLK>, 240 <&xo_board>; 241 clock-names = "iface", "core", "xo"; 242 status = "disabled"; 243 }; 244 245 blsp_dma: dma-controller@7884000 { 246 compatible = "qcom,bam-v1.7.0"; 247 reg = <0x07884000 0x1d000>; 248 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 250 clock-names = "bam_clk"; 251 #dma-cells = <1>; 252 qcom,ee = <0>; 253 }; 254 255 blsp1_uart0: serial@78af000 { 256 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 257 reg = <0x078af000 0x200>; 258 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 260 <&gcc GCC_BLSP1_AHB_CLK>; 261 clock-names = "core", "iface"; 262 status = "disabled"; 263 }; 264 265 blsp1_uart1: serial@78b0000 { 266 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 267 reg = <0x078b0000 0x200>; 268 interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 270 <&gcc GCC_BLSP1_AHB_CLK>; 271 clock-names = "core", "iface"; 272 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 273 dma-names = "tx", "rx"; 274 status = "disabled"; 275 }; 276 277 blsp1_spi0: spi@78b5000 { 278 compatible = "qcom,spi-qup-v2.2.1"; 279 reg = <0x078b5000 0x600>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 284 <&gcc GCC_BLSP1_AHB_CLK>; 285 clock-names = "core", "iface"; 286 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 287 dma-names = "tx", "rx"; 288 status = "disabled"; 289 }; 290 291 blsp1_i2c1: i2c@78b6000 { 292 compatible = "qcom,i2c-qup-v2.2.1"; 293 reg = <0x078b6000 0x600>; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 298 <&gcc GCC_BLSP1_AHB_CLK>; 299 clock-names = "core", "iface"; 300 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 301 dma-names = "tx", "rx"; 302 status = "disabled"; 303 }; 304 305 blsp1_spi2: spi@78b7000 { 306 compatible = "qcom,spi-qup-v2.2.1"; 307 reg = <0x078b7000 0x600>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 312 <&gcc GCC_BLSP1_AHB_CLK>; 313 clock-names = "core", "iface"; 314 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 315 dma-names = "tx", "rx"; 316 status = "disabled"; 317 }; 318 319 usb: usb@8af8800 { 320 compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; 321 reg = <0x08af8800 0x400>; 322 323 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 53 IRQ_TYPE_EDGE_BOTH>, 325 <GIC_SPI 52 IRQ_TYPE_EDGE_BOTH>; 326 interrupt-names = "pwr_event", 327 "dp_hs_phy_irq", 328 "dm_hs_phy_irq"; 329 330 clocks = <&gcc GCC_USB0_MASTER_CLK>, 331 <&gcc GCC_SNOC_USB_CLK>, 332 <&gcc GCC_USB0_SLEEP_CLK>, 333 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 334 clock-names = "core", 335 "iface", 336 "sleep", 337 "mock_utmi"; 338 339 resets = <&gcc GCC_USB_BCR>; 340 341 qcom,select-utmi-as-pipe-clk; 342 343 #address-cells = <1>; 344 #size-cells = <1>; 345 ranges; 346 347 status = "disabled"; 348 349 usb_dwc: usb@8a00000 { 350 compatible = "snps,dwc3"; 351 reg = <0x08a00000 0xe000>; 352 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 353 clock-names = "ref"; 354 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 355 phy-names = "usb2-phy"; 356 phys = <&usbphy0>; 357 tx-fifo-resize; 358 snps,is-utmi-l1-suspend; 359 snps,hird-threshold = /bits/ 8 <0x0>; 360 snps,dis_u2_susphy_quirk; 361 snps,dis_u3_susphy_quirk; 362 }; 363 }; 364 365 intc: interrupt-controller@b000000 { 366 compatible = "qcom,msm-qgic2"; 367 reg = <0x0b000000 0x1000>, /* GICD */ 368 <0x0b002000 0x1000>, /* GICC */ 369 <0x0b001000 0x1000>, /* GICH */ 370 <0x0b004000 0x1000>; /* GICV */ 371 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 372 interrupt-controller; 373 #interrupt-cells = <3>; 374 #address-cells = <1>; 375 #size-cells = <1>; 376 ranges = <0 0x0b00c000 0x3000>; 377 378 v2m0: v2m@0 { 379 compatible = "arm,gic-v2m-frame"; 380 reg = <0x00000000 0xffd>; 381 msi-controller; 382 }; 383 384 v2m1: v2m@1000 { 385 compatible = "arm,gic-v2m-frame"; 386 reg = <0x00001000 0xffd>; 387 msi-controller; 388 }; 389 390 v2m2: v2m@2000 { 391 compatible = "arm,gic-v2m-frame"; 392 reg = <0x00002000 0xffd>; 393 msi-controller; 394 }; 395 }; 396 397 watchdog: watchdog@b017000 { 398 compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt"; 399 reg = <0x0b017000 0x1000>; 400 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 401 clocks = <&sleep_clk>; 402 timeout-sec = <30>; 403 }; 404 405 apcs_glb: mailbox@b111000 { 406 compatible = "qcom,ipq5332-apcs-apps-global", 407 "qcom,ipq6018-apcs-apps-global"; 408 reg = <0x0b111000 0x1000>; 409 #clock-cells = <1>; 410 clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>; 411 clock-names = "pll", "xo", "gpll0"; 412 #mbox-cells = <1>; 413 }; 414 415 a53pll: clock@b116000 { 416 compatible = "qcom,ipq5332-a53pll"; 417 reg = <0x0b116000 0x40>; 418 #clock-cells = <0>; 419 clocks = <&xo_board>; 420 clock-names = "xo"; 421 }; 422 423 timer@b120000 { 424 compatible = "arm,armv7-timer-mem"; 425 reg = <0x0b120000 0x1000>; 426 #address-cells = <1>; 427 #size-cells = <1>; 428 ranges; 429 430 frame@b120000 { 431 reg = <0x0b121000 0x1000>, 432 <0x0b122000 0x1000>; 433 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 435 frame-number = <0>; 436 }; 437 438 frame@b123000 { 439 reg = <0x0b123000 0x1000>; 440 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 441 frame-number = <1>; 442 status = "disabled"; 443 }; 444 445 frame@b124000 { 446 reg = <0x0b124000 0x1000>; 447 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 448 frame-number = <2>; 449 status = "disabled"; 450 }; 451 452 frame@b125000 { 453 reg = <0x0b125000 0x1000>; 454 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 455 frame-number = <3>; 456 status = "disabled"; 457 }; 458 459 frame@b126000 { 460 reg = <0x0b126000 0x1000>; 461 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 462 frame-number = <4>; 463 status = "disabled"; 464 }; 465 466 frame@b127000 { 467 reg = <0x0b127000 0x1000>; 468 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 469 frame-number = <5>; 470 status = "disabled"; 471 }; 472 473 frame@b128000 { 474 reg = <0x0b128000 0x1000>; 475 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 476 frame-number = <6>; 477 status = "disabled"; 478 }; 479 }; 480 }; 481 482 timer { 483 compatible = "arm,armv8-timer"; 484 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 485 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 486 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 487 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 488 }; 489}; 490