xref: /linux/arch/arm64/boot/dts/qcom/hamoa.dtsi (revision e62decaf98e7c1385c4a22c61ba8bf94d24713a5)

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
#include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
#include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			clock-frequency = <76800000>;
			#clock-cells = <0>;
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			clock-frequency = <32764>;
			#clock-cells = <0>;
		};

		bi_tcxo_div2: bi-tcxo-div2-clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-mult = <1>;
			clock-div = <2>;
		};

		bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;

			clocks = <&rpmhcc RPMH_CXO_CLK_A>;
			clock-mult = <1>;
			clock-div = <2>;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,oryon";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
			power-domain-names = "psci", "perf";
			#cooling-cells = <2>;

			l2_0: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
			};
		};

		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,oryon";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
			power-domain-names = "psci", "perf";
			#cooling-cells = <2>;
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,oryon";
			reg = <0x0 0x200>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			power-domains = <&cpu_pd2>, <&scmi_dvfs 0>;
			power-domain-names = "psci", "perf";
			#cooling-cells = <2>;
		};

		cpu3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,oryon";
			reg = <0x0 0x300>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			power-domains = <&cpu_pd3>, <&scmi_dvfs 0>;
			power-domain-names = "psci", "perf";
			#cooling-cells = <2>;
		};

		cpu4: cpu@10000 {
			device_type = "cpu";
			compatible = "qcom,oryon";
			reg = <0x0 0x10000>;
			enable-method = "psci";
			next-level-cache = <&l2_1>;
			power-domains = <&cpu_pd4>, <&scmi_dvfs 1>;
			power-domain-names = "psci", "perf";
			#cooling-cells = <2>;

			l2_1: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
			};
		};

		cpu5: cpu@10100 {
			device_type = "cpu";
			compatible = "qcom,oryon";
			reg = <0x0 0x10100>;
			enable-method = "psci";
			next-level-cache = <&l2_1>;
			power-domains = <&cpu_pd5>, <&scmi_dvfs 1>;
			power-domain-names = "psci", "perf";
			#cooling-cells = <2>;
		};

		cpu6: cpu@10200 {
			device_type = "cpu";
			compatible = "qcom,oryon";
			reg = <0x0 0x10200>;
			enable-method = "psci";
			next-level-cache = <&l2_1>;
			power-domains = <&cpu_pd6>, <&scmi_dvfs 1>;
			power-domain-names = "psci", "perf";
			#cooling-cells = <2>;
		};

		cpu7: cpu@10300 {
			device_type = "cpu";
			compatible = "qcom,oryon";
			reg = <0x0 0x10300>;
			enable-method = "psci";
			next-level-cache = <&l2_1>;
			power-domains = <&cpu_pd7>, <&scmi_dvfs 1>;
			power-domain-names = "psci", "perf";
			#cooling-cells = <2>;
		};

		cpu8: cpu@20000 {
			device_type = "cpu";
			compatible = "qcom,oryon";
			reg = <0x0 0x20000>;
			enable-method = "psci";
			next-level-cache = <&l2_2>;
			power-domains = <&cpu_pd8>, <&scmi_dvfs 2>;
			power-domain-names = "psci", "perf";
			#cooling-cells = <2>;

			l2_2: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
			};
		};

		cpu9: cpu@20100 {
			device_type = "cpu";
			compatible = "qcom,oryon";
			reg = <0x0 0x20100>;
			enable-method = "psci";
			next-level-cache = <&l2_2>;
			power-domains = <&cpu_pd9>, <&scmi_dvfs 2>;
			power-domain-names = "psci", "perf";
			#cooling-cells = <2>;
		};

		cpu10: cpu@20200 {
			device_type = "cpu";
			compatible = "qcom,oryon";
			reg = <0x0 0x20200>;
			enable-method = "psci";
			next-level-cache = <&l2_2>;
			power-domains = <&cpu_pd10>, <&scmi_dvfs 2>;
			power-domain-names = "psci", "perf";
			#cooling-cells = <2>;
		};

		cpu11: cpu@20300 {
			device_type = "cpu";
			compatible = "qcom,oryon";
			reg = <0x0 0x20300>;
			enable-method = "psci";
			next-level-cache = <&l2_2>;
			power-domains = <&cpu_pd11>, <&scmi_dvfs 2>;
			power-domain-names = "psci", "perf";
			#cooling-cells = <2>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

				core2 {
					cpu = <&cpu2>;
				};

				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};

				core1 {
					cpu = <&cpu5>;
				};

				core2 {
					cpu = <&cpu6>;
				};

				core3 {
					cpu = <&cpu7>;
				};
			};

			cpu_map_cluster2: cluster2 {
				core0 {
					cpu = <&cpu8>;
				};

				core1 {
					cpu = <&cpu9>;
				};

				core2 {
					cpu = <&cpu10>;
				};

				core3 {
					cpu = <&cpu11>;
				};
			};
		};

		idle-states {
			entry-method = "psci";

			cluster_c4: cpu-sleep-0 {
				compatible = "arm,idle-state";
				idle-state-name = "ret";
				arm,psci-suspend-param = <0x00000004>;
				entry-latency-us = <180>;
				exit-latency-us = <320>;
				min-residency-us = <600>;
			};
		};

		domain-idle-states {
			cluster_cl4: cluster-sleep-0 {
				compatible = "domain-idle-state";
				arm,psci-suspend-param = <0x01000044>;
				entry-latency-us = <350>;
				exit-latency-us = <500>;
				min-residency-us = <2500>;
			};

			cluster_cl5: cluster-sleep-1 {
				compatible = "domain-idle-state";
				arm,psci-suspend-param = <0x01000054>;
				entry-latency-us = <2200>;
				exit-latency-us = <4000>;
				min-residency-us = <7000>;
			};
		};
	};

	dummy-sink {
		compatible = "arm,coresight-dummy-sink";

		in-ports {
			port {
				eud_in: endpoint {
					remote-endpoint = <&swao_rep_out1>;
				};
			};
		};
	};

	firmware {
		scm: scm {
			compatible = "qcom,scm-x1e80100", "qcom,scm";
			interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
			qcom,dload-mode = <&tcsr 0x19000>;
		};

		scmi {
			compatible = "arm,scmi";
			mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>;
			mbox-names = "tx", "rx";
			shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>;

			#address-cells = <1>;
			#size-cells = <0>;

			scmi_dvfs: protocol@13 {
				reg = <0x13>;
				#power-domain-cells = <1>;
			};
		};
	};

	clk_virt: interconnect-0 {
		compatible = "qcom,x1e80100-clk-virt";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	mc_virt: interconnect-1 {
		compatible = "qcom,x1e80100-mc-virt";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the size */
		reg = <0 0x80000000 0 0>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";

		cpu_pd0: power-domain-cpu0 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd0>;
			domain-idle-states = <&cluster_c4>;
		};

		cpu_pd1: power-domain-cpu1 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd0>;
			domain-idle-states = <&cluster_c4>;
		};

		cpu_pd2: power-domain-cpu2 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd0>;
			domain-idle-states = <&cluster_c4>;
		};

		cpu_pd3: power-domain-cpu3 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd0>;
			domain-idle-states = <&cluster_c4>;
		};

		cpu_pd4: power-domain-cpu4 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd1>;
			domain-idle-states = <&cluster_c4>;
		};

		cpu_pd5: power-domain-cpu5 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd1>;
			domain-idle-states = <&cluster_c4>;
		};

		cpu_pd6: power-domain-cpu6 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd1>;
			domain-idle-states = <&cluster_c4>;
		};

		cpu_pd7: power-domain-cpu7 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd1>;
			domain-idle-states = <&cluster_c4>;
		};

		cpu_pd8: power-domain-cpu8 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd2>;
			domain-idle-states = <&cluster_c4>;
		};

		cpu_pd9: power-domain-cpu9 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd2>;
			domain-idle-states = <&cluster_c4>;
		};

		cpu_pd10: power-domain-cpu10 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd2>;
			domain-idle-states = <&cluster_c4>;
		};

		cpu_pd11: power-domain-cpu11 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd2>;
			domain-idle-states = <&cluster_c4>;
		};

		cluster_pd0: power-domain-cpu-cluster0 {
			#power-domain-cells = <0>;
			domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
			power-domains = <&system_pd>;
		};

		cluster_pd1: power-domain-cpu-cluster1 {
			#power-domain-cells = <0>;
			domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
			power-domains = <&system_pd>;
		};

		cluster_pd2: power-domain-cpu-cluster2 {
			#power-domain-cells = <0>;
			domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
			power-domains = <&system_pd>;
		};

		system_pd: power-domain-system {
			#power-domain-cells = <0>;
			/* TODO: system-wide idle states */
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gunyah_hyp_mem: gunyah-hyp@80000000 {
			reg = <0x0 0x80000000 0x0 0x800000>;
			no-map;
		};

		hyp_elf_package_mem: hyp-elf-package@80800000 {
			reg = <0x0 0x80800000 0x0 0x200000>;
			no-map;
		};

		ncc_mem: ncc@80a00000 {
			reg = <0x0 0x80a00000 0x0 0x400000>;
			no-map;
		};

		cpucp_log_mem: cpucp-log@80e00000 {
			reg = <0x0 0x80e00000 0x0 0x40000>;
			no-map;
		};

		cpucp_mem: cpucp@80e40000 {
			reg = <0x0 0x80e40000 0x0 0x540000>;
			no-map;
		};

		reserved-region@81380000 {
			reg = <0x0 0x81380000 0x0 0x80000>;
			no-map;
		};

		tags_mem: tags-region@81400000 {
			reg = <0x0 0x81400000 0x0 0x1a0000>;
			no-map;
		};

		xbl_dtlog_mem: xbl-dtlog@81a00000 {
			reg = <0x0 0x81a00000 0x0 0x40000>;
			no-map;
		};

		xbl_ramdump_mem: xbl-ramdump@81a40000 {
			reg = <0x0 0x81a40000 0x0 0x1c0000>;
			no-map;
		};

		aop_image_mem: aop-image@81c00000 {
			reg = <0x0 0x81c00000 0x0 0x60000>;
			no-map;
		};

		aop_cmd_db_mem: aop-cmd-db@81c60000 {
			compatible = "qcom,cmd-db";
			reg = <0x0 0x81c60000 0x0 0x20000>;
			no-map;
		};

		aop_config_mem: aop-config@81c80000 {
			reg = <0x0 0x81c80000 0x0 0x20000>;
			no-map;
		};

		tme_crash_dump_mem: tme-crash-dump@81ca0000 {
			reg = <0x0 0x81ca0000 0x0 0x40000>;
			no-map;
		};

		tme_log_mem: tme-log@81ce0000 {
			reg = <0x0 0x81ce0000 0x0 0x4000>;
			no-map;
		};

		uefi_log_mem: uefi-log@81ce4000 {
			reg = <0x0 0x81ce4000 0x0 0x10000>;
			no-map;
		};

		secdata_apss_mem: secdata-apss@81cff000 {
			reg = <0x0 0x81cff000 0x0 0x1000>;
			no-map;
		};

		pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
			reg = <0x0 0x81e00000 0x0 0x100000>;
			no-map;
		};

		gpu_prr_mem: gpu-prr@81f00000 {
			reg = <0x0 0x81f00000 0x0 0x10000>;
			no-map;
		};

		tpm_control_mem: tpm-control@81f10000 {
			reg = <0x0 0x81f10000 0x0 0x10000>;
			no-map;
		};

		usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {
			reg = <0x0 0x81f20000 0x0 0x10000>;
			no-map;
		};

		pld_pep_mem: pld-pep@81f30000 {
			reg = <0x0 0x81f30000 0x0 0x6000>;
			no-map;
		};

		pld_gmu_mem: pld-gmu@81f36000 {
			reg = <0x0 0x81f36000 0x0 0x1000>;
			no-map;
		};

		pld_pdp_mem: pld-pdp@81f37000 {
			reg = <0x0 0x81f37000 0x0 0x1000>;
			no-map;
		};

		tz_stat_mem: tz-stat@82700000 {
			reg = <0x0 0x82700000 0x0 0x100000>;
			no-map;
		};

		xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {
			reg = <0x0 0x82800000 0x0 0xc00000>;
			no-map;
		};

		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {
			reg = <0x0 0x84b00000 0x0 0x800000>;
			no-map;
		};

		spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 {
			reg = <0x0 0x85300000 0x0 0x80000>;
			no-map;
		};

		adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 {
			reg = <0x0 0x866c0000 0x0 0x40000>;
			no-map;
		};

		spss_region_mem: spss-region@86700000 {
			reg = <0x0 0x86700000 0x0 0x400000>;
			no-map;
		};

		adsp_boot_mem: adsp-boot@86b00000 {
			reg = <0x0 0x86b00000 0x0 0xc00000>;
			no-map;
		};

		video_mem: video@87700000 {
			reg = <0x0 0x87700000 0x0 0x700000>;
			no-map;
		};

		adspslpi_mem: adspslpi@87e00000 {
			reg = <0x0 0x87e00000 0x0 0x3a00000>;
			no-map;
		};

		q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 {
			reg = <0x0 0x8b800000 0x0 0x80000>;
			no-map;
		};

		cdsp_mem: cdsp@8b900000 {
			reg = <0x0 0x8b900000 0x0 0x2000000>;
			no-map;
		};

		q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 {
			reg = <0x0 0x8d900000 0x0 0x80000>;
			no-map;
		};

		gpu_microcode_mem: gpu-microcode@8d9fe000 {
			reg = <0x0 0x8d9fe000 0x0 0x2000>;
			no-map;
		};

		cvp_mem: cvp@8da00000 {
			reg = <0x0 0x8da00000 0x0 0x700000>;
			no-map;
		};

		camera_mem: camera@8e100000 {
			reg = <0x0 0x8e100000 0x0 0x800000>;
			no-map;
		};

		av1_encoder_mem: av1-encoder@8e900000 {
			reg = <0x0 0x8e900000 0x0 0x700000>;
			no-map;
		};

		reserved-region@8f000000 {
			reg = <0x0 0x8f000000 0x0 0xa00000>;
			no-map;
		};

		wpss_mem: wpss@8fa00000 {
			reg = <0x0 0x8fa00000 0x0 0x1900000>;
			no-map;
		};

		q6_wpss_dtb_mem: q6-wpss-dtb@91300000 {
			reg = <0x0 0x91300000 0x0 0x80000>;
			no-map;
		};

		xbl_sc_mem: xbl-sc@d8000000 {
			reg = <0x0 0xd8000000 0x0 0x40000>;
			no-map;
		};

		reserved-region@d8040000 {
			reg = <0x0 0xd8040000 0x0 0xa0000>;
			no-map;
		};

		qtee_mem: qtee@d80e0000 {
			reg = <0x0 0xd80e0000 0x0 0x520000>;
			no-map;
		};

		ta_mem: ta@d8600000 {
			reg = <0x0 0xd8600000 0x0 0x8a00000>;
			no-map;
		};

		tags_mem1: tags@e1000000 {
			reg = <0x0 0xe1000000 0x0 0x26a0000>;
			no-map;
		};

		llcc_lpi_mem: llcc-lpi@ff800000 {
			reg = <0x0 0xff800000 0x0 0x600000>;
			no-map;
		};

		smem_mem: smem@ffe00000 {
			compatible = "qcom,smem";
			reg = <0x0 0xffe00000 0x0 0x200000>;
			hwlocks = <&tcsr_mutex 3>;
			no-map;
		};
	};

	qup_opp_table_100mhz: opp-table-qup100mhz {
		compatible = "operating-points-v2";

		opp-75000000 {
			opp-hz = /bits/ 64 <75000000>;
			required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			required-opps = <&rpmhpd_opp_svs>;
		};
	};

	qup_opp_table_120mhz: opp-table-qup120mhz {
		compatible = "operating-points-v2";

		opp-75000000 {
			opp-hz = /bits/ 64 <75000000>;
			required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-120000000 {
			opp-hz = /bits/ 64 <120000000>;
			required-opps = <&rpmhpd_opp_svs>;
		};
	};

	smp2p-adsp {
		compatible = "qcom,smp2p";

		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
					     IPCC_MPROC_SIGNAL_SMP2P
					     IRQ_TYPE_EDGE_RISING>;

		mboxes = <&ipcc IPCC_CLIENT_LPASS
				IPCC_MPROC_SIGNAL_SMP2P>;

		qcom,smem = <443>, <429>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		smp2p_adsp_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_adsp_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-cdsp {
		compatible = "qcom,smp2p";

		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
					     IPCC_MPROC_SIGNAL_SMP2P
					     IRQ_TYPE_EDGE_RISING>;

		mboxes = <&ipcc IPCC_CLIENT_CDSP
				IPCC_MPROC_SIGNAL_SMP2P>;

		qcom,smem = <94>, <432>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		smp2p_cdsp_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_cdsp_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	soc: soc@0 {
		compatible = "simple-bus";

		#address-cells = <2>;
		#size-cells = <2>;
		dma-ranges = <0 0 0 0 0x100 0>;
		ranges = <0 0 0 0 0x100 0>;

		gcc: clock-controller@100000 {
			compatible = "qcom,x1e80100-gcc";
			reg = <0 0x00100000 0 0x200000>;

			clocks = <&bi_tcxo_div2>,
				 <&sleep_clk>,
				 <&pcie3_phy>,
				 <&pcie4_phy>,
				 <&pcie5_phy>,
				 <&pcie6a_phy>,
				 <0>,
				 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
				 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
				 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <&ufs_mem_phy 0>,
				 <&ufs_mem_phy 1>,
				 <&ufs_mem_phy 2>;

			power-domains = <&rpmhpd RPMHPD_CX>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		ipcc: mailbox@408000 {
			compatible = "qcom,x1e80100-ipcc", "qcom,ipcc";
			reg = <0 0x00408000 0 0x1000>;

			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <3>;

			#mbox-cells = <2>;
		};

		gpi_dma2: dma-controller@800000 {
			compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
			reg = <0 0x00800000 0 0x60000>;

			interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;

			dma-channels = <12>;
			dma-channel-mask = <0x3e>;
			#dma-cells = <3>;

			iommus = <&apps_smmu 0x436 0x0>;

			status = "disabled";
		};

		qupv3_2: geniqup@8c0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0 0x008c0000 0 0x2000>;

			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
			clock-names = "m-ahb",
				      "s-ahb";

			iommus = <&apps_smmu 0x423 0x0>;

			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			status = "disabled";

			i2c16: i2c@880000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00880000 0 0x4000>;

				interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 0 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c16_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi16: spi@880000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00880000 0 0x4000>;

				interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_120mhz>;

				dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
				       <&gpi_dma2 1 0 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c17: i2c@884000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00884000 0 0x4000>;

				interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 1 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c17_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi17: spi@884000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00884000 0 0x4000>;

				interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_120mhz>;

				dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
				       <&gpi_dma2 1 1 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c18: i2c@888000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00888000 0 0x4000>;

				interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 2 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c18_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi18: spi@888000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00888000 0 0x4000>;

				interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
				       <&gpi_dma2 1 2 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c19: i2c@88c000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x0088c000 0 0x4000>;

				interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c19_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi19: spi@88c000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x0088c000 0 0x4000>;

				interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
				       <&gpi_dma2 1 3 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c20: i2c@890000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00890000 0 0x4000>;

				interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c20_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi20: spi@890000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00890000 0 0x4000>;

				interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
				       <&gpi_dma2 1 4 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c21: i2c@894000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00894000 0 0x4000>;

				interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 5 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c21_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi21: spi@894000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00894000 0 0x4000>;

				interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
				       <&gpi_dma2 1 5 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			uart21: serial@894000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00894000 0 0x4000>;

				interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
				interconnect-names = "qup-core",
						     "qup-config";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				pinctrl-0 = <&qup_uart21_default>;
				pinctrl-names = "default";

				status = "disabled";
			};

			i2c22: i2c@898000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00898000 0 0x4000>;

				interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 6 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c22_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi22: spi@898000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00898000 0 0x4000>;

				interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
				       <&gpi_dma2 1 6 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c23: i2c@89c000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x0089c000 0 0x4000>;

				interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 7 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c23_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi23: spi@89c000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x0089c000 0 0x4000>;

				interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
				       <&gpi_dma2 1 7 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};
		};

		gpi_dma1: dma-controller@a00000 {
			compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
			reg = <0 0x00a00000 0 0x60000>;

			interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>;

			dma-channels = <12>;
			dma-channel-mask = <0x3e>;
			#dma-cells = <3>;

			iommus = <&apps_smmu 0x136 0x0>;

			status = "disabled";
		};

		qupv3_1: geniqup@ac0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0 0x00ac0000 0 0x2000>;

			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
			clock-names = "m-ahb",
				      "s-ahb";

			iommus = <&apps_smmu 0x123 0x0>;

			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			status = "disabled";

			i2c8: i2c@a80000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a80000 0 0x4000>;

				interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c8_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi8: spi@a80000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00a80000 0 0x4000>;

				interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_120mhz>;

				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c9: i2c@a84000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a84000 0 0x4000>;

				interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c9_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi9: spi@a84000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00a84000 0 0x4000>;

				interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_120mhz>;

				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c10: i2c@a88000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a88000 0 0x4000>;

				interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c10_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi10: spi@a88000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00a88000 0 0x4000>;

				interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c11: i2c@a8c000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a8c000 0 0x4000>;

				interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c11_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi11: spi@a8c000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00a8c000 0 0x4000>;

				interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c12: i2c@a90000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a90000 0 0x4000>;

				interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c12_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi12: spi@a90000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00a90000 0 0x4000>;

				interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c13: i2c@a94000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a94000 0 0x4000>;

				interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c13_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi13: spi@a94000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00a94000 0 0x4000>;

				interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c14: i2c@a98000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a98000 0 0x4000>;

				interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 6 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c14_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi14: spi@a98000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00a98000 0 0x4000>;

				interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 6 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			uart14: serial@a98000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00a98000 0 0x4000>;

				interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
				interconnect-names = "qup-core",
						     "qup-config";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				pinctrl-0 = <&qup_uart14_default>;
				pinctrl-names = "default";

				status = "disabled";
			};

			i2c15: i2c@a9c000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a9c000 0 0x4000>;

				interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 7 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c15_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi15: spi@a9c000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00a9c000 0 0x4000>;

				interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 7 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};
		};

		gpi_dma0: dma-controller@b00000  {
			compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
			reg = <0 0x00b00000 0 0x60000>;

			interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;

			dma-channels = <12>;
			dma-channel-mask = <0x3e>;
			#dma-cells = <3>;

			iommus = <&apps_smmu 0x456 0x0>;

			status = "disabled";
		};

		qupv3_0: geniqup@bc0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0 0x00bc0000 0 0x2000>;

			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
			clock-names = "m-ahb",
				      "s-ahb";

			iommus = <&apps_smmu 0x443 0x0>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			status = "disabled";

			i2c0: i2c@b80000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00b80000 0 0x4000>;

				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c0_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi0: spi@b80000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00b80000 0 0x4000>;

				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_120mhz>;

				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c1: i2c@b84000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00b84000 0 0x4000>;

				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c1_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi1: spi@b84000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00b84000 0 0x4000>;

				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_120mhz>;

				dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 1 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c2: i2c@b88000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00b88000 0 0x4000>;

				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c2_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			uart2: serial@b88000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00b88000 0 0x4000>;

				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
				interconnect-names = "qup-core",
						     "qup-config";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				pinctrl-0 = <&qup_uart2_default>;
				pinctrl-names = "default";

				status = "disabled";
			};

			spi2: spi@b88000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00b88000 0 0x4000>;

				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c3: i2c@b8c000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00b8c000 0 0x4000>;

				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c3_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi3: spi@b8c000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00b8c000 0 0x4000>;

				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 3 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c4: i2c@b90000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00b90000 0 0x4000>;

				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c4_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi4: spi@b90000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00b90000 0 0x4000>;

				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 4 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c5: i2c@b94000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00b94000 0 0x4000>;

				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c5_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi5: spi@b94000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00b94000 0 0x4000>;

				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 5 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c6: i2c@b98000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00b98000 0 0x4000>;

				interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 6 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c6_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi6: spi@b98000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00b98000 0 0x4000>;

				interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 6 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			i2c7: i2c@b9c000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00b9c000 0 0x4000>;

				interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;

				dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 7 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_i2c7_data_clk>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			spi7: spi@b9c000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00b9c000 0 0x4000>;

				interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";

				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 7 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";

				pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
				pinctrl-names = "default";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};
		};

		tsens0: thermal-sensor@c271000 {
			compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
			reg = <0 0x0c271000 0 0x1000>,
			      <0 0x0c222000 0 0x1000>;

			interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow",
					  "critical";

			#qcom,sensors = <16>;

			#thermal-sensor-cells = <1>;
		};

		tsens1: thermal-sensor@c272000 {
			compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
			reg = <0 0x0c272000 0 0x1000>,
			      <0 0x0c223000 0 0x1000>;

			interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow",
					  "critical";

			#qcom,sensors = <16>;

			#thermal-sensor-cells = <1>;
		};

		tsens2: thermal-sensor@c273000 {
			compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
			reg = <0 0x0c273000 0 0x1000>,
			      <0 0x0c224000 0 0x1000>;

			interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow",
					  "critical";

			#qcom,sensors = <16>;

			#thermal-sensor-cells = <1>;
		};

		tsens3: thermal-sensor@c274000 {
			compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
			reg = <0 0x0c274000 0 0x1000>,
			      <0 0x0c225000 0 0x1000>;

			interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow",
					  "critical";

			#qcom,sensors = <16>;

			#thermal-sensor-cells = <1>;
		};

		usb_1_ss0_hsphy: phy@fd3000 {
			compatible = "qcom,x1e80100-snps-eusb2-phy",
				     "qcom,sm8550-snps-eusb2-phy";
			reg = <0 0x00fd3000 0 0x154>;
			#phy-cells = <0>;

			clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
			clock-names = "ref";

			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

			status = "disabled";
		};

		usb_1_ss0_qmpphy: phy@fd5000 {
			compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
			reg = <0 0x00fd5000 0 0x4000>;

			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
			clock-names = "aux",
				      "ref",
				      "com_aux",
				      "usb3_pipe";

			power-domains = <&gcc GCC_USB_0_PHY_GDSC>;

			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
				 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>;
			reset-names = "phy",
				      "common";

			#clock-cells = <1>;
			#phy-cells = <1>;

			mode-switch;
			orientation-switch;

			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					usb_1_ss0_qmpphy_out: endpoint {
					};
				};

				port@1 {
					reg = <1>;

					usb_1_ss0_qmpphy_usb_ss_in: endpoint {
						remote-endpoint = <&usb_1_ss0_dwc3_ss>;
					};
				};

				port@2 {
					reg = <2>;

					usb_1_ss0_qmpphy_dp_in: endpoint {
						remote-endpoint = <&mdss_dp0_out>;
					};
				};
			};
		};

		usb_1_ss1_hsphy: phy@fd9000 {
			compatible = "qcom,x1e80100-snps-eusb2-phy",
				     "qcom,sm8550-snps-eusb2-phy";
			reg = <0 0x00fd9000 0 0x154>;
			#phy-cells = <0>;

			clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
			clock-names = "ref";

			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;

			status = "disabled";
		};

		usb_1_ss1_qmpphy: phy@fda000 {
			compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
			reg = <0 0x00fda000 0 0x4000>;

			clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
				 <&tcsr TCSR_USB4_1_CLKREF_EN>,
				 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
				 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
			clock-names = "aux",
				      "ref",
				      "com_aux",
				      "usb3_pipe";

			power-domains = <&gcc GCC_USB_1_PHY_GDSC>;

			resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
				 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>;
			reset-names = "phy",
				      "common";

			#clock-cells = <1>;
			#phy-cells = <1>;

			mode-switch;
			orientation-switch;

			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					usb_1_ss1_qmpphy_out: endpoint {
					};
				};

				port@1 {
					reg = <1>;

					usb_1_ss1_qmpphy_usb_ss_in: endpoint {
						remote-endpoint = <&usb_1_ss1_dwc3_ss>;
					};
				};

				port@2 {
					reg = <2>;

					usb_1_ss1_qmpphy_dp_in: endpoint {
						remote-endpoint = <&mdss_dp1_out>;
					};
				};
			};
		};

		usb_1_ss2_hsphy: phy@fde000 {
			compatible = "qcom,x1e80100-snps-eusb2-phy",
				     "qcom,sm8550-snps-eusb2-phy";
			reg = <0 0x00fde000 0 0x154>;
			#phy-cells = <0>;

			clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
			clock-names = "ref";

			resets = <&gcc GCC_QUSB2PHY_TERT_BCR>;

			status = "disabled";
		};

		usb_1_ss2_qmpphy: phy@fdf000 {
			compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
			reg = <0 0x00fdf000 0 0x4000>;

			clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
				 <&tcsr TCSR_USB4_2_CLKREF_EN>,
				 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
				 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>;
			clock-names = "aux",
				      "ref",
				      "com_aux",
				      "usb3_pipe";

			power-domains = <&gcc GCC_USB_2_PHY_GDSC>;

			resets = <&gcc GCC_USB3_PHY_TERT_BCR>,
				 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>;
			reset-names = "phy",
				      "common";

			#clock-cells = <1>;
			#phy-cells = <1>;

			mode-switch;
			orientation-switch;

			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					usb_1_ss2_qmpphy_out: endpoint {
					};
				};

				port@1 {
					reg = <1>;

					usb_1_ss2_qmpphy_usb_ss_in: endpoint {
						remote-endpoint = <&usb_1_ss2_dwc3_ss>;
					};
				};

				port@2 {
					reg = <2>;

					usb_1_ss2_qmpphy_dp_in: endpoint {
						remote-endpoint = <&mdss_dp2_out>;
					};
				};
			};
		};

		rng: rng@10c3000 {
			compatible = "qcom,x1e80100-trng", "qcom,trng";
			reg = <0x0 0x010c3000 0x0 0x1000>;
		};

		cnoc_main: interconnect@1500000 {
			compatible = "qcom,x1e80100-cnoc-main";
			reg = <0 0x01500000 0 0x14400>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		config_noc: interconnect@1600000 {
			compatible = "qcom,x1e80100-cnoc-cfg";
			reg = <0 0x01600000 0 0x6600>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		system_noc: interconnect@1680000 {
			compatible = "qcom,x1e80100-system-noc";
			reg = <0 0x01680000 0 0x1c080>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		pcie_south_anoc: interconnect@16c0000 {
			compatible = "qcom,x1e80100-pcie-south-anoc";
			reg = <0 0x016c0000 0 0xd080>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		pcie_center_anoc: interconnect@16d0000 {
			compatible = "qcom,x1e80100-pcie-center-anoc";
			reg = <0 0x016d0000 0 0x7000>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		aggre1_noc: interconnect@16e0000 {
			compatible = "qcom,x1e80100-aggre1-noc";
			reg = <0 0x016e0000 0 0x14400>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		aggre2_noc: interconnect@1700000 {
			compatible = "qcom,x1e80100-aggre2-noc";
			reg = <0 0x01700000 0 0x1c400>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		pcie_north_anoc: interconnect@1740000 {
			compatible = "qcom,x1e80100-pcie-north-anoc";
			reg = <0 0x01740000 0 0x9080>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		usb_center_anoc: interconnect@1750000 {
			compatible = "qcom,x1e80100-usb-center-anoc";
			reg = <0 0x01750000 0 0x8800>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		usb_north_anoc: interconnect@1760000 {
			compatible = "qcom,x1e80100-usb-north-anoc";
			reg = <0 0x01760000 0 0x7080>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		usb_south_anoc: interconnect@1770000 {
			compatible = "qcom,x1e80100-usb-south-anoc";
			reg = <0 0x01770000 0 0xf080>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		mmss_noc: interconnect@1780000 {
			compatible = "qcom,x1e80100-mmss-noc";
			reg = <0 0x01780000 0 0x5b800>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		pcie3: pcie@1bd0000 {
			device_type = "pci";
			compatible = "qcom,pcie-x1e80100";
			reg = <0x0 0x01bd0000 0x0 0x3000>,
			      <0x0 0x78000000 0x0 0xf20>,
			      <0x0 0x78000f40 0x0 0xa8>,
			      <0x0 0x78001000 0x0 0x1000>,
			      <0x0 0x78100000 0x0 0x100000>,
			      <0x0 0x01bd3000 0x0 0x1000>;
			reg-names = "parf",
				    "dbi",
				    "elbi",
				    "atu",
				    "config",
				    "mhi";
			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>,
				 <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>,
				 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>;
			bus-range = <0x00 0xff>;

			dma-coherent;

			linux,pci-domain = <3>;
			num-lanes = <8>;

			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi0",
					  "msi1",
					  "msi2",
					  "msi3",
					  "msi4",
					  "msi5",
					  "msi6",
					  "msi7",
					  "global";

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
				 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
				 <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
				 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
				 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
				 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
			clock-names = "aux",
				      "cfg",
				      "bus_master",
				      "bus_slave",
				      "slave_q2a",
				      "noc_aggr",
				      "cnoc_sf_axi";

			assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
			assigned-clock-rates = <19200000>;

			interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "pcie-mem",
					     "cpu-pcie";

			resets = <&gcc GCC_PCIE_3_BCR>,
				 <&gcc GCC_PCIE_3_LINK_DOWN_BCR>;
			reset-names = "pci",
				      "link_down";

			power-domains = <&gcc GCC_PCIE_3_GDSC>;

			eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555
						     0x5555 0x5555 0x5555 0x5555>;
			eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>;

			operating-points-v2 = <&pcie3_opp_table>;

			status = "disabled";

			pcie3_opp_table: opp-table {
				compatible = "operating-points-v2";

				/* 2.5GT/s x1 */
				opp-2500000-1 {
					opp-hz = /bits/ 64 <2500000>;
					required-opps = <&rpmhpd_opp_low_svs>;
					opp-peak-kBps = <250000 1>;
					opp-level = <1>;
				};

				/* 2.5 GT/s x2 */
				opp-5000000-1 {
					opp-hz = /bits/ 64 <5000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
					opp-peak-kBps = <500000 1>;
					opp-level = <1>;
				};

				/* 2.5 GT/s x4 */
				opp-10000000-1 {
					opp-hz = /bits/ 64 <10000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
					opp-peak-kBps = <1000000 1>;
					opp-level = <1>;
				};

				/* 2.5 GT/s x8 */
				opp-20000000-1 {
					opp-hz = /bits/ 64 <20000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
					opp-peak-kBps = <2000000 1>;
					opp-level = <1>;
				};

				/* 5 GT/s x1 */
				opp-5000000-2 {
					opp-hz = /bits/ 64 <5000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
					opp-peak-kBps = <500000 1>;
					opp-level = <2>;
				};

				/* 5 GT/s x2 */
				opp-10000000-2 {
					opp-hz = /bits/ 64 <10000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
					opp-peak-kBps = <1000000 1>;
					opp-level = <2>;
				};

				/* 5 GT/s x4 */
				opp-20000000-2 {
					opp-hz = /bits/ 64 <20000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
					opp-peak-kBps = <2000000 1>;
					opp-level = <2>;
				};

				/* 5 GT/s x8 */
				opp-40000000-2 {
					opp-hz = /bits/ 64 <40000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
					opp-peak-kBps = <4000000 1>;
					opp-level = <2>;
				};

				/* 8 GT/s x1 */
				opp-8000000-3 {
					opp-hz = /bits/ 64 <8000000>;
					required-opps = <&rpmhpd_opp_svs>;
					opp-peak-kBps = <984500 1>;
					opp-level = <3>;
				};

				/* 8 GT/s x2 */
				opp-16000000-3 {
					opp-hz = /bits/ 64 <16000000>;
					required-opps = <&rpmhpd_opp_svs>;
					opp-peak-kBps = <1969000 1>;
					opp-level = <3>;
				};

				/* 8 GT/s x4 */
				opp-32000000-3 {
					opp-hz = /bits/ 64 <32000000>;
					required-opps = <&rpmhpd_opp_svs>;
					opp-peak-kBps = <3938000 1>;
					opp-level = <3>;
				};

				/* 8 GT/s x8 */
				opp-64000000-3 {
					opp-hz = /bits/ 64 <64000000>;
					required-opps = <&rpmhpd_opp_svs>;
					opp-peak-kBps = <7876000 1>;
					opp-level = <3>;
				};

				/* 16 GT/s x1 */
				opp-16000000-4 {
					opp-hz = /bits/ 64 <16000000>;
					required-opps = <&rpmhpd_opp_svs>;
					opp-peak-kBps = <1969000 1>;
					opp-level = <4>;
				};

				/* 16 GT/s x2 */
				opp-32000000-4 {
					opp-hz = /bits/ 64 <32000000>;
					required-opps = <&rpmhpd_opp_svs>;
					opp-peak-kBps = <3938000 1>;
					opp-level = <4>;
				};

				/* 16 GT/s x4 */
				opp-64000000-4 {
					opp-hz = /bits/ 64 <64000000>;
					required-opps = <&rpmhpd_opp_svs>;
					opp-peak-kBps = <7876000 1>;
					opp-level = <4>;
				};

				/* 16 GT/s x8 */
				opp-128000000-4 {
					opp-hz = /bits/ 64 <128000000>;
					required-opps = <&rpmhpd_opp_svs>;
					opp-peak-kBps = <15753000 1>;
					opp-level = <4>;
				};
			};

			pcie3_port0: pcie@0 {
				device_type = "pci";
				compatible = "pciclass,0604";
				reg = <0x0 0x0 0x0 0x0 0x0>;
				bus-range = <0x01 0xff>;

				phys = <&pcie3_phy>;

				#address-cells = <3>;
				#size-cells = <2>;
				ranges;
			};
		};

		pcie3_phy: phy@1be0000 {
			compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
			reg = <0 0x01be0000 0 0x10000>;

			clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
				 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
				 <&tcsr TCSR_PCIE_8L_CLKREF_EN>,
				 <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
				 <&gcc GCC_PCIE_3_PIPE_CLK>,
				 <&gcc GCC_PCIE_3_PIPEDIV2_CLK>;
			clock-names = "aux",
				      "cfg_ahb",
				      "ref",
				      "rchng",
				      "pipe",
				      "pipediv2";

			resets = <&gcc GCC_PCIE_3_PHY_BCR>,
				 <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>;
			reset-names = "phy",
				      "phy_nocsr";

			assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>;
			assigned-clock-rates = <100000000>;

			power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>;

			#clock-cells = <0>;
			clock-output-names = "pcie3_pipe_clk";

			#phy-cells = <0>;

			status = "disabled";
		};

		pcie6a: pci@1bf8000 {
			device_type = "pci";
			compatible = "qcom,pcie-x1e80100";
			reg = <0 0x01bf8000 0 0x3000>,
			      <0 0x70000000 0 0xf20>,
			      <0 0x70000f40 0 0xa8>,
			      <0 0x70001000 0 0x1000>,
			      <0 0x70100000 0 0x100000>,
			      <0 0x01bfb000 0 0x1000>;
			reg-names = "parf",
				    "dbi",
				    "elbi",
				    "atu",
				    "config",
				    "mhi";
			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>,
				 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
			bus-range = <0x00 0xff>;

			dma-coherent;

			linux,pci-domain = <6>;
			num-lanes = <4>;

			msi-map = <0x0 &gic_its 0xe0000 0x10000>;

			interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi0",
					  "msi1",
					  "msi2",
					  "msi3",
					  "msi4",
					  "msi5",
					  "msi6",
					  "msi7",
					  "global";

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &intc 0 0 GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &intc 0 0 GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &intc 0 0 GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_PCIE_6A_AUX_CLK>,
				 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>,
				 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>,
				 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>,
				 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>,
				 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>;
			clock-names = "aux",
				      "cfg",
				      "bus_master",
				      "bus_slave",
				      "slave_q2a",
				      "noc_aggr",
				      "cnoc_sf_axi";

			assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;
			assigned-clock-rates = <19200000>;

			interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "pcie-mem",
					     "cpu-pcie";

			resets = <&gcc GCC_PCIE_6A_BCR>,
				 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>;
			reset-names = "pci",
				      "link_down";

			power-domains = <&gcc GCC_PCIE_6A_GDSC>;
			required-opps = <&rpmhpd_opp_nom>;

			eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
			eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;

			status = "disabled";

			pcie6a_port0: pcie@0 {
				device_type = "pci";
				reg = <0x0 0x0 0x0 0x0 0x0>;
				bus-range = <0x01 0xff>;

				phys = <&pcie6a_phy>;

				#address-cells = <3>;
				#size-cells = <2>;
				ranges;
			};
		};

		pcie6a_phy: phy@1bfc000 {
			compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy";
			reg = <0 0x01bfc000 0 0x2000>,
			      <0 0x01bfe000 0 0x2000>;

			clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>,
				 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
				 <&tcsr TCSR_PCIE_4L_CLKREF_EN>,
				 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>,
				 <&gcc GCC_PCIE_6A_PIPE_CLK>,
				 <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>;
			clock-names = "aux",
				      "cfg_ahb",
				      "ref",
				      "rchng",
				      "pipe",
				      "pipediv2";

			resets = <&gcc GCC_PCIE_6A_PHY_BCR>,
				 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>;
			reset-names = "phy",
				      "phy_nocsr";

			assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;
			assigned-clock-rates = <100000000>;

			power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;

			qcom,4ln-config-sel = <&tcsr 0x1a000 0>;

			#clock-cells = <0>;
			clock-output-names = "pcie6a_pipe_clk";

			#phy-cells = <0>;

			status = "disabled";
		};

		pcie5: pci@1c00000 {
			device_type = "pci";
			compatible = "qcom,pcie-x1e80100";
			reg = <0 0x01c00000 0 0x3000>,
			      <0 0x7e000000 0 0xf1d>,
			      <0 0x7e000f40 0 0xa8>,
			      <0 0x7e001000 0 0x1000>,
			      <0 0x7e100000 0 0x100000>,
			      <0 0x01c03000 0 0x1000>;
			reg-names = "parf",
				    "dbi",
				    "elbi",
				    "atu",
				    "config",
				    "mhi";
			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>,
				 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>;
			bus-range = <0x00 0xff>;

			dma-coherent;

			linux,pci-domain = <5>;
			num-lanes = <2>;

			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi0",
					  "msi1",
					  "msi2",
					  "msi3",
					  "msi4",
					  "msi5",
					  "msi6",
					  "msi7",
					  "global";

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &intc 0 0 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &intc 0 0 GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &intc 0 0 GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
				 <&gcc GCC_PCIE_5_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>,
				 <&gcc GCC_PCIE_5_SLV_AXI_CLK>,
				 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>,
				 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
				 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
			clock-names = "aux",
				      "cfg",
				      "bus_master",
				      "bus_slave",
				      "slave_q2a",
				      "noc_aggr",
				      "cnoc_sf_axi";

			assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>;
			assigned-clock-rates = <19200000>;

			interconnects = <&pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "pcie-mem",
					     "cpu-pcie";

			resets = <&gcc GCC_PCIE_5_BCR>,
				 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>;
			reset-names = "pci",
				      "link_down";

			power-domains = <&gcc GCC_PCIE_5_GDSC>;
			required-opps = <&rpmhpd_opp_nom>;

			eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;

			status = "disabled";

			pcie5_port0: pcie@0 {
				device_type = "pci";
				reg = <0x0 0x0 0x0 0x0 0x0>;
				bus-range = <0x01 0xff>;

				phys = <&pcie5_phy>;

				#address-cells = <3>;
				#size-cells = <2>;
				ranges;
			};
		};

		pcie5_phy: phy@1c06000 {
			compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
			reg = <0 0x01c06000 0 0x2000>;

			clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
				 <&gcc GCC_PCIE_5_CFG_AHB_CLK>,
				 <&tcsr TCSR_PCIE_2L_5_CLKREF_EN>,
				 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>,
				 <&gcc GCC_PCIE_5_PIPE_CLK>,
				 <&gcc GCC_PCIE_5_PIPEDIV2_CLK>;
			clock-names = "aux",
				      "cfg_ahb",
				      "ref",
				      "rchng",
				      "pipe",
				      "pipediv2";

			resets = <&gcc GCC_PCIE_5_PHY_BCR>,
				 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>;
			reset-names = "phy",
				      "phy_nocsr";

			assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
			assigned-clock-rates = <100000000>;

			power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>;

			#clock-cells = <0>;
			clock-output-names = "pcie5_pipe_clk";

			#phy-cells = <0>;

			status = "disabled";
		};

		pcie4: pci@1c08000 {
			device_type = "pci";
			compatible = "qcom,pcie-x1e80100";
			reg = <0 0x01c08000 0 0x3000>,
			      <0 0x7c000000 0 0xf1d>,
			      <0 0x7c000f40 0 0xa8>,
			      <0 0x7c001000 0 0x1000>,
			      <0 0x7c100000 0 0x100000>,
			      <0 0x01c0b000 0 0x1000>;
			reg-names = "parf",
			            "dbi",
				    "elbi",
				    "atu",
				    "config",
				    "mhi";
			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>,
				 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>;
			bus-range = <0x00 0xff>;

			dma-coherent;

			linux,pci-domain = <4>;
			num-lanes = <2>;

			msi-map = <0x0 &gic_its 0xc0000 0x10000>;

			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi0",
					  "msi1",
					  "msi2",
					  "msi3",
					  "msi4",
					  "msi5",
					  "msi6",
					  "msi7",
					  "global";

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
				 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
				 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
				 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
				 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
				 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
			clock-names = "aux",
				      "cfg",
				      "bus_master",
				      "bus_slave",
				      "slave_q2a",
				      "noc_aggr",
				      "cnoc_sf_axi";

			assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
			assigned-clock-rates = <19200000>;

			interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "pcie-mem",
					     "cpu-pcie";

			resets = <&gcc GCC_PCIE_4_BCR>,
				 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>;
			reset-names = "pci",
				      "link_down";

			power-domains = <&gcc GCC_PCIE_4_GDSC>;
			required-opps = <&rpmhpd_opp_nom>;

			eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;

			status = "disabled";

			pcie4_port0: pcie@0 {
				device_type = "pci";
				reg = <0x0 0x0 0x0 0x0 0x0>;
				bus-range = <0x01 0xff>;

				phys = <&pcie4_phy>;

				#address-cells = <3>;
				#size-cells = <2>;
				ranges;
			};
		};

		pcie4_phy: phy@1c0e000 {
			compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
			reg = <0 0x01c0e000 0 0x2000>;

			clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
				 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
				 <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>,
				 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>,
				 <&gcc GCC_PCIE_4_PIPE_CLK>,
				 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
			clock-names = "aux",
				      "cfg_ahb",
				      "ref",
				      "rchng",
				      "pipe",
				      "pipediv2";

			resets = <&gcc GCC_PCIE_4_PHY_BCR>,
				 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>;
			reset-names = "phy",
				      "phy_nocsr";

			assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
			assigned-clock-rates = <100000000>;

			power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;

			#clock-cells = <0>;
			clock-output-names = "pcie4_pipe_clk";

			#phy-cells = <0>;

			status = "disabled";
		};

		ufs_mem_phy: phy@1d80000 {
			compatible = "qcom,x1e80100-qmp-ufs-phy",
				     "qcom,sm8550-qmp-ufs-phy";
			reg = <0x0 0x01d80000 0x0 0x2000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
				 <&tcsr TCSR_UFS_PHY_CLKREF_EN>;

			clock-names = "ref",
				      "ref_aux",
				      "qref";
			resets = <&ufs_mem_hc 0>;
			reset-names = "ufsphy";

			power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;

			#clock-cells = <1>;
			#phy-cells = <0>;

			status = "disabled";
		};

		ufs_mem_hc: ufshc@1d84000 {
			compatible = "qcom,x1e80100-ufshc",
				     "qcom,sm8550-ufshc",
				     "qcom,ufshc";
			reg = <0x0 0x01d84000 0x0 0x3000>;

			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
				 <&gcc GCC_UFS_PHY_AHB_CLK>,
				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
				 <&rpmhcc RPMH_LN_BB_CLK3>,
				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
			clock-names = "core_clk",
				      "bus_aggr_clk",
				      "iface_clk",
				      "core_clk_unipro",
				      "ref_clk",
				      "tx_lane0_sync_clk",
				      "rx_lane0_sync_clk",
				      "rx_lane1_sync_clk";

			operating-points-v2 = <&ufs_opp_table>;

			resets = <&gcc GCC_UFS_PHY_BCR>;
			reset-names = "rst";

			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "ufs-ddr",
					     "cpu-ufs";

			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
			required-opps = <&rpmhpd_opp_nom>;

			iommus = <&apps_smmu 0x1a0 0>;
			dma-coherent;

			lanes-per-direction = <2>;

			phys = <&ufs_mem_phy>;
			phy-names = "ufsphy";

			#reset-cells = <1>;

			status = "disabled";

			ufs_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-75000000 {
					opp-hz = /bits/ 64 <75000000>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <75000000>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>;
					required-opps = <&rpmhpd_opp_low_svs>;
				};

				opp-150000000 {
					opp-hz = /bits/ 64 <150000000>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <150000000>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>;
					required-opps = <&rpmhpd_opp_svs>;
				};

				opp-300000000 {
					opp-hz = /bits/ 64 <300000000>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <300000000>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>;
					required-opps = <&rpmhpd_opp_nom>;
				};
			};
		};

		cryptobam: dma-controller@1dc4000 {
			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
			reg = <0x0 0x01dc4000 0x0 0x28000>;
			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			iommus = <&apps_smmu 0x480 0x0>,
				 <&apps_smmu 0x481 0x0>;
			qcom,ee = <0>;
			qcom,controlled-remotely;
			num-channels = <20>;
			qcom,num-ees = <4>;
		};

		crypto: crypto@1dfa000 {
			compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce";
			reg = <0x0 0x01dfa000 0x0 0x6000>;
			dmas = <&cryptobam 4>, <&cryptobam 5>;
			dma-names = "rx",
				    "tx";
			iommus = <&apps_smmu 0x480 0x0>,
				 <&apps_smmu 0x481 0x0>;
			interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
			interconnect-names = "memory";
		};

		tcsr_mutex: hwlock@1f40000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0 0x01f40000 0 0x20000>;
			#hwlock-cells = <1>;
		};

		tcsr: clock-controller@1fc0000 {
			compatible = "qcom,x1e80100-tcsr", "syscon";
			reg = <0 0x01fc0000 0 0x30000>;
			clocks = <&rpmhcc RPMH_CXO_CLK>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		gpu: gpu@3d00000 {
			compatible = "qcom,adreno-43050c01", "qcom,adreno";
			reg = <0x0 0x03d00000 0x0 0x40000>,
			      <0x0 0x03d9e000 0x0 0x1000>,
			      <0x0 0x03d61000 0x0 0x800>;

			reg-names = "kgsl_3d0_reg_memory",
				    "cx_mem",
				    "cx_dbgc";

			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

			iommus = <&adreno_smmu 0 0x0>,
				 <&adreno_smmu 1 0x0>;

			operating-points-v2 = <&gpu_opp_table>;

			qcom,gmu = <&gmu>;
			#cooling-cells = <2>;

			nvmem-cells = <&gpu_speed_bin>;
			nvmem-cell-names = "speed_bin";

			interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
			interconnect-names = "gfx-mem";

			status = "disabled";

			gpu_zap_shader: zap-shader {
				memory-region = <&gpu_microcode_mem>;
			};

			gpu_opp_table: opp-table {
				compatible = "operating-points-v2-adreno", "operating-points-v2";

				opp-1500000000 {
					opp-hz = /bits/ 64 <1500000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>;
					opp-peak-kBps = <16500000>;
					qcom,opp-acd-level = <0xa82a5ffd>;
					opp-supported-hw = <0x03>;
				};

				opp-1375000000 {
					opp-hz = /bits/ 64 <1375000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
					opp-peak-kBps = <16500000>;
					qcom,opp-acd-level = <0xa82a5ffd>;
					opp-supported-hw = <0x03>;
				};

				opp-1250000000 {
					opp-hz = /bits/ 64 <1250000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
					opp-peak-kBps = <16500000>;
					qcom,opp-acd-level = <0xa82a5ffd>;
					opp-supported-hw = <0x07>;
				};

				opp-1175000000 {
					opp-hz = /bits/ 64 <1175000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
					opp-peak-kBps = <14398438>;
					qcom,opp-acd-level = <0xa82a5ffd>;
					opp-supported-hw = <0x07>;
				};

				opp-1100000000-0 {
					opp-hz = /bits/ 64 <1100000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
					opp-peak-kBps = <14398438>;
					qcom,opp-acd-level = <0xa82a5ffd>;
					opp-supported-hw = <0x07>;
				};

				/* Only applicable for SKUs which has 1100Mhz as Fmax */
				opp-1100000000-1 {
					opp-hz = /bits/ 64 <1100000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
					opp-peak-kBps = <16500000>;
					qcom,opp-acd-level = <0xa82a5ffd>;
					opp-supported-hw = <0x08>;
				};

				opp-1000000000 {
					opp-hz = /bits/ 64 <1000000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
					opp-peak-kBps = <14398438>;
					qcom,opp-acd-level = <0xa82b5ffd>;
					opp-supported-hw = <0x0f>;
				};

				opp-925000000 {
					opp-hz = /bits/ 64 <925000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
					opp-peak-kBps = <14398438>;
					qcom,opp-acd-level = <0xa82b5ffd>;
					opp-supported-hw = <0x0f>;
				};

				opp-800000000 {
					opp-hz = /bits/ 64 <800000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
					opp-peak-kBps = <12449219>;
					qcom,opp-acd-level = <0xa82c5ffd>;
					opp-supported-hw = <0x0f>;
				};

				opp-744000000 {
					opp-hz = /bits/ 64 <744000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
					opp-peak-kBps = <10687500>;
					qcom,opp-acd-level = <0x882e5ffd>;
					opp-supported-hw = <0x0f>;
				};

				opp-687000000-0 {
					opp-hz = /bits/ 64 <687000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
					opp-peak-kBps = <8171875>;
					qcom,opp-acd-level = <0x882e5ffd>;
					opp-supported-hw = <0x0f>;
				};

				/* Only applicable for SKUs which has 687Mhz as Fmax */
				opp-687000000-1 {
					opp-hz = /bits/ 64 <687000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
					opp-peak-kBps = <16500000>;
					qcom,opp-acd-level = <0x882e5ffd>;
					opp-supported-hw = <0x10>;
				};

				opp-550000000 {
					opp-hz = /bits/ 64 <550000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
					opp-peak-kBps = <6074219>;
					qcom,opp-acd-level = <0xc0285ffd>;
					opp-supported-hw = <0x1f>;
				};

				opp-390000000 {
					opp-hz = /bits/ 64 <390000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
					opp-peak-kBps = <3000000>;
					qcom,opp-acd-level = <0xc0285ffd>;
					opp-supported-hw = <0x1f>;
				};

				opp-300000000 {
					opp-hz = /bits/ 64 <300000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
					opp-peak-kBps = <2136719>;
					qcom,opp-acd-level = <0xc02b5ffd>;
					opp-supported-hw = <0x1f>;
				};
			};
		};

		gmu: gmu@3d6a000 {
			compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu";
			reg = <0x0 0x03d6a000 0x0 0x35000>,
			      <0x0 0x03d50000 0x0 0x10000>,
			      <0x0 0x0b280000 0x0 0x10000>;
			reg-names = "gmu", "rscc", "gmu_pdc";

			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hfi", "gmu";

			clocks = <&gpucc GPU_CC_AHB_CLK>,
				 <&gpucc GPU_CC_CX_GMU_CLK>,
				 <&gpucc GPU_CC_CXO_CLK>,
				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
				 <&gpucc GPU_CC_DEMET_CLK>;
			clock-names = "ahb",
				      "gmu",
				      "cxo",
				      "axi",
				      "memnoc",
				      "hub",
				      "demet";

			power-domains = <&gpucc GPU_CX_GDSC>,
					<&gpucc GPU_GX_GDSC>;
			power-domain-names = "cx",
					     "gx";

			iommus = <&adreno_smmu 5 0x0>;

			qcom,qmp = <&aoss_qmp>;

			operating-points-v2 = <&gmu_opp_table>;

			gmu_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-550000000 {
					opp-hz = /bits/ 64 <550000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
				};

				opp-220000000 {
					opp-hz = /bits/ 64 <220000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
				};
			};
		};

		gpucc: clock-controller@3d90000 {
			compatible = "qcom,x1e80100-gpucc";
			reg = <0 0x03d90000 0 0xa000>;
			clocks = <&bi_tcxo_div2>,
				 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
				 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		adreno_smmu: iommu@3da0000 {
			compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu",
				     "qcom,smmu-500", "arm,mmu-500";
			reg = <0x0 0x03da0000 0x0 0x40000>;
			#iommu-cells = <2>;
			#global-interrupts = <1>;
			interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
				 <&gpucc GPU_CC_AHB_CLK>;
			clock-names = "hlos",
				      "bus",
				      "iface",
				      "ahb";
			power-domains = <&gpucc GPU_CX_GDSC>;
			dma-coherent;
		};

		gem_noc: interconnect@26400000 {
			compatible = "qcom,x1e80100-gem-noc";
			reg = <0 0x26400000 0 0x311200>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		nsp_noc: interconnect@320c0000 {
			compatible = "qcom,x1e80100-nsp-noc";
			reg = <0 0x320c0000 0 0xe080>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		remoteproc_adsp: remoteproc@6800000 {
			compatible = "qcom,x1e80100-adsp-pas";
			reg = <0x0 0x06800000 0x0 0x10000>;

			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog",
					  "fatal",
					  "ready",
					  "handover",
					  "stop-ack";

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";

			power-domains = <&rpmhpd RPMHPD_LCX>,
					<&rpmhpd RPMHPD_LMX>;
			power-domain-names = "lcx",
					     "lmx";

			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;

			memory-region = <&adspslpi_mem>,
					<&q6_adsp_dtb_mem>;

			qcom,qmp = <&aoss_qmp>;

			qcom,smem-states = <&smp2p_adsp_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink-edge {
				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
							     IPCC_MPROC_SIGNAL_GLINK_QMP
							     IRQ_TYPE_EDGE_RISING>;
				mboxes = <&ipcc IPCC_CLIENT_LPASS
						IPCC_MPROC_SIGNAL_GLINK_QMP>;

				label = "lpass";
				qcom,remote-pid = <2>;

				fastrpc {
					compatible = "qcom,fastrpc";
					qcom,glink-channels = "fastrpcglink-apps-dsp";
					label = "adsp";
					qcom,non-secure-domain;
					#address-cells = <1>;
					#size-cells = <0>;

					compute-cb@3 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <3>;
						iommus = <&apps_smmu 0x1003 0x80>,
							 <&apps_smmu 0x1063 0x0>;
						dma-coherent;
					};

					compute-cb@4 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <4>;
						iommus = <&apps_smmu 0x1004 0x80>,
							 <&apps_smmu 0x1064 0x0>;
						dma-coherent;
					};

					compute-cb@5 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <5>;
						iommus = <&apps_smmu 0x1005 0x80>,
							 <&apps_smmu 0x1065 0x0>;
						dma-coherent;
					};

					compute-cb@6 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <6>;
						iommus = <&apps_smmu 0x1006 0x80>,
							 <&apps_smmu 0x1066 0x0>;
						dma-coherent;
					};

					compute-cb@7 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <7>;
						iommus = <&apps_smmu 0x1007 0x80>,
							 <&apps_smmu 0x1067 0x0>;
						dma-coherent;
					};
				};

				gpr {
					compatible = "qcom,gpr";
					qcom,glink-channels = "adsp_apps";
					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
					qcom,intents = <512 20>;
					#address-cells = <1>;
					#size-cells = <0>;

					q6apm: service@1 {
						compatible = "qcom,q6apm";
						reg = <GPR_APM_MODULE_IID>;
						#sound-dai-cells = <0>;
						qcom,protection-domain = "avs/audio",
									 "msm/adsp/audio_pd";

						q6apmbedai: bedais {
							compatible = "qcom,q6apm-lpass-dais";
							#sound-dai-cells = <1>;
						};

						q6apmdai: dais {
							compatible = "qcom,q6apm-dais";
							iommus = <&apps_smmu 0x1001 0x80>,
								 <&apps_smmu 0x1061 0x0>;
						};
					};

					q6prm: service@2 {
						compatible = "qcom,q6prm";
						reg = <GPR_PRM_MODULE_IID>;
						qcom,protection-domain = "avs/audio",
									 "msm/adsp/audio_pd";

						q6prmcc: clock-controller {
							compatible = "qcom,q6prm-lpass-clocks";
							#clock-cells = <2>;
						};
					};
				};
			};
		};

		lpass_wsa2macro: codec@6aa0000 {
			compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
			reg = <0 0x06aa0000 0 0x1000>;
			clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&lpass_vamacro>;
			clock-names = "mclk",
				      "macro",
				      "dcodec",
				      "fsgen";

			#clock-cells = <0>;
			clock-output-names = "wsa2-mclk";
			#sound-dai-cells = <1>;
			sound-name-prefix = "WSA2";
		};

		swr3: soundwire@6ab0000 {
			compatible = "qcom,soundwire-v2.0.0";
			reg = <0 0x06ab0000 0 0x10000>;
			clocks = <&lpass_wsa2macro>;
			clock-names = "iface";
			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
			label = "WSA2";

			pinctrl-0 = <&wsa2_swr_active>;
			pinctrl-names = "default";
			resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>;
			reset-names = "swr_audio_cgcr";

			qcom,din-ports = <4>;
			qcom,dout-ports = <9>;

			qcom,ports-sinterval =		/bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
			qcom,ports-offset1 =		/bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
			qcom,ports-offset2 =		/bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
			qcom,ports-block-pack-mode =	/bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-lane-control =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			#address-cells = <2>;
			#size-cells = <0>;
			#sound-dai-cells = <1>;
			status = "disabled";
		};

		lpass_rxmacro: codec@6ac0000 {
			compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
			reg = <0 0x06ac0000 0 0x1000>;
			clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&lpass_vamacro>;
			clock-names = "mclk",
				      "macro",
				      "dcodec",
				      "fsgen";

			#clock-cells = <0>;
			clock-output-names = "mclk";
			#sound-dai-cells = <1>;
		};

		swr1: soundwire@6ad0000 {
			compatible = "qcom,soundwire-v2.0.0";
			reg = <0 0x06ad0000 0 0x10000>;
			clocks = <&lpass_rxmacro>;
			clock-names = "iface";
			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
			label = "RX";

			pinctrl-0 = <&rx_swr_active>;
			pinctrl-names = "default";

			resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
			reset-names = "swr_audio_cgcr";
			qcom,din-ports = <1>;
			qcom,dout-ports = <11>;

			qcom,ports-sinterval =		/bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-offset1 =		/bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-offset2 =		/bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-hstart =		/bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-hstop =		/bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-word-length =	/bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-lane-control =	/bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			#address-cells = <2>;
			#size-cells = <0>;
			#sound-dai-cells = <1>;
			status = "disabled";
		};

		lpass_txmacro: codec@6ae0000 {
			compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
			reg = <0 0x06ae0000 0 0x1000>;
			clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&lpass_vamacro>;
			clock-names = "mclk",
				      "macro",
				      "dcodec",
				      "fsgen";

			#clock-cells = <0>;
			clock-output-names = "mclk";
			#sound-dai-cells = <1>;
		};

		lpass_wsamacro: codec@6b00000 {
			compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
			reg = <0 0x06b00000 0 0x1000>;
			clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&lpass_vamacro>;
			clock-names = "mclk",
				      "macro",
				      "dcodec",
				      "fsgen";

			#clock-cells = <0>;
			clock-output-names = "mclk";
			#sound-dai-cells = <1>;
			sound-name-prefix = "WSA";
		};

		swr0: soundwire@6b10000 {
			compatible = "qcom,soundwire-v2.0.0";
			reg = <0 0x06b10000 0 0x10000>;
			clocks = <&lpass_wsamacro>;
			clock-names = "iface";
			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
			label = "WSA";

			pinctrl-0 = <&wsa_swr_active>;
			pinctrl-names = "default";
			resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
			reset-names = "swr_audio_cgcr";

			qcom,din-ports = <4>;
			qcom,dout-ports = <9>;

			qcom,ports-sinterval =		/bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
			qcom,ports-offset1 =		/bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
			qcom,ports-offset2 =		/bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
			qcom,ports-block-pack-mode =	/bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-lane-control =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			#address-cells = <2>;
			#size-cells = <0>;
			#sound-dai-cells = <1>;
			status = "disabled";
		};

		lpass_audiocc: clock-controller@6b6c000 {
			compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc";
			reg = <0 0x06b6c000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		swr2: soundwire@6d30000 {
			compatible = "qcom,soundwire-v2.0.0";
			reg = <0 0x06d30000 0 0x10000>;
			clocks = <&lpass_txmacro>;
			clock-names = "iface";
			interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "core", "wakeup";
			label = "TX";
			resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>;
			reset-names = "swr_audio_cgcr";

			pinctrl-0 = <&tx_swr_active>;
			pinctrl-names = "default";

			qcom,din-ports = <4>;
			qcom,dout-ports = <1>;

			qcom,ports-sinterval-low =	/bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
			qcom,ports-offset1 =		/bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
			qcom,ports-offset2 =		/bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-lane-control =	/bits/ 8 <0xff 0x00 0x00 0x01 0xff>;

			#address-cells = <2>;
			#size-cells = <0>;
			#sound-dai-cells = <1>;
			status = "disabled";
		};

		lpass_vamacro: codec@6d44000 {
			compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
			reg = <0 0x06d44000 0 0x1000>;
			clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
			clock-names = "mclk",
				      "macro",
				      "dcodec";

			#clock-cells = <0>;
			clock-output-names = "fsgen";
			#sound-dai-cells = <1>;
		};

		lpass_tlmm: pinctrl@6e80000 {
			compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl";
			reg = <0 0x06e80000 0 0x20000>,
			      <0 0x07250000 0 0x10000>;

			clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
			clock-names = "core", "audio";

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&lpass_tlmm 0 0 23>;

			tx_swr_active: tx-swr-active-state {
				clk-pins {
					pins = "gpio0";
					function = "swr_tx_clk";
					drive-strength = <2>;
					slew-rate = <1>;
					bias-disable;
				};

				data-pins {
					pins = "gpio1", "gpio2";
					function = "swr_tx_data";
					drive-strength = <2>;
					slew-rate = <1>;
					bias-bus-hold;
				};
			};

			rx_swr_active: rx-swr-active-state {
				clk-pins {
					pins = "gpio3";
					function = "swr_rx_clk";
					drive-strength = <2>;
					slew-rate = <1>;
					bias-disable;
				};

				data-pins {
					pins = "gpio4", "gpio5";
					function = "swr_rx_data";
					drive-strength = <2>;
					slew-rate = <1>;
					bias-bus-hold;
				};
			};

			dmic01_default: dmic01-default-state {
				clk-pins {
					pins = "gpio6";
					function = "dmic1_clk";
					drive-strength = <8>;
					output-high;
				};

				data-pins {
					pins = "gpio7";
					function = "dmic1_data";
					drive-strength = <8>;
					input-enable;
				};
			};

			dmic23_default: dmic23-default-state {
				clk-pins {
					pins = "gpio8";
					function = "dmic2_clk";
					drive-strength = <8>;
					output-high;
				};

				data-pins {
					pins = "gpio9";
					function = "dmic2_data";
					drive-strength = <8>;
					input-enable;
				};
			};

			wsa_swr_active: wsa-swr-active-state {
				clk-pins {
					pins = "gpio10";
					function = "wsa_swr_clk";
					drive-strength = <2>;
					slew-rate = <1>;
					bias-disable;
				};

				data-pins {
					pins = "gpio11";
					function = "wsa_swr_data";
					drive-strength = <2>;
					slew-rate = <1>;
					bias-bus-hold;
				};
			};

			wsa2_swr_active: wsa2-swr-active-state {
				clk-pins {
					pins = "gpio15";
					function = "wsa2_swr_clk";
					drive-strength = <2>;
					slew-rate = <1>;
					bias-disable;
				};

				data-pins {
					pins = "gpio16";
					function = "wsa2_swr_data";
					drive-strength = <2>;
					slew-rate = <1>;
					bias-bus-hold;
				};
			};
		};

		lpasscc: clock-controller@6ea0000 {
			compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc";
			reg = <0 0x06ea0000 0 0x12000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		lpass_ag_noc: interconnect@7e40000 {
			compatible = "qcom,x1e80100-lpass-ag-noc";
			reg = <0 0x07e40000 0 0xe080>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		lpass_lpiaon_noc: interconnect@7400000 {
			compatible = "qcom,x1e80100-lpass-lpiaon-noc";
			reg = <0 0x07400000 0 0x19080>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		lpass_lpicx_noc: interconnect@7430000 {
			compatible = "qcom,x1e80100-lpass-lpicx-noc";
			reg = <0 0x07430000 0 0x3a200>;

			qcom,bcm-voters = <&apps_bcm_voter>;

			#interconnect-cells = <2>;
		};

		sdhc_2: mmc@8804000 {
			compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
			reg = <0 0x08804000 0 0x1000>;

			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
				 <&gcc GCC_SDCC2_APPS_CLK>,
				 <&bi_tcxo_div2>;
			clock-names = "iface", "core", "xo";
			iommus = <&apps_smmu 0x520 0>;
			qcom,dll-config = <0x0007642c>;
			qcom,ddr-config = <0x80040868>;
			power-domains = <&rpmhpd RPMHPD_CX>;
			operating-points-v2 = <&sdhc2_opp_table>;

			interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "sdhc-ddr", "cpu-sdhc";
			bus-width = <4>;
			dma-coherent;

			status = "disabled";

			sdhc2_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-19200000 {
					opp-hz = /bits/ 64 <19200000>;
					required-opps = <&rpmhpd_opp_min_svs>;
				};

				opp-50000000 {
					opp-hz = /bits/ 64 <50000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
				};

				opp-100000000 {
					opp-hz = /bits/ 64 <100000000>;
					required-opps = <&rpmhpd_opp_svs>;
				};

				opp-202000000 {
					opp-hz = /bits/ 64 <202000000>;
					required-opps = <&rpmhpd_opp_svs_l1>;
				};
			};
		};

		sdhc_4: mmc@8844000 {
			compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
			reg = <0 0x08844000 0 0x1000>;

			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC4_AHB_CLK>,
				 <&gcc GCC_SDCC4_APPS_CLK>,
				 <&bi_tcxo_div2>;
			clock-names = "iface", "core", "xo";
			iommus = <&apps_smmu 0x160 0>;
			qcom,dll-config = <0x0007642c>;
			qcom,ddr-config = <0x80040868>;
			power-domains = <&rpmhpd RPMHPD_CX>;
			operating-points-v2 = <&sdhc4_opp_table>;

			interconnects = <&aggre2_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "sdhc-ddr", "cpu-sdhc";
			bus-width = <4>;
			dma-coherent;

			status = "disabled";

			sdhc4_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-19200000 {
					opp-hz = /bits/ 64 <19200000>;
					required-opps = <&rpmhpd_opp_min_svs>;
				};

				opp-50000000 {
					opp-hz = /bits/ 64 <50000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
				};

				opp-100000000 {
					opp-hz = /bits/ 64 <100000000>;
					required-opps = <&rpmhpd_opp_svs>;
				};

				opp-202000000 {
					opp-hz = /bits/ 64 <202000000>;
					required-opps = <&rpmhpd_opp_svs_l1>;
				};
			};
		};

		usb_2_hsphy: phy@88e0000 {
			compatible = "qcom,x1e80100-snps-eusb2-phy",
				     "qcom,sm8550-snps-eusb2-phy";
			reg = <0 0x088e0000 0 0x154>;
			#phy-cells = <0>;

			clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
			clock-names = "ref";

			resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>;

			status = "disabled";
		};

		usb_mp_hsphy0: phy@88e1000 {
			compatible = "qcom,x1e80100-snps-eusb2-phy",
				     "qcom,sm8550-snps-eusb2-phy";
			reg = <0 0x088e1000 0 0x154>;
			#phy-cells = <0>;

			clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>;
			clock-names = "ref";

			resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;

			status = "disabled";
		};

		usb_mp_hsphy1: phy@88e2000 {
			compatible = "qcom,x1e80100-snps-eusb2-phy",
				     "qcom,sm8550-snps-eusb2-phy";
			reg = <0 0x088e2000 0 0x154>;
			#phy-cells = <0>;

			clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>;
			clock-names = "ref";

			resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;

			status = "disabled";
		};

		usb_mp_qmpphy0: phy@88e3000 {
			compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
			reg = <0 0x088e3000 0 0x2000>;

			clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
				 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
			clock-names = "aux",
				      "ref",
				      "com_aux",
				      "pipe";

			resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
				 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
			reset-names = "phy",
				      "phy_phy";

			power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;

			#clock-cells = <0>;
			clock-output-names = "usb_mp_phy0_pipe_clk";

			#phy-cells = <0>;

			status = "disabled";
		};

		usb_mp_qmpphy1: phy@88e5000 {
			compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
			reg = <0 0x088e5000 0 0x2000>;

			clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
				 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
			clock-names = "aux",
				      "ref",
				      "com_aux",
				      "pipe";

			resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
				 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
			reset-names = "phy",
				      "phy_phy";

			power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;

			#clock-cells = <0>;
			clock-output-names = "usb_mp_phy1_pipe_clk";

			#phy-cells = <0>;

			status = "disabled";
		};

		usb_1_ss2: usb@a000000 {
			compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3";
			reg = <0 0x0a000000 0 0xfc100>;

			clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>,
				 <&gcc GCC_USB30_TERT_MASTER_CLK>,
				 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
				 <&gcc GCC_USB30_TERT_SLEEP_CLK>,
				 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
				 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
				 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
			clock-names = "cfg_noc",
				      "core",
				      "iface",
				      "sleep",
				      "mock_utmi",
				      "noc_aggr",
				      "noc_aggr_north",
				      "noc_aggr_south",
				      "noc_sys";

			assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_TERT_MASTER_CLK>;
			assigned-clock-rates = <19200000>,
					       <200000000>;

			interrupts-extended = <&intc GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
					      <&pdc 58 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 57 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 10 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "dwc_usb3",
					  "pwr_event",
					  "dp_hs_phy_irq",
					  "dm_hs_phy_irq",
					  "ss_phy_irq";

			power-domains = <&gcc GCC_USB30_TERT_GDSC>;
			required-opps = <&rpmhpd_opp_nom>;

			resets = <&gcc GCC_USB30_TERT_BCR>;

			interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "usb-ddr",
					     "apps-usb";

			wakeup-source;

			iommus = <&apps_smmu 0x14a0 0x0>;

			phys = <&usb_1_ss2_hsphy>,
			       <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>;
			phy-names = "usb2-phy",
				    "usb3-phy";

			snps,dis_u2_susphy_quirk;
			snps,dis_enblslpm_quirk;
			snps,usb3_lpm_capable;
			snps,dis-u1-entry-quirk;
			snps,dis-u2-entry-quirk;

			dma-coherent;

			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					usb_1_ss2_dwc3_hs: endpoint {
					};
				};

				port@1 {
					reg = <1>;

					usb_1_ss2_dwc3_ss: endpoint {
						remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
					};
				};
			};
		};

		usb_2: usb@a200000 {
			compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3";
			reg = <0 0x0a200000 0 0xfc100>;

			clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
				 <&gcc GCC_USB20_MASTER_CLK>,
				 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
				 <&gcc GCC_USB20_SLEEP_CLK>,
				 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
				 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
				 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
			clock-names = "cfg_noc",
				      "core",
				      "iface",
				      "sleep",
				      "mock_utmi",
				      "noc_aggr",
				      "noc_aggr_north",
				      "noc_aggr_south",
				      "noc_sys";

			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB20_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <200000000>;

			interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
					      <&pdc 50 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 49 IRQ_TYPE_EDGE_BOTH>;
			interrupt-names = "dwc_usb3",
					  "pwr_event",
					  "dp_hs_phy_irq",
					  "dm_hs_phy_irq";

			power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
			required-opps = <&rpmhpd_opp_nom>;

			resets = <&gcc GCC_USB20_PRIM_BCR>;

			interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "usb-ddr",
					     "apps-usb";

			qcom,select-utmi-as-pipe-clk;
			wakeup-source;

			iommus = <&apps_smmu 0x14e0 0x0>;
			phys = <&usb_2_hsphy>;
			phy-names = "usb2-phy";
			maximum-speed = "high-speed";
			snps,dis-u1-entry-quirk;
			snps,dis-u2-entry-quirk;

			dma-coherent;

			status = "disabled";

			port {
				usb_2_dwc3_hs: endpoint {
				};
			};
		};

		usb_mp: usb@a400000 {
			compatible = "qcom,x1e80100-dwc3-mp", "qcom,snps-dwc3";
			reg = <0 0x0a400000 0 0xfc100>;

			clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
				 <&gcc GCC_USB30_MP_MASTER_CLK>,
				 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
				 <&gcc GCC_USB30_MP_SLEEP_CLK>,
				 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
				 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
				 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
			clock-names = "cfg_noc",
				      "core",
				      "iface",
				      "sleep",
				      "mock_utmi",
				      "noc_aggr",
				      "noc_aggr_north",
				      "noc_aggr_south",
				      "noc_sys";

			assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_MP_MASTER_CLK>;
			assigned-clock-rates = <19200000>,
					       <200000000>;

			interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
					      <&pdc 52 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 51 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 54 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 53 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 55 IRQ_TYPE_LEVEL_HIGH>,
					      <&pdc 56 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "dwc_usb3",
					  "pwr_event_1", "pwr_event_2",
					  "hs_phy_1",	 "hs_phy_2",
					  "dp_hs_phy_1", "dm_hs_phy_1",
					  "dp_hs_phy_2", "dm_hs_phy_2",
					  "ss_phy_1",	 "ss_phy_2";

			power-domains = <&gcc GCC_USB30_MP_GDSC>;
			required-opps = <&rpmhpd_opp_nom>;

			resets = <&gcc GCC_USB30_MP_BCR>;

			interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "usb-ddr",
					     "apps-usb";

			wakeup-source;

			iommus = <&apps_smmu 0x1400 0x0>;

			phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>,
			       <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>;
			phy-names = "usb2-0", "usb3-0",
				    "usb2-1", "usb3-1";
			dr_mode = "host";

			snps,dis_u2_susphy_quirk;
			snps,dis_enblslpm_quirk;
			snps,usb3_lpm_capable;
			snps,dis-u1-entry-quirk;
			snps,dis-u2-entry-quirk;

			dma-coherent;

			status = "disabled";
		};

		usb_1_ss0: usb@a600000 {
			compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3";
			reg = <0 0x0a600000 0 0xfc100>;

			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
				 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>,
				 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>,
				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
			clock-names = "cfg_noc",
				      "core",
				      "iface",
				      "sleep",
				      "mock_utmi",
				      "noc_aggr",
				      "noc_aggr_north",
				      "noc_aggr_south",
				      "noc_sys";

			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
			assigned-clock-rates = <19200000>,
					       <200000000>;

			interrupts-extended = <&intc GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
					      <&pdc 61 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "dwc_usb3",
					  "pwr_event",
					  "dp_hs_phy_irq",
					  "dm_hs_phy_irq",
					  "ss_phy_irq";

			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
			required-opps = <&rpmhpd_opp_nom>;

			resets = <&gcc GCC_USB30_PRIM_BCR>;

			wakeup-source;

			iommus = <&apps_smmu 0x1420 0x0>;

			phys = <&usb_1_ss0_hsphy>,
			       <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>;
			phy-names = "usb2-phy",
				    "usb3-phy";

			snps,dis_u2_susphy_quirk;
			snps,dis_enblslpm_quirk;
			snps,usb3_lpm_capable;
			snps,dis-u1-entry-quirk;
			snps,dis-u2-entry-quirk;

			dma-coherent;

			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					usb_1_ss0_dwc3_hs: endpoint {
					};
				};

				port@1 {
					reg = <1>;

					usb_1_ss0_dwc3_ss: endpoint {
						remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
					};
				};
			};
		};

		usb_1_ss1: usb@a800000 {
			compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3";
			reg = <0 0x0a800000 0 0xfc100>;

			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
				 <&gcc GCC_USB30_SEC_MASTER_CLK>,
				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
				 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
				 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
				 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
			clock-names = "cfg_noc",
				      "core",
				      "iface",
				      "sleep",
				      "mock_utmi",
				      "noc_aggr",
				      "noc_aggr_north",
				      "noc_aggr_south",
				      "noc_sys";

			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_SEC_MASTER_CLK>;
			assigned-clock-rates = <19200000>,
					       <200000000>;

			interrupts-extended = <&intc GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
					      <&pdc 60 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 47 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "dwc_usb3",
					  "pwr_event",
					  "dp_hs_phy_irq",
					  "dm_hs_phy_irq",
					  "ss_phy_irq";

			power-domains = <&gcc GCC_USB30_SEC_GDSC>;
			required-opps = <&rpmhpd_opp_nom>;

			resets = <&gcc GCC_USB30_SEC_BCR>;

			interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "usb-ddr",
					     "apps-usb";

			wakeup-source;

			iommus = <&apps_smmu 0x1460 0x0>;

			phys = <&usb_1_ss1_hsphy>,
			       <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>;
			phy-names = "usb2-phy",
				    "usb3-phy";

			snps,dis_u2_susphy_quirk;
			snps,dis_enblslpm_quirk;
			snps,usb3_lpm_capable;
			snps,dis-u1-entry-quirk;
			snps,dis-u2-entry-quirk;

			dma-coherent;

			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					usb_1_ss1_dwc3_hs: endpoint {
					};
				};

				port@1 {
					reg = <1>;

					usb_1_ss1_dwc3_ss: endpoint {
						remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
					};
				};
			};
		};

		iris: video-codec@aa00000 {
			compatible = "qcom,x1e80100-iris", "qcom,sm8550-iris";

			reg = <0 0x0aa00000 0 0xf0000>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;

			power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
					<&videocc VIDEO_CC_MVS0_GDSC>,
					<&rpmhpd RPMHPD_MXC>,
					<&rpmhpd RPMHPD_MMCX>;
			power-domain-names = "venus",
					     "vcodec0",
					     "mxc",
					     "mmcx";
			operating-points-v2 = <&iris_opp_table>;

			clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
				 <&videocc VIDEO_CC_MVS0C_CLK>,
				 <&videocc VIDEO_CC_MVS0_CLK>;
			clock-names = "iface",
				      "core",
				      "vcodec0_core";

			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
			interconnect-names = "cpu-cfg",
					     "video-mem";

			memory-region = <&video_mem>;

			resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
			reset-names = "bus";

			iommus = <&apps_smmu 0x1940 0>,
				 <&apps_smmu 0x1947 0>;
			dma-coherent;

			/*
			 * IRIS firmware is signed by vendors, only
			 * enable on boards where the proper signed firmware
			 * is available.
			 */
			status = "disabled";

			iris_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-192000000 {
					opp-hz = /bits/ 64 <192000000>;
					required-opps = <&rpmhpd_opp_low_svs_d1>,
							<&rpmhpd_opp_low_svs_d1>;
				};

				opp-240000000 {
					opp-hz = /bits/ 64 <240000000>;
					required-opps = <&rpmhpd_opp_svs>,
							<&rpmhpd_opp_low_svs>;
				};

				opp-338000000 {
					opp-hz = /bits/ 64 <338000000>;
					required-opps = <&rpmhpd_opp_svs>,
							<&rpmhpd_opp_svs>;
				};

				opp-366000000 {
					opp-hz = /bits/ 64 <366000000>;
					required-opps = <&rpmhpd_opp_svs>,
							<&rpmhpd_opp_svs_l1>;
				};

				opp-444000000 {
					opp-hz = /bits/ 64 <444000000>;
					required-opps = <&rpmhpd_opp_svs_l1>,
							<&rpmhpd_opp_nom>;
				};

				opp-481000000 {
					opp-hz = /bits/ 64 <481000000>;
					required-opps = <&rpmhpd_opp_svs_l1>,
							<&rpmhpd_opp_turbo>;
				};
			};
		};

		videocc: clock-controller@aaf0000 {
			compatible = "qcom,x1e80100-videocc";
			reg = <0 0x0aaf0000 0 0x10000>;
			clocks = <&bi_tcxo_div2>,
				 <&gcc GCC_VIDEO_AHB_CLK>;
			power-domains = <&rpmhpd RPMHPD_MMCX>,
					<&rpmhpd RPMHPD_MXC>;
			required-opps = <&rpmhpd_opp_low_svs>,
					<&rpmhpd_opp_low_svs>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		mdss: display-subsystem@ae00000 {
			compatible = "qcom,x1e80100-mdss";
			reg = <0 0x0ae00000 0 0x1000>;
			reg-names = "mdss";

			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
				 <&gcc GCC_DISP_HF_AXI_CLK>,
				 <&dispcc DISP_CC_MDSS_MDP_CLK>;

			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;

			interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
					<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "mdp0-mem",
					     "mdp1-mem",
					     "cpu-cfg";

			power-domains = <&dispcc MDSS_GDSC>;

			iommus = <&apps_smmu 0x1c00 0x2>;

			interrupt-controller;
			#interrupt-cells = <1>;

			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			status = "disabled";

			mdss_mdp: display-controller@ae01000 {
				compatible = "qcom,x1e80100-dpu";
				reg = <0 0x0ae01000 0 0x8f000>,
				      <0 0x0aeb0000 0 0x2008>;
				reg-names = "mdp",
					    "vbif";

				interrupts-extended = <&mdss 0>;

				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
					 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
					 <&dispcc DISP_CC_MDSS_MDP_CLK>,
					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
				clock-names = "nrt_bus",
					      "iface",
					      "lut",
					      "core",
					      "vsync";

				operating-points-v2 = <&mdp_opp_table>;

				power-domains = <&rpmhpd RPMHPD_MMCX>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;

						mdss_intf0_out: endpoint {
							remote-endpoint = <&mdss_dp0_in>;
						};
					};

					port@4 {
						reg = <4>;

						mdss_intf4_out: endpoint {
							remote-endpoint = <&mdss_dp1_in>;
						};
					};

					port@5 {
						reg = <5>;

						mdss_intf5_out: endpoint {
							remote-endpoint = <&mdss_dp3_in>;
						};
					};

					port@6 {
						reg = <6>;

						mdss_intf6_out: endpoint {
							remote-endpoint = <&mdss_dp2_in>;
						};
					};
				};

				mdp_opp_table: opp-table {
					compatible = "operating-points-v2";

					opp-200000000 {
						opp-hz = /bits/ 64 <200000000>;
						required-opps = <&rpmhpd_opp_low_svs>;
					};

					opp-325000000 {
						opp-hz = /bits/ 64 <325000000>;
						required-opps = <&rpmhpd_opp_svs>;
					};

					opp-375000000 {
						opp-hz = /bits/ 64 <375000000>;
						required-opps = <&rpmhpd_opp_svs_l1>;
					};

					opp-514000000 {
						opp-hz = /bits/ 64 <514000000>;
						required-opps = <&rpmhpd_opp_nom>;
					};

					opp-575000000 {
						opp-hz = /bits/ 64 <575000000>;
						required-opps = <&rpmhpd_opp_nom_l1>;
					};
				};
			};

			mdss_dp0: displayport-controller@ae90000 {
				compatible = "qcom,x1e80100-dp";
				reg = <0 0x0ae90000 0 0x200>,
				      <0 0x0ae90200 0 0x200>,
				      <0 0x0ae90400 0 0xc00>,
				      <0 0x0ae91000 0 0x400>,
				      <0 0x0ae91400 0 0x400>;

				interrupts-extended = <&mdss 12>;

				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
				clock-names = "core_iface",
					      "core_aux",
					      "ctrl_link",
					      "ctrl_link_iface",
					      "stream_pixel",
					      "stream_1_pixel";

				assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
						  <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
						  <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
				assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
							 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
							 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;

				operating-points-v2 = <&mdss_dp0_opp_table>;

				power-domains = <&rpmhpd RPMHPD_MMCX>;

				phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
				phy-names = "dp";

				#sound-dai-cells = <0>;
				sound-name-prefix = "DisplayPort0";

				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;

						mdss_dp0_in: endpoint {
							remote-endpoint = <&mdss_intf0_out>;
						};
					};

					port@1 {
						reg = <1>;

						mdss_dp0_out: endpoint {
							data-lanes = <0 1 2 3>;
							remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>;
						};
					};
				};

				mdss_dp0_opp_table: opp-table {
					compatible = "operating-points-v2";

					opp-270000000 {
						opp-hz = /bits/ 64 <270000000>;
						required-opps = <&rpmhpd_opp_low_svs>;
					};

					opp-540000000 {
						opp-hz = /bits/ 64 <540000000>;
						required-opps = <&rpmhpd_opp_svs>;
					};

					opp-594000000 {
						opp-hz = /bits/ 64 <594000000>;
						required-opps = <&rpmhpd_opp_svs_l1>;
					};

					opp-810000000 {
						opp-hz = /bits/ 64 <810000000>;
						required-opps = <&rpmhpd_opp_nom>;
					};
				};
			};

			mdss_dp1: displayport-controller@ae98000 {
				compatible = "qcom,x1e80100-dp";
				reg = <0 0x0ae98000 0 0x200>,
				      <0 0x0ae98200 0 0x200>,
				      <0 0x0ae98400 0 0xc00>,
				      <0 0x0ae99000 0 0x400>,
				      <0 0x0ae99400 0 0x400>;

				interrupts-extended = <&mdss 13>;

				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
				clock-names = "core_iface",
					      "core_aux",
					      "ctrl_link",
					      "ctrl_link_iface",
					      "stream_pixel",
					      "stream_1_pixel";

				assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
						  <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
						  <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
				assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
							 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
							 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;

				operating-points-v2 = <&mdss_dp0_opp_table>;

				power-domains = <&rpmhpd RPMHPD_MMCX>;

				phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>;
				phy-names = "dp";

				#sound-dai-cells = <0>;
				sound-name-prefix = "DisplayPort1";

				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;

						mdss_dp1_in: endpoint {
							remote-endpoint = <&mdss_intf4_out>;
						};
					};

					port@1 {
						reg = <1>;

						mdss_dp1_out: endpoint {
							data-lanes = <0 1 2 3>;
							remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>;
						};
					};
				};
			};

			mdss_dp2: displayport-controller@ae9a000 {
				compatible = "qcom,x1e80100-dp";
				reg = <0 0x0ae9a000 0 0x200>,
				      <0 0x0ae9a200 0 0x200>,
				      <0 0x0ae9a400 0 0xc00>,
				      <0 0x0ae9b000 0 0x400>,
				      <0 0x0ae9b400 0 0x400>;

				interrupts-extended = <&mdss 14>;

				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
				clock-names = "core_iface",
					      "core_aux",
					      "ctrl_link",
					      "ctrl_link_iface",
					      "stream_pixel",
					      "stream_1_pixel";

				assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
						  <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
						  <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
				assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
							 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
							 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;

				operating-points-v2 = <&mdss_dp0_opp_table>;

				power-domains = <&rpmhpd RPMHPD_MMCX>;

				phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>;
				phy-names = "dp";

				#sound-dai-cells = <0>;
				sound-name-prefix = "DisplayPort2";

				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						mdss_dp2_in: endpoint {
							remote-endpoint = <&mdss_intf6_out>;
						};
					};

					port@1 {
						reg = <1>;

						mdss_dp2_out: endpoint {
							data-lanes = <0 1 2 3>;
							remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>;
						};
					};
				};
			};

			mdss_dp3: displayport-controller@aea0000 {
				compatible = "qcom,x1e80100-dp";
				reg = <0 0x0aea0000 0 0x200>,
				      <0 0x0aea0200 0 0x200>,
				      <0 0x0aea0400 0 0xc00>,
				      <0 0x0aea1000 0 0x400>,
				      <0 0x0aea1400 0 0x400>;

				interrupts-extended = <&mdss 15>;

				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
				clock-names = "core_iface",
					      "core_aux",
					      "ctrl_link",
					      "ctrl_link_iface",
					      "stream_pixel";

				assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
						  <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
				assigned-clock-parents = <&mdss_dp3_phy 0>,
							 <&mdss_dp3_phy 1>;

				operating-points-v2 = <&mdss_dp3_opp_table>;

				power-domains = <&rpmhpd RPMHPD_MMCX>;

				phys = <&mdss_dp3_phy>;
				phy-names = "dp";

				#sound-dai-cells = <0>;
				sound-name-prefix = "DisplayPort3";

				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;

						mdss_dp3_in: endpoint {
							remote-endpoint = <&mdss_intf5_out>;
						};
					};

					port@1 {
						reg = <1>;

						mdss_dp3_out: endpoint {
						};
					};
				};

				mdss_dp3_opp_table: opp-table {
					compatible = "operating-points-v2";

					opp-270000000 {
						opp-hz = /bits/ 64 <270000000>;
						required-opps = <&rpmhpd_opp_low_svs>;
					};

					opp-594000000 {
						opp-hz = /bits/ 64 <594000000>;
						required-opps = <&rpmhpd_opp_svs>;
					};

					opp-810000000 {
						opp-hz = /bits/ 64 <810000000>;
						required-opps = <&rpmhpd_opp_nom>;
					};
				};
			};

		};

		mdss_dp2_phy: phy@aec2a00 {
			compatible = "qcom,x1e80100-dp-phy";
			reg = <0 0x0aec2a00 0 0x19c>,
			      <0 0x0aec2200 0 0xec>,
			      <0 0x0aec2600 0 0xec>,
			      <0 0x0aec2000 0 0x1c8>;

			clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
				 <&dispcc DISP_CC_MDSS_AHB_CLK>,
				 <&tcsr TCSR_EDP_CLKREF_EN>;
			clock-names = "aux",
				      "cfg_ahb",
				      "ref";

			power-domains = <&rpmhpd RPMHPD_MX>;

			#clock-cells = <1>;
			#phy-cells = <0>;

			status = "disabled";
		};

		mdss_dp3_phy: phy@aec5a00 {
			compatible = "qcom,x1e80100-dp-phy";
			reg = <0 0x0aec5a00 0 0x19c>,
			      <0 0x0aec5200 0 0xec>,
			      <0 0x0aec5600 0 0xec>,
			      <0 0x0aec5000 0 0x1c8>;

			clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
				 <&dispcc DISP_CC_MDSS_AHB_CLK>,
				 <&tcsr TCSR_EDP_CLKREF_EN>;
			clock-names = "aux",
				      "cfg_ahb",
				      "ref";

			power-domains = <&rpmhpd RPMHPD_MX>;

			#clock-cells = <1>;
			#phy-cells = <0>;

			status = "disabled";
		};

		dispcc: clock-controller@af00000 {
			compatible = "qcom,x1e80100-dispcc";
			reg = <0 0x0af00000 0 0x20000>;
			clocks = <&bi_tcxo_div2>,
				 <&bi_tcxo_ao_div2>,
				 <&gcc GCC_DISP_AHB_CLK>,
				 <&sleep_clk>,
				 <0>, /* dsi0 */
				 <0>,
				 <0>, /* dsi1 */
				 <0>,
				 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */
				 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
				 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */
				 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
				 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */
				 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
				 <&mdss_dp3_phy 0>, /* dp3 */
				 <&mdss_dp3_phy 1>;
			power-domains = <&rpmhpd RPMHPD_MMCX>;
			required-opps = <&rpmhpd_opp_low_svs>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		pdc: interrupt-controller@b220000 {
			compatible = "qcom,x1e80100-pdc", "qcom,pdc";
			reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;

			qcom,pdc-ranges = <0 480 42>, <42 251 5>,
					  <47 522 52>, <99 609 32>,
					  <131 717 12>, <143 816 19>;
			#interrupt-cells = <2>;
			interrupt-parent = <&intc>;
			interrupt-controller;
		};

		aoss_qmp: power-management@c300000 {
			compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp";
			reg = <0 0x0c300000 0 0x400>;
			interrupt-parent = <&ipcc>;
			interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
						     IRQ_TYPE_EDGE_RISING>;
			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;

			#clock-cells = <0>;
		};

		sram@c3f0000 {
			compatible = "qcom,rpmh-stats";
			reg = <0 0x0c3f0000 0 0x400>;
		};

		spmi: arbiter@c400000 {
			compatible = "qcom,x1e80100-spmi-pmic-arb";
			reg = <0 0x0c400000 0 0x3000>,
			      <0 0x0c500000 0 0x400000>,
			      <0 0x0c440000 0 0x80000>;
			reg-names = "core", "chnls", "obsrvr";

			qcom,ee = <0>;
			qcom,channel = <0>;

			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			spmi_bus0: spmi@c42d000 {
				reg = <0 0x0c42d000 0 0x4000>,
				      <0 0x0c4c0000 0 0x10000>;
				reg-names = "cnfg", "intr";

				interrupt-names = "periph_irq";
				interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-controller;
				#interrupt-cells = <4>;

				#address-cells = <2>;
				#size-cells = <0>;
			};

			spmi_bus1: spmi@c432000 {
				reg = <0 0x0c432000 0 0x4000>,
				      <0 0x0c4d0000 0 0x10000>;
				reg-names = "cnfg", "intr";

				interrupt-names = "periph_irq";
				interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-controller;
				#interrupt-cells = <4>;

				#address-cells = <2>;
				#size-cells = <0>;
			};
		};

		tlmm: pinctrl@f100000 {
			compatible = "qcom,x1e80100-tlmm";
			reg = <0 0x0f100000 0 0xf00000>;

			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;

			gpio-ranges = <&tlmm 0 0 239>;
			wakeup-parent = <&pdc>;

			edp0_hpd_default: edp0-hpd-default-state {
				pins = "gpio119";
				function = "edp0_hot";
				bias-disable;
			};

			qup_i2c0_data_clk: qup-i2c0-data-clk-state {
				/* SDA, SCL */
				pins = "gpio0", "gpio1";
				function = "qup0_se0";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c1_data_clk: qup-i2c1-data-clk-state {
				/* SDA, SCL */
				pins = "gpio4", "gpio5";
				function = "qup0_se1";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c2_data_clk: qup-i2c2-data-clk-state {
				/* SDA, SCL */
				pins = "gpio8", "gpio9";
				function = "qup0_se2";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c3_data_clk: qup-i2c3-data-clk-state {
				/* SDA, SCL */
				pins = "gpio12", "gpio13";
				function = "qup0_se3";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c4_data_clk: qup-i2c4-data-clk-state {
				/* SDA, SCL */
				pins = "gpio16", "gpio17";
				function = "qup0_se4";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c5_data_clk: qup-i2c5-data-clk-state {
				/* SDA, SCL */
				pins = "gpio20", "gpio21";
				function = "qup0_se5";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c6_data_clk: qup-i2c6-data-clk-state {
				/* SDA, SCL */
				pins = "gpio24", "gpio25";
				function = "qup0_se6";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c7_data_clk: qup-i2c7-data-clk-state {
				/* SDA, SCL */
				pins = "gpio14", "gpio15";
				function = "qup0_se7";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c8_data_clk: qup-i2c8-data-clk-state {
				/* SDA, SCL */
				pins = "gpio32", "gpio33";
				function = "qup1_se0";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c9_data_clk: qup-i2c9-data-clk-state {
				/* SDA, SCL */
				pins = "gpio36", "gpio37";
				function = "qup1_se1";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c10_data_clk: qup-i2c10-data-clk-state {
				/* SDA, SCL */
				pins = "gpio40", "gpio41";
				function = "qup1_se2";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c11_data_clk: qup-i2c11-data-clk-state {
				/* SDA, SCL */
				pins = "gpio44", "gpio45";
				function = "qup1_se3";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c12_data_clk: qup-i2c12-data-clk-state {
				/* SDA, SCL */
				pins = "gpio48", "gpio49";
				function = "qup1_se4";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c13_data_clk: qup-i2c13-data-clk-state {
				/* SDA, SCL */
				pins = "gpio52", "gpio53";
				function = "qup1_se5";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c14_data_clk: qup-i2c14-data-clk-state {
				/* SDA, SCL */
				pins = "gpio56", "gpio57";
				function = "qup1_se6";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c15_data_clk: qup-i2c15-data-clk-state {
				/* SDA, SCL */
				pins = "gpio54", "gpio55";
				function = "qup1_se7";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c16_data_clk: qup-i2c16-data-clk-state {
				/* SDA, SCL */
				pins = "gpio64", "gpio65";
				function = "qup2_se0";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c17_data_clk: qup-i2c17-data-clk-state {
				/* SDA, SCL */
				pins = "gpio68", "gpio69";
				function = "qup2_se1";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c18_data_clk: qup-i2c18-data-clk-state {
				/* SDA, SCL */
				pins = "gpio72", "gpio73";
				function = "qup2_se2";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c19_data_clk: qup-i2c19-data-clk-state {
				/* SDA, SCL */
				pins = "gpio76", "gpio77";
				function = "qup2_se3";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c20_data_clk: qup-i2c20-data-clk-state {
				/* SDA, SCL */
				pins = "gpio80", "gpio81";
				function = "qup2_se4";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c21_data_clk: qup-i2c21-data-clk-state {
				/* SDA, SCL */
				pins = "gpio84", "gpio85";
				function = "qup2_se5";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c22_data_clk: qup-i2c22-data-clk-state {
				/* SDA, SCL */
				pins = "gpio88", "gpio89";
				function = "qup2_se6";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_i2c23_data_clk: qup-i2c23-data-clk-state {
				/* SDA, SCL */
				pins = "gpio86", "gpio87";
				function = "qup2_se7";
				drive-strength = <2>;
				bias-pull-up = <2200>;
			};

			qup_spi0_cs: qup-spi0-cs-state {
				pins = "gpio3";
				function = "qup0_se0";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi0_data_clk: qup-spi0-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio0", "gpio1", "gpio2";
				function = "qup0_se0";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi1_cs: qup-spi1-cs-state {
				pins = "gpio7";
				function = "qup0_se1";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi1_data_clk: qup-spi1-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio4", "gpio5", "gpio6";
				function = "qup0_se1";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi2_cs: qup-spi2-cs-state {
				pins = "gpio11";
				function = "qup0_se2";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi2_data_clk: qup-spi2-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio8", "gpio9", "gpio10";
				function = "qup0_se2";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi3_cs: qup-spi3-cs-state {
				pins = "gpio15";
				function = "qup0_se3";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi3_data_clk: qup-spi3-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio12", "gpio13", "gpio14";
				function = "qup0_se3";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi4_cs: qup-spi4-cs-state {
				pins = "gpio19";
				function = "qup0_se4";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi4_data_clk: qup-spi4-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio16", "gpio17", "gpio18";
				function = "qup0_se4";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi5_cs: qup-spi5-cs-state {
				pins = "gpio23";
				function = "qup0_se5";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi5_data_clk: qup-spi5-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio20", "gpio21", "gpio22";
				function = "qup0_se5";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi6_cs: qup-spi6-cs-state {
				pins = "gpio27";
				function = "qup0_se6";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi6_data_clk: qup-spi6-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio24", "gpio25", "gpio26";
				function = "qup0_se6";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi7_cs: qup-spi7-cs-state {
				pins = "gpio13";
				function = "qup0_se7";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi7_data_clk: qup-spi7-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio14", "gpio15", "gpio12";
				function = "qup0_se7";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi8_cs: qup-spi8-cs-state {
				pins = "gpio35";
				function = "qup1_se0";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi8_data_clk: qup-spi8-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio32", "gpio33", "gpio34";
				function = "qup1_se0";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi9_cs: qup-spi9-cs-state {
				pins = "gpio39";
				function = "qup1_se1";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi9_data_clk: qup-spi9-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio36", "gpio37", "gpio38";
				function = "qup1_se1";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi10_cs: qup-spi10-cs-state {
				pins = "gpio43";
				function = "qup1_se2";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi10_data_clk: qup-spi10-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio40", "gpio41", "gpio42";
				function = "qup1_se2";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi11_cs: qup-spi11-cs-state {
				pins = "gpio47";
				function = "qup1_se3";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi11_data_clk: qup-spi11-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio44", "gpio45", "gpio46";
				function = "qup1_se3";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi12_cs: qup-spi12-cs-state {
				pins = "gpio51";
				function = "qup1_se4";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi12_data_clk: qup-spi12-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio48", "gpio49", "gpio50";
				function = "qup1_se4";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi13_cs: qup-spi13-cs-state {
				pins = "gpio55";
				function = "qup1_se5";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi13_data_clk: qup-spi13-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio52", "gpio53", "gpio54";
				function = "qup1_se5";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi14_cs: qup-spi14-cs-state {
				pins = "gpio59";
				function = "qup1_se6";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi14_data_clk: qup-spi14-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio56", "gpio57", "gpio58";
				function = "qup1_se6";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi15_cs: qup-spi15-cs-state {
				pins = "gpio53";
				function = "qup1_se7";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi15_data_clk: qup-spi15-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio54", "gpio55", "gpio52";
				function = "qup1_se7";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi16_cs: qup-spi16-cs-state {
				pins = "gpio67";
				function = "qup2_se0";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi16_data_clk: qup-spi16-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio64", "gpio65", "gpio66";
				function = "qup2_se0";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi17_cs: qup-spi17-cs-state {
				pins = "gpio71";
				function = "qup2_se1";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi17_data_clk: qup-spi17-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio68", "gpio69", "gpio70";
				function = "qup2_se1";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi18_cs: qup-spi18-cs-state {
				pins = "gpio75";
				function = "qup2_se2";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi18_data_clk: qup-spi18-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio72", "gpio73", "gpio74";
				function = "qup2_se2";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi19_cs: qup-spi19-cs-state {
				pins = "gpio79";
				function = "qup2_se3";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi19_data_clk: qup-spi19-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio76", "gpio77", "gpio78";
				function = "qup2_se3";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi20_cs: qup-spi20-cs-state {
				pins = "gpio83";
				function = "qup2_se4";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi20_data_clk: qup-spi20-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio80", "gpio81", "gpio82";
				function = "qup2_se4";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi21_cs: qup-spi21-cs-state {
				pins = "gpio87";
				function = "qup2_se5";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi21_data_clk: qup-spi21-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio84", "gpio85", "gpio86";
				function = "qup2_se5";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi22_cs: qup-spi22-cs-state {
				pins = "gpio91";
				function = "qup2_se6";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi22_data_clk: qup-spi22-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio88", "gpio89", "gpio90";
				function = "qup2_se6";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi23_cs: qup-spi23-cs-state {
				pins = "gpio85";
				function = "qup2_se7";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi23_data_clk: qup-spi23-data-clk-state {
				/* MISO, MOSI, CLK */
				pins = "gpio86", "gpio87", "gpio84";
				function = "qup2_se7";
				drive-strength = <6>;
				bias-disable;
			};

			qup_uart2_default: qup-uart2-default-state {
				cts-pins {
					pins = "gpio8";
					function = "qup0_se2";
					drive-strength = <2>;
					bias-disable;
				};

				rts-pins {
					pins = "gpio9";
					function = "qup0_se2";
					drive-strength = <2>;
					bias-disable;
				};

				tx-pins {
					pins = "gpio10";
					function = "qup0_se2";
					drive-strength = <2>;
					bias-disable;
				};

				rx-pins {
					pins = "gpio11";
					function = "qup0_se2";
					drive-strength = <2>;
					bias-disable;
				};
			};

			qup_uart14_default: qup-uart14-default-state {
				cts-pins {
					pins = "gpio56";
					function = "qup1_se6";
					bias-bus-hold;
				};

				rts-pins {
					pins = "gpio57";
					function = "qup1_se6";
					drive-strength = <2>;
					bias-disable;
				};

				tx-pins {
					pins = "gpio58";
					function = "qup1_se6";
					drive-strength = <2>;
					bias-disable;
				};

				rx-pins {
					pins = "gpio59";
					function = "qup1_se6";
					bias-pull-up;
				};
			};

			qup_uart21_default: qup-uart21-default-state {
				tx-pins {
					pins = "gpio86";
					function = "qup2_se5";
					drive-strength = <2>;
					bias-disable;
				};

				rx-pins {
					pins = "gpio87";
					function = "qup2_se5";
					drive-strength = <2>;
					bias-disable;
				};
			};

			sdc2_default: sdc2-default-state {
				clk-pins {
					pins = "sdc2_clk";
					drive-strength = <16>;
					bias-disable;
				};

				cmd-pins {
					pins = "sdc2_cmd";
					drive-strength = <10>;
					bias-pull-up;
				};

				data-pins {
					pins = "sdc2_data";
					drive-strength = <10>;
					bias-pull-up;
				};
			};

			sdc2_sleep: sdc2-sleep-state {
				clk-pins {
					pins = "sdc2_clk";
					drive-strength = <2>;
					bias-disable;
				};

				cmd-pins {
					pins = "sdc2_cmd";
					drive-strength = <2>;
					bias-pull-up;
				};

				data-pins {
					pins = "sdc2_data";
					drive-strength = <2>;
					bias-pull-up;
				};
			};
		};

		stm@10002000 {
			compatible = "arm,coresight-stm", "arm,primecell";
			reg = <0x0 0x10002000 0x0 0x1000>,
			      <0x0 0x16280000 0x0 0x180000>;
			reg-names = "stm-base",
				    "stm-stimulus-base";

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					stm_out: endpoint {
						remote-endpoint = <&funnel0_in7>;
					};
				};
			};
		};

		tpdm@10003000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10003000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;
			status = "disabled";

			out-ports {
				port {
					dcc_tpdm_out: endpoint {
						remote-endpoint = <&qdss_tpda_in0>;
					};
				};
			};
		};

		tpda@10004000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x10004000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					qdss_tpda_in0: endpoint {
						remote-endpoint = <&dcc_tpdm_out>;
					};
				};

				port@1 {
					reg = <1>;

					qdss_tpda_in1: endpoint {
						remote-endpoint = <&qdss_tpdm_out>;
					};
				};
			};

			out-ports {
				port {
					qdss_tpda_out: endpoint {
						remote-endpoint = <&funnel0_in6>;
					};
				};
			};
		};

		tpdm@1000f000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x1000f000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					qdss_tpdm_out: endpoint {
						remote-endpoint = <&qdss_tpda_in1>;
					};
				};
			};
		};

		funnel@10041000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x10041000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@6 {
					reg = <6>;

					funnel0_in6: endpoint {
						remote-endpoint = <&qdss_tpda_out>;
					};
				};

				port@7 {
					reg = <7>;

					funnel0_in7: endpoint {
						remote-endpoint = <&stm_out>;
					};
				};
			};

			out-ports {
				port {
					funnel0_out: endpoint {
						remote-endpoint = <&qdss_funnel_in0>;
					};
				};
			};
		};

		funnel@10042000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x10042000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@2 {
					reg = <2>;

					funnel1_in2: endpoint {
						remote-endpoint = <&tmess_funnel_out>;
					};
				};

				port@5 {
					reg = <5>;

					funnel1_in5: endpoint {
						remote-endpoint = <&dlst_funnel_out>;
					};
				};

				port@6 {
					reg = <6>;

					funnel1_in6: endpoint {
						remote-endpoint = <&dlct1_funnel_out>;
					};
				};
			};

			out-ports {
				port {
					funnel1_out: endpoint {
						remote-endpoint = <&qdss_funnel_in1>;
					};
				};
			};
		};

		funnel@10045000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x10045000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					qdss_funnel_in0: endpoint {
						remote-endpoint = <&funnel0_out>;
					};
				};

				port@1 {
					reg = <1>;

					qdss_funnel_in1: endpoint {
						remote-endpoint = <&funnel1_out>;
					};
				};
			};

			out-ports {
				port {
					qdss_funnel_out: endpoint {
						remote-endpoint = <&aoss_funnel_in7>;
					};
				};
			};
		};

		tpdm@10800000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10800000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					mxa_tpdm_out: endpoint {
						remote-endpoint = <&dlct2_tpda_in15>;
					};
				};
			};
		};

		tpdm@1082c000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x1082c000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					gcc_tpdm_out: endpoint {
						remote-endpoint = <&dlct1_tpda_in21>;
					};
				};
			};
		};

		tpdm@10841000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10841000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					prng_tpdm_out: endpoint {
						remote-endpoint = <&dlct1_tpda_in19>;
					};
				};
			};
		};

		tpdm@10844000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10844000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					lpass_cx_tpdm_out: endpoint {
						remote-endpoint = <&lpass_cx_funnel_in0>;
					};
				};
			};
		};

		funnel@10846000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x10846000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					lpass_cx_funnel_in0: endpoint {
						remote-endpoint = <&lpass_cx_tpdm_out>;
					};
				};
			};

			out-ports {
				port {
					lpass_cx_funnel_out: endpoint {
						remote-endpoint = <&dlct1_tpda_in4>;
					};
				};
			};
		};

		cti@1098b000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x1098b000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		tpdm@109d0000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x109d0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;
			status = "disabled";

			out-ports {
				port {
					qm_tpdm_out: endpoint {
						remote-endpoint = <&dlct1_tpda_in20>;
					};
				};
			};
		};

		tpdm@10ac0000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10ac0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;
			status = "disabled";

			out-ports {
				port {
					dlst_tpdm0_out: endpoint {
						remote-endpoint = <&dlst_tpda_in8>;
					};
				};
			};
		};

		tpdm@10ac1000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10ac1000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					dlst_tpdm1_out: endpoint {
						remote-endpoint = <&dlst_tpda_in9>;
					};
				};
			};
		};

		tpda@10ac4000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x10ac4000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@8 {
					reg = <8>;

					dlst_tpda_in8: endpoint {
						remote-endpoint = <&dlst_tpdm0_out>;
					};
				};

				port@9 {
					reg = <9>;

					dlst_tpda_in9: endpoint {
						remote-endpoint = <&dlst_tpdm1_out>;
					};
				};
			};

			out-ports {
				port {
					dlst_tpda_out: endpoint {
						remote-endpoint = <&dlst_funnel_in0>;
					};
				};
			};
		};

		funnel@10ac5000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x10ac5000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					dlst_funnel_in0: endpoint {
						remote-endpoint = <&dlst_tpda_out>;
					};
				};
			};

			out-ports {
				port {
					dlst_funnel_out: endpoint {
						remote-endpoint = <&funnel1_in5>;
					};
				};
			};
		};

		funnel@10b04000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x10b04000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@3 {
					reg = <3>;

					aoss_funnel_in3: endpoint {
						remote-endpoint = <&ddr_lpi_funnel_out>;
					};
				};

				port@6 {
					reg = <6>;

					aoss_funnel_in6: endpoint {
						remote-endpoint = <&aoss_tpda_out>;
					};
				};

				port@7 {
					reg = <7>;

					aoss_funnel_in7: endpoint {
						remote-endpoint = <&qdss_funnel_out>;
					};
				};
			};

			out-ports {
				port {
					aoss_funnel_out: endpoint {
						remote-endpoint = <&etf0_in>;
					};
				};
			};
		};

		etf0: tmc@10b05000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x0 0x10b05000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					etf0_in: endpoint {
						remote-endpoint = <&aoss_funnel_out>;
					};
				};
			};

			out-ports {
				port {
					etf0_out: endpoint {
						remote-endpoint = <&swao_rep_in>;
					};
				};
			};
		};

		replicator@10b06000 {
			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
			reg = <0x0 0x10b06000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					swao_rep_in: endpoint {
						remote-endpoint = <&etf0_out>;
					};
				};
			};

			out-ports {
				port {
					swao_rep_out1: endpoint {
						remote-endpoint = <&eud_in>;
					};
				};
			};
		};

		tpda@10b08000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x10b08000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					aoss_tpda_in0: endpoint {
						remote-endpoint = <&aoss_tpdm0_out>;
					};
				};

				port@1 {
					reg = <1>;

					aoss_tpda_in1: endpoint {
						remote-endpoint = <&aoss_tpdm1_out>;
					};
				};

				port@2 {
					reg = <2>;

					aoss_tpda_in2: endpoint {
						remote-endpoint = <&aoss_tpdm2_out>;
					};
				};

				port@3 {
					reg = <3>;

					aoss_tpda_in3: endpoint {
						remote-endpoint = <&aoss_tpdm3_out>;
					};
				};

				port@4 {
					reg = <4>;

					aoss_tpda_in4: endpoint {
						remote-endpoint = <&aoss_tpdm4_out>;
					};
				};
			};

			out-ports {
				port {
					aoss_tpda_out: endpoint {
						remote-endpoint = <&aoss_funnel_in6>;
					};
				};
			};
		};

		tpdm@10b09000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10b09000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					aoss_tpdm0_out: endpoint {
						remote-endpoint = <&aoss_tpda_in0>;
					};
				};
			};
		};

		tpdm@10b0a000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10b0a000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					aoss_tpdm1_out: endpoint {
						remote-endpoint = <&aoss_tpda_in1>;
					};
				};
			};
		};

		tpdm@10b0b000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10b0b000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					aoss_tpdm2_out: endpoint {
						remote-endpoint = <&aoss_tpda_in2>;
					};
				};
			};
		};

		tpdm@10b0c000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10b0c000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					aoss_tpdm3_out: endpoint {
						remote-endpoint = <&aoss_tpda_in3>;
					};
				};
			};
		};

		tpdm@10b0d000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10b0d000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					aoss_tpdm4_out: endpoint {
						remote-endpoint = <&aoss_tpda_in4>;
					};
				};
			};
		};

		tpdm@10b20000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10b20000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;
			status = "disabled";

			out-ports {
				port {
					lpicc_tpdm_out: endpoint {
						remote-endpoint = <&ddr_lpi_tpda_in>;
					};
				};
			};
		};

		tpda@10b23000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x10b23000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
			status = "disabled";

			in-ports {
				port {
					ddr_lpi_tpda_in: endpoint {
						remote-endpoint = <&lpicc_tpdm_out>;
					};
				};
			};

			out-ports {
				port {
					ddr_lpi_tpda_out: endpoint {
						remote-endpoint = <&ddr_lpi_funnel_in0>;
					};
				};
			};
		};

		funnel@10b24000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x10b24000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
			status = "disabled";

			in-ports {
				port {
					ddr_lpi_funnel_in0: endpoint {
						remote-endpoint = <&ddr_lpi_tpda_out>;
					};
				};
			};

			out-ports {
				port {
					ddr_lpi_funnel_out: endpoint {
						remote-endpoint = <&aoss_funnel_in3>;
					};
				};
			};
		};

		tpdm@10c08000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10c08000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					mm_tpdm_out: endpoint {
						remote-endpoint = <&mm_funnel_in4>;
					};
				};
			};
		};

		funnel@10c0b000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x10c0b000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@4 {
					reg = <4>;

					mm_funnel_in4: endpoint {
						remote-endpoint = <&mm_tpdm_out>;
					};
				};
			};

			out-ports {
				port {
					mm_funnel_out: endpoint {
						remote-endpoint = <&dlct2_tpda_in4>;
					};
				};
			};
		};

		tpdm@10c28000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10c28000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					dlct1_tpdm_out: endpoint {
						remote-endpoint = <&dlct1_tpda_in26>;
					};
				};
			};
		};

		tpdm@10c29000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10c29000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					ipcc_tpdm_out: endpoint {
						remote-endpoint = <&dlct1_tpda_in27>;
					};
				};
			};
		};

		tpda@10c2b000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x10c2b000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@4 {
					reg = <4>;

					dlct1_tpda_in4: endpoint {
						remote-endpoint = <&lpass_cx_funnel_out>;
					};
				};

				port@13 {
					reg = <19>;

					dlct1_tpda_in19: endpoint {
						remote-endpoint = <&prng_tpdm_out>;
					};
				};

				port@14 {
					reg = <20>;

					dlct1_tpda_in20: endpoint {
						remote-endpoint = <&qm_tpdm_out>;
					};
				};

				port@15 {
					reg = <21>;

					dlct1_tpda_in21: endpoint {
						remote-endpoint = <&gcc_tpdm_out>;
					};
				};

				port@1a {
					reg = <26>;

					dlct1_tpda_in26: endpoint {
						remote-endpoint = <&dlct1_tpdm_out>;
					};
				};

				port@1b {
					reg = <27>;

					dlct1_tpda_in27: endpoint {
						remote-endpoint = <&ipcc_tpdm_out>;
					};
				};
			};

			out-ports {
				port {
					dlct1_tpda_out: endpoint {
						remote-endpoint = <&dlct1_funnel_in0>;
					};
				};
			};
		};

		funnel@10c2c000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x10c2c000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					dlct1_funnel_in0: endpoint {
						remote-endpoint = <&dlct1_tpda_out>;
					};
				};

				port@4 {
					reg = <4>;

					dlct1_funnel_in4: endpoint {
						remote-endpoint = <&dlct2_funnel_out>;
					};
				};

				port@5 {
					reg = <5>;

					dlct1_funnel_in5: endpoint {
						remote-endpoint = <&ddr_funnel0_out>;
					};
				};
			};

			out-ports {
				port {
					dlct1_funnel_out: endpoint {
						remote-endpoint = <&funnel1_in6>;
					};
				};
			};
		};

		tpdm@10c38000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10c38000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					dlct2_tpdm0_out: endpoint {
						remote-endpoint = <&dlct2_tpda_in16>;
					};
				};
			};
		};

		tpdm@10c39000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10c39000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					dlct2_tpdm1_out: endpoint {
						remote-endpoint = <&dlct2_tpda_in17>;
					};
				};
			};
		};

		tpda@10c3c000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x10c3c000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@4 {
					reg = <4>;

					dlct2_tpda_in4: endpoint {
						remote-endpoint = <&mm_funnel_out>;
					};
				};

				port@f {
					reg = <15>;

					dlct2_tpda_in15: endpoint {
						remote-endpoint = <&mxa_tpdm_out>;
					};
				};

				port@10 {
					reg = <16>;

					dlct2_tpda_in16: endpoint {
						remote-endpoint = <&dlct2_tpdm0_out>;
					};
				};

				port@11 {
					reg = <17>;

					dlct2_tpda_in17: endpoint {
						remote-endpoint = <&dlct2_tpdm1_out>;
					};
				};
			};

			out-ports {
				port {
					dlct2_tpda_out: endpoint {
						remote-endpoint = <&dlct2_funnel_in0>;
					};
				};
			};
		};

		funnel@10c3d000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x10c3d000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					dlct2_funnel_in0: endpoint {
						remote-endpoint = <&dlct2_tpda_out>;
					};
				};
			};

			out-ports {
				port {
					dlct2_funnel_out: endpoint {
						remote-endpoint = <&dlct1_funnel_in4>;
					};
				};
			};
		};

		tpdm@10cc1000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10cc1000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;
			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;
			status = "disabled";

			out-ports {
				port {
					tmess_tpdm1_out: endpoint {
						remote-endpoint = <&tmess_tpda_in2>;
					};
				};
			};
		};

		tpda@10cc4000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x10cc4000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@2 {
					reg = <2>;

					tmess_tpda_in2: endpoint {
						remote-endpoint = <&tmess_tpdm1_out>;
					};
				};
			};

			out-ports {
				port {
					tmess_tpda_out: endpoint {
						remote-endpoint = <&tmess_funnel_in0>;
					};
				};
			};
		};

		funnel@10cc5000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x10cc5000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					tmess_funnel_in0: endpoint {
						remote-endpoint = <&tmess_tpda_out>;
					};
				};
			};

			out-ports {
				port {
					tmess_funnel_out: endpoint {
						remote-endpoint = <&funnel1_in2>;
					};
				};
			};
		};

		funnel@10d04000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x10d04000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@6 {
					reg = <6>;

					ddr_funnel0_in6: endpoint {
						remote-endpoint = <&ddr_funnel1_out>;
					};
				};
			};

			out-ports {
				port {
					ddr_funnel0_out: endpoint {
						remote-endpoint = <&dlct1_funnel_in5>;
					};
				};
			};
		};

		tpdm@10d08000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10d08000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					llcc0_tpdm_out: endpoint {
						remote-endpoint = <&llcc_tpda_in0>;
					};
				};
			};
		};

		tpdm@10d09000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10d09000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					llcc1_tpdm_out: endpoint {
						remote-endpoint = <&llcc_tpda_in1>;
					};
				};
			};
		};

		tpdm@10d0a000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10d0a000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					llcc2_tpdm_out: endpoint {
						remote-endpoint = <&llcc_tpda_in2>;
					};
				};
			};
		};

		tpdm@10d0b000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10d0b000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					llcc3_tpdm_out: endpoint {
						remote-endpoint = <&llcc_tpda_in3>;
					};
				};
			};
		};

		tpdm@10d0c000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10d0c000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					llcc4_tpdm_out: endpoint {
						remote-endpoint = <&llcc_tpda_in4>;
					};
				};
			};
		};

		tpdm@10d0d000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10d0d000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					llcc5_tpdm_out: endpoint {
						remote-endpoint = <&llcc_tpda_in5>;
					};
				};
			};
		};

		tpdm@10d0e000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10d0e000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					llcc6_tpdm_out: endpoint {
						remote-endpoint = <&llcc_tpda_in6>;
					};
				};
			};
		};

		tpdm@10d0f000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x10d0f000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					llcc7_tpdm_out: endpoint {
						remote-endpoint = <&llcc_tpda_in7>;
					};
				};
			};
		};

		tpda@10d12000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x10d12000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					llcc_tpda_in0: endpoint {
						remote-endpoint = <&llcc0_tpdm_out>;
					};
				};

				port@1 {
					reg = <1>;

					llcc_tpda_in1: endpoint {
						remote-endpoint = <&llcc1_tpdm_out>;
					};
				};

				port@2 {
					reg = <2>;

					llcc_tpda_in2: endpoint {
						remote-endpoint = <&llcc2_tpdm_out>;
					};
				};

				port@3 {
					reg = <3>;

					llcc_tpda_in3: endpoint {
						remote-endpoint = <&llcc3_tpdm_out>;
					};
				};

				port@4 {
					reg = <4>;

					llcc_tpda_in4: endpoint {
						remote-endpoint = <&llcc4_tpdm_out>;
					};
				};

				port@5 {
					reg = <5>;

					llcc_tpda_in5: endpoint {
						remote-endpoint = <&llcc5_tpdm_out>;
					};
				};

				port@6 {
					reg = <6>;

					llcc_tpda_in6: endpoint {
						remote-endpoint = <&llcc6_tpdm_out>;
					};
				};

				port@7 {
					reg = <7>;

					llcc_tpda_in7: endpoint {
						remote-endpoint = <&llcc7_tpdm_out>;
					};
				};
			};

			out-ports {
				port {
					llcc_tpda_out: endpoint {
						remote-endpoint = <&ddr_funnel1_in0>;
					};
				};
			};
		};

		funnel@10d13000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x10d13000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					ddr_funnel1_in0: endpoint {
						remote-endpoint = <&llcc_tpda_out>;
					};
				};
			};

			out-ports {
				port {
					ddr_funnel1_out: endpoint {
						remote-endpoint = <&ddr_funnel0_in6>;
					};
				};
			};
		};

		apps_smmu: iommu@15000000 {
			compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
			reg = <0 0x15000000 0 0x100000>;

			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;

			#iommu-cells = <2>;
			#global-interrupts = <1>;

			dma-coherent;
		};

		pcie_smmu: iommu@15400000 {
			compatible = "arm,smmu-v3";
			reg = <0 0x15400000 0 0x80000>;
			#iommu-cells = <1>;
			interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq",
					  "gerror",
					  "cmdq-sync";
			dma-coherent;
			status = "reserved"; /* Controlled by Gunyah. */
		};

		intc: interrupt-controller@17000000 {
			compatible = "arm,gic-v3";
			reg = <0 0x17000000 0 0x10000>,     /* GICD */
			      <0 0x17080000 0 0x300000>;    /* GICR * 12 */

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

			#interrupt-cells = <3>;
			interrupt-controller;

			#redistributor-regions = <1>;
			redistributor-stride = <0x0 0x40000>;

			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			gic_its: msi-controller@17040000 {
				compatible = "arm,gic-v3-its";
				reg = <0 0x17040000 0 0x40000>;

				msi-controller;
				#msi-cells = <1>;
			};
		};

		apss_watchdog: watchdog@17410000 {
			compatible = "qcom,apss-wdt-x1e80100", "qcom,kpss-wdt";
			reg = <0x0 0x17410000 0x0 0x1000>;
			clocks = <&sleep_clk>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
			status = "reserved"; /* Reserved by Gunyah */
		};

		cpucp_mbox: mailbox@17430000 {
			compatible = "qcom,x1e80100-cpucp-mbox";
			reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			#mbox-cells = <1>;
		};

		apps_rsc: rsc@17500000 {
			compatible = "qcom,rpmh-rsc";
			reg = <0 0x17500000 0 0x10000>,
			      <0 0x17510000 0 0x10000>,
			      <0 0x17520000 0 0x10000>;
			reg-names = "drv-0", "drv-1", "drv-2";

			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			qcom,tcs-offset = <0xd00>;
			qcom,drv-id = <2>;
			qcom,tcs-config = <ACTIVE_TCS    3>, <SLEEP_TCS     2>,
					  <WAKE_TCS      2>, <CONTROL_TCS   0>;

			label = "apps_rsc";
			power-domains = <&system_pd>;

			apps_bcm_voter: bcm-voter {
				compatible = "qcom,bcm-voter";
			};

			rpmhcc: clock-controller {
				compatible = "qcom,x1e80100-rpmh-clk";

				clocks = <&xo_board>;
				clock-names = "xo";

				#clock-cells = <1>;
			};

			rpmhpd: power-controller {
				compatible = "qcom,x1e80100-rpmhpd";

				operating-points-v2 = <&rpmhpd_opp_table>;

				#power-domain-cells = <1>;

				rpmhpd_opp_table: opp-table {
					compatible = "operating-points-v2";

					rpmhpd_opp_ret: opp-16 {
						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
					};

					rpmhpd_opp_min_svs: opp-48 {
						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
					};

					rpmhpd_opp_low_svs_d2: opp-52 {
						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
					};

					rpmhpd_opp_low_svs_d1: opp-56 {
						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
					};

					rpmhpd_opp_low_svs_d0: opp-60 {
						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
					};

					rpmhpd_opp_low_svs: opp-64 {
						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
					};

					rpmhpd_opp_low_svs_l1: opp-80 {
						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
					};

					rpmhpd_opp_svs: opp-128 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
					};

					rpmhpd_opp_svs_l0: opp-144 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
					};

					rpmhpd_opp_svs_l1: opp-192 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
					};

					rpmhpd_opp_nom: opp-256 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
					};

					rpmhpd_opp_nom_l1: opp-320 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
					};

					rpmhpd_opp_nom_l2: opp-336 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
					};

					rpmhpd_opp_turbo: opp-384 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
					};

					rpmhpd_opp_turbo_l1: opp-416 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
					};
				};
			};
		};

		timer@17800000 {
			compatible = "arm,armv7-timer-mem";
			reg = <0 0x17800000 0 0x1000>;

			#address-cells = <2>;
			#size-cells = <1>;
			ranges = <0 0 0 0 0x20000000>;

			frame@17801000 {
				reg = <0 0x17801000 0x1000>,
				      <0 0x17802000 0x1000>;

				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

				frame-number = <0>;
			};

			frame@17803000 {
				reg = <0 0x17803000 0x1000>;

				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

				frame-number = <1>;

				status = "disabled";
			};

			frame@17805000 {
				reg = <0 0x17805000 0x1000>;

				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

				frame-number = <2>;

				status = "disabled";
			};

			frame@17807000 {
				reg = <0 0x17807000 0x1000>;

				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				frame-number = <3>;

				status = "disabled";
			};

			frame@17809000 {
				reg = <0 0x17809000 0x1000>;

				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

				frame-number = <4>;

				status = "disabled";
			};

			frame@1780b000 {
				reg = <0 0x1780b000 0x1000>;

				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

				frame-number = <5>;

				status = "disabled";
			};

			frame@1780d000 {
				reg = <0 0x1780d000 0x1000>;

				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

				frame-number = <6>;

				status = "disabled";
			};
		};

		sram: sram@18b4e000 {
			compatible = "mmio-sram";
			reg = <0x0 0x18b4e000 0x0 0x400>;

			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x18b4e000 0x400>;

			cpu_scp_lpri0: scp-sram-section@0 {
				compatible = "arm,scmi-shmem";
				reg = <0x0 0x200>;
			};

			cpu_scp_lpri1: scp-sram-section@200 {
				compatible = "arm,scmi-shmem";
				reg = <0x200 0x200>;
			};
		};

		sbsa_watchdog: watchdog@1c840000 {
			compatible = "arm,sbsa-gwdt";
			reg = <0 0x1c840000 0 0x1000>,
			      <0 0x1c850000 0 0x1000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
		};

		qfprom: efuse@221c8000 {
			compatible = "qcom,x1e80100-qfprom", "qcom,qfprom";
			reg = <0 0x221c8000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			gpu_speed_bin: gpu-speed-bin@119 {
				reg = <0x119 0x2>;
				bits = <7 8>;
			};
		};

		pmu@24091000 {
			compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
			reg = <0 0x24091000 0 0x1000>;

			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;

			interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;

			operating-points-v2 = <&llcc_bwmon_opp_table>;

			llcc_bwmon_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-0 {
					opp-peak-kBps = <800000>;
				};

				opp-1 {
					opp-peak-kBps = <2188000>;
				};

				opp-2 {
					opp-peak-kBps = <3072000>;
				};

				opp-3 {
					opp-peak-kBps = <6220800>;
				};

				opp-4 {
					opp-peak-kBps = <6835200>;
				};

				opp-5 {
					opp-peak-kBps = <8371200>;
				};

				opp-6 {
					opp-peak-kBps = <10944000>;
				};

				opp-7 {
					opp-peak-kBps = <12748800>;
				};

				opp-8 {
					opp-peak-kBps = <14745600>;
				};

				opp-9 {
					opp-peak-kBps = <16896000>;
				};
			};
		};

		/* cluster0 */
		bwmon_cluster0: pmu@240b3400 {
			compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
			reg = <0 0x240b3400 0 0x600>;

			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;

			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;

			operating-points-v2 = <&cpu_bwmon_opp_table>;
		};

		/* cluster2 */
		bwmon_cluster2: pmu@240b5400 {
			compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
			reg = <0 0x240b5400 0 0x600>;

			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;

			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;

			operating-points-v2 = <&cpu_bwmon_opp_table>;

			cpu_bwmon_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-0 {
					opp-peak-kBps = <4800000>;
				};

				opp-1 {
					opp-peak-kBps = <7464000>;
				};

				opp-2 {
					opp-peak-kBps = <9600000>;
				};

				opp-3 {
					opp-peak-kBps = <12896000>;
				};

				opp-4 {
					opp-peak-kBps = <14928000>;
				};

				opp-5 {
					opp-peak-kBps = <17064000>;
				};
			};
		};

		/* cluster1 */
		pmu@240b6400 {
			compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
			reg = <0 0x240b6400 0 0x600>;

			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;

			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;

			operating-points-v2 = <&cpu_bwmon_opp_table>;
		};

		system-cache-controller@25000000 {
			compatible = "qcom,x1e80100-llcc";
			reg = <0 0x25000000 0 0x200000>,
			      <0 0x25200000 0 0x200000>,
			      <0 0x25400000 0 0x200000>,
			      <0 0x25600000 0 0x200000>,
			      <0 0x25800000 0 0x200000>,
			      <0 0x25a00000 0 0x200000>,
			      <0 0x25c00000 0 0x200000>,
			      <0 0x25e00000 0 0x200000>,
			      <0 0x26000000 0 0x200000>,
			      <0 0x26200000 0 0x200000>;
			reg-names = "llcc0_base",
				    "llcc1_base",
				    "llcc2_base",
				    "llcc3_base",
				    "llcc4_base",
				    "llcc5_base",
				    "llcc6_base",
				    "llcc7_base",
				    "llcc_broadcast_base",
				    "llcc_broadcast_and_base";
			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
		};

		remoteproc_cdsp: remoteproc@32300000 {
			compatible = "qcom,x1e80100-cdsp-pas";
			reg = <0x0 0x32300000 0x0 0x10000>;

			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog",
					  "fatal",
					  "ready",
					  "handover",
					  "stop-ack";

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";

			power-domains = <&rpmhpd RPMHPD_CX>,
					<&rpmhpd RPMHPD_MXC>,
					<&rpmhpd RPMHPD_NSP>;
			power-domain-names = "cx",
					     "mxc",
					     "nsp";

			interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;

			memory-region = <&cdsp_mem>,
					<&q6_cdsp_dtb_mem>;

			qcom,qmp = <&aoss_qmp>;

			qcom,smem-states = <&smp2p_cdsp_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink-edge {
				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
							     IPCC_MPROC_SIGNAL_GLINK_QMP
							     IRQ_TYPE_EDGE_RISING>;
				mboxes = <&ipcc IPCC_CLIENT_CDSP
						IPCC_MPROC_SIGNAL_GLINK_QMP>;

				label = "cdsp";
				qcom,remote-pid = <5>;

				fastrpc {
					compatible = "qcom,fastrpc";
					qcom,glink-channels = "fastrpcglink-apps-dsp";
					label = "cdsp";
					qcom,non-secure-domain;
					#address-cells = <1>;
					#size-cells = <0>;

					compute-cb@1 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <1>;
						iommus = <&apps_smmu 0x0c01 0x20>;
						dma-coherent;
					};

					compute-cb@2 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <2>;
						iommus = <&apps_smmu 0x0c02 0x20>;
						dma-coherent;
					};

					compute-cb@3 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <3>;
						iommus = <&apps_smmu 0x0c03 0x20>;
						dma-coherent;
					};

					compute-cb@4 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <4>;
						iommus = <&apps_smmu 0x0c04 0x20>;
						dma-coherent;
					};

					compute-cb@5 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <5>;
						iommus = <&apps_smmu 0x0c05 0x20>;
						dma-coherent;
					};

					compute-cb@6 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <6>;
						iommus = <&apps_smmu 0x0c06 0x20>;
						dma-coherent;
					};

					compute-cb@7 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <7>;
						iommus = <&apps_smmu 0x0c07 0x20>;
						dma-coherent;
					};

					compute-cb@8 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <8>;
						iommus = <&apps_smmu 0x0c08 0x20>;
						dma-coherent;
					};

					/* note: compute-cb@9 is secure */

					compute-cb@10 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <10>;
						iommus = <&apps_smmu 0x0c0c 0x20>;
						dma-coherent;
					};

					compute-cb@11 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <11>;
						iommus = <&apps_smmu 0x0c0d 0x20>;
						dma-coherent;
					};

					compute-cb@12 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <12>;
						iommus = <&apps_smmu 0x0c0e 0x20>;
						dma-coherent;
					};

					compute-cb@13 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <13>;
						iommus = <&apps_smmu 0x0c0f 0x20>;
						dma-coherent;
					};
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	thermal_zones: thermal-zones {
		aoss0-thermal {
			thermal-sensors = <&tsens0 0>;

			trips {
				trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};

				aoss0-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu0-0-top-thermal {
			thermal-sensors = <&tsens0 1>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu0-0-btm-thermal {
			thermal-sensors = <&tsens0 2>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu0-1-top-thermal {
			thermal-sensors = <&tsens0 3>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu0-1-btm-thermal {
			thermal-sensors = <&tsens0 4>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu0-2-top-thermal {
			thermal-sensors = <&tsens0 5>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu0-2-btm-thermal {
			thermal-sensors = <&tsens0 6>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu0-3-top-thermal {
			thermal-sensors = <&tsens0 7>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu0-3-btm-thermal {
			thermal-sensors = <&tsens0 8>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpuss0-top-thermal {
			thermal-sensors = <&tsens0 9>;

			trips {
				cpuss2-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpuss0-btm-thermal {
			thermal-sensors = <&tsens0 10>;

			trips {
				cpuss2-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		mem-thermal {
			thermal-sensors = <&tsens0 11>;

			trips {
				trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};

				mem-critical {
					temperature = <115000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
		};

		video-thermal {
			thermal-sensors = <&tsens0 12>;

			trips {
				trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};

				video-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		aoss1-thermal {
			thermal-sensors = <&tsens1 0>;

			trips {
				trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};

				aoss0-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu1-0-top-thermal {
			thermal-sensors = <&tsens1 1>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu1-0-btm-thermal {
			thermal-sensors = <&tsens1 2>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu1-1-top-thermal {
			thermal-sensors = <&tsens1 3>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu1-1-btm-thermal {
			thermal-sensors = <&tsens1 4>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu1-2-top-thermal {
			thermal-sensors = <&tsens1 5>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu1-2-btm-thermal {
			thermal-sensors = <&tsens1 6>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu1-3-top-thermal {
			thermal-sensors = <&tsens1 7>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu1-3-btm-thermal {
			thermal-sensors = <&tsens1 8>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpuss1-top-thermal {
			thermal-sensors = <&tsens1 9>;

			trips {
				cpuss2-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpuss1-btm-thermal {
			thermal-sensors = <&tsens1 10>;

			trips {
				cpuss2-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		aoss2-thermal {
			thermal-sensors = <&tsens2 0>;

			trips {
				trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};

				aoss0-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_cpu2_0_top: cpu2-0-top-thermal {
			thermal-sensors = <&tsens2 1>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_cpu2_0_btm: cpu2-0-btm-thermal {
			thermal-sensors = <&tsens2 2>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_cpu2_1_top: cpu2-1-top-thermal {
			thermal-sensors = <&tsens2 3>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_cpu2_1_btm: cpu2-1-btm-thermal {
			thermal-sensors = <&tsens2 4>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_cpu2_2_top: cpu2-2-top-thermal {
			thermal-sensors = <&tsens2 5>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_cpu2_2_btm: cpu2-2-btm-thermal {
			thermal-sensors = <&tsens2 6>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_cpu2_3_top: cpu2-3-top-thermal {
			thermal-sensors = <&tsens2 7>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_cpu2_3_btm: cpu2-3-btm-thermal {
			thermal-sensors = <&tsens2 8>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_cpuss2_top: cpuss2-top-thermal {
			thermal-sensors = <&tsens2 9>;

			trips {
				cpuss2-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_cpuss2_btm: cpuss2-btm-thermal {
			thermal-sensors = <&tsens2 10>;

			trips {
				cpuss2-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_aoss3: aoss3-thermal {
			thermal-sensors = <&tsens3 0>;

			trips {
				trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};

				aoss0-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_nsp0: nsp0-thermal {
			thermal-sensors = <&tsens3 1>;

			trips {
				trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};

				nsp0-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_nsp1: nsp1-thermal {
			thermal-sensors = <&tsens3 2>;

			trips {
				trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};

				nsp1-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_nsp2: nsp2-thermal {
			thermal-sensors = <&tsens3 3>;

			trips {
				trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};

				nsp2-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_nsp3: nsp3-thermal {
			thermal-sensors = <&tsens3 4>;

			trips {
				trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};

				nsp3-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_gpuss_0: gpuss-0-thermal {
			polling-delay-passive = <200>;

			thermal-sensors = <&tsens3 5>;

			cooling-maps {
				map0 {
					trip = <&gpuss0_alert0>;
					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				gpuss0_alert0: trip-point0 {
					temperature = <95000>;
					hysteresis = <1000>;
					type = "passive";
				};

				gpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_gpuss_1: gpuss-1-thermal {
			polling-delay-passive = <200>;

			thermal-sensors = <&tsens3 6>;

			cooling-maps {
				map0 {
					trip = <&gpuss1_alert0>;
					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				gpuss1_alert0: trip-point0 {
					temperature = <95000>;
					hysteresis = <1000>;
					type = "passive";
				};

				gpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_gpuss_2: gpuss-2-thermal {
			polling-delay-passive = <200>;

			thermal-sensors = <&tsens3 7>;

			cooling-maps {
				map0 {
					trip = <&gpuss2_alert0>;
					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				gpuss2_alert0: trip-point0 {
					temperature = <95000>;
					hysteresis = <1000>;
					type = "passive";
				};

				gpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_gpuss_3: gpuss-3-thermal {
			polling-delay-passive = <200>;

			thermal-sensors = <&tsens3 8>;

			cooling-maps {
				map0 {
					trip = <&gpuss3_alert0>;
					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				gpuss3_alert0: trip-point0 {
					temperature = <95000>;
					hysteresis = <1000>;
					type = "passive";
				};

				gpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_gpuss_4: gpuss-4-thermal {
			polling-delay-passive = <200>;

			thermal-sensors = <&tsens3 9>;

			cooling-maps {
				map0 {
					trip = <&gpuss4_alert0>;
					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				gpuss4_alert0: trip-point0 {
					temperature = <95000>;
					hysteresis = <1000>;
					type = "passive";
				};

				gpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_gpuss_5: gpuss-5-thermal {
			polling-delay-passive = <200>;

			thermal-sensors = <&tsens3 10>;

			cooling-maps {
				map0 {
					trip = <&gpuss5_alert0>;
					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				gpuss5_alert0: trip-point0 {
					temperature = <95000>;
					hysteresis = <1000>;
					type = "passive";
				};

				gpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_gpuss_6: gpuss-6-thermal {
			polling-delay-passive = <200>;

			thermal-sensors = <&tsens3 11>;

			cooling-maps {
				map0 {
					trip = <&gpuss6_alert0>;
					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				gpuss6_alert0: trip-point0 {
					temperature = <95000>;
					hysteresis = <1000>;
					type = "passive";
				};

				gpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_gpuss_7: gpuss-7-thermal {
			polling-delay-passive = <200>;

			thermal-sensors = <&tsens3 12>;

			cooling-maps {
				map0 {
					trip = <&gpuss7_alert0>;
					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				gpuss7_alert0: trip-point0 {
					temperature = <95000>;
					hysteresis = <1000>;
					type = "passive";
				};

				gpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_camera0: camera0-thermal {
			thermal-sensors = <&tsens3 13>;

			trips {
				trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};

				camera0-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		thermal_camera1: camera1-thermal {
			thermal-sensors = <&tsens3 14>;

			trips {
				trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};

				camera0-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};
	};
};