1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 8#include <dt-bindings/clock/qcom,sm8450-videocc.h> 9#include <dt-bindings/clock/qcom,x1e80100-camcc.h> 10#include <dt-bindings/clock/qcom,x1e80100-dispcc.h> 11#include <dt-bindings/clock/qcom,x1e80100-gcc.h> 12#include <dt-bindings/clock/qcom,x1e80100-gpucc.h> 13#include <dt-bindings/clock/qcom,x1e80100-tcsr.h> 14#include <dt-bindings/dma/qcom-gpi.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/interconnect/qcom,icc.h> 17#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/phy/phy-qcom-qmp.h> 21#include <dt-bindings/power/qcom,rpmhpd.h> 22#include <dt-bindings/power/qcom-rpmpd.h> 23#include <dt-bindings/soc/qcom,gpr.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 clocks { 37 xo_board: xo-board { 38 compatible = "fixed-clock"; 39 clock-frequency = <76800000>; 40 #clock-cells = <0>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 clock-frequency = <32764>; 46 #clock-cells = <0>; 47 }; 48 49 bi_tcxo_div2: bi-tcxo-div2-clk { 50 compatible = "fixed-factor-clock"; 51 #clock-cells = <0>; 52 53 clocks = <&rpmhcc RPMH_CXO_CLK>; 54 clock-mult = <1>; 55 clock-div = <2>; 56 }; 57 58 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 59 compatible = "fixed-factor-clock"; 60 #clock-cells = <0>; 61 62 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 63 clock-mult = <1>; 64 clock-div = <2>; 65 }; 66 }; 67 68 cpus { 69 #address-cells = <2>; 70 #size-cells = <0>; 71 72 cpu0: cpu@0 { 73 device_type = "cpu"; 74 compatible = "qcom,oryon"; 75 reg = <0x0 0x0>; 76 enable-method = "psci"; 77 next-level-cache = <&l2_0>; 78 power-domains = <&cpu_pd0>, <&scmi_dvfs 0>; 79 power-domain-names = "psci", "perf"; 80 #cooling-cells = <2>; 81 82 l2_0: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 cache-unified; 86 }; 87 }; 88 89 cpu1: cpu@100 { 90 device_type = "cpu"; 91 compatible = "qcom,oryon"; 92 reg = <0x0 0x100>; 93 enable-method = "psci"; 94 next-level-cache = <&l2_0>; 95 power-domains = <&cpu_pd1>, <&scmi_dvfs 0>; 96 power-domain-names = "psci", "perf"; 97 #cooling-cells = <2>; 98 }; 99 100 cpu2: cpu@200 { 101 device_type = "cpu"; 102 compatible = "qcom,oryon"; 103 reg = <0x0 0x200>; 104 enable-method = "psci"; 105 next-level-cache = <&l2_0>; 106 power-domains = <&cpu_pd2>, <&scmi_dvfs 0>; 107 power-domain-names = "psci", "perf"; 108 #cooling-cells = <2>; 109 }; 110 111 cpu3: cpu@300 { 112 device_type = "cpu"; 113 compatible = "qcom,oryon"; 114 reg = <0x0 0x300>; 115 enable-method = "psci"; 116 next-level-cache = <&l2_0>; 117 power-domains = <&cpu_pd3>, <&scmi_dvfs 0>; 118 power-domain-names = "psci", "perf"; 119 #cooling-cells = <2>; 120 }; 121 122 cpu4: cpu@10000 { 123 device_type = "cpu"; 124 compatible = "qcom,oryon"; 125 reg = <0x0 0x10000>; 126 enable-method = "psci"; 127 next-level-cache = <&l2_1>; 128 power-domains = <&cpu_pd4>, <&scmi_dvfs 1>; 129 power-domain-names = "psci", "perf"; 130 #cooling-cells = <2>; 131 132 l2_1: l2-cache { 133 compatible = "cache"; 134 cache-level = <2>; 135 cache-unified; 136 }; 137 }; 138 139 cpu5: cpu@10100 { 140 device_type = "cpu"; 141 compatible = "qcom,oryon"; 142 reg = <0x0 0x10100>; 143 enable-method = "psci"; 144 next-level-cache = <&l2_1>; 145 power-domains = <&cpu_pd5>, <&scmi_dvfs 1>; 146 power-domain-names = "psci", "perf"; 147 #cooling-cells = <2>; 148 }; 149 150 cpu6: cpu@10200 { 151 device_type = "cpu"; 152 compatible = "qcom,oryon"; 153 reg = <0x0 0x10200>; 154 enable-method = "psci"; 155 next-level-cache = <&l2_1>; 156 power-domains = <&cpu_pd6>, <&scmi_dvfs 1>; 157 power-domain-names = "psci", "perf"; 158 #cooling-cells = <2>; 159 }; 160 161 cpu7: cpu@10300 { 162 device_type = "cpu"; 163 compatible = "qcom,oryon"; 164 reg = <0x0 0x10300>; 165 enable-method = "psci"; 166 next-level-cache = <&l2_1>; 167 power-domains = <&cpu_pd7>, <&scmi_dvfs 1>; 168 power-domain-names = "psci", "perf"; 169 #cooling-cells = <2>; 170 }; 171 172 cpu8: cpu@20000 { 173 device_type = "cpu"; 174 compatible = "qcom,oryon"; 175 reg = <0x0 0x20000>; 176 enable-method = "psci"; 177 next-level-cache = <&l2_2>; 178 power-domains = <&cpu_pd8>, <&scmi_dvfs 2>; 179 power-domain-names = "psci", "perf"; 180 #cooling-cells = <2>; 181 182 l2_2: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 cache-unified; 186 }; 187 }; 188 189 cpu9: cpu@20100 { 190 device_type = "cpu"; 191 compatible = "qcom,oryon"; 192 reg = <0x0 0x20100>; 193 enable-method = "psci"; 194 next-level-cache = <&l2_2>; 195 power-domains = <&cpu_pd9>, <&scmi_dvfs 2>; 196 power-domain-names = "psci", "perf"; 197 #cooling-cells = <2>; 198 }; 199 200 cpu10: cpu@20200 { 201 device_type = "cpu"; 202 compatible = "qcom,oryon"; 203 reg = <0x0 0x20200>; 204 enable-method = "psci"; 205 next-level-cache = <&l2_2>; 206 power-domains = <&cpu_pd10>, <&scmi_dvfs 2>; 207 power-domain-names = "psci", "perf"; 208 #cooling-cells = <2>; 209 }; 210 211 cpu11: cpu@20300 { 212 device_type = "cpu"; 213 compatible = "qcom,oryon"; 214 reg = <0x0 0x20300>; 215 enable-method = "psci"; 216 next-level-cache = <&l2_2>; 217 power-domains = <&cpu_pd11>, <&scmi_dvfs 2>; 218 power-domain-names = "psci", "perf"; 219 #cooling-cells = <2>; 220 }; 221 222 cpu-map { 223 cluster0 { 224 core0 { 225 cpu = <&cpu0>; 226 }; 227 228 core1 { 229 cpu = <&cpu1>; 230 }; 231 232 core2 { 233 cpu = <&cpu2>; 234 }; 235 236 core3 { 237 cpu = <&cpu3>; 238 }; 239 }; 240 241 cluster1 { 242 core0 { 243 cpu = <&cpu4>; 244 }; 245 246 core1 { 247 cpu = <&cpu5>; 248 }; 249 250 core2 { 251 cpu = <&cpu6>; 252 }; 253 254 core3 { 255 cpu = <&cpu7>; 256 }; 257 }; 258 259 cpu_map_cluster2: cluster2 { 260 core0 { 261 cpu = <&cpu8>; 262 }; 263 264 core1 { 265 cpu = <&cpu9>; 266 }; 267 268 core2 { 269 cpu = <&cpu10>; 270 }; 271 272 core3 { 273 cpu = <&cpu11>; 274 }; 275 }; 276 }; 277 278 idle-states { 279 entry-method = "psci"; 280 281 cluster_c4: cpu-sleep-0 { 282 compatible = "arm,idle-state"; 283 idle-state-name = "ret"; 284 arm,psci-suspend-param = <0x00000004>; 285 entry-latency-us = <180>; 286 exit-latency-us = <320>; 287 min-residency-us = <600>; 288 }; 289 }; 290 291 domain-idle-states { 292 cluster_cl4: cluster-sleep-0 { 293 compatible = "domain-idle-state"; 294 arm,psci-suspend-param = <0x01000044>; 295 entry-latency-us = <350>; 296 exit-latency-us = <500>; 297 min-residency-us = <2500>; 298 }; 299 300 cluster_cl5: cluster-sleep-1 { 301 compatible = "domain-idle-state"; 302 arm,psci-suspend-param = <0x01000054>; 303 entry-latency-us = <2000>; 304 exit-latency-us = <2000>; 305 min-residency-us = <7000>; 306 }; 307 308 domain_ss3: domain-sleep-0 { 309 compatible = "domain-idle-state"; 310 arm,psci-suspend-param = <0x0200c354>; 311 entry-latency-us = <2500>; 312 exit-latency-us = <2500>; 313 min-residency-us = <9000>; 314 }; 315 }; 316 }; 317 318 dummy-sink { 319 compatible = "arm,coresight-dummy-sink"; 320 321 in-ports { 322 port { 323 eud_in: endpoint { 324 remote-endpoint = <&swao_rep_out1>; 325 }; 326 }; 327 }; 328 }; 329 330 firmware { 331 scm: scm { 332 compatible = "qcom,scm-x1e80100", "qcom,scm"; 333 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 334 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 335 qcom,dload-mode = <&tcsr 0x19000>; 336 }; 337 338 scmi { 339 compatible = "arm,scmi"; 340 mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>; 341 mbox-names = "tx", "rx"; 342 shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; 343 344 #address-cells = <1>; 345 #size-cells = <0>; 346 347 scmi_dvfs: protocol@13 { 348 reg = <0x13>; 349 #power-domain-cells = <1>; 350 }; 351 }; 352 }; 353 354 clk_virt: interconnect-0 { 355 compatible = "qcom,x1e80100-clk-virt"; 356 #interconnect-cells = <2>; 357 qcom,bcm-voters = <&apps_bcm_voter>; 358 }; 359 360 mc_virt: interconnect-1 { 361 compatible = "qcom,x1e80100-mc-virt"; 362 #interconnect-cells = <2>; 363 qcom,bcm-voters = <&apps_bcm_voter>; 364 }; 365 366 memory@80000000 { 367 device_type = "memory"; 368 /* We expect the bootloader to fill in the size */ 369 reg = <0 0x80000000 0 0>; 370 }; 371 372 pmu { 373 compatible = "arm,armv8-pmuv3"; 374 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 375 }; 376 377 psci { 378 compatible = "arm,psci-1.0"; 379 method = "smc"; 380 381 cpu_pd0: power-domain-cpu0 { 382 #power-domain-cells = <0>; 383 power-domains = <&cluster_pd0>; 384 domain-idle-states = <&cluster_c4>; 385 }; 386 387 cpu_pd1: power-domain-cpu1 { 388 #power-domain-cells = <0>; 389 power-domains = <&cluster_pd0>; 390 domain-idle-states = <&cluster_c4>; 391 }; 392 393 cpu_pd2: power-domain-cpu2 { 394 #power-domain-cells = <0>; 395 power-domains = <&cluster_pd0>; 396 domain-idle-states = <&cluster_c4>; 397 }; 398 399 cpu_pd3: power-domain-cpu3 { 400 #power-domain-cells = <0>; 401 power-domains = <&cluster_pd0>; 402 domain-idle-states = <&cluster_c4>; 403 }; 404 405 cpu_pd4: power-domain-cpu4 { 406 #power-domain-cells = <0>; 407 power-domains = <&cluster_pd1>; 408 domain-idle-states = <&cluster_c4>; 409 }; 410 411 cpu_pd5: power-domain-cpu5 { 412 #power-domain-cells = <0>; 413 power-domains = <&cluster_pd1>; 414 domain-idle-states = <&cluster_c4>; 415 }; 416 417 cpu_pd6: power-domain-cpu6 { 418 #power-domain-cells = <0>; 419 power-domains = <&cluster_pd1>; 420 domain-idle-states = <&cluster_c4>; 421 }; 422 423 cpu_pd7: power-domain-cpu7 { 424 #power-domain-cells = <0>; 425 power-domains = <&cluster_pd1>; 426 domain-idle-states = <&cluster_c4>; 427 }; 428 429 cpu_pd8: power-domain-cpu8 { 430 #power-domain-cells = <0>; 431 power-domains = <&cluster_pd2>; 432 domain-idle-states = <&cluster_c4>; 433 }; 434 435 cpu_pd9: power-domain-cpu9 { 436 #power-domain-cells = <0>; 437 power-domains = <&cluster_pd2>; 438 domain-idle-states = <&cluster_c4>; 439 }; 440 441 cpu_pd10: power-domain-cpu10 { 442 #power-domain-cells = <0>; 443 power-domains = <&cluster_pd2>; 444 domain-idle-states = <&cluster_c4>; 445 }; 446 447 cpu_pd11: power-domain-cpu11 { 448 #power-domain-cells = <0>; 449 power-domains = <&cluster_pd2>; 450 domain-idle-states = <&cluster_c4>; 451 }; 452 453 cluster_pd0: power-domain-cpu-cluster0 { 454 #power-domain-cells = <0>; 455 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 456 power-domains = <&system_pd>; 457 }; 458 459 cluster_pd1: power-domain-cpu-cluster1 { 460 #power-domain-cells = <0>; 461 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 462 power-domains = <&system_pd>; 463 }; 464 465 cluster_pd2: power-domain-cpu-cluster2 { 466 #power-domain-cells = <0>; 467 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 468 power-domains = <&system_pd>; 469 }; 470 471 system_pd: power-domain-system { 472 #power-domain-cells = <0>; 473 domain-idle-states = <&domain_ss3>; 474 }; 475 }; 476 477 reserved-memory { 478 #address-cells = <2>; 479 #size-cells = <2>; 480 ranges; 481 482 gunyah_hyp_mem: gunyah-hyp@80000000 { 483 reg = <0x0 0x80000000 0x0 0x800000>; 484 no-map; 485 }; 486 487 cpucp_log_mem: cpucp-log@80e00000 { 488 reg = <0x0 0x80e00000 0x0 0x40000>; 489 no-map; 490 }; 491 492 cpucp_mem: cpucp@80e40000 { 493 reg = <0x0 0x80e40000 0x0 0x540000>; 494 no-map; 495 }; 496 497 reserved-region@81380000 { 498 reg = <0x0 0x81380000 0x0 0x80000>; 499 no-map; 500 }; 501 502 tags_mem: tags-region@81400000 { 503 reg = <0x0 0x81400000 0x0 0x1a0000>; 504 no-map; 505 }; 506 507 xbl_ramdump_mem: xbl-ramdump@81a40000 { 508 reg = <0x0 0x81a40000 0x0 0x1c0000>; 509 no-map; 510 }; 511 512 aop_image_mem: aop-image@81c00000 { 513 reg = <0x0 0x81c00000 0x0 0x60000>; 514 no-map; 515 }; 516 517 aop_cmd_db_mem: aop-cmd-db@81c60000 { 518 compatible = "qcom,cmd-db"; 519 reg = <0x0 0x81c60000 0x0 0x20000>; 520 no-map; 521 }; 522 523 aop_config_mem: aop-config@81c80000 { 524 reg = <0x0 0x81c80000 0x0 0x20000>; 525 no-map; 526 }; 527 528 tme_crash_dump_mem: tme-crash-dump@81ca0000 { 529 reg = <0x0 0x81ca0000 0x0 0x40000>; 530 no-map; 531 }; 532 533 tme_log_mem: tme-log@81ce0000 { 534 reg = <0x0 0x81ce0000 0x0 0x4000>; 535 no-map; 536 }; 537 538 uefi_log_mem: uefi-log@81ce4000 { 539 reg = <0x0 0x81ce4000 0x0 0x10000>; 540 no-map; 541 }; 542 543 secdata_apss_mem: secdata-apss@81cff000 { 544 reg = <0x0 0x81cff000 0x0 0x1000>; 545 no-map; 546 }; 547 548 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 { 549 reg = <0x0 0x84b00000 0x0 0x800000>; 550 no-map; 551 }; 552 553 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 { 554 reg = <0x0 0x85300000 0x0 0x80000>; 555 no-map; 556 }; 557 558 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 { 559 reg = <0x0 0x866c0000 0x0 0x40000>; 560 no-map; 561 }; 562 563 spss_region_mem: spss-region@86700000 { 564 reg = <0x0 0x86700000 0x0 0x400000>; 565 no-map; 566 }; 567 568 adsp_boot_mem: adsp-boot@86b00000 { 569 reg = <0x0 0x86b00000 0x0 0xc00000>; 570 no-map; 571 }; 572 573 video_mem: video@87700000 { 574 reg = <0x0 0x87700000 0x0 0x700000>; 575 no-map; 576 }; 577 578 adspslpi_mem: adspslpi@87e00000 { 579 reg = <0x0 0x87e00000 0x0 0x3a00000>; 580 no-map; 581 }; 582 583 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 { 584 reg = <0x0 0x8b800000 0x0 0x80000>; 585 no-map; 586 }; 587 588 cdsp_mem: cdsp@8b900000 { 589 reg = <0x0 0x8b900000 0x0 0x2000000>; 590 no-map; 591 }; 592 593 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 { 594 reg = <0x0 0x8d900000 0x0 0x80000>; 595 no-map; 596 }; 597 598 gpu_microcode_mem: gpu-microcode@8d9fe000 { 599 reg = <0x0 0x8d9fe000 0x0 0x2000>; 600 no-map; 601 }; 602 603 cvp_mem: cvp@8da00000 { 604 reg = <0x0 0x8da00000 0x0 0x700000>; 605 no-map; 606 }; 607 608 camera_mem: camera@8e100000 { 609 reg = <0x0 0x8e100000 0x0 0x800000>; 610 no-map; 611 }; 612 613 av1_encoder_mem: av1-encoder@8e900000 { 614 reg = <0x0 0x8e900000 0x0 0x700000>; 615 no-map; 616 }; 617 618 reserved-region@8f000000 { 619 reg = <0x0 0x8f000000 0x0 0xa00000>; 620 no-map; 621 }; 622 623 wpss_mem: wpss@8fa00000 { 624 reg = <0x0 0x8fa00000 0x0 0x1900000>; 625 no-map; 626 }; 627 628 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 { 629 reg = <0x0 0x91300000 0x0 0x80000>; 630 no-map; 631 }; 632 633 xbl_sc_mem: xbl-sc@d8000000 { 634 reg = <0x0 0xd8000000 0x0 0x40000>; 635 no-map; 636 }; 637 638 reserved-region@d8040000 { 639 reg = <0x0 0xd8040000 0x0 0xa0000>; 640 no-map; 641 }; 642 643 qtee_mem: qtee@d80e0000 { 644 reg = <0x0 0xd80e0000 0x0 0x520000>; 645 no-map; 646 }; 647 648 ta_mem: ta@d8600000 { 649 reg = <0x0 0xd8600000 0x0 0x8a00000>; 650 no-map; 651 }; 652 653 tags_mem1: tags@e1000000 { 654 reg = <0x0 0xe1000000 0x0 0x26a0000>; 655 no-map; 656 }; 657 658 llcc_lpi_mem: llcc-lpi@ff800000 { 659 reg = <0x0 0xff800000 0x0 0x600000>; 660 no-map; 661 }; 662 663 smem_mem: smem@ffe00000 { 664 compatible = "qcom,smem"; 665 reg = <0x0 0xffe00000 0x0 0x200000>; 666 hwlocks = <&tcsr_mutex 3>; 667 no-map; 668 }; 669 }; 670 671 qup_opp_table_100mhz: opp-table-qup100mhz { 672 compatible = "operating-points-v2"; 673 674 opp-75000000 { 675 opp-hz = /bits/ 64 <75000000>; 676 required-opps = <&rpmhpd_opp_low_svs>; 677 }; 678 679 opp-100000000 { 680 opp-hz = /bits/ 64 <100000000>; 681 required-opps = <&rpmhpd_opp_svs>; 682 }; 683 }; 684 685 qup_opp_table_120mhz: opp-table-qup120mhz { 686 compatible = "operating-points-v2"; 687 688 opp-75000000 { 689 opp-hz = /bits/ 64 <75000000>; 690 required-opps = <&rpmhpd_opp_low_svs>; 691 }; 692 693 opp-120000000 { 694 opp-hz = /bits/ 64 <120000000>; 695 required-opps = <&rpmhpd_opp_svs>; 696 }; 697 }; 698 699 smp2p-adsp { 700 compatible = "qcom,smp2p"; 701 702 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 703 IPCC_MPROC_SIGNAL_SMP2P 704 IRQ_TYPE_EDGE_RISING>; 705 706 mboxes = <&ipcc IPCC_CLIENT_LPASS 707 IPCC_MPROC_SIGNAL_SMP2P>; 708 709 qcom,smem = <443>, <429>; 710 qcom,local-pid = <0>; 711 qcom,remote-pid = <2>; 712 713 smp2p_adsp_out: master-kernel { 714 qcom,entry-name = "master-kernel"; 715 #qcom,smem-state-cells = <1>; 716 }; 717 718 smp2p_adsp_in: slave-kernel { 719 qcom,entry-name = "slave-kernel"; 720 interrupt-controller; 721 #interrupt-cells = <2>; 722 }; 723 }; 724 725 smp2p-cdsp { 726 compatible = "qcom,smp2p"; 727 728 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 729 IPCC_MPROC_SIGNAL_SMP2P 730 IRQ_TYPE_EDGE_RISING>; 731 732 mboxes = <&ipcc IPCC_CLIENT_CDSP 733 IPCC_MPROC_SIGNAL_SMP2P>; 734 735 qcom,smem = <94>, <432>; 736 qcom,local-pid = <0>; 737 qcom,remote-pid = <5>; 738 739 smp2p_cdsp_out: master-kernel { 740 qcom,entry-name = "master-kernel"; 741 #qcom,smem-state-cells = <1>; 742 }; 743 744 smp2p_cdsp_in: slave-kernel { 745 qcom,entry-name = "slave-kernel"; 746 interrupt-controller; 747 #interrupt-cells = <2>; 748 }; 749 }; 750 751 soc: soc@0 { 752 compatible = "simple-bus"; 753 754 #address-cells = <2>; 755 #size-cells = <2>; 756 dma-ranges = <0 0 0 0 0x100 0>; 757 ranges = <0 0 0 0 0x100 0>; 758 759 gcc: clock-controller@100000 { 760 compatible = "qcom,x1e80100-gcc"; 761 reg = <0 0x00100000 0 0x200000>; 762 763 clocks = <&bi_tcxo_div2>, 764 <&sleep_clk>, 765 <&pcie3_phy>, 766 <&pcie4_phy>, 767 <&pcie5_phy>, 768 <&pcie6a_phy>, 769 <0>, 770 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 771 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 772 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 773 <0>, 774 <0>, 775 <0>, 776 <0>, 777 <0>, 778 <0>, 779 <0>, 780 <0>, 781 <0>, 782 <0>, 783 <0>, 784 <0>, 785 <0>, 786 <0>, 787 <0>, 788 <0>, 789 <0>, 790 <0>, 791 <0>, 792 <0>, 793 <0>, 794 <0>, 795 <0>, 796 <0>, 797 <0>, 798 <0>, 799 <0>, 800 <&ufs_mem_phy 0>, 801 <&ufs_mem_phy 1>, 802 <&ufs_mem_phy 2>; 803 804 power-domains = <&rpmhpd RPMHPD_CX>; 805 #clock-cells = <1>; 806 #reset-cells = <1>; 807 #power-domain-cells = <1>; 808 }; 809 810 ipcc: mailbox@408000 { 811 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; 812 reg = <0 0x00408000 0 0x1000>; 813 814 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 815 interrupt-controller; 816 #interrupt-cells = <3>; 817 818 #mbox-cells = <2>; 819 }; 820 821 gpi_dma2: dma-controller@800000 { 822 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 823 reg = <0 0x00800000 0 0x60000>; 824 825 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 837 838 dma-channels = <12>; 839 dma-channel-mask = <0x3e>; 840 #dma-cells = <3>; 841 842 iommus = <&apps_smmu 0x436 0x0>; 843 844 status = "disabled"; 845 }; 846 847 qupv3_2: geniqup@8c0000 { 848 compatible = "qcom,geni-se-qup"; 849 reg = <0 0x008c0000 0 0x2000>; 850 851 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 852 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 853 clock-names = "m-ahb", 854 "s-ahb"; 855 856 iommus = <&apps_smmu 0x423 0x0>; 857 858 #address-cells = <2>; 859 #size-cells = <2>; 860 ranges; 861 862 status = "disabled"; 863 864 i2c16: i2c@880000 { 865 compatible = "qcom,geni-i2c"; 866 reg = <0 0x00880000 0 0x4000>; 867 868 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 869 870 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 871 clock-names = "se"; 872 873 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 874 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 875 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 876 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 877 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 878 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 879 interconnect-names = "qup-core", 880 "qup-config", 881 "qup-memory"; 882 883 power-domains = <&rpmhpd RPMHPD_CX>; 884 required-opps = <&rpmhpd_opp_low_svs>; 885 886 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 887 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 888 dma-names = "tx", 889 "rx"; 890 891 pinctrl-0 = <&qup_i2c16_data_clk>; 892 pinctrl-names = "default"; 893 894 #address-cells = <1>; 895 #size-cells = <0>; 896 897 status = "disabled"; 898 }; 899 900 spi16: spi@880000 { 901 compatible = "qcom,geni-spi"; 902 reg = <0 0x00880000 0 0x4000>; 903 904 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 905 906 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 907 clock-names = "se"; 908 909 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 910 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 911 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 912 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 913 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 914 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 915 interconnect-names = "qup-core", 916 "qup-config", 917 "qup-memory"; 918 919 power-domains = <&rpmhpd RPMHPD_CX>; 920 operating-points-v2 = <&qup_opp_table_120mhz>; 921 922 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 923 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 924 dma-names = "tx", 925 "rx"; 926 927 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 928 pinctrl-names = "default"; 929 930 #address-cells = <1>; 931 #size-cells = <0>; 932 933 status = "disabled"; 934 }; 935 936 i2c17: i2c@884000 { 937 compatible = "qcom,geni-i2c"; 938 reg = <0 0x00884000 0 0x4000>; 939 940 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 941 942 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 943 clock-names = "se"; 944 945 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 946 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 947 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 948 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 949 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 950 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 951 interconnect-names = "qup-core", 952 "qup-config", 953 "qup-memory"; 954 955 power-domains = <&rpmhpd RPMHPD_CX>; 956 required-opps = <&rpmhpd_opp_low_svs>; 957 958 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 959 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 960 dma-names = "tx", 961 "rx"; 962 963 pinctrl-0 = <&qup_i2c17_data_clk>; 964 pinctrl-names = "default"; 965 966 #address-cells = <1>; 967 #size-cells = <0>; 968 969 status = "disabled"; 970 }; 971 972 spi17: spi@884000 { 973 compatible = "qcom,geni-spi"; 974 reg = <0 0x00884000 0 0x4000>; 975 976 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 977 978 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 979 clock-names = "se"; 980 981 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 982 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 983 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 984 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 985 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 986 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 987 interconnect-names = "qup-core", 988 "qup-config", 989 "qup-memory"; 990 991 power-domains = <&rpmhpd RPMHPD_CX>; 992 operating-points-v2 = <&qup_opp_table_120mhz>; 993 994 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 995 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 996 dma-names = "tx", 997 "rx"; 998 999 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 1000 pinctrl-names = "default"; 1001 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 1005 status = "disabled"; 1006 }; 1007 1008 i2c18: i2c@888000 { 1009 compatible = "qcom,geni-i2c"; 1010 reg = <0 0x00888000 0 0x4000>; 1011 1012 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1013 1014 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1015 clock-names = "se"; 1016 1017 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1018 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1019 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1020 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1021 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1022 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1023 interconnect-names = "qup-core", 1024 "qup-config", 1025 "qup-memory"; 1026 1027 power-domains = <&rpmhpd RPMHPD_CX>; 1028 required-opps = <&rpmhpd_opp_low_svs>; 1029 1030 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1031 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1032 dma-names = "tx", 1033 "rx"; 1034 1035 pinctrl-0 = <&qup_i2c18_data_clk>; 1036 pinctrl-names = "default"; 1037 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 1041 status = "disabled"; 1042 }; 1043 1044 spi18: spi@888000 { 1045 compatible = "qcom,geni-spi"; 1046 reg = <0 0x00888000 0 0x4000>; 1047 1048 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1049 1050 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1051 clock-names = "se"; 1052 1053 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1054 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1055 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1056 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1057 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1058 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1059 interconnect-names = "qup-core", 1060 "qup-config", 1061 "qup-memory"; 1062 1063 power-domains = <&rpmhpd RPMHPD_CX>; 1064 operating-points-v2 = <&qup_opp_table_100mhz>; 1065 1066 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1067 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1068 dma-names = "tx", 1069 "rx"; 1070 1071 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1072 pinctrl-names = "default"; 1073 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 1077 status = "disabled"; 1078 }; 1079 1080 i2c19: i2c@88c000 { 1081 compatible = "qcom,geni-i2c"; 1082 reg = <0 0x0088c000 0 0x4000>; 1083 1084 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1085 1086 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1087 clock-names = "se"; 1088 1089 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1090 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1091 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1092 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1093 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1094 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1095 interconnect-names = "qup-core", 1096 "qup-config", 1097 "qup-memory"; 1098 1099 power-domains = <&rpmhpd RPMHPD_CX>; 1100 required-opps = <&rpmhpd_opp_low_svs>; 1101 1102 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1103 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1104 dma-names = "tx", 1105 "rx"; 1106 1107 pinctrl-0 = <&qup_i2c19_data_clk>; 1108 pinctrl-names = "default"; 1109 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 1113 status = "disabled"; 1114 }; 1115 1116 spi19: spi@88c000 { 1117 compatible = "qcom,geni-spi"; 1118 reg = <0 0x0088c000 0 0x4000>; 1119 1120 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1121 1122 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1123 clock-names = "se"; 1124 1125 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1126 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1127 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1128 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1129 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1130 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1131 interconnect-names = "qup-core", 1132 "qup-config", 1133 "qup-memory"; 1134 1135 power-domains = <&rpmhpd RPMHPD_CX>; 1136 operating-points-v2 = <&qup_opp_table_100mhz>; 1137 1138 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1139 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1140 dma-names = "tx", 1141 "rx"; 1142 1143 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1144 pinctrl-names = "default"; 1145 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 1149 status = "disabled"; 1150 }; 1151 1152 i2c20: i2c@890000 { 1153 compatible = "qcom,geni-i2c"; 1154 reg = <0 0x00890000 0 0x4000>; 1155 1156 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1157 1158 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1159 clock-names = "se"; 1160 1161 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1162 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1163 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1164 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1165 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1166 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1167 interconnect-names = "qup-core", 1168 "qup-config", 1169 "qup-memory"; 1170 1171 power-domains = <&rpmhpd RPMHPD_CX>; 1172 required-opps = <&rpmhpd_opp_low_svs>; 1173 1174 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1175 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1176 dma-names = "tx", 1177 "rx"; 1178 1179 pinctrl-0 = <&qup_i2c20_data_clk>; 1180 pinctrl-names = "default"; 1181 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 1185 status = "disabled"; 1186 }; 1187 1188 spi20: spi@890000 { 1189 compatible = "qcom,geni-spi"; 1190 reg = <0 0x00890000 0 0x4000>; 1191 1192 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1193 1194 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1195 clock-names = "se"; 1196 1197 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1198 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1199 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1200 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1201 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1202 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1203 interconnect-names = "qup-core", 1204 "qup-config", 1205 "qup-memory"; 1206 1207 power-domains = <&rpmhpd RPMHPD_CX>; 1208 operating-points-v2 = <&qup_opp_table_100mhz>; 1209 1210 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1211 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1212 dma-names = "tx", 1213 "rx"; 1214 1215 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1216 pinctrl-names = "default"; 1217 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 1221 status = "disabled"; 1222 }; 1223 1224 i2c21: i2c@894000 { 1225 compatible = "qcom,geni-i2c"; 1226 reg = <0 0x00894000 0 0x4000>; 1227 1228 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1229 1230 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1231 clock-names = "se"; 1232 1233 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1234 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1235 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1236 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1237 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1238 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1239 interconnect-names = "qup-core", 1240 "qup-config", 1241 "qup-memory"; 1242 1243 power-domains = <&rpmhpd RPMHPD_CX>; 1244 required-opps = <&rpmhpd_opp_low_svs>; 1245 1246 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1247 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1248 dma-names = "tx", 1249 "rx"; 1250 1251 pinctrl-0 = <&qup_i2c21_data_clk>; 1252 pinctrl-names = "default"; 1253 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 1257 status = "disabled"; 1258 }; 1259 1260 spi21: spi@894000 { 1261 compatible = "qcom,geni-spi"; 1262 reg = <0 0x00894000 0 0x4000>; 1263 1264 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1265 1266 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1267 clock-names = "se"; 1268 1269 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1270 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1271 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1272 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1273 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1274 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1275 interconnect-names = "qup-core", 1276 "qup-config", 1277 "qup-memory"; 1278 1279 power-domains = <&rpmhpd RPMHPD_CX>; 1280 operating-points-v2 = <&qup_opp_table_100mhz>; 1281 1282 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1283 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1284 dma-names = "tx", 1285 "rx"; 1286 1287 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1288 pinctrl-names = "default"; 1289 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 1293 status = "disabled"; 1294 }; 1295 1296 uart21: serial@894000 { 1297 compatible = "qcom,geni-uart"; 1298 reg = <0 0x00894000 0 0x4000>; 1299 1300 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1301 1302 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1303 clock-names = "se"; 1304 1305 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1306 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1307 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1308 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 1309 interconnect-names = "qup-core", 1310 "qup-config"; 1311 1312 power-domains = <&rpmhpd RPMHPD_CX>; 1313 operating-points-v2 = <&qup_opp_table_100mhz>; 1314 1315 pinctrl-0 = <&qup_uart21_default>; 1316 pinctrl-names = "default"; 1317 1318 status = "disabled"; 1319 }; 1320 1321 i2c22: i2c@898000 { 1322 compatible = "qcom,geni-i2c"; 1323 reg = <0 0x00898000 0 0x4000>; 1324 1325 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1326 1327 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1328 clock-names = "se"; 1329 1330 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1331 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1332 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1333 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1334 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1335 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1336 interconnect-names = "qup-core", 1337 "qup-config", 1338 "qup-memory"; 1339 1340 power-domains = <&rpmhpd RPMHPD_CX>; 1341 required-opps = <&rpmhpd_opp_low_svs>; 1342 1343 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1344 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1345 dma-names = "tx", 1346 "rx"; 1347 1348 pinctrl-0 = <&qup_i2c22_data_clk>; 1349 pinctrl-names = "default"; 1350 1351 #address-cells = <1>; 1352 #size-cells = <0>; 1353 1354 status = "disabled"; 1355 }; 1356 1357 spi22: spi@898000 { 1358 compatible = "qcom,geni-spi"; 1359 reg = <0 0x00898000 0 0x4000>; 1360 1361 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1362 1363 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1364 clock-names = "se"; 1365 1366 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1367 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1368 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1369 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1370 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1371 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1372 interconnect-names = "qup-core", 1373 "qup-config", 1374 "qup-memory"; 1375 1376 power-domains = <&rpmhpd RPMHPD_CX>; 1377 operating-points-v2 = <&qup_opp_table_100mhz>; 1378 1379 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1380 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1381 dma-names = "tx", 1382 "rx"; 1383 1384 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1385 pinctrl-names = "default"; 1386 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 1390 status = "disabled"; 1391 }; 1392 1393 i2c23: i2c@89c000 { 1394 compatible = "qcom,geni-i2c"; 1395 reg = <0 0x0089c000 0 0x4000>; 1396 1397 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1398 1399 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1400 clock-names = "se"; 1401 1402 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1403 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1404 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1405 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1406 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1407 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1408 interconnect-names = "qup-core", 1409 "qup-config", 1410 "qup-memory"; 1411 1412 power-domains = <&rpmhpd RPMHPD_CX>; 1413 required-opps = <&rpmhpd_opp_low_svs>; 1414 1415 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1416 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1417 dma-names = "tx", 1418 "rx"; 1419 1420 pinctrl-0 = <&qup_i2c23_data_clk>; 1421 pinctrl-names = "default"; 1422 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 1426 status = "disabled"; 1427 }; 1428 1429 spi23: spi@89c000 { 1430 compatible = "qcom,geni-spi"; 1431 reg = <0 0x0089c000 0 0x4000>; 1432 1433 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1434 1435 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1436 clock-names = "se"; 1437 1438 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1439 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1440 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1441 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1442 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1443 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1444 interconnect-names = "qup-core", 1445 "qup-config", 1446 "qup-memory"; 1447 1448 power-domains = <&rpmhpd RPMHPD_CX>; 1449 operating-points-v2 = <&qup_opp_table_100mhz>; 1450 1451 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1452 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1453 dma-names = "tx", 1454 "rx"; 1455 1456 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1457 pinctrl-names = "default"; 1458 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 1462 status = "disabled"; 1463 }; 1464 }; 1465 1466 gpi_dma1: dma-controller@a00000 { 1467 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1468 reg = <0 0x00a00000 0 0x60000>; 1469 1470 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 1482 1483 dma-channels = <12>; 1484 dma-channel-mask = <0x3e>; 1485 #dma-cells = <3>; 1486 1487 iommus = <&apps_smmu 0x136 0x0>; 1488 1489 status = "disabled"; 1490 }; 1491 1492 qupv3_1: geniqup@ac0000 { 1493 compatible = "qcom,geni-se-qup"; 1494 reg = <0 0x00ac0000 0 0x2000>; 1495 1496 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1497 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1498 clock-names = "m-ahb", 1499 "s-ahb"; 1500 1501 iommus = <&apps_smmu 0x123 0x0>; 1502 1503 #address-cells = <2>; 1504 #size-cells = <2>; 1505 ranges; 1506 1507 status = "disabled"; 1508 1509 i2c8: i2c@a80000 { 1510 compatible = "qcom,geni-i2c"; 1511 reg = <0 0x00a80000 0 0x4000>; 1512 1513 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1514 1515 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1516 clock-names = "se"; 1517 1518 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1519 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1520 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1521 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1522 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1523 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1524 interconnect-names = "qup-core", 1525 "qup-config", 1526 "qup-memory"; 1527 1528 power-domains = <&rpmhpd RPMHPD_CX>; 1529 required-opps = <&rpmhpd_opp_low_svs>; 1530 1531 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1532 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1533 dma-names = "tx", 1534 "rx"; 1535 1536 pinctrl-0 = <&qup_i2c8_data_clk>; 1537 pinctrl-names = "default"; 1538 1539 #address-cells = <1>; 1540 #size-cells = <0>; 1541 1542 status = "disabled"; 1543 }; 1544 1545 spi8: spi@a80000 { 1546 compatible = "qcom,geni-spi"; 1547 reg = <0 0x00a80000 0 0x4000>; 1548 1549 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1550 1551 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1552 clock-names = "se"; 1553 1554 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1555 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1556 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1557 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1558 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1559 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1560 interconnect-names = "qup-core", 1561 "qup-config", 1562 "qup-memory"; 1563 1564 power-domains = <&rpmhpd RPMHPD_CX>; 1565 operating-points-v2 = <&qup_opp_table_120mhz>; 1566 1567 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1568 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1569 dma-names = "tx", 1570 "rx"; 1571 1572 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1573 pinctrl-names = "default"; 1574 1575 #address-cells = <1>; 1576 #size-cells = <0>; 1577 1578 status = "disabled"; 1579 }; 1580 1581 i2c9: i2c@a84000 { 1582 compatible = "qcom,geni-i2c"; 1583 reg = <0 0x00a84000 0 0x4000>; 1584 1585 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1586 1587 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1588 clock-names = "se"; 1589 1590 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1591 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1592 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1593 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1594 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1595 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1596 interconnect-names = "qup-core", 1597 "qup-config", 1598 "qup-memory"; 1599 1600 power-domains = <&rpmhpd RPMHPD_CX>; 1601 required-opps = <&rpmhpd_opp_low_svs>; 1602 1603 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1604 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1605 dma-names = "tx", 1606 "rx"; 1607 1608 pinctrl-0 = <&qup_i2c9_data_clk>; 1609 pinctrl-names = "default"; 1610 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 1614 status = "disabled"; 1615 }; 1616 1617 spi9: spi@a84000 { 1618 compatible = "qcom,geni-spi"; 1619 reg = <0 0x00a84000 0 0x4000>; 1620 1621 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1622 1623 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1624 clock-names = "se"; 1625 1626 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1627 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1628 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1629 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1630 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1631 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1632 interconnect-names = "qup-core", 1633 "qup-config", 1634 "qup-memory"; 1635 1636 power-domains = <&rpmhpd RPMHPD_CX>; 1637 operating-points-v2 = <&qup_opp_table_120mhz>; 1638 1639 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1640 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1641 dma-names = "tx", 1642 "rx"; 1643 1644 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1645 pinctrl-names = "default"; 1646 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 1650 status = "disabled"; 1651 }; 1652 1653 i2c10: i2c@a88000 { 1654 compatible = "qcom,geni-i2c"; 1655 reg = <0 0x00a88000 0 0x4000>; 1656 1657 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1658 1659 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1660 clock-names = "se"; 1661 1662 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1663 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1664 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1665 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1666 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1667 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1668 interconnect-names = "qup-core", 1669 "qup-config", 1670 "qup-memory"; 1671 1672 power-domains = <&rpmhpd RPMHPD_CX>; 1673 required-opps = <&rpmhpd_opp_low_svs>; 1674 1675 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1676 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1677 dma-names = "tx", 1678 "rx"; 1679 1680 pinctrl-0 = <&qup_i2c10_data_clk>; 1681 pinctrl-names = "default"; 1682 1683 #address-cells = <1>; 1684 #size-cells = <0>; 1685 1686 status = "disabled"; 1687 }; 1688 1689 spi10: spi@a88000 { 1690 compatible = "qcom,geni-spi"; 1691 reg = <0 0x00a88000 0 0x4000>; 1692 1693 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1694 1695 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1696 clock-names = "se"; 1697 1698 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1699 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1700 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1701 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1702 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1703 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1704 interconnect-names = "qup-core", 1705 "qup-config", 1706 "qup-memory"; 1707 1708 power-domains = <&rpmhpd RPMHPD_CX>; 1709 operating-points-v2 = <&qup_opp_table_100mhz>; 1710 1711 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1712 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1713 dma-names = "tx", 1714 "rx"; 1715 1716 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1717 pinctrl-names = "default"; 1718 1719 #address-cells = <1>; 1720 #size-cells = <0>; 1721 1722 status = "disabled"; 1723 }; 1724 1725 i2c11: i2c@a8c000 { 1726 compatible = "qcom,geni-i2c"; 1727 reg = <0 0x00a8c000 0 0x4000>; 1728 1729 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1730 1731 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1732 clock-names = "se"; 1733 1734 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1735 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1736 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1737 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1738 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1739 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1740 interconnect-names = "qup-core", 1741 "qup-config", 1742 "qup-memory"; 1743 1744 power-domains = <&rpmhpd RPMHPD_CX>; 1745 required-opps = <&rpmhpd_opp_low_svs>; 1746 1747 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1748 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1749 dma-names = "tx", 1750 "rx"; 1751 1752 pinctrl-0 = <&qup_i2c11_data_clk>; 1753 pinctrl-names = "default"; 1754 1755 #address-cells = <1>; 1756 #size-cells = <0>; 1757 1758 status = "disabled"; 1759 }; 1760 1761 spi11: spi@a8c000 { 1762 compatible = "qcom,geni-spi"; 1763 reg = <0 0x00a8c000 0 0x4000>; 1764 1765 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1766 1767 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1768 clock-names = "se"; 1769 1770 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1771 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1772 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1773 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1774 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1775 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1776 interconnect-names = "qup-core", 1777 "qup-config", 1778 "qup-memory"; 1779 1780 power-domains = <&rpmhpd RPMHPD_CX>; 1781 operating-points-v2 = <&qup_opp_table_100mhz>; 1782 1783 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1784 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1785 dma-names = "tx", 1786 "rx"; 1787 1788 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1789 pinctrl-names = "default"; 1790 1791 #address-cells = <1>; 1792 #size-cells = <0>; 1793 1794 status = "disabled"; 1795 }; 1796 1797 i2c12: i2c@a90000 { 1798 compatible = "qcom,geni-i2c"; 1799 reg = <0 0x00a90000 0 0x4000>; 1800 1801 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1802 1803 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1804 clock-names = "se"; 1805 1806 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1807 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1808 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1809 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1810 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1811 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1812 interconnect-names = "qup-core", 1813 "qup-config", 1814 "qup-memory"; 1815 1816 power-domains = <&rpmhpd RPMHPD_CX>; 1817 required-opps = <&rpmhpd_opp_low_svs>; 1818 1819 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1820 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1821 dma-names = "tx", 1822 "rx"; 1823 1824 pinctrl-0 = <&qup_i2c12_data_clk>; 1825 pinctrl-names = "default"; 1826 1827 #address-cells = <1>; 1828 #size-cells = <0>; 1829 1830 status = "disabled"; 1831 }; 1832 1833 spi12: spi@a90000 { 1834 compatible = "qcom,geni-spi"; 1835 reg = <0 0x00a90000 0 0x4000>; 1836 1837 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1838 1839 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1840 clock-names = "se"; 1841 1842 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1843 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1844 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1845 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1846 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1847 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1848 interconnect-names = "qup-core", 1849 "qup-config", 1850 "qup-memory"; 1851 1852 power-domains = <&rpmhpd RPMHPD_CX>; 1853 operating-points-v2 = <&qup_opp_table_100mhz>; 1854 1855 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1856 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1857 dma-names = "tx", 1858 "rx"; 1859 1860 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1861 pinctrl-names = "default"; 1862 1863 #address-cells = <1>; 1864 #size-cells = <0>; 1865 1866 status = "disabled"; 1867 }; 1868 1869 i2c13: i2c@a94000 { 1870 compatible = "qcom,geni-i2c"; 1871 reg = <0 0x00a94000 0 0x4000>; 1872 1873 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1874 1875 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1876 clock-names = "se"; 1877 1878 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1879 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1880 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1881 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1882 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1883 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1884 interconnect-names = "qup-core", 1885 "qup-config", 1886 "qup-memory"; 1887 1888 power-domains = <&rpmhpd RPMHPD_CX>; 1889 required-opps = <&rpmhpd_opp_low_svs>; 1890 1891 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1892 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1893 dma-names = "tx", 1894 "rx"; 1895 1896 pinctrl-0 = <&qup_i2c13_data_clk>; 1897 pinctrl-names = "default"; 1898 1899 #address-cells = <1>; 1900 #size-cells = <0>; 1901 1902 status = "disabled"; 1903 }; 1904 1905 spi13: spi@a94000 { 1906 compatible = "qcom,geni-spi"; 1907 reg = <0 0x00a94000 0 0x4000>; 1908 1909 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1910 1911 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1912 clock-names = "se"; 1913 1914 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1915 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1916 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1917 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1918 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1919 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1920 interconnect-names = "qup-core", 1921 "qup-config", 1922 "qup-memory"; 1923 1924 power-domains = <&rpmhpd RPMHPD_CX>; 1925 operating-points-v2 = <&qup_opp_table_100mhz>; 1926 1927 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1928 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1929 dma-names = "tx", 1930 "rx"; 1931 1932 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1933 pinctrl-names = "default"; 1934 1935 #address-cells = <1>; 1936 #size-cells = <0>; 1937 1938 status = "disabled"; 1939 }; 1940 1941 i2c14: i2c@a98000 { 1942 compatible = "qcom,geni-i2c"; 1943 reg = <0 0x00a98000 0 0x4000>; 1944 1945 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1946 1947 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1948 clock-names = "se"; 1949 1950 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1951 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1952 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1953 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1954 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1955 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1956 interconnect-names = "qup-core", 1957 "qup-config", 1958 "qup-memory"; 1959 1960 power-domains = <&rpmhpd RPMHPD_CX>; 1961 required-opps = <&rpmhpd_opp_low_svs>; 1962 1963 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1964 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1965 dma-names = "tx", 1966 "rx"; 1967 1968 pinctrl-0 = <&qup_i2c14_data_clk>; 1969 pinctrl-names = "default"; 1970 1971 #address-cells = <1>; 1972 #size-cells = <0>; 1973 1974 status = "disabled"; 1975 }; 1976 1977 spi14: spi@a98000 { 1978 compatible = "qcom,geni-spi"; 1979 reg = <0 0x00a98000 0 0x4000>; 1980 1981 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1982 1983 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1984 clock-names = "se"; 1985 1986 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1987 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1988 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1989 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1990 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1991 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1992 interconnect-names = "qup-core", 1993 "qup-config", 1994 "qup-memory"; 1995 1996 power-domains = <&rpmhpd RPMHPD_CX>; 1997 operating-points-v2 = <&qup_opp_table_100mhz>; 1998 1999 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2000 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2001 dma-names = "tx", 2002 "rx"; 2003 2004 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2005 pinctrl-names = "default"; 2006 2007 #address-cells = <1>; 2008 #size-cells = <0>; 2009 2010 status = "disabled"; 2011 }; 2012 2013 uart14: serial@a98000 { 2014 compatible = "qcom,geni-uart"; 2015 reg = <0 0x00a98000 0 0x4000>; 2016 2017 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 2018 2019 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2020 clock-names = "se"; 2021 2022 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2023 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2024 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2025 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2026 interconnect-names = "qup-core", 2027 "qup-config"; 2028 2029 power-domains = <&rpmhpd RPMHPD_CX>; 2030 operating-points-v2 = <&qup_opp_table_100mhz>; 2031 2032 pinctrl-0 = <&qup_uart14_default>; 2033 pinctrl-names = "default"; 2034 2035 status = "disabled"; 2036 }; 2037 2038 i2c15: i2c@a9c000 { 2039 compatible = "qcom,geni-i2c"; 2040 reg = <0 0x00a9c000 0 0x4000>; 2041 2042 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 2043 2044 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2045 clock-names = "se"; 2046 2047 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2048 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2049 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2050 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2051 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2052 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2053 interconnect-names = "qup-core", 2054 "qup-config", 2055 "qup-memory"; 2056 2057 power-domains = <&rpmhpd RPMHPD_CX>; 2058 required-opps = <&rpmhpd_opp_low_svs>; 2059 2060 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2061 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2062 dma-names = "tx", 2063 "rx"; 2064 2065 pinctrl-0 = <&qup_i2c15_data_clk>; 2066 pinctrl-names = "default"; 2067 2068 #address-cells = <1>; 2069 #size-cells = <0>; 2070 2071 status = "disabled"; 2072 }; 2073 2074 spi15: spi@a9c000 { 2075 compatible = "qcom,geni-spi"; 2076 reg = <0 0x00a9c000 0 0x4000>; 2077 2078 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 2079 2080 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2081 clock-names = "se"; 2082 2083 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2084 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2085 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2086 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2087 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2088 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2089 interconnect-names = "qup-core", 2090 "qup-config", 2091 "qup-memory"; 2092 2093 power-domains = <&rpmhpd RPMHPD_CX>; 2094 operating-points-v2 = <&qup_opp_table_100mhz>; 2095 2096 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2097 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2098 dma-names = "tx", 2099 "rx"; 2100 2101 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2102 pinctrl-names = "default"; 2103 2104 #address-cells = <1>; 2105 #size-cells = <0>; 2106 2107 status = "disabled"; 2108 }; 2109 }; 2110 2111 gpi_dma0: dma-controller@b00000 { 2112 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 2113 reg = <0 0x00b00000 0 0x60000>; 2114 2115 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 2125 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 2126 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 2127 2128 dma-channels = <12>; 2129 dma-channel-mask = <0x3e>; 2130 #dma-cells = <3>; 2131 2132 iommus = <&apps_smmu 0x456 0x0>; 2133 2134 status = "disabled"; 2135 }; 2136 2137 qupv3_0: geniqup@bc0000 { 2138 compatible = "qcom,geni-se-qup"; 2139 reg = <0 0x00bc0000 0 0x2000>; 2140 2141 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 2142 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 2143 clock-names = "m-ahb", 2144 "s-ahb"; 2145 2146 iommus = <&apps_smmu 0x443 0x0>; 2147 #address-cells = <2>; 2148 #size-cells = <2>; 2149 ranges; 2150 2151 status = "disabled"; 2152 2153 i2c0: i2c@b80000 { 2154 compatible = "qcom,geni-i2c"; 2155 reg = <0 0x00b80000 0 0x4000>; 2156 2157 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2158 2159 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2160 clock-names = "se"; 2161 2162 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2163 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2164 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2165 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2166 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2167 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2168 interconnect-names = "qup-core", 2169 "qup-config", 2170 "qup-memory"; 2171 2172 power-domains = <&rpmhpd RPMHPD_CX>; 2173 required-opps = <&rpmhpd_opp_low_svs>; 2174 2175 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 2176 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 2177 dma-names = "tx", 2178 "rx"; 2179 2180 pinctrl-0 = <&qup_i2c0_data_clk>; 2181 pinctrl-names = "default"; 2182 2183 #address-cells = <1>; 2184 #size-cells = <0>; 2185 2186 status = "disabled"; 2187 }; 2188 2189 spi0: spi@b80000 { 2190 compatible = "qcom,geni-spi"; 2191 reg = <0 0x00b80000 0 0x4000>; 2192 2193 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2194 2195 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2196 clock-names = "se"; 2197 2198 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2199 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2200 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2201 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2202 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2203 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2204 interconnect-names = "qup-core", 2205 "qup-config", 2206 "qup-memory"; 2207 2208 power-domains = <&rpmhpd RPMHPD_CX>; 2209 operating-points-v2 = <&qup_opp_table_120mhz>; 2210 2211 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 2212 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 2213 dma-names = "tx", 2214 "rx"; 2215 2216 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 2217 pinctrl-names = "default"; 2218 2219 #address-cells = <1>; 2220 #size-cells = <0>; 2221 2222 status = "disabled"; 2223 }; 2224 2225 i2c1: i2c@b84000 { 2226 compatible = "qcom,geni-i2c"; 2227 reg = <0 0x00b84000 0 0x4000>; 2228 2229 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2230 2231 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2232 clock-names = "se"; 2233 2234 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2235 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2236 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2237 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2238 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2239 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2240 interconnect-names = "qup-core", 2241 "qup-config", 2242 "qup-memory"; 2243 2244 power-domains = <&rpmhpd RPMHPD_CX>; 2245 required-opps = <&rpmhpd_opp_low_svs>; 2246 2247 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 2248 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 2249 dma-names = "tx", 2250 "rx"; 2251 2252 pinctrl-0 = <&qup_i2c1_data_clk>; 2253 pinctrl-names = "default"; 2254 2255 #address-cells = <1>; 2256 #size-cells = <0>; 2257 2258 status = "disabled"; 2259 }; 2260 2261 spi1: spi@b84000 { 2262 compatible = "qcom,geni-spi"; 2263 reg = <0 0x00b84000 0 0x4000>; 2264 2265 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2266 2267 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2268 clock-names = "se"; 2269 2270 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2271 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2272 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2273 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2274 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2275 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2276 interconnect-names = "qup-core", 2277 "qup-config", 2278 "qup-memory"; 2279 2280 power-domains = <&rpmhpd RPMHPD_CX>; 2281 operating-points-v2 = <&qup_opp_table_120mhz>; 2282 2283 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 2284 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 2285 dma-names = "tx", 2286 "rx"; 2287 2288 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 2289 pinctrl-names = "default"; 2290 2291 #address-cells = <1>; 2292 #size-cells = <0>; 2293 2294 status = "disabled"; 2295 }; 2296 2297 i2c2: i2c@b88000 { 2298 compatible = "qcom,geni-i2c"; 2299 reg = <0 0x00b88000 0 0x4000>; 2300 2301 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2302 2303 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2304 clock-names = "se"; 2305 2306 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2307 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2308 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2309 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2310 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2311 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2312 interconnect-names = "qup-core", 2313 "qup-config", 2314 "qup-memory"; 2315 2316 power-domains = <&rpmhpd RPMHPD_CX>; 2317 required-opps = <&rpmhpd_opp_low_svs>; 2318 2319 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 2320 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 2321 dma-names = "tx", 2322 "rx"; 2323 2324 pinctrl-0 = <&qup_i2c2_data_clk>; 2325 pinctrl-names = "default"; 2326 2327 #address-cells = <1>; 2328 #size-cells = <0>; 2329 2330 status = "disabled"; 2331 }; 2332 2333 uart2: serial@b88000 { 2334 compatible = "qcom,geni-uart"; 2335 reg = <0 0x00b88000 0 0x4000>; 2336 2337 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2338 2339 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2340 clock-names = "se"; 2341 2342 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2343 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2344 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2345 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2346 interconnect-names = "qup-core", 2347 "qup-config"; 2348 2349 power-domains = <&rpmhpd RPMHPD_CX>; 2350 operating-points-v2 = <&qup_opp_table_100mhz>; 2351 2352 pinctrl-0 = <&qup_uart2_default>; 2353 pinctrl-names = "default"; 2354 2355 status = "disabled"; 2356 }; 2357 2358 spi2: spi@b88000 { 2359 compatible = "qcom,geni-spi"; 2360 reg = <0 0x00b88000 0 0x4000>; 2361 2362 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2363 2364 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2365 clock-names = "se"; 2366 2367 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2368 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2369 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2370 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2371 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2372 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2373 interconnect-names = "qup-core", 2374 "qup-config", 2375 "qup-memory"; 2376 2377 power-domains = <&rpmhpd RPMHPD_CX>; 2378 operating-points-v2 = <&qup_opp_table_100mhz>; 2379 2380 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2381 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2382 dma-names = "tx", 2383 "rx"; 2384 2385 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2386 pinctrl-names = "default"; 2387 2388 #address-cells = <1>; 2389 #size-cells = <0>; 2390 2391 status = "disabled"; 2392 }; 2393 2394 i2c3: i2c@b8c000 { 2395 compatible = "qcom,geni-i2c"; 2396 reg = <0 0x00b8c000 0 0x4000>; 2397 2398 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2399 2400 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2401 clock-names = "se"; 2402 2403 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2404 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2405 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2406 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2407 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2408 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2409 interconnect-names = "qup-core", 2410 "qup-config", 2411 "qup-memory"; 2412 2413 power-domains = <&rpmhpd RPMHPD_CX>; 2414 required-opps = <&rpmhpd_opp_low_svs>; 2415 2416 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2417 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2418 dma-names = "tx", 2419 "rx"; 2420 2421 pinctrl-0 = <&qup_i2c3_data_clk>; 2422 pinctrl-names = "default"; 2423 2424 #address-cells = <1>; 2425 #size-cells = <0>; 2426 2427 status = "disabled"; 2428 }; 2429 2430 spi3: spi@b8c000 { 2431 compatible = "qcom,geni-spi"; 2432 reg = <0 0x00b8c000 0 0x4000>; 2433 2434 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2435 2436 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2437 clock-names = "se"; 2438 2439 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2440 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2441 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2442 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2443 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2444 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2445 interconnect-names = "qup-core", 2446 "qup-config", 2447 "qup-memory"; 2448 2449 power-domains = <&rpmhpd RPMHPD_CX>; 2450 operating-points-v2 = <&qup_opp_table_100mhz>; 2451 2452 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2453 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2454 dma-names = "tx", 2455 "rx"; 2456 2457 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2458 pinctrl-names = "default"; 2459 2460 #address-cells = <1>; 2461 #size-cells = <0>; 2462 2463 status = "disabled"; 2464 }; 2465 2466 i2c4: i2c@b90000 { 2467 compatible = "qcom,geni-i2c"; 2468 reg = <0 0x00b90000 0 0x4000>; 2469 2470 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2471 2472 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2473 clock-names = "se"; 2474 2475 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2476 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2477 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2478 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2479 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2480 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2481 interconnect-names = "qup-core", 2482 "qup-config", 2483 "qup-memory"; 2484 2485 power-domains = <&rpmhpd RPMHPD_CX>; 2486 required-opps = <&rpmhpd_opp_low_svs>; 2487 2488 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2489 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2490 dma-names = "tx", 2491 "rx"; 2492 2493 pinctrl-0 = <&qup_i2c4_data_clk>; 2494 pinctrl-names = "default"; 2495 2496 #address-cells = <1>; 2497 #size-cells = <0>; 2498 2499 status = "disabled"; 2500 }; 2501 2502 spi4: spi@b90000 { 2503 compatible = "qcom,geni-spi"; 2504 reg = <0 0x00b90000 0 0x4000>; 2505 2506 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2507 2508 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2509 clock-names = "se"; 2510 2511 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2512 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2513 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2514 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2515 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2516 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2517 interconnect-names = "qup-core", 2518 "qup-config", 2519 "qup-memory"; 2520 2521 power-domains = <&rpmhpd RPMHPD_CX>; 2522 operating-points-v2 = <&qup_opp_table_100mhz>; 2523 2524 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2525 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2526 dma-names = "tx", 2527 "rx"; 2528 2529 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2530 pinctrl-names = "default"; 2531 2532 #address-cells = <1>; 2533 #size-cells = <0>; 2534 2535 status = "disabled"; 2536 }; 2537 2538 i2c5: i2c@b94000 { 2539 compatible = "qcom,geni-i2c"; 2540 reg = <0 0x00b94000 0 0x4000>; 2541 2542 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2543 2544 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2545 clock-names = "se"; 2546 2547 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2548 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2549 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2550 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2551 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2552 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2553 interconnect-names = "qup-core", 2554 "qup-config", 2555 "qup-memory"; 2556 2557 power-domains = <&rpmhpd RPMHPD_CX>; 2558 required-opps = <&rpmhpd_opp_low_svs>; 2559 2560 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2561 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2562 dma-names = "tx", 2563 "rx"; 2564 2565 pinctrl-0 = <&qup_i2c5_data_clk>; 2566 pinctrl-names = "default"; 2567 2568 #address-cells = <1>; 2569 #size-cells = <0>; 2570 2571 status = "disabled"; 2572 }; 2573 2574 spi5: spi@b94000 { 2575 compatible = "qcom,geni-spi"; 2576 reg = <0 0x00b94000 0 0x4000>; 2577 2578 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2579 2580 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2581 clock-names = "se"; 2582 2583 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2584 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2585 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2586 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2587 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2588 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2589 interconnect-names = "qup-core", 2590 "qup-config", 2591 "qup-memory"; 2592 2593 power-domains = <&rpmhpd RPMHPD_CX>; 2594 operating-points-v2 = <&qup_opp_table_100mhz>; 2595 2596 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2597 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2598 dma-names = "tx", 2599 "rx"; 2600 2601 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2602 pinctrl-names = "default"; 2603 2604 #address-cells = <1>; 2605 #size-cells = <0>; 2606 2607 status = "disabled"; 2608 }; 2609 2610 i2c6: i2c@b98000 { 2611 compatible = "qcom,geni-i2c"; 2612 reg = <0 0x00b98000 0 0x4000>; 2613 2614 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2615 2616 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2617 clock-names = "se"; 2618 2619 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2620 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2621 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2622 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2623 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2624 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2625 interconnect-names = "qup-core", 2626 "qup-config", 2627 "qup-memory"; 2628 2629 power-domains = <&rpmhpd RPMHPD_CX>; 2630 required-opps = <&rpmhpd_opp_low_svs>; 2631 2632 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2633 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2634 dma-names = "tx", 2635 "rx"; 2636 2637 pinctrl-0 = <&qup_i2c6_data_clk>; 2638 pinctrl-names = "default"; 2639 2640 #address-cells = <1>; 2641 #size-cells = <0>; 2642 2643 status = "disabled"; 2644 }; 2645 2646 spi6: spi@b98000 { 2647 compatible = "qcom,geni-spi"; 2648 reg = <0 0x00b98000 0 0x4000>; 2649 2650 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2651 2652 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2653 clock-names = "se"; 2654 2655 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2656 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2657 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2658 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2659 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2660 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2661 interconnect-names = "qup-core", 2662 "qup-config", 2663 "qup-memory"; 2664 2665 power-domains = <&rpmhpd RPMHPD_CX>; 2666 operating-points-v2 = <&qup_opp_table_100mhz>; 2667 2668 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2669 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2670 dma-names = "tx", 2671 "rx"; 2672 2673 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2674 pinctrl-names = "default"; 2675 2676 #address-cells = <1>; 2677 #size-cells = <0>; 2678 2679 status = "disabled"; 2680 }; 2681 2682 i2c7: i2c@b9c000 { 2683 compatible = "qcom,geni-i2c"; 2684 reg = <0 0x00b9c000 0 0x4000>; 2685 2686 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2687 2688 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2689 clock-names = "se"; 2690 2691 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2692 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2693 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2694 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2695 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2696 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2697 interconnect-names = "qup-core", 2698 "qup-config", 2699 "qup-memory"; 2700 2701 power-domains = <&rpmhpd RPMHPD_CX>; 2702 required-opps = <&rpmhpd_opp_low_svs>; 2703 2704 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2705 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2706 dma-names = "tx", 2707 "rx"; 2708 2709 pinctrl-0 = <&qup_i2c7_data_clk>; 2710 pinctrl-names = "default"; 2711 2712 #address-cells = <1>; 2713 #size-cells = <0>; 2714 2715 status = "disabled"; 2716 }; 2717 2718 spi7: spi@b9c000 { 2719 compatible = "qcom,geni-spi"; 2720 reg = <0 0x00b9c000 0 0x4000>; 2721 2722 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2723 2724 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2725 clock-names = "se"; 2726 2727 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2728 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2729 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2730 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2731 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2732 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2733 interconnect-names = "qup-core", 2734 "qup-config", 2735 "qup-memory"; 2736 2737 power-domains = <&rpmhpd RPMHPD_CX>; 2738 operating-points-v2 = <&qup_opp_table_100mhz>; 2739 2740 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2741 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2742 dma-names = "tx", 2743 "rx"; 2744 2745 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2746 pinctrl-names = "default"; 2747 2748 #address-cells = <1>; 2749 #size-cells = <0>; 2750 2751 status = "disabled"; 2752 }; 2753 }; 2754 2755 tsens0: thermal-sensor@c271000 { 2756 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2757 reg = <0 0x0c271000 0 0x1000>, 2758 <0 0x0c222000 0 0x1000>; 2759 2760 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2761 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2762 interrupt-names = "uplow", 2763 "critical"; 2764 2765 #qcom,sensors = <16>; 2766 2767 #thermal-sensor-cells = <1>; 2768 }; 2769 2770 tsens1: thermal-sensor@c272000 { 2771 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2772 reg = <0 0x0c272000 0 0x1000>, 2773 <0 0x0c223000 0 0x1000>; 2774 2775 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2776 <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2777 interrupt-names = "uplow", 2778 "critical"; 2779 2780 #qcom,sensors = <16>; 2781 2782 #thermal-sensor-cells = <1>; 2783 }; 2784 2785 tsens2: thermal-sensor@c273000 { 2786 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2787 reg = <0 0x0c273000 0 0x1000>, 2788 <0 0x0c224000 0 0x1000>; 2789 2790 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>, 2791 <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; 2792 interrupt-names = "uplow", 2793 "critical"; 2794 2795 #qcom,sensors = <16>; 2796 2797 #thermal-sensor-cells = <1>; 2798 }; 2799 2800 tsens3: thermal-sensor@c274000 { 2801 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2802 reg = <0 0x0c274000 0 0x1000>, 2803 <0 0x0c225000 0 0x1000>; 2804 2805 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>, 2806 <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; 2807 interrupt-names = "uplow", 2808 "critical"; 2809 2810 #qcom,sensors = <16>; 2811 2812 #thermal-sensor-cells = <1>; 2813 }; 2814 2815 usb_1_ss0_hsphy: phy@fd3000 { 2816 compatible = "qcom,x1e80100-snps-eusb2-phy", 2817 "qcom,sm8550-snps-eusb2-phy"; 2818 reg = <0 0x00fd3000 0 0x154>; 2819 #phy-cells = <0>; 2820 2821 clocks = <&rpmhcc RPMH_CXO_CLK>; 2822 clock-names = "ref"; 2823 2824 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2825 2826 status = "disabled"; 2827 }; 2828 2829 usb_1_ss0_qmpphy: phy@fd5000 { 2830 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2831 reg = <0 0x00fd5000 0 0x4000>; 2832 2833 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2834 <&rpmhcc RPMH_CXO_CLK>, 2835 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2836 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2837 clock-names = "aux", 2838 "ref", 2839 "com_aux", 2840 "usb3_pipe"; 2841 2842 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2843 2844 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2845 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>; 2846 reset-names = "phy", 2847 "common"; 2848 2849 #clock-cells = <1>; 2850 #phy-cells = <1>; 2851 2852 mode-switch; 2853 orientation-switch; 2854 2855 status = "disabled"; 2856 2857 ports { 2858 #address-cells = <1>; 2859 #size-cells = <0>; 2860 2861 port@0 { 2862 reg = <0>; 2863 2864 usb_1_ss0_qmpphy_out: endpoint { 2865 }; 2866 }; 2867 2868 port@1 { 2869 reg = <1>; 2870 2871 usb_1_ss0_qmpphy_usb_ss_in: endpoint { 2872 remote-endpoint = <&usb_1_ss0_dwc3_ss>; 2873 }; 2874 }; 2875 2876 port@2 { 2877 reg = <2>; 2878 2879 usb_1_ss0_qmpphy_dp_in: endpoint { 2880 remote-endpoint = <&mdss_dp0_out>; 2881 }; 2882 }; 2883 }; 2884 }; 2885 2886 usb_1_ss1_hsphy: phy@fd9000 { 2887 compatible = "qcom,x1e80100-snps-eusb2-phy", 2888 "qcom,sm8550-snps-eusb2-phy"; 2889 reg = <0 0x00fd9000 0 0x154>; 2890 #phy-cells = <0>; 2891 2892 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2893 clock-names = "ref"; 2894 2895 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2896 2897 status = "disabled"; 2898 }; 2899 2900 usb_1_ss1_qmpphy: phy@fda000 { 2901 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2902 reg = <0 0x00fda000 0 0x4000>; 2903 2904 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2905 <&tcsr TCSR_USB4_1_CLKREF_EN>, 2906 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2907 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2908 clock-names = "aux", 2909 "ref", 2910 "com_aux", 2911 "usb3_pipe"; 2912 2913 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2914 2915 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2916 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>; 2917 reset-names = "phy", 2918 "common"; 2919 2920 #clock-cells = <1>; 2921 #phy-cells = <1>; 2922 2923 mode-switch; 2924 orientation-switch; 2925 2926 status = "disabled"; 2927 2928 ports { 2929 #address-cells = <1>; 2930 #size-cells = <0>; 2931 2932 port@0 { 2933 reg = <0>; 2934 2935 usb_1_ss1_qmpphy_out: endpoint { 2936 }; 2937 }; 2938 2939 port@1 { 2940 reg = <1>; 2941 2942 usb_1_ss1_qmpphy_usb_ss_in: endpoint { 2943 remote-endpoint = <&usb_1_ss1_dwc3_ss>; 2944 }; 2945 }; 2946 2947 port@2 { 2948 reg = <2>; 2949 2950 usb_1_ss1_qmpphy_dp_in: endpoint { 2951 remote-endpoint = <&mdss_dp1_out>; 2952 }; 2953 }; 2954 }; 2955 }; 2956 2957 usb_1_ss2_hsphy: phy@fde000 { 2958 compatible = "qcom,x1e80100-snps-eusb2-phy", 2959 "qcom,sm8550-snps-eusb2-phy"; 2960 reg = <0 0x00fde000 0 0x154>; 2961 #phy-cells = <0>; 2962 2963 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 2964 clock-names = "ref"; 2965 2966 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 2967 2968 status = "disabled"; 2969 }; 2970 2971 usb_1_ss2_qmpphy: phy@fdf000 { 2972 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2973 reg = <0 0x00fdf000 0 0x4000>; 2974 2975 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 2976 <&tcsr TCSR_USB4_2_CLKREF_EN>, 2977 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 2978 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 2979 clock-names = "aux", 2980 "ref", 2981 "com_aux", 2982 "usb3_pipe"; 2983 2984 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 2985 2986 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 2987 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>; 2988 reset-names = "phy", 2989 "common"; 2990 2991 #clock-cells = <1>; 2992 #phy-cells = <1>; 2993 2994 mode-switch; 2995 orientation-switch; 2996 2997 status = "disabled"; 2998 2999 ports { 3000 #address-cells = <1>; 3001 #size-cells = <0>; 3002 3003 port@0 { 3004 reg = <0>; 3005 3006 usb_1_ss2_qmpphy_out: endpoint { 3007 }; 3008 }; 3009 3010 port@1 { 3011 reg = <1>; 3012 3013 usb_1_ss2_qmpphy_usb_ss_in: endpoint { 3014 remote-endpoint = <&usb_1_ss2_dwc3_ss>; 3015 }; 3016 }; 3017 3018 port@2 { 3019 reg = <2>; 3020 3021 usb_1_ss2_qmpphy_dp_in: endpoint { 3022 remote-endpoint = <&mdss_dp2_out>; 3023 }; 3024 }; 3025 }; 3026 }; 3027 3028 rng: rng@10c3000 { 3029 compatible = "qcom,x1e80100-trng", "qcom,trng"; 3030 reg = <0x0 0x010c3000 0x0 0x1000>; 3031 }; 3032 3033 cnoc_main: interconnect@1500000 { 3034 compatible = "qcom,x1e80100-cnoc-main"; 3035 reg = <0 0x01500000 0 0x14400>; 3036 3037 qcom,bcm-voters = <&apps_bcm_voter>; 3038 3039 #interconnect-cells = <2>; 3040 }; 3041 3042 config_noc: interconnect@1600000 { 3043 compatible = "qcom,x1e80100-cnoc-cfg"; 3044 reg = <0 0x01600000 0 0x6600>; 3045 3046 qcom,bcm-voters = <&apps_bcm_voter>; 3047 3048 #interconnect-cells = <2>; 3049 }; 3050 3051 system_noc: interconnect@1680000 { 3052 compatible = "qcom,x1e80100-system-noc"; 3053 reg = <0 0x01680000 0 0x1c080>; 3054 3055 qcom,bcm-voters = <&apps_bcm_voter>; 3056 3057 #interconnect-cells = <2>; 3058 }; 3059 3060 pcie_south_anoc: interconnect@16c0000 { 3061 compatible = "qcom,x1e80100-pcie-south-anoc"; 3062 reg = <0 0x016c0000 0 0xd080>; 3063 3064 qcom,bcm-voters = <&apps_bcm_voter>; 3065 3066 #interconnect-cells = <2>; 3067 }; 3068 3069 pcie_center_anoc: interconnect@16d0000 { 3070 compatible = "qcom,x1e80100-pcie-center-anoc"; 3071 reg = <0 0x016d0000 0 0x7000>; 3072 3073 qcom,bcm-voters = <&apps_bcm_voter>; 3074 3075 #interconnect-cells = <2>; 3076 }; 3077 3078 aggre1_noc: interconnect@16e0000 { 3079 compatible = "qcom,x1e80100-aggre1-noc"; 3080 reg = <0 0x016e0000 0 0x14400>; 3081 3082 qcom,bcm-voters = <&apps_bcm_voter>; 3083 3084 #interconnect-cells = <2>; 3085 }; 3086 3087 aggre2_noc: interconnect@1700000 { 3088 compatible = "qcom,x1e80100-aggre2-noc"; 3089 reg = <0 0x01700000 0 0x1c400>; 3090 3091 qcom,bcm-voters = <&apps_bcm_voter>; 3092 3093 #interconnect-cells = <2>; 3094 }; 3095 3096 pcie_north_anoc: interconnect@1740000 { 3097 compatible = "qcom,x1e80100-pcie-north-anoc"; 3098 reg = <0 0x01740000 0 0x9080>; 3099 3100 qcom,bcm-voters = <&apps_bcm_voter>; 3101 3102 #interconnect-cells = <2>; 3103 }; 3104 3105 usb_center_anoc: interconnect@1750000 { 3106 compatible = "qcom,x1e80100-usb-center-anoc"; 3107 reg = <0 0x01750000 0 0x8800>; 3108 3109 qcom,bcm-voters = <&apps_bcm_voter>; 3110 3111 #interconnect-cells = <2>; 3112 }; 3113 3114 usb_north_anoc: interconnect@1760000 { 3115 compatible = "qcom,x1e80100-usb-north-anoc"; 3116 reg = <0 0x01760000 0 0x7080>; 3117 3118 qcom,bcm-voters = <&apps_bcm_voter>; 3119 3120 #interconnect-cells = <2>; 3121 }; 3122 3123 usb_south_anoc: interconnect@1770000 { 3124 compatible = "qcom,x1e80100-usb-south-anoc"; 3125 reg = <0 0x01770000 0 0xf080>; 3126 3127 qcom,bcm-voters = <&apps_bcm_voter>; 3128 3129 #interconnect-cells = <2>; 3130 }; 3131 3132 mmss_noc: interconnect@1780000 { 3133 compatible = "qcom,x1e80100-mmss-noc"; 3134 reg = <0 0x01780000 0 0x5b800>; 3135 3136 qcom,bcm-voters = <&apps_bcm_voter>; 3137 3138 #interconnect-cells = <2>; 3139 }; 3140 3141 pcie3: pcie@1bd0000 { 3142 device_type = "pci"; 3143 compatible = "qcom,pcie-x1e80100"; 3144 reg = <0x0 0x01bd0000 0x0 0x3000>, 3145 <0x0 0x78000000 0x0 0xf20>, 3146 <0x0 0x78000f40 0x0 0xa8>, 3147 <0x0 0x78001000 0x0 0x1000>, 3148 <0x0 0x78100000 0x0 0x100000>, 3149 <0x0 0x01bd3000 0x0 0x1000>; 3150 reg-names = "parf", 3151 "dbi", 3152 "elbi", 3153 "atu", 3154 "config", 3155 "mhi"; 3156 #address-cells = <3>; 3157 #size-cells = <2>; 3158 ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>, 3159 <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>, 3160 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; 3161 bus-range = <0x00 0xff>; 3162 3163 dma-coherent; 3164 3165 linux,pci-domain = <3>; 3166 num-lanes = <8>; 3167 3168 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 3169 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 3170 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3171 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 3172 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 3173 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 3174 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 3175 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 3176 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 3177 interrupt-names = "msi0", 3178 "msi1", 3179 "msi2", 3180 "msi3", 3181 "msi4", 3182 "msi5", 3183 "msi6", 3184 "msi7", 3185 "global"; 3186 3187 #interrupt-cells = <1>; 3188 interrupt-map-mask = <0 0 0 0x7>; 3189 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 3190 <0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 3191 <0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 3192 <0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3193 3194 clocks = <&gcc GCC_PCIE_3_AUX_CLK>, 3195 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 3196 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 3197 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 3198 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, 3199 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3200 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3201 clock-names = "aux", 3202 "cfg", 3203 "bus_master", 3204 "bus_slave", 3205 "slave_q2a", 3206 "noc_aggr", 3207 "cnoc_sf_axi"; 3208 3209 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 3210 assigned-clock-rates = <19200000>; 3211 3212 interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS 3213 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3214 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3215 &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ACTIVE_ONLY>; 3216 interconnect-names = "pcie-mem", 3217 "cpu-pcie"; 3218 3219 resets = <&gcc GCC_PCIE_3_BCR>, 3220 <&gcc GCC_PCIE_3_LINK_DOWN_BCR>; 3221 reset-names = "pci", 3222 "link_down"; 3223 3224 power-domains = <&gcc GCC_PCIE_3_GDSC>; 3225 3226 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 3227 0x5555 0x5555 0x5555 0x5555>; 3228 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; 3229 3230 operating-points-v2 = <&pcie3_opp_table>; 3231 3232 status = "disabled"; 3233 3234 pcie3_opp_table: opp-table { 3235 compatible = "operating-points-v2"; 3236 3237 /* 2.5GT/s x1 */ 3238 opp-2500000-1 { 3239 opp-hz = /bits/ 64 <2500000>; 3240 required-opps = <&rpmhpd_opp_low_svs>; 3241 opp-peak-kBps = <250000 1>; 3242 opp-level = <1>; 3243 }; 3244 3245 /* 2.5 GT/s x2 */ 3246 opp-5000000-1 { 3247 opp-hz = /bits/ 64 <5000000>; 3248 required-opps = <&rpmhpd_opp_low_svs>; 3249 opp-peak-kBps = <500000 1>; 3250 opp-level = <1>; 3251 }; 3252 3253 /* 2.5 GT/s x4 */ 3254 opp-10000000-1 { 3255 opp-hz = /bits/ 64 <10000000>; 3256 required-opps = <&rpmhpd_opp_low_svs>; 3257 opp-peak-kBps = <1000000 1>; 3258 opp-level = <1>; 3259 }; 3260 3261 /* 2.5 GT/s x8 */ 3262 opp-20000000-1 { 3263 opp-hz = /bits/ 64 <20000000>; 3264 required-opps = <&rpmhpd_opp_low_svs>; 3265 opp-peak-kBps = <2000000 1>; 3266 opp-level = <1>; 3267 }; 3268 3269 /* 5 GT/s x1 */ 3270 opp-5000000-2 { 3271 opp-hz = /bits/ 64 <5000000>; 3272 required-opps = <&rpmhpd_opp_low_svs>; 3273 opp-peak-kBps = <500000 1>; 3274 opp-level = <2>; 3275 }; 3276 3277 /* 5 GT/s x2 */ 3278 opp-10000000-2 { 3279 opp-hz = /bits/ 64 <10000000>; 3280 required-opps = <&rpmhpd_opp_low_svs>; 3281 opp-peak-kBps = <1000000 1>; 3282 opp-level = <2>; 3283 }; 3284 3285 /* 5 GT/s x4 */ 3286 opp-20000000-2 { 3287 opp-hz = /bits/ 64 <20000000>; 3288 required-opps = <&rpmhpd_opp_low_svs>; 3289 opp-peak-kBps = <2000000 1>; 3290 opp-level = <2>; 3291 }; 3292 3293 /* 5 GT/s x8 */ 3294 opp-40000000-2 { 3295 opp-hz = /bits/ 64 <40000000>; 3296 required-opps = <&rpmhpd_opp_low_svs>; 3297 opp-peak-kBps = <4000000 1>; 3298 opp-level = <2>; 3299 }; 3300 3301 /* 8 GT/s x1 */ 3302 opp-8000000-3 { 3303 opp-hz = /bits/ 64 <8000000>; 3304 required-opps = <&rpmhpd_opp_svs>; 3305 opp-peak-kBps = <984500 1>; 3306 opp-level = <3>; 3307 }; 3308 3309 /* 8 GT/s x2 */ 3310 opp-16000000-3 { 3311 opp-hz = /bits/ 64 <16000000>; 3312 required-opps = <&rpmhpd_opp_svs>; 3313 opp-peak-kBps = <1969000 1>; 3314 opp-level = <3>; 3315 }; 3316 3317 /* 8 GT/s x4 */ 3318 opp-32000000-3 { 3319 opp-hz = /bits/ 64 <32000000>; 3320 required-opps = <&rpmhpd_opp_svs>; 3321 opp-peak-kBps = <3938000 1>; 3322 opp-level = <3>; 3323 }; 3324 3325 /* 8 GT/s x8 */ 3326 opp-64000000-3 { 3327 opp-hz = /bits/ 64 <64000000>; 3328 required-opps = <&rpmhpd_opp_svs>; 3329 opp-peak-kBps = <7876000 1>; 3330 opp-level = <3>; 3331 }; 3332 3333 /* 16 GT/s x1 */ 3334 opp-16000000-4 { 3335 opp-hz = /bits/ 64 <16000000>; 3336 required-opps = <&rpmhpd_opp_svs>; 3337 opp-peak-kBps = <1969000 1>; 3338 opp-level = <4>; 3339 }; 3340 3341 /* 16 GT/s x2 */ 3342 opp-32000000-4 { 3343 opp-hz = /bits/ 64 <32000000>; 3344 required-opps = <&rpmhpd_opp_svs>; 3345 opp-peak-kBps = <3938000 1>; 3346 opp-level = <4>; 3347 }; 3348 3349 /* 16 GT/s x4 */ 3350 opp-64000000-4 { 3351 opp-hz = /bits/ 64 <64000000>; 3352 required-opps = <&rpmhpd_opp_svs>; 3353 opp-peak-kBps = <7876000 1>; 3354 opp-level = <4>; 3355 }; 3356 3357 /* 16 GT/s x8 */ 3358 opp-128000000-4 { 3359 opp-hz = /bits/ 64 <128000000>; 3360 required-opps = <&rpmhpd_opp_svs>; 3361 opp-peak-kBps = <15753000 1>; 3362 opp-level = <4>; 3363 }; 3364 }; 3365 3366 pcie3_port0: pcie@0 { 3367 device_type = "pci"; 3368 compatible = "pciclass,0604"; 3369 reg = <0x0 0x0 0x0 0x0 0x0>; 3370 bus-range = <0x01 0xff>; 3371 3372 phys = <&pcie3_phy>; 3373 3374 #address-cells = <3>; 3375 #size-cells = <2>; 3376 ranges; 3377 }; 3378 }; 3379 3380 pcie3_phy: phy@1be0000 { 3381 compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy"; 3382 reg = <0 0x01be0000 0 0x10000>; 3383 3384 clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>, 3385 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 3386 <&tcsr TCSR_PCIE_8L_CLKREF_EN>, 3387 <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>, 3388 <&gcc GCC_PCIE_3_PIPE_CLK>, 3389 <&gcc GCC_PCIE_3_PIPEDIV2_CLK>; 3390 clock-names = "aux", 3391 "cfg_ahb", 3392 "ref", 3393 "rchng", 3394 "pipe", 3395 "pipediv2"; 3396 3397 resets = <&gcc GCC_PCIE_3_PHY_BCR>, 3398 <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>; 3399 reset-names = "phy", 3400 "phy_nocsr"; 3401 3402 assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>; 3403 assigned-clock-rates = <100000000>; 3404 3405 power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>; 3406 3407 #clock-cells = <0>; 3408 clock-output-names = "pcie3_pipe_clk"; 3409 3410 #phy-cells = <0>; 3411 3412 status = "disabled"; 3413 }; 3414 3415 pcie6a: pcie@1bf8000 { 3416 device_type = "pci"; 3417 compatible = "qcom,pcie-x1e80100"; 3418 reg = <0 0x01bf8000 0 0x3000>, 3419 <0 0x70000000 0 0xf20>, 3420 <0 0x70000f40 0 0xa8>, 3421 <0 0x70001000 0 0x1000>, 3422 <0 0x70100000 0 0x100000>, 3423 <0 0x01bfb000 0 0x1000>; 3424 reg-names = "parf", 3425 "dbi", 3426 "elbi", 3427 "atu", 3428 "config", 3429 "mhi"; 3430 #address-cells = <3>; 3431 #size-cells = <2>; 3432 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, 3433 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 3434 bus-range = <0x00 0xff>; 3435 3436 dma-coherent; 3437 3438 linux,pci-domain = <6>; 3439 num-lanes = <4>; 3440 3441 msi-map = <0x0 &gic_its 0xe0000 0x10000>; 3442 3443 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3444 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3445 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 3446 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 3447 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 3448 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 3451 <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>; 3452 interrupt-names = "msi0", 3453 "msi1", 3454 "msi2", 3455 "msi3", 3456 "msi4", 3457 "msi5", 3458 "msi6", 3459 "msi7", 3460 "global"; 3461 3462 #interrupt-cells = <1>; 3463 interrupt-map-mask = <0 0 0 0x7>; 3464 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 3465 <0 0 0 2 &intc 0 0 GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 3466 <0 0 0 3 &intc 0 0 GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 3467 <0 0 0 4 &intc 0 0 GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>; 3468 3469 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, 3470 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3471 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>, 3472 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>, 3473 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>, 3474 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>, 3475 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>; 3476 clock-names = "aux", 3477 "cfg", 3478 "bus_master", 3479 "bus_slave", 3480 "slave_q2a", 3481 "noc_aggr", 3482 "cnoc_sf_axi"; 3483 3484 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>; 3485 assigned-clock-rates = <19200000>; 3486 3487 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS 3488 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3489 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3490 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ACTIVE_ONLY>; 3491 interconnect-names = "pcie-mem", 3492 "cpu-pcie"; 3493 3494 resets = <&gcc GCC_PCIE_6A_BCR>, 3495 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; 3496 reset-names = "pci", 3497 "link_down"; 3498 3499 power-domains = <&gcc GCC_PCIE_6A_GDSC>; 3500 required-opps = <&rpmhpd_opp_nom>; 3501 3502 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3503 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3504 3505 status = "disabled"; 3506 3507 pcie6a_port0: pcie@0 { 3508 device_type = "pci"; 3509 reg = <0x0 0x0 0x0 0x0 0x0>; 3510 bus-range = <0x01 0xff>; 3511 3512 phys = <&pcie6a_phy>; 3513 3514 #address-cells = <3>; 3515 #size-cells = <2>; 3516 ranges; 3517 }; 3518 }; 3519 3520 pcie6a_phy: phy@1bfc000 { 3521 compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy"; 3522 reg = <0 0x01bfc000 0 0x2000>, 3523 <0 0x01bfe000 0 0x2000>; 3524 3525 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, 3526 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3527 <&tcsr TCSR_PCIE_4L_CLKREF_EN>, 3528 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, 3529 <&gcc GCC_PCIE_6A_PIPE_CLK>, 3530 <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>; 3531 clock-names = "aux", 3532 "cfg_ahb", 3533 "ref", 3534 "rchng", 3535 "pipe", 3536 "pipediv2"; 3537 3538 resets = <&gcc GCC_PCIE_6A_PHY_BCR>, 3539 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; 3540 reset-names = "phy", 3541 "phy_nocsr"; 3542 3543 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>; 3544 assigned-clock-rates = <100000000>; 3545 3546 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3547 3548 qcom,4ln-config-sel = <&tcsr 0x1a000 0>; 3549 3550 #clock-cells = <0>; 3551 clock-output-names = "pcie6a_pipe_clk"; 3552 3553 #phy-cells = <0>; 3554 3555 status = "disabled"; 3556 }; 3557 3558 pcie5: pcie@1c00000 { 3559 device_type = "pci"; 3560 compatible = "qcom,pcie-x1e80100"; 3561 reg = <0 0x01c00000 0 0x3000>, 3562 <0 0x7e000000 0 0xf1d>, 3563 <0 0x7e000f40 0 0xa8>, 3564 <0 0x7e001000 0 0x1000>, 3565 <0 0x7e100000 0 0x100000>, 3566 <0 0x01c03000 0 0x1000>; 3567 reg-names = "parf", 3568 "dbi", 3569 "elbi", 3570 "atu", 3571 "config", 3572 "mhi"; 3573 #address-cells = <3>; 3574 #size-cells = <2>; 3575 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3576 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>; 3577 bus-range = <0x00 0xff>; 3578 3579 dma-coherent; 3580 3581 linux,pci-domain = <5>; 3582 num-lanes = <2>; 3583 3584 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3585 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3586 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3587 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 3588 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 3589 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 3590 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 3591 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 3592 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 3593 interrupt-names = "msi0", 3594 "msi1", 3595 "msi2", 3596 "msi3", 3597 "msi4", 3598 "msi5", 3599 "msi6", 3600 "msi7", 3601 "global"; 3602 3603 #interrupt-cells = <1>; 3604 interrupt-map-mask = <0 0 0 0x7>; 3605 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 3606 <0 0 0 2 &intc 0 0 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 3607 <0 0 0 3 &intc 0 0 GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 3608 <0 0 0 4 &intc 0 0 GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 3609 3610 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3611 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3612 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 3613 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 3614 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 3615 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3616 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3617 clock-names = "aux", 3618 "cfg", 3619 "bus_master", 3620 "bus_slave", 3621 "slave_q2a", 3622 "noc_aggr", 3623 "cnoc_sf_axi"; 3624 3625 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3626 assigned-clock-rates = <19200000>; 3627 3628 interconnects = <&pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3629 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3630 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3631 &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ACTIVE_ONLY>; 3632 interconnect-names = "pcie-mem", 3633 "cpu-pcie"; 3634 3635 resets = <&gcc GCC_PCIE_5_BCR>, 3636 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3637 reset-names = "pci", 3638 "link_down"; 3639 3640 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3641 required-opps = <&rpmhpd_opp_nom>; 3642 3643 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3644 3645 status = "disabled"; 3646 3647 pcie5_port0: pcie@0 { 3648 device_type = "pci"; 3649 reg = <0x0 0x0 0x0 0x0 0x0>; 3650 bus-range = <0x01 0xff>; 3651 3652 phys = <&pcie5_phy>; 3653 3654 #address-cells = <3>; 3655 #size-cells = <2>; 3656 ranges; 3657 }; 3658 }; 3659 3660 pcie5_phy: phy@1c06000 { 3661 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3662 reg = <0 0x01c06000 0 0x2000>; 3663 3664 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3665 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3666 <&tcsr TCSR_PCIE_2L_5_CLKREF_EN>, 3667 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3668 <&gcc GCC_PCIE_5_PIPE_CLK>, 3669 <&gcc GCC_PCIE_5_PIPEDIV2_CLK>; 3670 clock-names = "aux", 3671 "cfg_ahb", 3672 "ref", 3673 "rchng", 3674 "pipe", 3675 "pipediv2"; 3676 3677 resets = <&gcc GCC_PCIE_5_PHY_BCR>, 3678 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; 3679 reset-names = "phy", 3680 "phy_nocsr"; 3681 3682 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3683 assigned-clock-rates = <100000000>; 3684 3685 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3686 3687 #clock-cells = <0>; 3688 clock-output-names = "pcie5_pipe_clk"; 3689 3690 #phy-cells = <0>; 3691 3692 status = "disabled"; 3693 }; 3694 3695 pcie4: pcie@1c08000 { 3696 device_type = "pci"; 3697 compatible = "qcom,pcie-x1e80100"; 3698 reg = <0 0x01c08000 0 0x3000>, 3699 <0 0x7c000000 0 0xf1d>, 3700 <0 0x7c000f40 0 0xa8>, 3701 <0 0x7c001000 0 0x1000>, 3702 <0 0x7c100000 0 0x100000>, 3703 <0 0x01c0b000 0 0x1000>; 3704 reg-names = "parf", 3705 "dbi", 3706 "elbi", 3707 "atu", 3708 "config", 3709 "mhi"; 3710 #address-cells = <3>; 3711 #size-cells = <2>; 3712 ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>, 3713 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>; 3714 bus-range = <0x00 0xff>; 3715 3716 dma-coherent; 3717 3718 linux,pci-domain = <4>; 3719 num-lanes = <2>; 3720 3721 msi-map = <0x0 &gic_its 0xc0000 0x10000>; 3722 3723 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3724 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 3725 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3726 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3727 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3728 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3729 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3730 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 3731 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 3732 interrupt-names = "msi0", 3733 "msi1", 3734 "msi2", 3735 "msi3", 3736 "msi4", 3737 "msi5", 3738 "msi6", 3739 "msi7", 3740 "global"; 3741 3742 #interrupt-cells = <1>; 3743 interrupt-map-mask = <0 0 0 0x7>; 3744 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 3745 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 3746 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 3747 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 3748 3749 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3750 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3751 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 3752 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 3753 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 3754 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3755 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3756 clock-names = "aux", 3757 "cfg", 3758 "bus_master", 3759 "bus_slave", 3760 "slave_q2a", 3761 "noc_aggr", 3762 "cnoc_sf_axi"; 3763 3764 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 3765 assigned-clock-rates = <19200000>; 3766 3767 interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 3768 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3769 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3770 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 3771 interconnect-names = "pcie-mem", 3772 "cpu-pcie"; 3773 3774 resets = <&gcc GCC_PCIE_4_BCR>, 3775 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 3776 reset-names = "pci", 3777 "link_down"; 3778 3779 power-domains = <&gcc GCC_PCIE_4_GDSC>; 3780 required-opps = <&rpmhpd_opp_nom>; 3781 3782 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3783 3784 status = "disabled"; 3785 3786 pcie4_port0: pcie@0 { 3787 device_type = "pci"; 3788 reg = <0x0 0x0 0x0 0x0 0x0>; 3789 bus-range = <0x01 0xff>; 3790 3791 phys = <&pcie4_phy>; 3792 3793 #address-cells = <3>; 3794 #size-cells = <2>; 3795 ranges; 3796 }; 3797 }; 3798 3799 pcie4_phy: phy@1c0e000 { 3800 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3801 reg = <0 0x01c0e000 0 0x2000>; 3802 3803 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3804 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3805 <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>, 3806 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 3807 <&gcc GCC_PCIE_4_PIPE_CLK>, 3808 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 3809 clock-names = "aux", 3810 "cfg_ahb", 3811 "ref", 3812 "rchng", 3813 "pipe", 3814 "pipediv2"; 3815 3816 resets = <&gcc GCC_PCIE_4_PHY_BCR>, 3817 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; 3818 reset-names = "phy", 3819 "phy_nocsr"; 3820 3821 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 3822 assigned-clock-rates = <100000000>; 3823 3824 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 3825 3826 #clock-cells = <0>; 3827 clock-output-names = "pcie4_pipe_clk"; 3828 3829 #phy-cells = <0>; 3830 3831 status = "disabled"; 3832 }; 3833 3834 ufs_mem_phy: phy@1d80000 { 3835 compatible = "qcom,x1e80100-qmp-ufs-phy", 3836 "qcom,sm8550-qmp-ufs-phy"; 3837 reg = <0x0 0x01d80000 0x0 0x2000>; 3838 3839 clocks = <&rpmhcc RPMH_CXO_CLK>, 3840 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 3841 <&tcsr TCSR_UFS_PHY_CLKREF_EN>; 3842 3843 clock-names = "ref", 3844 "ref_aux", 3845 "qref"; 3846 resets = <&ufs_mem_hc 0>; 3847 reset-names = "ufsphy"; 3848 3849 power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; 3850 3851 #clock-cells = <1>; 3852 #phy-cells = <0>; 3853 3854 status = "disabled"; 3855 }; 3856 3857 ufs_mem_hc: ufshc@1d84000 { 3858 compatible = "qcom,x1e80100-ufshc", 3859 "qcom,sm8550-ufshc", 3860 "qcom,ufshc"; 3861 reg = <0x0 0x01d84000 0x0 0x3000>; 3862 3863 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 3864 3865 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 3866 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 3867 <&gcc GCC_UFS_PHY_AHB_CLK>, 3868 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 3869 <&rpmhcc RPMH_LN_BB_CLK3>, 3870 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 3871 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 3872 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 3873 clock-names = "core_clk", 3874 "bus_aggr_clk", 3875 "iface_clk", 3876 "core_clk_unipro", 3877 "ref_clk", 3878 "tx_lane0_sync_clk", 3879 "rx_lane0_sync_clk", 3880 "rx_lane1_sync_clk"; 3881 3882 operating-points-v2 = <&ufs_opp_table>; 3883 3884 resets = <&gcc GCC_UFS_PHY_BCR>; 3885 reset-names = "rst"; 3886 3887 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 3888 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3889 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3890 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3891 interconnect-names = "ufs-ddr", 3892 "cpu-ufs"; 3893 3894 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 3895 required-opps = <&rpmhpd_opp_nom>; 3896 3897 iommus = <&apps_smmu 0x1a0 0>; 3898 dma-coherent; 3899 3900 lanes-per-direction = <2>; 3901 3902 phys = <&ufs_mem_phy>; 3903 phy-names = "ufsphy"; 3904 3905 #reset-cells = <1>; 3906 3907 status = "disabled"; 3908 3909 ufs_opp_table: opp-table { 3910 compatible = "operating-points-v2"; 3911 3912 opp-75000000 { 3913 opp-hz = /bits/ 64 <75000000>, 3914 /bits/ 64 <0>, 3915 /bits/ 64 <0>, 3916 /bits/ 64 <75000000>, 3917 /bits/ 64 <0>, 3918 /bits/ 64 <0>, 3919 /bits/ 64 <0>, 3920 /bits/ 64 <0>; 3921 required-opps = <&rpmhpd_opp_low_svs>; 3922 }; 3923 3924 opp-150000000 { 3925 opp-hz = /bits/ 64 <150000000>, 3926 /bits/ 64 <0>, 3927 /bits/ 64 <0>, 3928 /bits/ 64 <150000000>, 3929 /bits/ 64 <0>, 3930 /bits/ 64 <0>, 3931 /bits/ 64 <0>, 3932 /bits/ 64 <0>; 3933 required-opps = <&rpmhpd_opp_svs>; 3934 }; 3935 3936 opp-300000000 { 3937 opp-hz = /bits/ 64 <300000000>, 3938 /bits/ 64 <0>, 3939 /bits/ 64 <0>, 3940 /bits/ 64 <300000000>, 3941 /bits/ 64 <0>, 3942 /bits/ 64 <0>, 3943 /bits/ 64 <0>, 3944 /bits/ 64 <0>; 3945 required-opps = <&rpmhpd_opp_nom>; 3946 }; 3947 }; 3948 }; 3949 3950 cryptobam: dma-controller@1dc4000 { 3951 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 3952 reg = <0x0 0x01dc4000 0x0 0x28000>; 3953 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 3954 #dma-cells = <1>; 3955 iommus = <&apps_smmu 0x480 0x0>, 3956 <&apps_smmu 0x481 0x0>; 3957 qcom,ee = <0>; 3958 qcom,controlled-remotely; 3959 num-channels = <20>; 3960 qcom,num-ees = <4>; 3961 }; 3962 3963 crypto: crypto@1dfa000 { 3964 compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce"; 3965 reg = <0x0 0x01dfa000 0x0 0x6000>; 3966 dmas = <&cryptobam 4>, <&cryptobam 5>; 3967 dma-names = "rx", 3968 "tx"; 3969 iommus = <&apps_smmu 0x480 0x0>, 3970 <&apps_smmu 0x481 0x0>; 3971 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 3972 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3973 interconnect-names = "memory"; 3974 }; 3975 3976 tcsr_mutex: hwlock@1f40000 { 3977 compatible = "qcom,tcsr-mutex"; 3978 reg = <0 0x01f40000 0 0x20000>; 3979 #hwlock-cells = <1>; 3980 }; 3981 3982 tcsr: clock-controller@1fc0000 { 3983 compatible = "qcom,x1e80100-tcsr", "syscon"; 3984 reg = <0 0x01fc0000 0 0x30000>; 3985 clocks = <&rpmhcc RPMH_CXO_CLK>; 3986 #clock-cells = <1>; 3987 #reset-cells = <1>; 3988 }; 3989 3990 gpu: gpu@3d00000 { 3991 compatible = "qcom,adreno-43050c01", "qcom,adreno"; 3992 reg = <0x0 0x03d00000 0x0 0x40000>, 3993 <0x0 0x03d9e000 0x0 0x1000>, 3994 <0x0 0x03d61000 0x0 0x800>; 3995 3996 reg-names = "kgsl_3d0_reg_memory", 3997 "cx_mem", 3998 "cx_dbgc"; 3999 4000 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4001 4002 iommus = <&adreno_smmu 0 0x0>, 4003 <&adreno_smmu 1 0x0>; 4004 4005 operating-points-v2 = <&gpu_opp_table>; 4006 4007 qcom,gmu = <&gmu>; 4008 #cooling-cells = <2>; 4009 4010 nvmem-cells = <&gpu_speed_bin>; 4011 nvmem-cell-names = "speed_bin"; 4012 4013 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 4014 interconnect-names = "gfx-mem"; 4015 4016 status = "disabled"; 4017 4018 gpu_zap_shader: zap-shader { 4019 memory-region = <&gpu_microcode_mem>; 4020 }; 4021 4022 gpu_opp_table: opp-table { 4023 compatible = "operating-points-v2-adreno", "operating-points-v2"; 4024 4025 opp-1500000000 { 4026 opp-hz = /bits/ 64 <1500000000>; 4027 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>; 4028 opp-peak-kBps = <16500000>; 4029 qcom,opp-acd-level = <0xa82a5ffd>; 4030 opp-supported-hw = <0x03>; 4031 }; 4032 4033 opp-1375000000 { 4034 opp-hz = /bits/ 64 <1375000000>; 4035 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 4036 opp-peak-kBps = <16500000>; 4037 qcom,opp-acd-level = <0xa82a5ffd>; 4038 opp-supported-hw = <0x03>; 4039 }; 4040 4041 opp-1250000000 { 4042 opp-hz = /bits/ 64 <1250000000>; 4043 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 4044 opp-peak-kBps = <16500000>; 4045 qcom,opp-acd-level = <0xa82a5ffd>; 4046 opp-supported-hw = <0x07>; 4047 }; 4048 4049 opp-1175000000 { 4050 opp-hz = /bits/ 64 <1175000000>; 4051 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; 4052 opp-peak-kBps = <14398438>; 4053 qcom,opp-acd-level = <0xa82a5ffd>; 4054 opp-supported-hw = <0x07>; 4055 }; 4056 4057 opp-1100000000-0 { 4058 opp-hz = /bits/ 64 <1100000000>; 4059 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4060 opp-peak-kBps = <14398438>; 4061 qcom,opp-acd-level = <0xa82a5ffd>; 4062 opp-supported-hw = <0x07>; 4063 }; 4064 4065 /* Only applicable for SKUs which has 1100Mhz as Fmax */ 4066 opp-1100000000-1 { 4067 opp-hz = /bits/ 64 <1100000000>; 4068 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4069 opp-peak-kBps = <16500000>; 4070 qcom,opp-acd-level = <0xa82a5ffd>; 4071 opp-supported-hw = <0x08>; 4072 }; 4073 4074 opp-1000000000 { 4075 opp-hz = /bits/ 64 <1000000000>; 4076 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4077 opp-peak-kBps = <14398438>; 4078 qcom,opp-acd-level = <0xa82b5ffd>; 4079 opp-supported-hw = <0x0f>; 4080 }; 4081 4082 opp-925000000 { 4083 opp-hz = /bits/ 64 <925000000>; 4084 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4085 opp-peak-kBps = <14398438>; 4086 qcom,opp-acd-level = <0xa82b5ffd>; 4087 opp-supported-hw = <0x0f>; 4088 }; 4089 4090 opp-800000000 { 4091 opp-hz = /bits/ 64 <800000000>; 4092 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4093 opp-peak-kBps = <12449219>; 4094 qcom,opp-acd-level = <0xa82c5ffd>; 4095 opp-supported-hw = <0x0f>; 4096 }; 4097 4098 opp-744000000 { 4099 opp-hz = /bits/ 64 <744000000>; 4100 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4101 opp-peak-kBps = <10687500>; 4102 qcom,opp-acd-level = <0x882e5ffd>; 4103 opp-supported-hw = <0x0f>; 4104 }; 4105 4106 opp-687000000-0 { 4107 opp-hz = /bits/ 64 <687000000>; 4108 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4109 opp-peak-kBps = <8171875>; 4110 qcom,opp-acd-level = <0x882e5ffd>; 4111 opp-supported-hw = <0x0f>; 4112 }; 4113 4114 /* Only applicable for SKUs which has 687Mhz as Fmax */ 4115 opp-687000000-1 { 4116 opp-hz = /bits/ 64 <687000000>; 4117 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4118 opp-peak-kBps = <16500000>; 4119 qcom,opp-acd-level = <0x882e5ffd>; 4120 opp-supported-hw = <0x10>; 4121 }; 4122 4123 opp-550000000 { 4124 opp-hz = /bits/ 64 <550000000>; 4125 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4126 opp-peak-kBps = <6074219>; 4127 qcom,opp-acd-level = <0xc0285ffd>; 4128 opp-supported-hw = <0x1f>; 4129 }; 4130 4131 opp-390000000 { 4132 opp-hz = /bits/ 64 <390000000>; 4133 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4134 opp-peak-kBps = <3000000>; 4135 qcom,opp-acd-level = <0xc0285ffd>; 4136 opp-supported-hw = <0x1f>; 4137 }; 4138 4139 opp-300000000 { 4140 opp-hz = /bits/ 64 <300000000>; 4141 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4142 opp-peak-kBps = <2136719>; 4143 qcom,opp-acd-level = <0xc02b5ffd>; 4144 opp-supported-hw = <0x1f>; 4145 }; 4146 }; 4147 }; 4148 4149 gmu: gmu@3d6a000 { 4150 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; 4151 reg = <0x0 0x03d6a000 0x0 0x35000>, 4152 <0x0 0x03d50000 0x0 0x10000>, 4153 <0x0 0x0b280000 0x0 0x10000>; 4154 reg-names = "gmu", "rscc", "gmu_pdc"; 4155 4156 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4157 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4158 interrupt-names = "hfi", "gmu"; 4159 4160 clocks = <&gpucc GPU_CC_AHB_CLK>, 4161 <&gpucc GPU_CC_CX_GMU_CLK>, 4162 <&gpucc GPU_CC_CXO_CLK>, 4163 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4164 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4165 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4166 <&gpucc GPU_CC_DEMET_CLK>; 4167 clock-names = "ahb", 4168 "gmu", 4169 "cxo", 4170 "axi", 4171 "memnoc", 4172 "hub", 4173 "demet"; 4174 4175 power-domains = <&gpucc GPU_CX_GDSC>, 4176 <&gpucc GPU_GX_GDSC>; 4177 power-domain-names = "cx", 4178 "gx"; 4179 4180 iommus = <&adreno_smmu 5 0x0>; 4181 4182 qcom,qmp = <&aoss_qmp>; 4183 4184 operating-points-v2 = <&gmu_opp_table>; 4185 4186 gmu_opp_table: opp-table { 4187 compatible = "operating-points-v2"; 4188 4189 opp-550000000 { 4190 opp-hz = /bits/ 64 <550000000>; 4191 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4192 }; 4193 4194 opp-220000000 { 4195 opp-hz = /bits/ 64 <220000000>; 4196 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4197 }; 4198 }; 4199 }; 4200 4201 gpucc: clock-controller@3d90000 { 4202 compatible = "qcom,x1e80100-gpucc"; 4203 reg = <0 0x03d90000 0 0xa000>; 4204 clocks = <&bi_tcxo_div2>, 4205 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, 4206 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; 4207 #clock-cells = <1>; 4208 #reset-cells = <1>; 4209 #power-domain-cells = <1>; 4210 }; 4211 4212 adreno_smmu: iommu@3da0000 { 4213 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu", 4214 "qcom,smmu-500", "arm,mmu-500"; 4215 reg = <0x0 0x03da0000 0x0 0x40000>; 4216 #iommu-cells = <2>; 4217 #global-interrupts = <1>; 4218 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 4219 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4220 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4221 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4222 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4223 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4224 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4225 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4226 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4227 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4228 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 4229 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 4230 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4231 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 4232 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 4233 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 4234 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 4235 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 4236 <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, 4237 <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 4238 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 4239 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 4240 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 4241 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 4242 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 4243 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 4244 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4245 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4246 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4247 <&gpucc GPU_CC_AHB_CLK>; 4248 clock-names = "hlos", 4249 "bus", 4250 "iface", 4251 "ahb"; 4252 power-domains = <&gpucc GPU_CX_GDSC>; 4253 dma-coherent; 4254 }; 4255 4256 gem_noc: interconnect@26400000 { 4257 compatible = "qcom,x1e80100-gem-noc"; 4258 reg = <0 0x26400000 0 0x311200>; 4259 4260 qcom,bcm-voters = <&apps_bcm_voter>; 4261 4262 #interconnect-cells = <2>; 4263 }; 4264 4265 nsp_noc: interconnect@320c0000 { 4266 compatible = "qcom,x1e80100-nsp-noc"; 4267 reg = <0 0x320c0000 0 0xe080>; 4268 4269 qcom,bcm-voters = <&apps_bcm_voter>; 4270 4271 #interconnect-cells = <2>; 4272 }; 4273 4274 remoteproc_adsp: remoteproc@6800000 { 4275 compatible = "qcom,x1e80100-adsp-pas"; 4276 reg = <0x0 0x06800000 0x0 0x10000>; 4277 4278 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4279 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4280 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4281 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4282 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4283 interrupt-names = "wdog", 4284 "fatal", 4285 "ready", 4286 "handover", 4287 "stop-ack"; 4288 4289 clocks = <&rpmhcc RPMH_CXO_CLK>; 4290 clock-names = "xo"; 4291 4292 power-domains = <&rpmhpd RPMHPD_LCX>, 4293 <&rpmhpd RPMHPD_LMX>; 4294 power-domain-names = "lcx", 4295 "lmx"; 4296 4297 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 4298 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4299 4300 memory-region = <&adspslpi_mem>, 4301 <&q6_adsp_dtb_mem>; 4302 4303 qcom,qmp = <&aoss_qmp>; 4304 4305 qcom,smem-states = <&smp2p_adsp_out 0>; 4306 qcom,smem-state-names = "stop"; 4307 4308 status = "disabled"; 4309 4310 glink-edge { 4311 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4312 IPCC_MPROC_SIGNAL_GLINK_QMP 4313 IRQ_TYPE_EDGE_RISING>; 4314 mboxes = <&ipcc IPCC_CLIENT_LPASS 4315 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4316 4317 label = "lpass"; 4318 qcom,remote-pid = <2>; 4319 4320 fastrpc { 4321 compatible = "qcom,fastrpc"; 4322 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4323 label = "adsp"; 4324 memory-region = <&adsp_rpc_remote_heap_mem>; 4325 qcom,vmids = <QCOM_SCM_VMID_LPASS 4326 QCOM_SCM_VMID_ADSP_HEAP>; 4327 qcom,non-secure-domain; 4328 #address-cells = <1>; 4329 #size-cells = <0>; 4330 4331 compute-cb@3 { 4332 compatible = "qcom,fastrpc-compute-cb"; 4333 reg = <3>; 4334 iommus = <&apps_smmu 0x1003 0x80>, 4335 <&apps_smmu 0x1063 0x0>; 4336 dma-coherent; 4337 }; 4338 4339 compute-cb@4 { 4340 compatible = "qcom,fastrpc-compute-cb"; 4341 reg = <4>; 4342 iommus = <&apps_smmu 0x1004 0x80>, 4343 <&apps_smmu 0x1064 0x0>; 4344 dma-coherent; 4345 }; 4346 4347 compute-cb@5 { 4348 compatible = "qcom,fastrpc-compute-cb"; 4349 reg = <5>; 4350 iommus = <&apps_smmu 0x1005 0x80>, 4351 <&apps_smmu 0x1065 0x0>; 4352 dma-coherent; 4353 }; 4354 4355 compute-cb@6 { 4356 compatible = "qcom,fastrpc-compute-cb"; 4357 reg = <6>; 4358 iommus = <&apps_smmu 0x1006 0x80>, 4359 <&apps_smmu 0x1066 0x0>; 4360 dma-coherent; 4361 }; 4362 4363 compute-cb@7 { 4364 compatible = "qcom,fastrpc-compute-cb"; 4365 reg = <7>; 4366 iommus = <&apps_smmu 0x1007 0x80>, 4367 <&apps_smmu 0x1067 0x0>; 4368 dma-coherent; 4369 }; 4370 }; 4371 4372 gpr { 4373 compatible = "qcom,gpr"; 4374 qcom,glink-channels = "adsp_apps"; 4375 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4376 qcom,intents = <512 20>; 4377 #address-cells = <1>; 4378 #size-cells = <0>; 4379 4380 q6apm: service@1 { 4381 compatible = "qcom,q6apm"; 4382 reg = <GPR_APM_MODULE_IID>; 4383 #sound-dai-cells = <0>; 4384 qcom,protection-domain = "avs/audio", 4385 "msm/adsp/audio_pd"; 4386 4387 q6apmbedai: bedais { 4388 compatible = "qcom,q6apm-lpass-dais"; 4389 #sound-dai-cells = <1>; 4390 }; 4391 4392 q6apmdai: dais { 4393 compatible = "qcom,q6apm-dais"; 4394 iommus = <&apps_smmu 0x1001 0x80>, 4395 <&apps_smmu 0x1061 0x0>; 4396 }; 4397 }; 4398 4399 q6prm: service@2 { 4400 compatible = "qcom,q6prm"; 4401 reg = <GPR_PRM_MODULE_IID>; 4402 qcom,protection-domain = "avs/audio", 4403 "msm/adsp/audio_pd"; 4404 4405 q6prmcc: clock-controller { 4406 compatible = "qcom,q6prm-lpass-clocks"; 4407 #clock-cells = <2>; 4408 }; 4409 }; 4410 }; 4411 }; 4412 }; 4413 4414 lpass_wsa2macro: codec@6aa0000 { 4415 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4416 reg = <0 0x06aa0000 0 0x1000>; 4417 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4418 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4419 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4420 <&lpass_vamacro>; 4421 clock-names = "mclk", 4422 "macro", 4423 "dcodec", 4424 "fsgen"; 4425 4426 #clock-cells = <0>; 4427 clock-output-names = "wsa2-mclk"; 4428 #sound-dai-cells = <1>; 4429 sound-name-prefix = "WSA2"; 4430 }; 4431 4432 swr3: soundwire@6ab0000 { 4433 compatible = "qcom,soundwire-v2.0.0"; 4434 reg = <0 0x06ab0000 0 0x10000>; 4435 clocks = <&lpass_wsa2macro>; 4436 clock-names = "iface"; 4437 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 4438 label = "WSA2"; 4439 4440 pinctrl-0 = <&wsa2_swr_active>; 4441 pinctrl-names = "default"; 4442 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>; 4443 reset-names = "swr_audio_cgcr"; 4444 4445 qcom,din-ports = <4>; 4446 qcom,dout-ports = <9>; 4447 4448 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4449 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4450 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4451 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4452 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4453 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4454 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4455 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4456 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4457 4458 #address-cells = <2>; 4459 #size-cells = <0>; 4460 #sound-dai-cells = <1>; 4461 status = "disabled"; 4462 }; 4463 4464 lpass_rxmacro: codec@6ac0000 { 4465 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 4466 reg = <0 0x06ac0000 0 0x1000>; 4467 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4468 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4469 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4470 <&lpass_vamacro>; 4471 clock-names = "mclk", 4472 "macro", 4473 "dcodec", 4474 "fsgen"; 4475 4476 #clock-cells = <0>; 4477 clock-output-names = "mclk"; 4478 #sound-dai-cells = <1>; 4479 }; 4480 4481 swr1: soundwire@6ad0000 { 4482 compatible = "qcom,soundwire-v2.0.0"; 4483 reg = <0 0x06ad0000 0 0x10000>; 4484 clocks = <&lpass_rxmacro>; 4485 clock-names = "iface"; 4486 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 4487 label = "RX"; 4488 4489 pinctrl-0 = <&rx_swr_active>; 4490 pinctrl-names = "default"; 4491 4492 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 4493 reset-names = "swr_audio_cgcr"; 4494 qcom,din-ports = <1>; 4495 qcom,dout-ports = <11>; 4496 4497 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4498 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4499 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4500 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4501 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4502 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4503 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4504 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4505 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4506 4507 #address-cells = <2>; 4508 #size-cells = <0>; 4509 #sound-dai-cells = <1>; 4510 status = "disabled"; 4511 }; 4512 4513 lpass_txmacro: codec@6ae0000 { 4514 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 4515 reg = <0 0x06ae0000 0 0x1000>; 4516 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4517 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4518 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4519 <&lpass_vamacro>; 4520 clock-names = "mclk", 4521 "macro", 4522 "dcodec", 4523 "fsgen"; 4524 4525 #clock-cells = <0>; 4526 clock-output-names = "mclk"; 4527 #sound-dai-cells = <1>; 4528 }; 4529 4530 lpass_wsamacro: codec@6b00000 { 4531 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4532 reg = <0 0x06b00000 0 0x1000>; 4533 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4534 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4535 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4536 <&lpass_vamacro>; 4537 clock-names = "mclk", 4538 "macro", 4539 "dcodec", 4540 "fsgen"; 4541 4542 #clock-cells = <0>; 4543 clock-output-names = "mclk"; 4544 #sound-dai-cells = <1>; 4545 sound-name-prefix = "WSA"; 4546 }; 4547 4548 swr0: soundwire@6b10000 { 4549 compatible = "qcom,soundwire-v2.0.0"; 4550 reg = <0 0x06b10000 0 0x10000>; 4551 clocks = <&lpass_wsamacro>; 4552 clock-names = "iface"; 4553 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 4554 label = "WSA"; 4555 4556 pinctrl-0 = <&wsa_swr_active>; 4557 pinctrl-names = "default"; 4558 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 4559 reset-names = "swr_audio_cgcr"; 4560 4561 qcom,din-ports = <4>; 4562 qcom,dout-ports = <9>; 4563 4564 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4565 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4566 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4567 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4568 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4569 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4570 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4571 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4572 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4573 4574 #address-cells = <2>; 4575 #size-cells = <0>; 4576 #sound-dai-cells = <1>; 4577 status = "disabled"; 4578 }; 4579 4580 lpass_audiocc: clock-controller@6b6c000 { 4581 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc"; 4582 reg = <0 0x06b6c000 0 0x1000>; 4583 #clock-cells = <1>; 4584 #reset-cells = <1>; 4585 }; 4586 4587 swr2: soundwire@6d30000 { 4588 compatible = "qcom,soundwire-v2.0.0"; 4589 reg = <0 0x06d30000 0 0x10000>; 4590 clocks = <&lpass_txmacro>; 4591 clock-names = "iface"; 4592 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 4593 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 4594 interrupt-names = "core", "wakeup"; 4595 label = "TX"; 4596 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 4597 reset-names = "swr_audio_cgcr"; 4598 4599 pinctrl-0 = <&tx_swr_active>; 4600 pinctrl-names = "default"; 4601 4602 qcom,din-ports = <4>; 4603 qcom,dout-ports = <1>; 4604 4605 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>; 4606 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>; 4607 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>; 4608 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4609 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4610 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4611 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4612 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4613 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>; 4614 4615 #address-cells = <2>; 4616 #size-cells = <0>; 4617 #sound-dai-cells = <1>; 4618 status = "disabled"; 4619 }; 4620 4621 lpass_vamacro: codec@6d44000 { 4622 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 4623 reg = <0 0x06d44000 0 0x1000>; 4624 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4625 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4626 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4627 clock-names = "mclk", 4628 "macro", 4629 "dcodec"; 4630 4631 #clock-cells = <0>; 4632 clock-output-names = "fsgen"; 4633 #sound-dai-cells = <1>; 4634 }; 4635 4636 lpass_tlmm: pinctrl@6e80000 { 4637 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl"; 4638 reg = <0 0x06e80000 0 0x20000>, 4639 <0 0x07250000 0 0x10000>; 4640 4641 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4642 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4643 clock-names = "core", "audio"; 4644 4645 gpio-controller; 4646 #gpio-cells = <2>; 4647 gpio-ranges = <&lpass_tlmm 0 0 23>; 4648 4649 tx_swr_active: tx-swr-active-state { 4650 clk-pins { 4651 pins = "gpio0"; 4652 function = "swr_tx_clk"; 4653 drive-strength = <2>; 4654 slew-rate = <1>; 4655 bias-disable; 4656 }; 4657 4658 data-pins { 4659 pins = "gpio1", "gpio2"; 4660 function = "swr_tx_data"; 4661 drive-strength = <2>; 4662 slew-rate = <1>; 4663 bias-bus-hold; 4664 }; 4665 }; 4666 4667 rx_swr_active: rx-swr-active-state { 4668 clk-pins { 4669 pins = "gpio3"; 4670 function = "swr_rx_clk"; 4671 drive-strength = <2>; 4672 slew-rate = <1>; 4673 bias-disable; 4674 }; 4675 4676 data-pins { 4677 pins = "gpio4", "gpio5"; 4678 function = "swr_rx_data"; 4679 drive-strength = <2>; 4680 slew-rate = <1>; 4681 bias-bus-hold; 4682 }; 4683 }; 4684 4685 dmic01_default: dmic01-default-state { 4686 clk-pins { 4687 pins = "gpio6"; 4688 function = "dmic1_clk"; 4689 drive-strength = <8>; 4690 output-high; 4691 }; 4692 4693 data-pins { 4694 pins = "gpio7"; 4695 function = "dmic1_data"; 4696 drive-strength = <8>; 4697 input-enable; 4698 }; 4699 }; 4700 4701 dmic23_default: dmic23-default-state { 4702 clk-pins { 4703 pins = "gpio8"; 4704 function = "dmic2_clk"; 4705 drive-strength = <8>; 4706 output-high; 4707 }; 4708 4709 data-pins { 4710 pins = "gpio9"; 4711 function = "dmic2_data"; 4712 drive-strength = <8>; 4713 input-enable; 4714 }; 4715 }; 4716 4717 wsa_swr_active: wsa-swr-active-state { 4718 clk-pins { 4719 pins = "gpio10"; 4720 function = "wsa_swr_clk"; 4721 drive-strength = <2>; 4722 slew-rate = <1>; 4723 bias-disable; 4724 }; 4725 4726 data-pins { 4727 pins = "gpio11"; 4728 function = "wsa_swr_data"; 4729 drive-strength = <2>; 4730 slew-rate = <1>; 4731 bias-bus-hold; 4732 }; 4733 }; 4734 4735 wsa2_swr_active: wsa2-swr-active-state { 4736 clk-pins { 4737 pins = "gpio15"; 4738 function = "wsa2_swr_clk"; 4739 drive-strength = <2>; 4740 slew-rate = <1>; 4741 bias-disable; 4742 }; 4743 4744 data-pins { 4745 pins = "gpio16"; 4746 function = "wsa2_swr_data"; 4747 drive-strength = <2>; 4748 slew-rate = <1>; 4749 bias-bus-hold; 4750 }; 4751 }; 4752 }; 4753 4754 lpasscc: clock-controller@6ea0000 { 4755 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc"; 4756 reg = <0 0x06ea0000 0 0x12000>; 4757 #clock-cells = <1>; 4758 #reset-cells = <1>; 4759 }; 4760 4761 lpass_ag_noc: interconnect@7e40000 { 4762 compatible = "qcom,x1e80100-lpass-ag-noc"; 4763 reg = <0 0x07e40000 0 0xe080>; 4764 4765 qcom,bcm-voters = <&apps_bcm_voter>; 4766 4767 #interconnect-cells = <2>; 4768 }; 4769 4770 lpass_lpiaon_noc: interconnect@7400000 { 4771 compatible = "qcom,x1e80100-lpass-lpiaon-noc"; 4772 reg = <0 0x07400000 0 0x19080>; 4773 4774 qcom,bcm-voters = <&apps_bcm_voter>; 4775 4776 #interconnect-cells = <2>; 4777 }; 4778 4779 lpass_lpicx_noc: interconnect@7430000 { 4780 compatible = "qcom,x1e80100-lpass-lpicx-noc"; 4781 reg = <0 0x07430000 0 0x3a200>; 4782 4783 qcom,bcm-voters = <&apps_bcm_voter>; 4784 4785 #interconnect-cells = <2>; 4786 }; 4787 4788 sdhc_2: mmc@8804000 { 4789 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; 4790 reg = <0 0x08804000 0 0x1000>; 4791 4792 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4793 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4794 interrupt-names = "hc_irq", "pwr_irq"; 4795 4796 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4797 <&gcc GCC_SDCC2_APPS_CLK>, 4798 <&bi_tcxo_div2>; 4799 clock-names = "iface", "core", "xo"; 4800 iommus = <&apps_smmu 0x520 0>; 4801 qcom,dll-config = <0x0007642c>; 4802 qcom,ddr-config = <0x80040868>; 4803 power-domains = <&rpmhpd RPMHPD_CX>; 4804 operating-points-v2 = <&sdhc2_opp_table>; 4805 4806 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 4807 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4808 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4809 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4810 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 4811 bus-width = <4>; 4812 dma-coherent; 4813 4814 status = "disabled"; 4815 4816 sdhc2_opp_table: opp-table { 4817 compatible = "operating-points-v2"; 4818 4819 opp-19200000 { 4820 opp-hz = /bits/ 64 <19200000>; 4821 required-opps = <&rpmhpd_opp_min_svs>; 4822 }; 4823 4824 opp-50000000 { 4825 opp-hz = /bits/ 64 <50000000>; 4826 required-opps = <&rpmhpd_opp_low_svs>; 4827 }; 4828 4829 opp-100000000 { 4830 opp-hz = /bits/ 64 <100000000>; 4831 required-opps = <&rpmhpd_opp_svs>; 4832 }; 4833 4834 opp-202000000 { 4835 opp-hz = /bits/ 64 <202000000>; 4836 required-opps = <&rpmhpd_opp_svs_l1>; 4837 }; 4838 }; 4839 }; 4840 4841 sdhc_4: mmc@8844000 { 4842 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; 4843 reg = <0 0x08844000 0 0x1000>; 4844 4845 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 4846 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 4847 interrupt-names = "hc_irq", "pwr_irq"; 4848 4849 clocks = <&gcc GCC_SDCC4_AHB_CLK>, 4850 <&gcc GCC_SDCC4_APPS_CLK>, 4851 <&bi_tcxo_div2>; 4852 clock-names = "iface", "core", "xo"; 4853 iommus = <&apps_smmu 0x160 0>; 4854 qcom,dll-config = <0x0007642c>; 4855 qcom,ddr-config = <0x80040868>; 4856 power-domains = <&rpmhpd RPMHPD_CX>; 4857 operating-points-v2 = <&sdhc4_opp_table>; 4858 4859 interconnects = <&aggre2_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS 4860 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4861 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4862 &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 4863 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 4864 bus-width = <4>; 4865 dma-coherent; 4866 4867 status = "disabled"; 4868 4869 sdhc4_opp_table: opp-table { 4870 compatible = "operating-points-v2"; 4871 4872 opp-19200000 { 4873 opp-hz = /bits/ 64 <19200000>; 4874 required-opps = <&rpmhpd_opp_min_svs>; 4875 }; 4876 4877 opp-50000000 { 4878 opp-hz = /bits/ 64 <50000000>; 4879 required-opps = <&rpmhpd_opp_low_svs>; 4880 }; 4881 4882 opp-100000000 { 4883 opp-hz = /bits/ 64 <100000000>; 4884 required-opps = <&rpmhpd_opp_svs>; 4885 }; 4886 4887 opp-202000000 { 4888 opp-hz = /bits/ 64 <202000000>; 4889 required-opps = <&rpmhpd_opp_svs_l1>; 4890 }; 4891 }; 4892 }; 4893 4894 usb_2_hsphy: phy@88e0000 { 4895 compatible = "qcom,x1e80100-snps-eusb2-phy", 4896 "qcom,sm8550-snps-eusb2-phy"; 4897 reg = <0 0x088e0000 0 0x154>; 4898 #phy-cells = <0>; 4899 4900 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 4901 clock-names = "ref"; 4902 4903 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 4904 4905 status = "disabled"; 4906 }; 4907 4908 usb_mp_hsphy0: phy@88e1000 { 4909 compatible = "qcom,x1e80100-snps-eusb2-phy", 4910 "qcom,sm8550-snps-eusb2-phy"; 4911 reg = <0 0x088e1000 0 0x154>; 4912 #phy-cells = <0>; 4913 4914 clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>; 4915 clock-names = "ref"; 4916 4917 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 4918 4919 status = "disabled"; 4920 }; 4921 4922 usb_mp_hsphy1: phy@88e2000 { 4923 compatible = "qcom,x1e80100-snps-eusb2-phy", 4924 "qcom,sm8550-snps-eusb2-phy"; 4925 reg = <0 0x088e2000 0 0x154>; 4926 #phy-cells = <0>; 4927 4928 clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>; 4929 clock-names = "ref"; 4930 4931 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 4932 4933 status = "disabled"; 4934 }; 4935 4936 usb_mp_qmpphy0: phy@88e3000 { 4937 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4938 reg = <0 0x088e3000 0 0x2000>; 4939 4940 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4941 <&rpmhcc RPMH_CXO_CLK>, 4942 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4943 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 4944 clock-names = "aux", 4945 "ref", 4946 "com_aux", 4947 "pipe"; 4948 4949 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 4950 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 4951 reset-names = "phy", 4952 "phy_phy"; 4953 4954 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 4955 4956 #clock-cells = <0>; 4957 clock-output-names = "usb_mp_phy0_pipe_clk"; 4958 4959 #phy-cells = <0>; 4960 4961 status = "disabled"; 4962 }; 4963 4964 usb_mp_qmpphy1: phy@88e5000 { 4965 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4966 reg = <0 0x088e5000 0 0x2000>; 4967 4968 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4969 <&rpmhcc RPMH_CXO_CLK>, 4970 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4971 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 4972 clock-names = "aux", 4973 "ref", 4974 "com_aux", 4975 "pipe"; 4976 4977 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 4978 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 4979 reset-names = "phy", 4980 "phy_phy"; 4981 4982 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 4983 4984 #clock-cells = <0>; 4985 clock-output-names = "usb_mp_phy1_pipe_clk"; 4986 4987 #phy-cells = <0>; 4988 4989 status = "disabled"; 4990 }; 4991 4992 usb_1_ss2: usb@a000000 { 4993 compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3"; 4994 reg = <0 0x0a000000 0 0xfc100>; 4995 4996 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 4997 <&gcc GCC_USB30_TERT_MASTER_CLK>, 4998 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 4999 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 5000 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 5001 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5002 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5003 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5004 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5005 clock-names = "cfg_noc", 5006 "core", 5007 "iface", 5008 "sleep", 5009 "mock_utmi", 5010 "noc_aggr", 5011 "noc_aggr_north", 5012 "noc_aggr_south", 5013 "noc_sys"; 5014 5015 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 5016 <&gcc GCC_USB30_TERT_MASTER_CLK>; 5017 assigned-clock-rates = <19200000>, 5018 <200000000>; 5019 5020 interrupts-extended = <&intc GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 5021 <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 5022 <&pdc 58 IRQ_TYPE_EDGE_BOTH>, 5023 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 5024 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>; 5025 interrupt-names = "dwc_usb3", 5026 "pwr_event", 5027 "dp_hs_phy_irq", 5028 "dm_hs_phy_irq", 5029 "ss_phy_irq"; 5030 5031 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 5032 required-opps = <&rpmhpd_opp_nom>; 5033 5034 resets = <&gcc GCC_USB30_TERT_BCR>; 5035 5036 interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS 5037 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5038 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5039 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 5040 interconnect-names = "usb-ddr", 5041 "apps-usb"; 5042 5043 wakeup-source; 5044 5045 iommus = <&apps_smmu 0x14a0 0x0>; 5046 5047 phys = <&usb_1_ss2_hsphy>, 5048 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; 5049 phy-names = "usb2-phy", 5050 "usb3-phy"; 5051 5052 snps,dis_u2_susphy_quirk; 5053 snps,dis_enblslpm_quirk; 5054 snps,usb3_lpm_capable; 5055 snps,dis-u1-entry-quirk; 5056 snps,dis-u2-entry-quirk; 5057 5058 dma-coherent; 5059 5060 status = "disabled"; 5061 5062 ports { 5063 #address-cells = <1>; 5064 #size-cells = <0>; 5065 5066 port@0 { 5067 reg = <0>; 5068 5069 usb_1_ss2_dwc3_hs: endpoint { 5070 }; 5071 }; 5072 5073 port@1 { 5074 reg = <1>; 5075 5076 usb_1_ss2_dwc3_ss: endpoint { 5077 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; 5078 }; 5079 }; 5080 }; 5081 }; 5082 5083 usb_2: usb@a200000 { 5084 compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3"; 5085 reg = <0 0x0a200000 0 0xfc100>; 5086 5087 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 5088 <&gcc GCC_USB20_MASTER_CLK>, 5089 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 5090 <&gcc GCC_USB20_SLEEP_CLK>, 5091 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 5092 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5093 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5094 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5095 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5096 clock-names = "cfg_noc", 5097 "core", 5098 "iface", 5099 "sleep", 5100 "mock_utmi", 5101 "noc_aggr", 5102 "noc_aggr_north", 5103 "noc_aggr_south", 5104 "noc_sys"; 5105 5106 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 5107 <&gcc GCC_USB20_MASTER_CLK>; 5108 assigned-clock-rates = <19200000>, <200000000>; 5109 5110 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 5111 <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 5112 <&pdc 50 IRQ_TYPE_EDGE_BOTH>, 5113 <&pdc 49 IRQ_TYPE_EDGE_BOTH>; 5114 interrupt-names = "dwc_usb3", 5115 "pwr_event", 5116 "dp_hs_phy_irq", 5117 "dm_hs_phy_irq"; 5118 5119 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 5120 required-opps = <&rpmhpd_opp_nom>; 5121 5122 resets = <&gcc GCC_USB20_PRIM_BCR>; 5123 5124 interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 5125 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5126 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5127 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; 5128 interconnect-names = "usb-ddr", 5129 "apps-usb"; 5130 5131 qcom,select-utmi-as-pipe-clk; 5132 wakeup-source; 5133 5134 iommus = <&apps_smmu 0x14e0 0x0>; 5135 phys = <&usb_2_hsphy>; 5136 phy-names = "usb2-phy"; 5137 maximum-speed = "high-speed"; 5138 snps,dis-u1-entry-quirk; 5139 snps,dis-u2-entry-quirk; 5140 5141 dma-coherent; 5142 5143 status = "disabled"; 5144 5145 port { 5146 usb_2_dwc3_hs: endpoint { 5147 }; 5148 }; 5149 }; 5150 5151 usb_mp: usb@a400000 { 5152 compatible = "qcom,x1e80100-dwc3-mp", "qcom,snps-dwc3"; 5153 reg = <0 0x0a400000 0 0xfc100>; 5154 5155 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 5156 <&gcc GCC_USB30_MP_MASTER_CLK>, 5157 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 5158 <&gcc GCC_USB30_MP_SLEEP_CLK>, 5159 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 5160 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5161 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5162 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5163 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5164 clock-names = "cfg_noc", 5165 "core", 5166 "iface", 5167 "sleep", 5168 "mock_utmi", 5169 "noc_aggr", 5170 "noc_aggr_north", 5171 "noc_aggr_south", 5172 "noc_sys"; 5173 5174 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 5175 <&gcc GCC_USB30_MP_MASTER_CLK>; 5176 assigned-clock-rates = <19200000>, 5177 <200000000>; 5178 5179 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 5180 <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 5181 <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 5182 <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 5183 <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 5184 <&pdc 52 IRQ_TYPE_EDGE_BOTH>, 5185 <&pdc 51 IRQ_TYPE_EDGE_BOTH>, 5186 <&pdc 54 IRQ_TYPE_EDGE_BOTH>, 5187 <&pdc 53 IRQ_TYPE_EDGE_BOTH>, 5188 <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, 5189 <&pdc 56 IRQ_TYPE_LEVEL_HIGH>; 5190 interrupt-names = "dwc_usb3", 5191 "pwr_event_1", "pwr_event_2", 5192 "hs_phy_1", "hs_phy_2", 5193 "dp_hs_phy_1", "dm_hs_phy_1", 5194 "dp_hs_phy_2", "dm_hs_phy_2", 5195 "ss_phy_1", "ss_phy_2"; 5196 5197 power-domains = <&gcc GCC_USB30_MP_GDSC>; 5198 required-opps = <&rpmhpd_opp_nom>; 5199 5200 resets = <&gcc GCC_USB30_MP_BCR>; 5201 5202 interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS 5203 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5204 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5205 &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ACTIVE_ONLY>; 5206 interconnect-names = "usb-ddr", 5207 "apps-usb"; 5208 5209 wakeup-source; 5210 5211 iommus = <&apps_smmu 0x1400 0x0>; 5212 5213 phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>, 5214 <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>; 5215 phy-names = "usb2-0", "usb3-0", 5216 "usb2-1", "usb3-1"; 5217 dr_mode = "host"; 5218 5219 snps,dis_u2_susphy_quirk; 5220 snps,dis_enblslpm_quirk; 5221 snps,usb3_lpm_capable; 5222 snps,dis-u1-entry-quirk; 5223 snps,dis-u2-entry-quirk; 5224 5225 dma-coherent; 5226 5227 status = "disabled"; 5228 }; 5229 5230 usb_1_ss0: usb@a600000 { 5231 compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3"; 5232 reg = <0 0x0a600000 0 0xfc100>; 5233 5234 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5235 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5236 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5237 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5238 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5239 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5240 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>, 5241 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>, 5242 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5243 clock-names = "cfg_noc", 5244 "core", 5245 "iface", 5246 "sleep", 5247 "mock_utmi", 5248 "noc_aggr", 5249 "noc_aggr_north", 5250 "noc_aggr_south", 5251 "noc_sys"; 5252 5253 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5254 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5255 assigned-clock-rates = <19200000>, 5256 <200000000>; 5257 5258 interrupts-extended = <&intc GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 5259 <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 5260 <&pdc 61 IRQ_TYPE_EDGE_BOTH>, 5261 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 5262 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 5263 interrupt-names = "dwc_usb3", 5264 "pwr_event", 5265 "dp_hs_phy_irq", 5266 "dm_hs_phy_irq", 5267 "ss_phy_irq"; 5268 5269 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 5270 required-opps = <&rpmhpd_opp_nom>; 5271 5272 resets = <&gcc GCC_USB30_PRIM_BCR>; 5273 5274 interconnects = <&usb_south_anoc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 5275 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5276 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5277 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 5278 interconnect-names = "usb-ddr", 5279 "apps-usb"; 5280 5281 wakeup-source; 5282 5283 iommus = <&apps_smmu 0x1420 0x0>; 5284 5285 phys = <&usb_1_ss0_hsphy>, 5286 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; 5287 phy-names = "usb2-phy", 5288 "usb3-phy"; 5289 5290 snps,dis_u2_susphy_quirk; 5291 snps,dis_enblslpm_quirk; 5292 snps,usb3_lpm_capable; 5293 snps,dis-u1-entry-quirk; 5294 snps,dis-u2-entry-quirk; 5295 5296 dma-coherent; 5297 5298 status = "disabled"; 5299 5300 ports { 5301 #address-cells = <1>; 5302 #size-cells = <0>; 5303 5304 port@0 { 5305 reg = <0>; 5306 5307 usb_1_ss0_dwc3_hs: endpoint { 5308 }; 5309 }; 5310 5311 port@1 { 5312 reg = <1>; 5313 5314 usb_1_ss0_dwc3_ss: endpoint { 5315 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; 5316 }; 5317 }; 5318 }; 5319 }; 5320 5321 usb_1_ss1: usb@a800000 { 5322 compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3"; 5323 reg = <0 0x0a800000 0 0xfc100>; 5324 5325 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 5326 <&gcc GCC_USB30_SEC_MASTER_CLK>, 5327 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 5328 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 5329 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5330 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5331 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5332 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5333 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5334 clock-names = "cfg_noc", 5335 "core", 5336 "iface", 5337 "sleep", 5338 "mock_utmi", 5339 "noc_aggr", 5340 "noc_aggr_north", 5341 "noc_aggr_south", 5342 "noc_sys"; 5343 5344 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5345 <&gcc GCC_USB30_SEC_MASTER_CLK>; 5346 assigned-clock-rates = <19200000>, 5347 <200000000>; 5348 5349 interrupts-extended = <&intc GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 5350 <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 5351 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 5352 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 5353 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; 5354 interrupt-names = "dwc_usb3", 5355 "pwr_event", 5356 "dp_hs_phy_irq", 5357 "dm_hs_phy_irq", 5358 "ss_phy_irq"; 5359 5360 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 5361 required-opps = <&rpmhpd_opp_nom>; 5362 5363 resets = <&gcc GCC_USB30_SEC_BCR>; 5364 5365 interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS 5366 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5367 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5368 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5369 interconnect-names = "usb-ddr", 5370 "apps-usb"; 5371 5372 wakeup-source; 5373 5374 iommus = <&apps_smmu 0x1460 0x0>; 5375 5376 phys = <&usb_1_ss1_hsphy>, 5377 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; 5378 phy-names = "usb2-phy", 5379 "usb3-phy"; 5380 5381 snps,dis_u2_susphy_quirk; 5382 snps,dis_enblslpm_quirk; 5383 snps,usb3_lpm_capable; 5384 snps,dis-u1-entry-quirk; 5385 snps,dis-u2-entry-quirk; 5386 5387 dma-coherent; 5388 5389 status = "disabled"; 5390 5391 ports { 5392 #address-cells = <1>; 5393 #size-cells = <0>; 5394 5395 port@0 { 5396 reg = <0>; 5397 5398 usb_1_ss1_dwc3_hs: endpoint { 5399 }; 5400 }; 5401 5402 port@1 { 5403 reg = <1>; 5404 5405 usb_1_ss1_dwc3_ss: endpoint { 5406 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; 5407 }; 5408 }; 5409 }; 5410 }; 5411 5412 iris: video-codec@aa00000 { 5413 compatible = "qcom,x1e80100-iris", "qcom,sm8550-iris"; 5414 5415 reg = <0 0x0aa00000 0 0xf0000>; 5416 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 5417 5418 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 5419 <&videocc VIDEO_CC_MVS0_GDSC>, 5420 <&rpmhpd RPMHPD_MXC>, 5421 <&rpmhpd RPMHPD_MMCX>; 5422 power-domain-names = "venus", 5423 "vcodec0", 5424 "mxc", 5425 "mmcx"; 5426 operating-points-v2 = <&iris_opp_table>; 5427 5428 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 5429 <&videocc VIDEO_CC_MVS0C_CLK>, 5430 <&videocc VIDEO_CC_MVS0_CLK>; 5431 clock-names = "iface", 5432 "core", 5433 "vcodec0_core"; 5434 5435 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5436 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5437 <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS 5438 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5439 interconnect-names = "cpu-cfg", 5440 "video-mem"; 5441 5442 memory-region = <&video_mem>; 5443 5444 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 5445 reset-names = "bus"; 5446 5447 iommus = <&apps_smmu 0x1940 0>, 5448 <&apps_smmu 0x1947 0>; 5449 dma-coherent; 5450 5451 /* 5452 * IRIS firmware is signed by vendors, only 5453 * enable on boards where the proper signed firmware 5454 * is available. 5455 */ 5456 status = "disabled"; 5457 5458 iris_opp_table: opp-table { 5459 compatible = "operating-points-v2"; 5460 5461 opp-192000000 { 5462 opp-hz = /bits/ 64 <192000000>; 5463 required-opps = <&rpmhpd_opp_low_svs_d1>, 5464 <&rpmhpd_opp_low_svs_d1>; 5465 }; 5466 5467 opp-240000000 { 5468 opp-hz = /bits/ 64 <240000000>; 5469 required-opps = <&rpmhpd_opp_svs>, 5470 <&rpmhpd_opp_low_svs>; 5471 }; 5472 5473 opp-338000000 { 5474 opp-hz = /bits/ 64 <338000000>; 5475 required-opps = <&rpmhpd_opp_svs>, 5476 <&rpmhpd_opp_svs>; 5477 }; 5478 5479 opp-366000000 { 5480 opp-hz = /bits/ 64 <366000000>; 5481 required-opps = <&rpmhpd_opp_svs>, 5482 <&rpmhpd_opp_svs_l1>; 5483 }; 5484 5485 opp-444000000 { 5486 opp-hz = /bits/ 64 <444000000>; 5487 required-opps = <&rpmhpd_opp_svs_l1>, 5488 <&rpmhpd_opp_nom>; 5489 }; 5490 5491 opp-481000000 { 5492 opp-hz = /bits/ 64 <481000000>; 5493 required-opps = <&rpmhpd_opp_svs_l1>, 5494 <&rpmhpd_opp_turbo>; 5495 }; 5496 }; 5497 }; 5498 5499 videocc: clock-controller@aaf0000 { 5500 compatible = "qcom,x1e80100-videocc"; 5501 reg = <0 0x0aaf0000 0 0x10000>; 5502 clocks = <&bi_tcxo_div2>, 5503 <&gcc GCC_VIDEO_AHB_CLK>; 5504 power-domains = <&rpmhpd RPMHPD_MMCX>, 5505 <&rpmhpd RPMHPD_MXC>; 5506 required-opps = <&rpmhpd_opp_low_svs>, 5507 <&rpmhpd_opp_low_svs>; 5508 #clock-cells = <1>; 5509 #reset-cells = <1>; 5510 #power-domain-cells = <1>; 5511 }; 5512 5513 camcc: clock-controller@ade0000 { 5514 compatible = "qcom,x1e80100-camcc"; 5515 reg = <0x0 0x0ade0000 0x0 0x20000>; 5516 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 5517 <&bi_tcxo_div2>, 5518 <&bi_tcxo_ao_div2>, 5519 <&sleep_clk>; 5520 power-domains = <&rpmhpd RPMHPD_MXC>, 5521 <&rpmhpd RPMHPD_MMCX>; 5522 required-opps = <&rpmhpd_opp_low_svs>, 5523 <&rpmhpd_opp_low_svs>; 5524 #clock-cells = <1>; 5525 #reset-cells = <1>; 5526 #power-domain-cells = <1>; 5527 }; 5528 5529 mdss: display-subsystem@ae00000 { 5530 compatible = "qcom,x1e80100-mdss"; 5531 reg = <0 0x0ae00000 0 0x1000>; 5532 reg-names = "mdss"; 5533 5534 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 5535 5536 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5537 <&gcc GCC_DISP_HF_AXI_CLK>, 5538 <&dispcc DISP_CC_MDSS_MDP_CLK>; 5539 5540 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 5541 5542 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 5543 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 5544 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 5545 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5546 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5547 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5548 interconnect-names = "mdp0-mem", 5549 "mdp1-mem", 5550 "cpu-cfg"; 5551 5552 power-domains = <&dispcc MDSS_GDSC>; 5553 5554 iommus = <&apps_smmu 0x1c00 0x2>; 5555 5556 interrupt-controller; 5557 #interrupt-cells = <1>; 5558 5559 #address-cells = <2>; 5560 #size-cells = <2>; 5561 ranges; 5562 5563 status = "disabled"; 5564 5565 mdss_mdp: display-controller@ae01000 { 5566 compatible = "qcom,x1e80100-dpu"; 5567 reg = <0 0x0ae01000 0 0x8f000>, 5568 <0 0x0aeb0000 0 0x2008>; 5569 reg-names = "mdp", 5570 "vbif"; 5571 5572 interrupts-extended = <&mdss 0>; 5573 5574 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5575 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5576 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 5577 <&dispcc DISP_CC_MDSS_MDP_CLK>, 5578 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5579 clock-names = "nrt_bus", 5580 "iface", 5581 "lut", 5582 "core", 5583 "vsync"; 5584 5585 operating-points-v2 = <&mdp_opp_table>; 5586 5587 power-domains = <&rpmhpd RPMHPD_MMCX>; 5588 5589 ports { 5590 #address-cells = <1>; 5591 #size-cells = <0>; 5592 5593 port@0 { 5594 reg = <0>; 5595 5596 mdss_intf0_out: endpoint { 5597 remote-endpoint = <&mdss_dp0_in>; 5598 }; 5599 }; 5600 5601 port@4 { 5602 reg = <4>; 5603 5604 mdss_intf4_out: endpoint { 5605 remote-endpoint = <&mdss_dp1_in>; 5606 }; 5607 }; 5608 5609 port@5 { 5610 reg = <5>; 5611 5612 mdss_intf5_out: endpoint { 5613 remote-endpoint = <&mdss_dp3_in>; 5614 }; 5615 }; 5616 5617 port@6 { 5618 reg = <6>; 5619 5620 mdss_intf6_out: endpoint { 5621 remote-endpoint = <&mdss_dp2_in>; 5622 }; 5623 }; 5624 }; 5625 5626 mdp_opp_table: opp-table { 5627 compatible = "operating-points-v2"; 5628 5629 opp-200000000 { 5630 opp-hz = /bits/ 64 <200000000>; 5631 required-opps = <&rpmhpd_opp_low_svs>; 5632 }; 5633 5634 opp-325000000 { 5635 opp-hz = /bits/ 64 <325000000>; 5636 required-opps = <&rpmhpd_opp_svs>; 5637 }; 5638 5639 opp-375000000 { 5640 opp-hz = /bits/ 64 <375000000>; 5641 required-opps = <&rpmhpd_opp_svs_l1>; 5642 }; 5643 5644 opp-514000000 { 5645 opp-hz = /bits/ 64 <514000000>; 5646 required-opps = <&rpmhpd_opp_nom>; 5647 }; 5648 5649 opp-575000000 { 5650 opp-hz = /bits/ 64 <575000000>; 5651 required-opps = <&rpmhpd_opp_nom_l1>; 5652 }; 5653 }; 5654 }; 5655 5656 mdss_dp0: displayport-controller@ae90000 { 5657 compatible = "qcom,x1e80100-dp"; 5658 reg = <0 0x0ae90000 0 0x200>, 5659 <0 0x0ae90200 0 0x200>, 5660 <0 0x0ae90400 0 0xc00>, 5661 <0 0x0ae91000 0 0x400>, 5662 <0 0x0ae91400 0 0x400>; 5663 5664 interrupts-extended = <&mdss 12>; 5665 5666 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5667 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 5668 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 5669 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5670 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5671 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 5672 clock-names = "core_iface", 5673 "core_aux", 5674 "ctrl_link", 5675 "ctrl_link_iface", 5676 "stream_pixel", 5677 "stream_1_pixel"; 5678 5679 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5680 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5681 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 5682 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5683 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5684 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5685 5686 operating-points-v2 = <&mdss_dp0_opp_table>; 5687 5688 power-domains = <&rpmhpd RPMHPD_MMCX>; 5689 5690 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; 5691 phy-names = "dp"; 5692 5693 #sound-dai-cells = <0>; 5694 sound-name-prefix = "DisplayPort0"; 5695 5696 status = "disabled"; 5697 5698 ports { 5699 #address-cells = <1>; 5700 #size-cells = <0>; 5701 5702 port@0 { 5703 reg = <0>; 5704 5705 mdss_dp0_in: endpoint { 5706 remote-endpoint = <&mdss_intf0_out>; 5707 }; 5708 }; 5709 5710 port@1 { 5711 reg = <1>; 5712 5713 mdss_dp0_out: endpoint { 5714 data-lanes = <0 1 2 3>; 5715 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; 5716 }; 5717 }; 5718 }; 5719 5720 mdss_dp0_opp_table: opp-table { 5721 compatible = "operating-points-v2"; 5722 5723 opp-270000000 { 5724 opp-hz = /bits/ 64 <270000000>; 5725 required-opps = <&rpmhpd_opp_low_svs>; 5726 }; 5727 5728 opp-540000000 { 5729 opp-hz = /bits/ 64 <540000000>; 5730 required-opps = <&rpmhpd_opp_svs>; 5731 }; 5732 5733 opp-594000000 { 5734 opp-hz = /bits/ 64 <594000000>; 5735 required-opps = <&rpmhpd_opp_svs_l1>; 5736 }; 5737 5738 opp-810000000 { 5739 opp-hz = /bits/ 64 <810000000>; 5740 required-opps = <&rpmhpd_opp_nom>; 5741 }; 5742 }; 5743 }; 5744 5745 mdss_dp1: displayport-controller@ae98000 { 5746 compatible = "qcom,x1e80100-dp"; 5747 reg = <0 0x0ae98000 0 0x200>, 5748 <0 0x0ae98200 0 0x200>, 5749 <0 0x0ae98400 0 0xc00>, 5750 <0 0x0ae99000 0 0x400>, 5751 <0 0x0ae99400 0 0x400>; 5752 5753 interrupts-extended = <&mdss 13>; 5754 5755 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5756 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 5757 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 5758 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5759 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 5760 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 5761 clock-names = "core_iface", 5762 "core_aux", 5763 "ctrl_link", 5764 "ctrl_link_iface", 5765 "stream_pixel", 5766 "stream_1_pixel"; 5767 5768 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5769 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 5770 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 5771 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5772 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5773 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5774 5775 operating-points-v2 = <&mdss_dp0_opp_table>; 5776 5777 power-domains = <&rpmhpd RPMHPD_MMCX>; 5778 5779 phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; 5780 phy-names = "dp"; 5781 5782 #sound-dai-cells = <0>; 5783 sound-name-prefix = "DisplayPort1"; 5784 5785 status = "disabled"; 5786 5787 ports { 5788 #address-cells = <1>; 5789 #size-cells = <0>; 5790 5791 port@0 { 5792 reg = <0>; 5793 5794 mdss_dp1_in: endpoint { 5795 remote-endpoint = <&mdss_intf4_out>; 5796 }; 5797 }; 5798 5799 port@1 { 5800 reg = <1>; 5801 5802 mdss_dp1_out: endpoint { 5803 data-lanes = <0 1 2 3>; 5804 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; 5805 }; 5806 }; 5807 }; 5808 }; 5809 5810 mdss_dp2: displayport-controller@ae9a000 { 5811 compatible = "qcom,x1e80100-dp"; 5812 reg = <0 0x0ae9a000 0 0x200>, 5813 <0 0x0ae9a200 0 0x200>, 5814 <0 0x0ae9a400 0 0xc00>, 5815 <0 0x0ae9b000 0 0x400>, 5816 <0 0x0ae9b400 0 0x400>; 5817 5818 interrupts-extended = <&mdss 14>; 5819 5820 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5821 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5822 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 5823 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5824 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 5825 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 5826 clock-names = "core_iface", 5827 "core_aux", 5828 "ctrl_link", 5829 "ctrl_link_iface", 5830 "stream_pixel", 5831 "stream_1_pixel"; 5832 5833 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5834 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 5835 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 5836 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5837 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5838 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5839 5840 operating-points-v2 = <&mdss_dp0_opp_table>; 5841 5842 power-domains = <&rpmhpd RPMHPD_MMCX>; 5843 5844 phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>; 5845 phy-names = "dp"; 5846 5847 #sound-dai-cells = <0>; 5848 sound-name-prefix = "DisplayPort2"; 5849 5850 status = "disabled"; 5851 5852 ports { 5853 #address-cells = <1>; 5854 #size-cells = <0>; 5855 5856 port@0 { 5857 reg = <0>; 5858 mdss_dp2_in: endpoint { 5859 remote-endpoint = <&mdss_intf6_out>; 5860 }; 5861 }; 5862 5863 port@1 { 5864 reg = <1>; 5865 5866 mdss_dp2_out: endpoint { 5867 data-lanes = <0 1 2 3>; 5868 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; 5869 }; 5870 }; 5871 }; 5872 }; 5873 5874 mdss_dp3: displayport-controller@aea0000 { 5875 compatible = "qcom,x1e80100-dp"; 5876 reg = <0 0x0aea0000 0 0x200>, 5877 <0 0x0aea0200 0 0x200>, 5878 <0 0x0aea0400 0 0xc00>, 5879 <0 0x0aea1000 0 0x400>, 5880 <0 0x0aea1400 0 0x400>; 5881 5882 interrupts-extended = <&mdss 15>; 5883 5884 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5885 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5886 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 5887 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5888 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5889 clock-names = "core_iface", 5890 "core_aux", 5891 "ctrl_link", 5892 "ctrl_link_iface", 5893 "stream_pixel"; 5894 5895 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5896 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5897 assigned-clock-parents = <&mdss_dp3_phy 0>, 5898 <&mdss_dp3_phy 1>; 5899 5900 operating-points-v2 = <&mdss_dp3_opp_table>; 5901 5902 power-domains = <&rpmhpd RPMHPD_MMCX>; 5903 5904 phys = <&mdss_dp3_phy>; 5905 phy-names = "dp"; 5906 5907 #sound-dai-cells = <0>; 5908 sound-name-prefix = "DisplayPort3"; 5909 5910 status = "disabled"; 5911 5912 ports { 5913 #address-cells = <1>; 5914 #size-cells = <0>; 5915 5916 port@0 { 5917 reg = <0>; 5918 5919 mdss_dp3_in: endpoint { 5920 remote-endpoint = <&mdss_intf5_out>; 5921 }; 5922 }; 5923 5924 port@1 { 5925 reg = <1>; 5926 5927 mdss_dp3_out: endpoint { 5928 }; 5929 }; 5930 }; 5931 5932 mdss_dp3_opp_table: opp-table { 5933 compatible = "operating-points-v2"; 5934 5935 opp-270000000 { 5936 opp-hz = /bits/ 64 <270000000>; 5937 required-opps = <&rpmhpd_opp_low_svs>; 5938 }; 5939 5940 opp-594000000 { 5941 opp-hz = /bits/ 64 <594000000>; 5942 required-opps = <&rpmhpd_opp_svs>; 5943 }; 5944 5945 opp-810000000 { 5946 opp-hz = /bits/ 64 <810000000>; 5947 required-opps = <&rpmhpd_opp_nom>; 5948 }; 5949 }; 5950 }; 5951 5952 }; 5953 5954 mdss_dp2_phy: phy@aec2a00 { 5955 compatible = "qcom,x1e80100-dp-phy"; 5956 reg = <0 0x0aec2a00 0 0x19c>, 5957 <0 0x0aec2200 0 0xec>, 5958 <0 0x0aec2600 0 0xec>, 5959 <0 0x0aec2000 0 0x1c8>; 5960 5961 clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5962 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5963 <&tcsr TCSR_EDP_CLKREF_EN>; 5964 clock-names = "aux", 5965 "cfg_ahb", 5966 "ref"; 5967 5968 power-domains = <&rpmhpd RPMHPD_MX>; 5969 5970 #clock-cells = <1>; 5971 #phy-cells = <0>; 5972 5973 status = "disabled"; 5974 }; 5975 5976 mdss_dp3_phy: phy@aec5a00 { 5977 compatible = "qcom,x1e80100-dp-phy"; 5978 reg = <0 0x0aec5a00 0 0x19c>, 5979 <0 0x0aec5200 0 0xec>, 5980 <0 0x0aec5600 0 0xec>, 5981 <0 0x0aec5000 0 0x1c8>; 5982 5983 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5984 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5985 <&tcsr TCSR_EDP_CLKREF_EN>; 5986 clock-names = "aux", 5987 "cfg_ahb", 5988 "ref"; 5989 5990 power-domains = <&rpmhpd RPMHPD_MX>; 5991 5992 #clock-cells = <1>; 5993 #phy-cells = <0>; 5994 5995 status = "disabled"; 5996 }; 5997 5998 dispcc: clock-controller@af00000 { 5999 compatible = "qcom,x1e80100-dispcc"; 6000 reg = <0 0x0af00000 0 0x20000>; 6001 clocks = <&bi_tcxo_div2>, 6002 <&bi_tcxo_ao_div2>, 6003 <&gcc GCC_DISP_AHB_CLK>, 6004 <&sleep_clk>, 6005 <0>, /* dsi0 */ 6006 <0>, 6007 <0>, /* dsi1 */ 6008 <0>, 6009 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 6010 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 6011 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 6012 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 6013 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 6014 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 6015 <&mdss_dp3_phy 0>, /* dp3 */ 6016 <&mdss_dp3_phy 1>; 6017 power-domains = <&rpmhpd RPMHPD_MMCX>; 6018 required-opps = <&rpmhpd_opp_low_svs>; 6019 #clock-cells = <1>; 6020 #reset-cells = <1>; 6021 #power-domain-cells = <1>; 6022 }; 6023 6024 pdc: interrupt-controller@b220000 { 6025 compatible = "qcom,x1e80100-pdc", "qcom,pdc"; 6026 reg = <0 0x0b220000 0 0x10000>, <0 0x174000f0 0 0x64>; 6027 6028 qcom,pdc-ranges = <0 480 42>, <42 251 5>, 6029 <47 522 52>, <99 609 32>, 6030 <131 717 12>, <143 816 19>; 6031 #interrupt-cells = <2>; 6032 interrupt-parent = <&intc>; 6033 interrupt-controller; 6034 }; 6035 6036 aoss_qmp: power-management@c300000 { 6037 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp"; 6038 reg = <0 0x0c300000 0 0x400>; 6039 interrupt-parent = <&ipcc>; 6040 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 6041 IRQ_TYPE_EDGE_RISING>; 6042 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 6043 6044 #clock-cells = <0>; 6045 }; 6046 6047 sram@c3f0000 { 6048 compatible = "qcom,rpmh-stats"; 6049 reg = <0 0x0c3f0000 0 0x400>; 6050 }; 6051 6052 spmi: arbiter@c400000 { 6053 compatible = "qcom,x1e80100-spmi-pmic-arb"; 6054 reg = <0 0x0c400000 0 0x3000>, 6055 <0 0x0c500000 0 0x400000>, 6056 <0 0x0c440000 0 0x80000>; 6057 reg-names = "core", "chnls", "obsrvr"; 6058 6059 qcom,ee = <0>; 6060 qcom,channel = <0>; 6061 6062 #address-cells = <2>; 6063 #size-cells = <2>; 6064 ranges; 6065 6066 spmi_bus0: spmi@c42d000 { 6067 reg = <0 0x0c42d000 0 0x4000>, 6068 <0 0x0c4c0000 0 0x10000>; 6069 reg-names = "cnfg", "intr"; 6070 6071 interrupt-names = "periph_irq"; 6072 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 6073 interrupt-controller; 6074 #interrupt-cells = <4>; 6075 6076 #address-cells = <2>; 6077 #size-cells = <0>; 6078 }; 6079 6080 spmi_bus1: spmi@c432000 { 6081 reg = <0 0x0c432000 0 0x4000>, 6082 <0 0x0c4d0000 0 0x10000>; 6083 reg-names = "cnfg", "intr"; 6084 6085 interrupt-names = "periph_irq"; 6086 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 6087 interrupt-controller; 6088 #interrupt-cells = <4>; 6089 6090 #address-cells = <2>; 6091 #size-cells = <0>; 6092 }; 6093 }; 6094 6095 tlmm: pinctrl@f100000 { 6096 compatible = "qcom,x1e80100-tlmm"; 6097 reg = <0 0x0f100000 0 0xf00000>; 6098 6099 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 6100 6101 gpio-controller; 6102 #gpio-cells = <2>; 6103 6104 interrupt-controller; 6105 #interrupt-cells = <2>; 6106 6107 gpio-ranges = <&tlmm 0 0 239>; 6108 wakeup-parent = <&pdc>; 6109 6110 edp0_hpd_default: edp0-hpd-default-state { 6111 pins = "gpio119"; 6112 function = "edp0_hot"; 6113 bias-disable; 6114 }; 6115 6116 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 6117 /* SDA, SCL */ 6118 pins = "gpio0", "gpio1"; 6119 function = "qup0_se0"; 6120 drive-strength = <2>; 6121 bias-pull-up = <2200>; 6122 }; 6123 6124 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 6125 /* SDA, SCL */ 6126 pins = "gpio4", "gpio5"; 6127 function = "qup0_se1"; 6128 drive-strength = <2>; 6129 bias-pull-up = <2200>; 6130 }; 6131 6132 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 6133 /* SDA, SCL */ 6134 pins = "gpio8", "gpio9"; 6135 function = "qup0_se2"; 6136 drive-strength = <2>; 6137 bias-pull-up = <2200>; 6138 }; 6139 6140 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 6141 /* SDA, SCL */ 6142 pins = "gpio12", "gpio13"; 6143 function = "qup0_se3"; 6144 drive-strength = <2>; 6145 bias-pull-up = <2200>; 6146 }; 6147 6148 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 6149 /* SDA, SCL */ 6150 pins = "gpio16", "gpio17"; 6151 function = "qup0_se4"; 6152 drive-strength = <2>; 6153 bias-pull-up = <2200>; 6154 }; 6155 6156 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 6157 /* SDA, SCL */ 6158 pins = "gpio20", "gpio21"; 6159 function = "qup0_se5"; 6160 drive-strength = <2>; 6161 bias-pull-up = <2200>; 6162 }; 6163 6164 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 6165 /* SDA, SCL */ 6166 pins = "gpio24", "gpio25"; 6167 function = "qup0_se6"; 6168 drive-strength = <2>; 6169 bias-pull-up = <2200>; 6170 }; 6171 6172 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 6173 /* SDA, SCL */ 6174 pins = "gpio14", "gpio15"; 6175 function = "qup0_se7"; 6176 drive-strength = <2>; 6177 bias-pull-up = <2200>; 6178 }; 6179 6180 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 6181 /* SDA, SCL */ 6182 pins = "gpio32", "gpio33"; 6183 function = "qup1_se0"; 6184 drive-strength = <2>; 6185 bias-pull-up = <2200>; 6186 }; 6187 6188 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 6189 /* SDA, SCL */ 6190 pins = "gpio36", "gpio37"; 6191 function = "qup1_se1"; 6192 drive-strength = <2>; 6193 bias-pull-up = <2200>; 6194 }; 6195 6196 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 6197 /* SDA, SCL */ 6198 pins = "gpio40", "gpio41"; 6199 function = "qup1_se2"; 6200 drive-strength = <2>; 6201 bias-pull-up = <2200>; 6202 }; 6203 6204 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 6205 /* SDA, SCL */ 6206 pins = "gpio44", "gpio45"; 6207 function = "qup1_se3"; 6208 drive-strength = <2>; 6209 bias-pull-up = <2200>; 6210 }; 6211 6212 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 6213 /* SDA, SCL */ 6214 pins = "gpio48", "gpio49"; 6215 function = "qup1_se4"; 6216 drive-strength = <2>; 6217 bias-pull-up = <2200>; 6218 }; 6219 6220 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 6221 /* SDA, SCL */ 6222 pins = "gpio52", "gpio53"; 6223 function = "qup1_se5"; 6224 drive-strength = <2>; 6225 bias-pull-up = <2200>; 6226 }; 6227 6228 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 6229 /* SDA, SCL */ 6230 pins = "gpio56", "gpio57"; 6231 function = "qup1_se6"; 6232 drive-strength = <2>; 6233 bias-pull-up = <2200>; 6234 }; 6235 6236 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 6237 /* SDA, SCL */ 6238 pins = "gpio54", "gpio55"; 6239 function = "qup1_se7"; 6240 drive-strength = <2>; 6241 bias-pull-up = <2200>; 6242 }; 6243 6244 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 6245 /* SDA, SCL */ 6246 pins = "gpio64", "gpio65"; 6247 function = "qup2_se0"; 6248 drive-strength = <2>; 6249 bias-pull-up = <2200>; 6250 }; 6251 6252 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 6253 /* SDA, SCL */ 6254 pins = "gpio68", "gpio69"; 6255 function = "qup2_se1"; 6256 drive-strength = <2>; 6257 bias-pull-up = <2200>; 6258 }; 6259 6260 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 6261 /* SDA, SCL */ 6262 pins = "gpio72", "gpio73"; 6263 function = "qup2_se2"; 6264 drive-strength = <2>; 6265 bias-pull-up = <2200>; 6266 }; 6267 6268 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 6269 /* SDA, SCL */ 6270 pins = "gpio76", "gpio77"; 6271 function = "qup2_se3"; 6272 drive-strength = <2>; 6273 bias-pull-up = <2200>; 6274 }; 6275 6276 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 6277 /* SDA, SCL */ 6278 pins = "gpio80", "gpio81"; 6279 function = "qup2_se4"; 6280 drive-strength = <2>; 6281 bias-pull-up = <2200>; 6282 }; 6283 6284 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 6285 /* SDA, SCL */ 6286 pins = "gpio84", "gpio85"; 6287 function = "qup2_se5"; 6288 drive-strength = <2>; 6289 bias-pull-up = <2200>; 6290 }; 6291 6292 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 6293 /* SDA, SCL */ 6294 pins = "gpio88", "gpio89"; 6295 function = "qup2_se6"; 6296 drive-strength = <2>; 6297 bias-pull-up = <2200>; 6298 }; 6299 6300 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 6301 /* SDA, SCL */ 6302 pins = "gpio86", "gpio87"; 6303 function = "qup2_se7"; 6304 drive-strength = <2>; 6305 bias-pull-up = <2200>; 6306 }; 6307 6308 qup_spi0_cs: qup-spi0-cs-state { 6309 pins = "gpio3"; 6310 function = "qup0_se0"; 6311 drive-strength = <6>; 6312 bias-disable; 6313 }; 6314 6315 qup_spi0_data_clk: qup-spi0-data-clk-state { 6316 /* MISO, MOSI, CLK */ 6317 pins = "gpio0", "gpio1", "gpio2"; 6318 function = "qup0_se0"; 6319 drive-strength = <6>; 6320 bias-disable; 6321 }; 6322 6323 qup_spi1_cs: qup-spi1-cs-state { 6324 pins = "gpio7"; 6325 function = "qup0_se1"; 6326 drive-strength = <6>; 6327 bias-disable; 6328 }; 6329 6330 qup_spi1_data_clk: qup-spi1-data-clk-state { 6331 /* MISO, MOSI, CLK */ 6332 pins = "gpio4", "gpio5", "gpio6"; 6333 function = "qup0_se1"; 6334 drive-strength = <6>; 6335 bias-disable; 6336 }; 6337 6338 qup_spi2_cs: qup-spi2-cs-state { 6339 pins = "gpio11"; 6340 function = "qup0_se2"; 6341 drive-strength = <6>; 6342 bias-disable; 6343 }; 6344 6345 qup_spi2_data_clk: qup-spi2-data-clk-state { 6346 /* MISO, MOSI, CLK */ 6347 pins = "gpio8", "gpio9", "gpio10"; 6348 function = "qup0_se2"; 6349 drive-strength = <6>; 6350 bias-disable; 6351 }; 6352 6353 qup_spi3_cs: qup-spi3-cs-state { 6354 pins = "gpio15"; 6355 function = "qup0_se3"; 6356 drive-strength = <6>; 6357 bias-disable; 6358 }; 6359 6360 qup_spi3_data_clk: qup-spi3-data-clk-state { 6361 /* MISO, MOSI, CLK */ 6362 pins = "gpio12", "gpio13", "gpio14"; 6363 function = "qup0_se3"; 6364 drive-strength = <6>; 6365 bias-disable; 6366 }; 6367 6368 qup_spi4_cs: qup-spi4-cs-state { 6369 pins = "gpio19"; 6370 function = "qup0_se4"; 6371 drive-strength = <6>; 6372 bias-disable; 6373 }; 6374 6375 qup_spi4_data_clk: qup-spi4-data-clk-state { 6376 /* MISO, MOSI, CLK */ 6377 pins = "gpio16", "gpio17", "gpio18"; 6378 function = "qup0_se4"; 6379 drive-strength = <6>; 6380 bias-disable; 6381 }; 6382 6383 qup_spi5_cs: qup-spi5-cs-state { 6384 pins = "gpio23"; 6385 function = "qup0_se5"; 6386 drive-strength = <6>; 6387 bias-disable; 6388 }; 6389 6390 qup_spi5_data_clk: qup-spi5-data-clk-state { 6391 /* MISO, MOSI, CLK */ 6392 pins = "gpio20", "gpio21", "gpio22"; 6393 function = "qup0_se5"; 6394 drive-strength = <6>; 6395 bias-disable; 6396 }; 6397 6398 qup_spi6_cs: qup-spi6-cs-state { 6399 pins = "gpio27"; 6400 function = "qup0_se6"; 6401 drive-strength = <6>; 6402 bias-disable; 6403 }; 6404 6405 qup_spi6_data_clk: qup-spi6-data-clk-state { 6406 /* MISO, MOSI, CLK */ 6407 pins = "gpio24", "gpio25", "gpio26"; 6408 function = "qup0_se6"; 6409 drive-strength = <6>; 6410 bias-disable; 6411 }; 6412 6413 qup_spi7_cs: qup-spi7-cs-state { 6414 pins = "gpio13"; 6415 function = "qup0_se7"; 6416 drive-strength = <6>; 6417 bias-disable; 6418 }; 6419 6420 qup_spi7_data_clk: qup-spi7-data-clk-state { 6421 /* MISO, MOSI, CLK */ 6422 pins = "gpio14", "gpio15", "gpio12"; 6423 function = "qup0_se7"; 6424 drive-strength = <6>; 6425 bias-disable; 6426 }; 6427 6428 qup_spi8_cs: qup-spi8-cs-state { 6429 pins = "gpio35"; 6430 function = "qup1_se0"; 6431 drive-strength = <6>; 6432 bias-disable; 6433 }; 6434 6435 qup_spi8_data_clk: qup-spi8-data-clk-state { 6436 /* MISO, MOSI, CLK */ 6437 pins = "gpio32", "gpio33", "gpio34"; 6438 function = "qup1_se0"; 6439 drive-strength = <6>; 6440 bias-disable; 6441 }; 6442 6443 qup_spi9_cs: qup-spi9-cs-state { 6444 pins = "gpio39"; 6445 function = "qup1_se1"; 6446 drive-strength = <6>; 6447 bias-disable; 6448 }; 6449 6450 qup_spi9_data_clk: qup-spi9-data-clk-state { 6451 /* MISO, MOSI, CLK */ 6452 pins = "gpio36", "gpio37", "gpio38"; 6453 function = "qup1_se1"; 6454 drive-strength = <6>; 6455 bias-disable; 6456 }; 6457 6458 qup_spi10_cs: qup-spi10-cs-state { 6459 pins = "gpio43"; 6460 function = "qup1_se2"; 6461 drive-strength = <6>; 6462 bias-disable; 6463 }; 6464 6465 qup_spi10_data_clk: qup-spi10-data-clk-state { 6466 /* MISO, MOSI, CLK */ 6467 pins = "gpio40", "gpio41", "gpio42"; 6468 function = "qup1_se2"; 6469 drive-strength = <6>; 6470 bias-disable; 6471 }; 6472 6473 qup_spi11_cs: qup-spi11-cs-state { 6474 pins = "gpio47"; 6475 function = "qup1_se3"; 6476 drive-strength = <6>; 6477 bias-disable; 6478 }; 6479 6480 qup_spi11_data_clk: qup-spi11-data-clk-state { 6481 /* MISO, MOSI, CLK */ 6482 pins = "gpio44", "gpio45", "gpio46"; 6483 function = "qup1_se3"; 6484 drive-strength = <6>; 6485 bias-disable; 6486 }; 6487 6488 qup_spi12_cs: qup-spi12-cs-state { 6489 pins = "gpio51"; 6490 function = "qup1_se4"; 6491 drive-strength = <6>; 6492 bias-disable; 6493 }; 6494 6495 qup_spi12_data_clk: qup-spi12-data-clk-state { 6496 /* MISO, MOSI, CLK */ 6497 pins = "gpio48", "gpio49", "gpio50"; 6498 function = "qup1_se4"; 6499 drive-strength = <6>; 6500 bias-disable; 6501 }; 6502 6503 qup_spi13_cs: qup-spi13-cs-state { 6504 pins = "gpio55"; 6505 function = "qup1_se5"; 6506 drive-strength = <6>; 6507 bias-disable; 6508 }; 6509 6510 qup_spi13_data_clk: qup-spi13-data-clk-state { 6511 /* MISO, MOSI, CLK */ 6512 pins = "gpio52", "gpio53", "gpio54"; 6513 function = "qup1_se5"; 6514 drive-strength = <6>; 6515 bias-disable; 6516 }; 6517 6518 qup_spi14_cs: qup-spi14-cs-state { 6519 pins = "gpio59"; 6520 function = "qup1_se6"; 6521 drive-strength = <6>; 6522 bias-disable; 6523 }; 6524 6525 qup_spi14_data_clk: qup-spi14-data-clk-state { 6526 /* MISO, MOSI, CLK */ 6527 pins = "gpio56", "gpio57", "gpio58"; 6528 function = "qup1_se6"; 6529 drive-strength = <6>; 6530 bias-disable; 6531 }; 6532 6533 qup_spi15_cs: qup-spi15-cs-state { 6534 pins = "gpio53"; 6535 function = "qup1_se7"; 6536 drive-strength = <6>; 6537 bias-disable; 6538 }; 6539 6540 qup_spi15_data_clk: qup-spi15-data-clk-state { 6541 /* MISO, MOSI, CLK */ 6542 pins = "gpio54", "gpio55", "gpio52"; 6543 function = "qup1_se7"; 6544 drive-strength = <6>; 6545 bias-disable; 6546 }; 6547 6548 qup_spi16_cs: qup-spi16-cs-state { 6549 pins = "gpio67"; 6550 function = "qup2_se0"; 6551 drive-strength = <6>; 6552 bias-disable; 6553 }; 6554 6555 qup_spi16_data_clk: qup-spi16-data-clk-state { 6556 /* MISO, MOSI, CLK */ 6557 pins = "gpio64", "gpio65", "gpio66"; 6558 function = "qup2_se0"; 6559 drive-strength = <6>; 6560 bias-disable; 6561 }; 6562 6563 qup_spi17_cs: qup-spi17-cs-state { 6564 pins = "gpio71"; 6565 function = "qup2_se1"; 6566 drive-strength = <6>; 6567 bias-disable; 6568 }; 6569 6570 qup_spi17_data_clk: qup-spi17-data-clk-state { 6571 /* MISO, MOSI, CLK */ 6572 pins = "gpio68", "gpio69", "gpio70"; 6573 function = "qup2_se1"; 6574 drive-strength = <6>; 6575 bias-disable; 6576 }; 6577 6578 qup_spi18_cs: qup-spi18-cs-state { 6579 pins = "gpio75"; 6580 function = "qup2_se2"; 6581 drive-strength = <6>; 6582 bias-disable; 6583 }; 6584 6585 qup_spi18_data_clk: qup-spi18-data-clk-state { 6586 /* MISO, MOSI, CLK */ 6587 pins = "gpio72", "gpio73", "gpio74"; 6588 function = "qup2_se2"; 6589 drive-strength = <6>; 6590 bias-disable; 6591 }; 6592 6593 qup_spi19_cs: qup-spi19-cs-state { 6594 pins = "gpio79"; 6595 function = "qup2_se3"; 6596 drive-strength = <6>; 6597 bias-disable; 6598 }; 6599 6600 qup_spi19_data_clk: qup-spi19-data-clk-state { 6601 /* MISO, MOSI, CLK */ 6602 pins = "gpio76", "gpio77", "gpio78"; 6603 function = "qup2_se3"; 6604 drive-strength = <6>; 6605 bias-disable; 6606 }; 6607 6608 qup_spi20_cs: qup-spi20-cs-state { 6609 pins = "gpio83"; 6610 function = "qup2_se4"; 6611 drive-strength = <6>; 6612 bias-disable; 6613 }; 6614 6615 qup_spi20_data_clk: qup-spi20-data-clk-state { 6616 /* MISO, MOSI, CLK */ 6617 pins = "gpio80", "gpio81", "gpio82"; 6618 function = "qup2_se4"; 6619 drive-strength = <6>; 6620 bias-disable; 6621 }; 6622 6623 qup_spi21_cs: qup-spi21-cs-state { 6624 pins = "gpio87"; 6625 function = "qup2_se5"; 6626 drive-strength = <6>; 6627 bias-disable; 6628 }; 6629 6630 qup_spi21_data_clk: qup-spi21-data-clk-state { 6631 /* MISO, MOSI, CLK */ 6632 pins = "gpio84", "gpio85", "gpio86"; 6633 function = "qup2_se5"; 6634 drive-strength = <6>; 6635 bias-disable; 6636 }; 6637 6638 qup_spi22_cs: qup-spi22-cs-state { 6639 pins = "gpio91"; 6640 function = "qup2_se6"; 6641 drive-strength = <6>; 6642 bias-disable; 6643 }; 6644 6645 qup_spi22_data_clk: qup-spi22-data-clk-state { 6646 /* MISO, MOSI, CLK */ 6647 pins = "gpio88", "gpio89", "gpio90"; 6648 function = "qup2_se6"; 6649 drive-strength = <6>; 6650 bias-disable; 6651 }; 6652 6653 qup_spi23_cs: qup-spi23-cs-state { 6654 pins = "gpio85"; 6655 function = "qup2_se7"; 6656 drive-strength = <6>; 6657 bias-disable; 6658 }; 6659 6660 qup_spi23_data_clk: qup-spi23-data-clk-state { 6661 /* MISO, MOSI, CLK */ 6662 pins = "gpio86", "gpio87", "gpio84"; 6663 function = "qup2_se7"; 6664 drive-strength = <6>; 6665 bias-disable; 6666 }; 6667 6668 qup_uart2_default: qup-uart2-default-state { 6669 cts-pins { 6670 pins = "gpio8"; 6671 function = "qup0_se2"; 6672 drive-strength = <2>; 6673 bias-disable; 6674 }; 6675 6676 rts-pins { 6677 pins = "gpio9"; 6678 function = "qup0_se2"; 6679 drive-strength = <2>; 6680 bias-disable; 6681 }; 6682 6683 tx-pins { 6684 pins = "gpio10"; 6685 function = "qup0_se2"; 6686 drive-strength = <2>; 6687 bias-disable; 6688 }; 6689 6690 rx-pins { 6691 pins = "gpio11"; 6692 function = "qup0_se2"; 6693 drive-strength = <2>; 6694 bias-disable; 6695 }; 6696 }; 6697 6698 qup_uart14_default: qup-uart14-default-state { 6699 cts-pins { 6700 pins = "gpio56"; 6701 function = "qup1_se6"; 6702 bias-bus-hold; 6703 }; 6704 6705 rts-pins { 6706 pins = "gpio57"; 6707 function = "qup1_se6"; 6708 drive-strength = <2>; 6709 bias-disable; 6710 }; 6711 6712 tx-pins { 6713 pins = "gpio58"; 6714 function = "qup1_se6"; 6715 drive-strength = <2>; 6716 bias-disable; 6717 }; 6718 6719 rx-pins { 6720 pins = "gpio59"; 6721 function = "qup1_se6"; 6722 bias-pull-up; 6723 }; 6724 }; 6725 6726 qup_uart21_default: qup-uart21-default-state { 6727 tx-pins { 6728 pins = "gpio86"; 6729 function = "qup2_se5"; 6730 drive-strength = <2>; 6731 bias-disable; 6732 }; 6733 6734 rx-pins { 6735 pins = "gpio87"; 6736 function = "qup2_se5"; 6737 drive-strength = <2>; 6738 bias-disable; 6739 }; 6740 }; 6741 6742 sdc2_default: sdc2-default-state { 6743 clk-pins { 6744 pins = "sdc2_clk"; 6745 drive-strength = <16>; 6746 bias-disable; 6747 }; 6748 6749 cmd-pins { 6750 pins = "sdc2_cmd"; 6751 drive-strength = <10>; 6752 bias-pull-up; 6753 }; 6754 6755 data-pins { 6756 pins = "sdc2_data"; 6757 drive-strength = <10>; 6758 bias-pull-up; 6759 }; 6760 }; 6761 6762 sdc2_sleep: sdc2-sleep-state { 6763 clk-pins { 6764 pins = "sdc2_clk"; 6765 drive-strength = <2>; 6766 bias-disable; 6767 }; 6768 6769 cmd-pins { 6770 pins = "sdc2_cmd"; 6771 drive-strength = <2>; 6772 bias-pull-up; 6773 }; 6774 6775 data-pins { 6776 pins = "sdc2_data"; 6777 drive-strength = <2>; 6778 bias-pull-up; 6779 }; 6780 }; 6781 }; 6782 6783 ctcu@10001000 { 6784 compatible = "qcom,x1e80100-ctcu", "qcom,sa8775p-ctcu"; 6785 reg = <0x0 0x10001000 0x0 0x1000>; 6786 6787 clocks = <&aoss_qmp>; 6788 clock-names = "apb"; 6789 6790 in-ports { 6791 #address-cells = <1>; 6792 #size-cells = <0>; 6793 6794 port@0 { 6795 reg = <0>; 6796 6797 ctcu_in0: endpoint { 6798 remote-endpoint = <&etr0_out>; 6799 }; 6800 }; 6801 6802 port@1 { 6803 reg = <1>; 6804 6805 ctcu_in1: endpoint { 6806 remote-endpoint = <&etr1_out>; 6807 }; 6808 }; 6809 }; 6810 }; 6811 6812 stm@10002000 { 6813 compatible = "arm,coresight-stm", "arm,primecell"; 6814 reg = <0x0 0x10002000 0x0 0x1000>, 6815 <0x0 0x16280000 0x0 0x180000>; 6816 reg-names = "stm-base", 6817 "stm-stimulus-base"; 6818 6819 clocks = <&aoss_qmp>; 6820 clock-names = "apb_pclk"; 6821 6822 out-ports { 6823 port { 6824 stm_out: endpoint { 6825 remote-endpoint = <&funnel0_in7>; 6826 }; 6827 }; 6828 }; 6829 }; 6830 6831 tpdm@10003000 { 6832 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6833 reg = <0x0 0x10003000 0x0 0x1000>; 6834 6835 clocks = <&aoss_qmp>; 6836 clock-names = "apb_pclk"; 6837 label = "tpdm_prng"; 6838 6839 qcom,cmb-element-bits = <32>; 6840 qcom,cmb-msrs-num = <32>; 6841 status = "disabled"; 6842 6843 out-ports { 6844 port { 6845 dcc_tpdm_out: endpoint { 6846 remote-endpoint = <&qdss_tpda_in0>; 6847 }; 6848 }; 6849 }; 6850 }; 6851 6852 tpda@10004000 { 6853 compatible = "qcom,coresight-tpda", "arm,primecell"; 6854 reg = <0x0 0x10004000 0x0 0x1000>; 6855 6856 clocks = <&aoss_qmp>; 6857 clock-names = "apb_pclk"; 6858 6859 in-ports { 6860 #address-cells = <1>; 6861 #size-cells = <0>; 6862 6863 port@0 { 6864 reg = <0>; 6865 6866 qdss_tpda_in0: endpoint { 6867 remote-endpoint = <&dcc_tpdm_out>; 6868 }; 6869 }; 6870 6871 port@1 { 6872 reg = <1>; 6873 6874 qdss_tpda_in1: endpoint { 6875 remote-endpoint = <&qdss_tpdm_out>; 6876 }; 6877 }; 6878 }; 6879 6880 out-ports { 6881 port { 6882 qdss_tpda_out: endpoint { 6883 remote-endpoint = <&funnel0_in6>; 6884 }; 6885 }; 6886 }; 6887 }; 6888 6889 tpdm@1000f000 { 6890 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6891 reg = <0x0 0x1000f000 0x0 0x1000>; 6892 6893 clocks = <&aoss_qmp>; 6894 clock-names = "apb_pclk"; 6895 label = "tpdm_dcc"; 6896 6897 qcom,cmb-element-bits = <32>; 6898 qcom,cmb-msrs-num = <32>; 6899 6900 out-ports { 6901 port { 6902 qdss_tpdm_out: endpoint { 6903 remote-endpoint = <&qdss_tpda_in1>; 6904 }; 6905 }; 6906 }; 6907 }; 6908 6909 funnel@10041000 { 6910 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6911 reg = <0x0 0x10041000 0x0 0x1000>; 6912 6913 clocks = <&aoss_qmp>; 6914 clock-names = "apb_pclk"; 6915 6916 in-ports { 6917 #address-cells = <1>; 6918 #size-cells = <0>; 6919 6920 port@6 { 6921 reg = <6>; 6922 6923 funnel0_in6: endpoint { 6924 remote-endpoint = <&qdss_tpda_out>; 6925 }; 6926 }; 6927 6928 port@7 { 6929 reg = <7>; 6930 6931 funnel0_in7: endpoint { 6932 remote-endpoint = <&stm_out>; 6933 }; 6934 }; 6935 }; 6936 6937 out-ports { 6938 port { 6939 funnel0_out: endpoint { 6940 remote-endpoint = <&qdss_funnel_in0>; 6941 }; 6942 }; 6943 }; 6944 }; 6945 6946 funnel@10042000 { 6947 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6948 reg = <0x0 0x10042000 0x0 0x1000>; 6949 6950 clocks = <&aoss_qmp>; 6951 clock-names = "apb_pclk"; 6952 6953 in-ports { 6954 #address-cells = <1>; 6955 #size-cells = <0>; 6956 6957 port@2 { 6958 reg = <2>; 6959 6960 funnel1_in2: endpoint { 6961 remote-endpoint = <&tmess_funnel_out>; 6962 }; 6963 }; 6964 6965 port@5 { 6966 reg = <5>; 6967 6968 funnel1_in5: endpoint { 6969 remote-endpoint = <&dlst_funnel_out>; 6970 }; 6971 }; 6972 6973 port@6 { 6974 reg = <6>; 6975 6976 funnel1_in6: endpoint { 6977 remote-endpoint = <&dlct1_funnel_out>; 6978 }; 6979 }; 6980 }; 6981 6982 out-ports { 6983 port { 6984 funnel1_out: endpoint { 6985 remote-endpoint = <&qdss_funnel_in1>; 6986 }; 6987 }; 6988 }; 6989 }; 6990 6991 funnel@10045000 { 6992 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6993 reg = <0x0 0x10045000 0x0 0x1000>; 6994 6995 clocks = <&aoss_qmp>; 6996 clock-names = "apb_pclk"; 6997 6998 in-ports { 6999 #address-cells = <1>; 7000 #size-cells = <0>; 7001 7002 port@0 { 7003 reg = <0>; 7004 7005 qdss_funnel_in0: endpoint { 7006 remote-endpoint = <&funnel0_out>; 7007 }; 7008 }; 7009 7010 port@1 { 7011 reg = <1>; 7012 7013 qdss_funnel_in1: endpoint { 7014 remote-endpoint = <&funnel1_out>; 7015 }; 7016 }; 7017 }; 7018 7019 out-ports { 7020 port { 7021 qdss_funnel_out: endpoint { 7022 remote-endpoint = <&aoss_funnel_in7>; 7023 }; 7024 }; 7025 }; 7026 }; 7027 7028 replicator@10046000 { 7029 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 7030 reg = <0x0 0x10046000 0x0 0x1000>; 7031 7032 clocks = <&aoss_qmp>; 7033 clock-names = "apb_pclk"; 7034 7035 in-ports { 7036 port { 7037 qdss_rep_in: endpoint { 7038 remote-endpoint = <&swao_rep_out0>; 7039 }; 7040 }; 7041 }; 7042 7043 out-ports { 7044 port { 7045 qdss_rep_out0: endpoint { 7046 remote-endpoint = <&etr_rep_in>; 7047 }; 7048 }; 7049 }; 7050 }; 7051 7052 tmc_etr: tmc@10048000 { 7053 compatible = "arm,coresight-tmc", "arm,primecell"; 7054 reg = <0x0 0x10048000 0x0 0x1000>; 7055 7056 clocks = <&aoss_qmp>; 7057 clock-names = "apb_pclk"; 7058 iommus = <&apps_smmu 0x04e0 0x0>; 7059 7060 arm,scatter-gather; 7061 7062 in-ports { 7063 port { 7064 etr0_in: endpoint { 7065 remote-endpoint = <&etr_rep_out0>; 7066 }; 7067 }; 7068 }; 7069 7070 out-ports { 7071 port { 7072 etr0_out: endpoint { 7073 remote-endpoint = <&ctcu_in0>; 7074 }; 7075 }; 7076 }; 7077 }; 7078 7079 replicator@1004e000 { 7080 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 7081 reg = <0x0 0x1004e000 0x0 0x1000>; 7082 7083 clocks = <&aoss_qmp>; 7084 clock-names = "apb_pclk"; 7085 7086 in-ports { 7087 port { 7088 etr_rep_in: endpoint { 7089 remote-endpoint = <&qdss_rep_out0>; 7090 }; 7091 }; 7092 }; 7093 7094 out-ports { 7095 #address-cells = <1>; 7096 #size-cells = <0>; 7097 7098 port@0 { 7099 reg = <0>; 7100 7101 etr_rep_out0: endpoint { 7102 remote-endpoint = <&etr0_in>; 7103 }; 7104 }; 7105 7106 port@1 { 7107 reg = <1>; 7108 7109 etr_rep_out1: endpoint { 7110 remote-endpoint = <&etr1_in>; 7111 }; 7112 }; 7113 }; 7114 }; 7115 7116 tmc_etr1: tmc@1004f000 { 7117 compatible = "arm,coresight-tmc", "arm,primecell"; 7118 reg = <0x0 0x1004f000 0x0 0x1000>; 7119 7120 clocks = <&aoss_qmp>; 7121 clock-names = "apb_pclk"; 7122 iommus = <&apps_smmu 0x0500 0x0>; 7123 7124 arm,scatter-gather; 7125 arm,buffer-size = <0x400000>; 7126 7127 in-ports { 7128 port { 7129 etr1_in: endpoint { 7130 remote-endpoint = <&etr_rep_out1>; 7131 }; 7132 }; 7133 }; 7134 7135 out-ports { 7136 port { 7137 etr1_out: endpoint { 7138 remote-endpoint = <&ctcu_in1>; 7139 }; 7140 }; 7141 }; 7142 }; 7143 7144 tpdm@10800000 { 7145 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7146 reg = <0x0 0x10800000 0x0 0x1000>; 7147 7148 clocks = <&aoss_qmp>; 7149 clock-names = "apb_pclk"; 7150 label = "tpdm_tmess_0"; 7151 7152 qcom,cmb-element-bits = <64>; 7153 qcom,cmb-msrs-num = <32>; 7154 7155 out-ports { 7156 port { 7157 mxa_tpdm_out: endpoint { 7158 remote-endpoint = <&dlct2_tpda_in15>; 7159 }; 7160 }; 7161 }; 7162 }; 7163 7164 tpdm@1082c000 { 7165 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7166 reg = <0x0 0x1082c000 0x0 0x1000>; 7167 7168 clocks = <&aoss_qmp>; 7169 clock-names = "apb_pclk"; 7170 label = "tpdm_dl_south_0"; 7171 7172 qcom,dsb-element-bits = <32>; 7173 qcom,dsb-msrs-num = <32>; 7174 7175 out-ports { 7176 port { 7177 gcc_tpdm_out: endpoint { 7178 remote-endpoint = <&dlct1_tpda_in21>; 7179 }; 7180 }; 7181 }; 7182 }; 7183 7184 tpdm@10841000 { 7185 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7186 reg = <0x0 0x10841000 0x0 0x1000>; 7187 7188 clocks = <&aoss_qmp>; 7189 clock-names = "apb_pclk"; 7190 label = "tpdm_spdm"; 7191 7192 qcom,cmb-element-bits = <32>; 7193 qcom,cmb-msrs-num = <32>; 7194 7195 out-ports { 7196 port { 7197 prng_tpdm_out: endpoint { 7198 remote-endpoint = <&dlct1_tpda_in19>; 7199 }; 7200 }; 7201 }; 7202 }; 7203 7204 tpdm@10844000 { 7205 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7206 reg = <0x0 0x10844000 0x0 0x1000>; 7207 7208 clocks = <&aoss_qmp>; 7209 clock-names = "apb_pclk"; 7210 label = "tpdm_qm"; 7211 7212 qcom,dsb-element-bits = <32>; 7213 qcom,dsb-msrs-num = <32>; 7214 7215 out-ports { 7216 port { 7217 lpass_cx_tpdm_out: endpoint { 7218 remote-endpoint = <&lpass_cx_funnel_in0>; 7219 }; 7220 }; 7221 }; 7222 }; 7223 7224 funnel@10846000 { 7225 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7226 reg = <0x0 0x10846000 0x0 0x1000>; 7227 7228 clocks = <&aoss_qmp>; 7229 clock-names = "apb_pclk"; 7230 7231 in-ports { 7232 port { 7233 lpass_cx_funnel_in0: endpoint { 7234 remote-endpoint = <&lpass_cx_tpdm_out>; 7235 }; 7236 }; 7237 }; 7238 7239 out-ports { 7240 port { 7241 lpass_cx_funnel_out: endpoint { 7242 remote-endpoint = <&dlct1_tpda_in4>; 7243 }; 7244 }; 7245 }; 7246 }; 7247 7248 cti@1098b000 { 7249 compatible = "arm,coresight-cti", "arm,primecell"; 7250 reg = <0x0 0x1098b000 0x0 0x1000>; 7251 7252 clocks = <&aoss_qmp>; 7253 clock-names = "apb_pclk"; 7254 label = "cti_cdsp_cscti"; 7255 }; 7256 7257 tpdm@109d0000 { 7258 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7259 reg = <0x0 0x109d0000 0x0 0x1000>; 7260 7261 clocks = <&aoss_qmp>; 7262 clock-names = "apb_pclk"; 7263 label = "tpdm_lpass"; 7264 7265 qcom,dsb-element-bits = <32>; 7266 qcom,dsb-msrs-num = <32>; 7267 status = "disabled"; 7268 7269 out-ports { 7270 port { 7271 qm_tpdm_out: endpoint { 7272 remote-endpoint = <&dlct1_tpda_in20>; 7273 }; 7274 }; 7275 }; 7276 }; 7277 7278 tpdm@10ac0000 { 7279 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7280 reg = <0x0 0x10ac0000 0x0 0x1000>; 7281 7282 clocks = <&aoss_qmp>; 7283 clock-names = "apb_pclk"; 7284 label = "tpdm_gcc"; 7285 7286 qcom,dsb-element-bits = <32>; 7287 qcom,dsb-msrs-num = <32>; 7288 status = "disabled"; 7289 7290 out-ports { 7291 port { 7292 dlst_tpdm0_out: endpoint { 7293 remote-endpoint = <&dlst_tpda_in8>; 7294 }; 7295 }; 7296 }; 7297 }; 7298 7299 tpdm@10ac1000 { 7300 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7301 reg = <0x0 0x10ac1000 0x0 0x1000>; 7302 7303 clocks = <&aoss_qmp>; 7304 clock-names = "apb_pclk"; 7305 label = "tpdm_rpdm_mxa"; 7306 7307 qcom,cmb-element-bits = <64>; 7308 qcom,cmb-msrs-num = <32>; 7309 7310 out-ports { 7311 port { 7312 dlst_tpdm1_out: endpoint { 7313 remote-endpoint = <&dlst_tpda_in9>; 7314 }; 7315 }; 7316 }; 7317 }; 7318 7319 tpda@10ac4000 { 7320 compatible = "qcom,coresight-tpda", "arm,primecell"; 7321 reg = <0x0 0x10ac4000 0x0 0x1000>; 7322 7323 clocks = <&aoss_qmp>; 7324 clock-names = "apb_pclk"; 7325 7326 in-ports { 7327 #address-cells = <1>; 7328 #size-cells = <0>; 7329 7330 port@8 { 7331 reg = <8>; 7332 7333 dlst_tpda_in8: endpoint { 7334 remote-endpoint = <&dlst_tpdm0_out>; 7335 }; 7336 }; 7337 7338 port@9 { 7339 reg = <9>; 7340 7341 dlst_tpda_in9: endpoint { 7342 remote-endpoint = <&dlst_tpdm1_out>; 7343 }; 7344 }; 7345 }; 7346 7347 out-ports { 7348 port { 7349 dlst_tpda_out: endpoint { 7350 remote-endpoint = <&dlst_funnel_in0>; 7351 }; 7352 }; 7353 }; 7354 }; 7355 7356 funnel@10ac5000 { 7357 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7358 reg = <0x0 0x10ac5000 0x0 0x1000>; 7359 7360 clocks = <&aoss_qmp>; 7361 clock-names = "apb_pclk"; 7362 7363 in-ports { 7364 port { 7365 dlst_funnel_in0: endpoint { 7366 remote-endpoint = <&dlst_tpda_out>; 7367 }; 7368 }; 7369 }; 7370 7371 out-ports { 7372 port { 7373 dlst_funnel_out: endpoint { 7374 remote-endpoint = <&funnel1_in5>; 7375 }; 7376 }; 7377 }; 7378 }; 7379 7380 funnel@10b04000 { 7381 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7382 reg = <0x0 0x10b04000 0x0 0x1000>; 7383 7384 clocks = <&aoss_qmp>; 7385 clock-names = "apb_pclk"; 7386 7387 in-ports { 7388 #address-cells = <1>; 7389 #size-cells = <0>; 7390 7391 port@3 { 7392 reg = <3>; 7393 7394 aoss_funnel_in3: endpoint { 7395 remote-endpoint = <&ddr_lpi_funnel_out>; 7396 }; 7397 }; 7398 7399 port@6 { 7400 reg = <6>; 7401 7402 aoss_funnel_in6: endpoint { 7403 remote-endpoint = <&aoss_tpda_out>; 7404 }; 7405 }; 7406 7407 port@7 { 7408 reg = <7>; 7409 7410 aoss_funnel_in7: endpoint { 7411 remote-endpoint = <&qdss_funnel_out>; 7412 }; 7413 }; 7414 }; 7415 7416 out-ports { 7417 port { 7418 aoss_funnel_out: endpoint { 7419 remote-endpoint = <&etf0_in>; 7420 }; 7421 }; 7422 }; 7423 }; 7424 7425 etf0: tmc@10b05000 { 7426 compatible = "arm,coresight-tmc", "arm,primecell"; 7427 reg = <0x0 0x10b05000 0x0 0x1000>; 7428 7429 clocks = <&aoss_qmp>; 7430 clock-names = "apb_pclk"; 7431 7432 in-ports { 7433 port { 7434 etf0_in: endpoint { 7435 remote-endpoint = <&aoss_funnel_out>; 7436 }; 7437 }; 7438 }; 7439 7440 out-ports { 7441 port { 7442 etf0_out: endpoint { 7443 remote-endpoint = <&swao_rep_in>; 7444 }; 7445 }; 7446 }; 7447 }; 7448 7449 replicator@10b06000 { 7450 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 7451 reg = <0x0 0x10b06000 0x0 0x1000>; 7452 7453 clocks = <&aoss_qmp>; 7454 clock-names = "apb_pclk"; 7455 7456 in-ports { 7457 port { 7458 swao_rep_in: endpoint { 7459 remote-endpoint = <&etf0_out>; 7460 }; 7461 }; 7462 }; 7463 7464 out-ports { 7465 #address-cells = <1>; 7466 #size-cells = <0>; 7467 7468 port@0 { 7469 reg = <0>; 7470 7471 swao_rep_out0: endpoint { 7472 remote-endpoint = <&qdss_rep_in>; 7473 }; 7474 }; 7475 7476 port@1 { 7477 reg = <1>; 7478 7479 swao_rep_out1: endpoint { 7480 remote-endpoint = <&eud_in>; 7481 }; 7482 }; 7483 }; 7484 }; 7485 7486 tpda@10b08000 { 7487 compatible = "qcom,coresight-tpda", "arm,primecell"; 7488 reg = <0x0 0x10b08000 0x0 0x1000>; 7489 7490 clocks = <&aoss_qmp>; 7491 clock-names = "apb_pclk"; 7492 7493 in-ports { 7494 #address-cells = <1>; 7495 #size-cells = <0>; 7496 7497 port@0 { 7498 reg = <0>; 7499 7500 aoss_tpda_in0: endpoint { 7501 remote-endpoint = <&aoss_tpdm0_out>; 7502 }; 7503 }; 7504 7505 port@1 { 7506 reg = <1>; 7507 7508 aoss_tpda_in1: endpoint { 7509 remote-endpoint = <&aoss_tpdm1_out>; 7510 }; 7511 }; 7512 7513 port@2 { 7514 reg = <2>; 7515 7516 aoss_tpda_in2: endpoint { 7517 remote-endpoint = <&aoss_tpdm2_out>; 7518 }; 7519 }; 7520 7521 port@3 { 7522 reg = <3>; 7523 7524 aoss_tpda_in3: endpoint { 7525 remote-endpoint = <&aoss_tpdm3_out>; 7526 }; 7527 }; 7528 7529 port@4 { 7530 reg = <4>; 7531 7532 aoss_tpda_in4: endpoint { 7533 remote-endpoint = <&aoss_tpdm4_out>; 7534 }; 7535 }; 7536 }; 7537 7538 out-ports { 7539 port { 7540 aoss_tpda_out: endpoint { 7541 remote-endpoint = <&aoss_funnel_in6>; 7542 }; 7543 }; 7544 }; 7545 }; 7546 7547 tpdm@10b09000 { 7548 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7549 reg = <0x0 0x10b09000 0x0 0x1000>; 7550 7551 clocks = <&aoss_qmp>; 7552 clock-names = "apb_pclk"; 7553 label = "tpdm_dl_south_1"; 7554 7555 qcom,cmb-element-bits = <64>; 7556 qcom,cmb-msrs-num = <32>; 7557 7558 out-ports { 7559 port { 7560 aoss_tpdm0_out: endpoint { 7561 remote-endpoint = <&aoss_tpda_in0>; 7562 }; 7563 }; 7564 }; 7565 }; 7566 7567 tpdm@10b0a000 { 7568 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7569 reg = <0x0 0x10b0a000 0x0 0x1000>; 7570 7571 clocks = <&aoss_qmp>; 7572 clock-names = "apb_pclk"; 7573 label = "tpdm_swao_prio_3"; 7574 7575 qcom,cmb-element-bits = <64>; 7576 qcom,cmb-msrs-num = <32>; 7577 7578 out-ports { 7579 port { 7580 aoss_tpdm1_out: endpoint { 7581 remote-endpoint = <&aoss_tpda_in1>; 7582 }; 7583 }; 7584 }; 7585 }; 7586 7587 tpdm@10b0b000 { 7588 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7589 reg = <0x0 0x10b0b000 0x0 0x1000>; 7590 7591 clocks = <&aoss_qmp>; 7592 clock-names = "apb_pclk"; 7593 label = "tpdm_swao_prio_1"; 7594 7595 qcom,cmb-element-bits = <64>; 7596 qcom,cmb-msrs-num = <32>; 7597 7598 out-ports { 7599 port { 7600 aoss_tpdm2_out: endpoint { 7601 remote-endpoint = <&aoss_tpda_in2>; 7602 }; 7603 }; 7604 }; 7605 }; 7606 7607 tpdm@10b0c000 { 7608 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7609 reg = <0x0 0x10b0c000 0x0 0x1000>; 7610 7611 clocks = <&aoss_qmp>; 7612 clock-names = "apb_pclk"; 7613 label = "tpdm_swao_prio_0"; 7614 7615 qcom,cmb-element-bits = <64>; 7616 qcom,cmb-msrs-num = <32>; 7617 7618 out-ports { 7619 port { 7620 aoss_tpdm3_out: endpoint { 7621 remote-endpoint = <&aoss_tpda_in3>; 7622 }; 7623 }; 7624 }; 7625 }; 7626 7627 tpdm@10b0d000 { 7628 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7629 reg = <0x0 0x10b0d000 0x0 0x1000>; 7630 7631 clocks = <&aoss_qmp>; 7632 clock-names = "apb_pclk"; 7633 label = "tpdm_dlct"; 7634 7635 qcom,dsb-element-bits = <32>; 7636 qcom,dsb-msrs-num = <32>; 7637 7638 out-ports { 7639 port { 7640 aoss_tpdm4_out: endpoint { 7641 remote-endpoint = <&aoss_tpda_in4>; 7642 }; 7643 }; 7644 }; 7645 }; 7646 7647 tpdm@10b20000 { 7648 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7649 reg = <0x0 0x10b20000 0x0 0x1000>; 7650 7651 clocks = <&aoss_qmp>; 7652 clock-names = "apb_pclk"; 7653 label = "tpdm_dlmm"; 7654 7655 qcom,dsb-element-bits = <32>; 7656 qcom,dsb-msrs-num = <32>; 7657 status = "disabled"; 7658 7659 out-ports { 7660 port { 7661 lpicc_tpdm_out: endpoint { 7662 remote-endpoint = <&ddr_lpi_tpda_in>; 7663 }; 7664 }; 7665 }; 7666 }; 7667 7668 tpda@10b23000 { 7669 compatible = "qcom,coresight-tpda", "arm,primecell"; 7670 reg = <0x0 0x10b23000 0x0 0x1000>; 7671 7672 clocks = <&aoss_qmp>; 7673 clock-names = "apb_pclk"; 7674 status = "disabled"; 7675 7676 in-ports { 7677 port { 7678 ddr_lpi_tpda_in: endpoint { 7679 remote-endpoint = <&lpicc_tpdm_out>; 7680 }; 7681 }; 7682 }; 7683 7684 out-ports { 7685 port { 7686 ddr_lpi_tpda_out: endpoint { 7687 remote-endpoint = <&ddr_lpi_funnel_in0>; 7688 }; 7689 }; 7690 }; 7691 }; 7692 7693 funnel@10b24000 { 7694 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7695 reg = <0x0 0x10b24000 0x0 0x1000>; 7696 7697 clocks = <&aoss_qmp>; 7698 clock-names = "apb_pclk"; 7699 status = "disabled"; 7700 7701 in-ports { 7702 port { 7703 ddr_lpi_funnel_in0: endpoint { 7704 remote-endpoint = <&ddr_lpi_tpda_out>; 7705 }; 7706 }; 7707 }; 7708 7709 out-ports { 7710 port { 7711 ddr_lpi_funnel_out: endpoint { 7712 remote-endpoint = <&aoss_funnel_in3>; 7713 }; 7714 }; 7715 }; 7716 }; 7717 7718 tpdm@10c08000 { 7719 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7720 reg = <0x0 0x10c08000 0x0 0x1000>; 7721 7722 clocks = <&aoss_qmp>; 7723 clock-names = "apb_pclk"; 7724 label = "tpdm_swao_1"; 7725 7726 qcom,dsb-element-bits = <32>; 7727 qcom,dsb-msrs-num = <32>; 7728 7729 out-ports { 7730 port { 7731 mm_tpdm_out: endpoint { 7732 remote-endpoint = <&mm_funnel_in4>; 7733 }; 7734 }; 7735 }; 7736 }; 7737 7738 funnel@10c0b000 { 7739 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7740 reg = <0x0 0x10c0b000 0x0 0x1000>; 7741 7742 clocks = <&aoss_qmp>; 7743 clock-names = "apb_pclk"; 7744 7745 in-ports { 7746 #address-cells = <1>; 7747 #size-cells = <0>; 7748 7749 port@4 { 7750 reg = <4>; 7751 7752 mm_funnel_in4: endpoint { 7753 remote-endpoint = <&mm_tpdm_out>; 7754 }; 7755 }; 7756 }; 7757 7758 out-ports { 7759 port { 7760 mm_funnel_out: endpoint { 7761 remote-endpoint = <&dlct2_tpda_in4>; 7762 }; 7763 }; 7764 }; 7765 }; 7766 7767 tpdm@10c28000 { 7768 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7769 reg = <0x0 0x10c28000 0x0 0x1000>; 7770 7771 clocks = <&aoss_qmp>; 7772 clock-names = "apb_pclk"; 7773 label = "tpdm_ddr_lpi"; 7774 7775 qcom,dsb-element-bits = <32>; 7776 qcom,dsb-msrs-num = <32>; 7777 7778 out-ports { 7779 port { 7780 dlct1_tpdm_out: endpoint { 7781 remote-endpoint = <&dlct1_tpda_in26>; 7782 }; 7783 }; 7784 }; 7785 }; 7786 7787 tpdm@10c29000 { 7788 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7789 reg = <0x0 0x10c29000 0x0 0x1000>; 7790 7791 clocks = <&aoss_qmp>; 7792 clock-names = "apb_pclk"; 7793 label = "tpdm_swao_prio_2"; 7794 7795 qcom,cmb-element-bits = <64>; 7796 qcom,cmb-msrs-num = <32>; 7797 7798 out-ports { 7799 port { 7800 ipcc_tpdm_out: endpoint { 7801 remote-endpoint = <&dlct1_tpda_in27>; 7802 }; 7803 }; 7804 }; 7805 }; 7806 7807 tpda@10c2b000 { 7808 compatible = "qcom,coresight-tpda", "arm,primecell"; 7809 reg = <0x0 0x10c2b000 0x0 0x1000>; 7810 7811 clocks = <&aoss_qmp>; 7812 clock-names = "apb_pclk"; 7813 7814 in-ports { 7815 #address-cells = <1>; 7816 #size-cells = <0>; 7817 7818 port@4 { 7819 reg = <4>; 7820 7821 dlct1_tpda_in4: endpoint { 7822 remote-endpoint = <&lpass_cx_funnel_out>; 7823 }; 7824 }; 7825 7826 port@13 { 7827 reg = <19>; 7828 7829 dlct1_tpda_in19: endpoint { 7830 remote-endpoint = <&prng_tpdm_out>; 7831 }; 7832 }; 7833 7834 port@14 { 7835 reg = <20>; 7836 7837 dlct1_tpda_in20: endpoint { 7838 remote-endpoint = <&qm_tpdm_out>; 7839 }; 7840 }; 7841 7842 port@15 { 7843 reg = <21>; 7844 7845 dlct1_tpda_in21: endpoint { 7846 remote-endpoint = <&gcc_tpdm_out>; 7847 }; 7848 }; 7849 7850 port@1a { 7851 reg = <26>; 7852 7853 dlct1_tpda_in26: endpoint { 7854 remote-endpoint = <&dlct1_tpdm_out>; 7855 }; 7856 }; 7857 7858 port@1b { 7859 reg = <27>; 7860 7861 dlct1_tpda_in27: endpoint { 7862 remote-endpoint = <&ipcc_tpdm_out>; 7863 }; 7864 }; 7865 }; 7866 7867 out-ports { 7868 port { 7869 dlct1_tpda_out: endpoint { 7870 remote-endpoint = <&dlct1_funnel_in0>; 7871 }; 7872 }; 7873 }; 7874 }; 7875 7876 funnel@10c2c000 { 7877 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7878 reg = <0x0 0x10c2c000 0x0 0x1000>; 7879 7880 clocks = <&aoss_qmp>; 7881 clock-names = "apb_pclk"; 7882 7883 in-ports { 7884 #address-cells = <1>; 7885 #size-cells = <0>; 7886 7887 port@0 { 7888 reg = <0>; 7889 7890 dlct1_funnel_in0: endpoint { 7891 remote-endpoint = <&dlct1_tpda_out>; 7892 }; 7893 }; 7894 7895 port@4 { 7896 reg = <4>; 7897 7898 dlct1_funnel_in4: endpoint { 7899 remote-endpoint = <&dlct2_funnel_out>; 7900 }; 7901 }; 7902 7903 port@5 { 7904 reg = <5>; 7905 7906 dlct1_funnel_in5: endpoint { 7907 remote-endpoint = <&ddr_funnel0_out>; 7908 }; 7909 }; 7910 }; 7911 7912 out-ports { 7913 port { 7914 dlct1_funnel_out: endpoint { 7915 remote-endpoint = <&funnel1_in6>; 7916 }; 7917 }; 7918 }; 7919 }; 7920 7921 tpdm@10c38000 { 7922 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7923 reg = <0x0 0x10c38000 0x0 0x1000>; 7924 7925 clocks = <&aoss_qmp>; 7926 clock-names = "apb_pclk"; 7927 label = "tpdm_ipcc"; 7928 7929 qcom,cmb-element-bits = <64>; 7930 qcom,cmb-msrs-num = <32>; 7931 7932 out-ports { 7933 port { 7934 dlct2_tpdm0_out: endpoint { 7935 remote-endpoint = <&dlct2_tpda_in16>; 7936 }; 7937 }; 7938 }; 7939 }; 7940 7941 tpdm@10c39000 { 7942 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7943 reg = <0x0 0x10c39000 0x0 0x1000>; 7944 7945 clocks = <&aoss_qmp>; 7946 clock-names = "apb_pclk"; 7947 label = "tpdm_rdpm_mx"; 7948 7949 qcom,cmb-element-bits = <64>; 7950 qcom,cmb-msrs-num = <32>; 7951 7952 out-ports { 7953 port { 7954 dlct2_tpdm1_out: endpoint { 7955 remote-endpoint = <&dlct2_tpda_in17>; 7956 }; 7957 }; 7958 }; 7959 }; 7960 7961 tpda@10c3c000 { 7962 compatible = "qcom,coresight-tpda", "arm,primecell"; 7963 reg = <0x0 0x10c3c000 0x0 0x1000>; 7964 7965 clocks = <&aoss_qmp>; 7966 clock-names = "apb_pclk"; 7967 7968 in-ports { 7969 #address-cells = <1>; 7970 #size-cells = <0>; 7971 7972 port@4 { 7973 reg = <4>; 7974 7975 dlct2_tpda_in4: endpoint { 7976 remote-endpoint = <&mm_funnel_out>; 7977 }; 7978 }; 7979 7980 port@f { 7981 reg = <15>; 7982 7983 dlct2_tpda_in15: endpoint { 7984 remote-endpoint = <&mxa_tpdm_out>; 7985 }; 7986 }; 7987 7988 port@10 { 7989 reg = <16>; 7990 7991 dlct2_tpda_in16: endpoint { 7992 remote-endpoint = <&dlct2_tpdm0_out>; 7993 }; 7994 }; 7995 7996 port@11 { 7997 reg = <17>; 7998 7999 dlct2_tpda_in17: endpoint { 8000 remote-endpoint = <&dlct2_tpdm1_out>; 8001 }; 8002 }; 8003 }; 8004 8005 out-ports { 8006 port { 8007 dlct2_tpda_out: endpoint { 8008 remote-endpoint = <&dlct2_funnel_in0>; 8009 }; 8010 }; 8011 }; 8012 }; 8013 8014 funnel@10c3d000 { 8015 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 8016 reg = <0x0 0x10c3d000 0x0 0x1000>; 8017 8018 clocks = <&aoss_qmp>; 8019 clock-names = "apb_pclk"; 8020 8021 in-ports { 8022 port { 8023 dlct2_funnel_in0: endpoint { 8024 remote-endpoint = <&dlct2_tpda_out>; 8025 }; 8026 }; 8027 }; 8028 8029 out-ports { 8030 port { 8031 dlct2_funnel_out: endpoint { 8032 remote-endpoint = <&dlct1_funnel_in4>; 8033 }; 8034 }; 8035 }; 8036 }; 8037 8038 tpdm@10cc1000 { 8039 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8040 reg = <0x0 0x10cc1000 0x0 0x1000>; 8041 8042 clocks = <&aoss_qmp>; 8043 clock-names = "apb_pclk"; 8044 label = "tpdm_rdpm"; 8045 8046 qcom,cmb-element-bits = <64>; 8047 qcom,cmb-msrs-num = <32>; 8048 qcom,dsb-element-bits = <32>; 8049 qcom,dsb-msrs-num = <32>; 8050 status = "disabled"; 8051 8052 out-ports { 8053 port { 8054 tmess_tpdm1_out: endpoint { 8055 remote-endpoint = <&tmess_tpda_in2>; 8056 }; 8057 }; 8058 }; 8059 }; 8060 8061 tpda@10cc4000 { 8062 compatible = "qcom,coresight-tpda", "arm,primecell"; 8063 reg = <0x0 0x10cc4000 0x0 0x1000>; 8064 8065 clocks = <&aoss_qmp>; 8066 clock-names = "apb_pclk"; 8067 8068 in-ports { 8069 #address-cells = <1>; 8070 #size-cells = <0>; 8071 8072 port@2 { 8073 reg = <2>; 8074 8075 tmess_tpda_in2: endpoint { 8076 remote-endpoint = <&tmess_tpdm1_out>; 8077 }; 8078 }; 8079 }; 8080 8081 out-ports { 8082 port { 8083 tmess_tpda_out: endpoint { 8084 remote-endpoint = <&tmess_funnel_in0>; 8085 }; 8086 }; 8087 }; 8088 }; 8089 8090 funnel@10cc5000 { 8091 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 8092 reg = <0x0 0x10cc5000 0x0 0x1000>; 8093 8094 clocks = <&aoss_qmp>; 8095 clock-names = "apb_pclk"; 8096 8097 in-ports { 8098 port { 8099 tmess_funnel_in0: endpoint { 8100 remote-endpoint = <&tmess_tpda_out>; 8101 }; 8102 }; 8103 }; 8104 8105 out-ports { 8106 port { 8107 tmess_funnel_out: endpoint { 8108 remote-endpoint = <&funnel1_in2>; 8109 }; 8110 }; 8111 }; 8112 }; 8113 8114 funnel@10d04000 { 8115 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 8116 reg = <0x0 0x10d04000 0x0 0x1000>; 8117 8118 clocks = <&aoss_qmp>; 8119 clock-names = "apb_pclk"; 8120 8121 in-ports { 8122 #address-cells = <1>; 8123 #size-cells = <0>; 8124 8125 port@6 { 8126 reg = <6>; 8127 8128 ddr_funnel0_in6: endpoint { 8129 remote-endpoint = <&ddr_funnel1_out>; 8130 }; 8131 }; 8132 }; 8133 8134 out-ports { 8135 port { 8136 ddr_funnel0_out: endpoint { 8137 remote-endpoint = <&dlct1_funnel_in5>; 8138 }; 8139 }; 8140 }; 8141 }; 8142 8143 tpdm@10d08000 { 8144 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8145 reg = <0x0 0x10d08000 0x0 0x1000>; 8146 8147 clocks = <&aoss_qmp>; 8148 clock-names = "apb_pclk"; 8149 label = "tpdm_llcc_7"; 8150 8151 qcom,cmb-element-bits = <32>; 8152 qcom,cmb-msrs-num = <32>; 8153 8154 out-ports { 8155 port { 8156 llcc0_tpdm_out: endpoint { 8157 remote-endpoint = <&llcc_tpda_in0>; 8158 }; 8159 }; 8160 }; 8161 }; 8162 8163 tpdm@10d09000 { 8164 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8165 reg = <0x0 0x10d09000 0x0 0x1000>; 8166 8167 clocks = <&aoss_qmp>; 8168 clock-names = "apb_pclk"; 8169 label = "tpdm_llcc_6"; 8170 8171 qcom,cmb-element-bits = <32>; 8172 qcom,cmb-msrs-num = <32>; 8173 8174 out-ports { 8175 port { 8176 llcc1_tpdm_out: endpoint { 8177 remote-endpoint = <&llcc_tpda_in1>; 8178 }; 8179 }; 8180 }; 8181 }; 8182 8183 tpdm@10d0a000 { 8184 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8185 reg = <0x0 0x10d0a000 0x0 0x1000>; 8186 8187 clocks = <&aoss_qmp>; 8188 clock-names = "apb_pclk"; 8189 label = "tpdm_llcc_5"; 8190 8191 qcom,cmb-element-bits = <32>; 8192 qcom,cmb-msrs-num = <32>; 8193 8194 out-ports { 8195 port { 8196 llcc2_tpdm_out: endpoint { 8197 remote-endpoint = <&llcc_tpda_in2>; 8198 }; 8199 }; 8200 }; 8201 }; 8202 8203 tpdm@10d0b000 { 8204 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8205 reg = <0x0 0x10d0b000 0x0 0x1000>; 8206 8207 clocks = <&aoss_qmp>; 8208 clock-names = "apb_pclk"; 8209 label = "tpdm_llcc_4"; 8210 8211 qcom,cmb-element-bits = <32>; 8212 qcom,cmb-msrs-num = <32>; 8213 8214 out-ports { 8215 port { 8216 llcc3_tpdm_out: endpoint { 8217 remote-endpoint = <&llcc_tpda_in3>; 8218 }; 8219 }; 8220 }; 8221 }; 8222 8223 tpdm@10d0c000 { 8224 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8225 reg = <0x0 0x10d0c000 0x0 0x1000>; 8226 8227 clocks = <&aoss_qmp>; 8228 clock-names = "apb_pclk"; 8229 label = "tpdm_llcc_3"; 8230 8231 qcom,cmb-element-bits = <32>; 8232 qcom,cmb-msrs-num = <32>; 8233 8234 out-ports { 8235 port { 8236 llcc4_tpdm_out: endpoint { 8237 remote-endpoint = <&llcc_tpda_in4>; 8238 }; 8239 }; 8240 }; 8241 }; 8242 8243 tpdm@10d0d000 { 8244 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8245 reg = <0x0 0x10d0d000 0x0 0x1000>; 8246 8247 clocks = <&aoss_qmp>; 8248 clock-names = "apb_pclk"; 8249 label = "tpdm_llcc_0"; 8250 8251 qcom,cmb-element-bits = <32>; 8252 qcom,cmb-msrs-num = <32>; 8253 8254 out-ports { 8255 port { 8256 llcc5_tpdm_out: endpoint { 8257 remote-endpoint = <&llcc_tpda_in5>; 8258 }; 8259 }; 8260 }; 8261 }; 8262 8263 tpdm@10d0e000 { 8264 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8265 reg = <0x0 0x10d0e000 0x0 0x1000>; 8266 8267 clocks = <&aoss_qmp>; 8268 clock-names = "apb_pclk"; 8269 label = "tpdm_llcc_1"; 8270 8271 qcom,cmb-element-bits = <32>; 8272 qcom,cmb-msrs-num = <32>; 8273 8274 out-ports { 8275 port { 8276 llcc6_tpdm_out: endpoint { 8277 remote-endpoint = <&llcc_tpda_in6>; 8278 }; 8279 }; 8280 }; 8281 }; 8282 8283 tpdm@10d0f000 { 8284 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8285 reg = <0x0 0x10d0f000 0x0 0x1000>; 8286 8287 clocks = <&aoss_qmp>; 8288 clock-names = "apb_pclk"; 8289 label = "tpdm_llcc_2"; 8290 8291 qcom,cmb-element-bits = <32>; 8292 qcom,cmb-msrs-num = <32>; 8293 8294 out-ports { 8295 port { 8296 llcc7_tpdm_out: endpoint { 8297 remote-endpoint = <&llcc_tpda_in7>; 8298 }; 8299 }; 8300 }; 8301 }; 8302 8303 tpda@10d12000 { 8304 compatible = "qcom,coresight-tpda", "arm,primecell"; 8305 reg = <0x0 0x10d12000 0x0 0x1000>; 8306 8307 clocks = <&aoss_qmp>; 8308 clock-names = "apb_pclk"; 8309 8310 in-ports { 8311 #address-cells = <1>; 8312 #size-cells = <0>; 8313 8314 port@0 { 8315 reg = <0>; 8316 8317 llcc_tpda_in0: endpoint { 8318 remote-endpoint = <&llcc0_tpdm_out>; 8319 }; 8320 }; 8321 8322 port@1 { 8323 reg = <1>; 8324 8325 llcc_tpda_in1: endpoint { 8326 remote-endpoint = <&llcc1_tpdm_out>; 8327 }; 8328 }; 8329 8330 port@2 { 8331 reg = <2>; 8332 8333 llcc_tpda_in2: endpoint { 8334 remote-endpoint = <&llcc2_tpdm_out>; 8335 }; 8336 }; 8337 8338 port@3 { 8339 reg = <3>; 8340 8341 llcc_tpda_in3: endpoint { 8342 remote-endpoint = <&llcc3_tpdm_out>; 8343 }; 8344 }; 8345 8346 port@4 { 8347 reg = <4>; 8348 8349 llcc_tpda_in4: endpoint { 8350 remote-endpoint = <&llcc4_tpdm_out>; 8351 }; 8352 }; 8353 8354 port@5 { 8355 reg = <5>; 8356 8357 llcc_tpda_in5: endpoint { 8358 remote-endpoint = <&llcc5_tpdm_out>; 8359 }; 8360 }; 8361 8362 port@6 { 8363 reg = <6>; 8364 8365 llcc_tpda_in6: endpoint { 8366 remote-endpoint = <&llcc6_tpdm_out>; 8367 }; 8368 }; 8369 8370 port@7 { 8371 reg = <7>; 8372 8373 llcc_tpda_in7: endpoint { 8374 remote-endpoint = <&llcc7_tpdm_out>; 8375 }; 8376 }; 8377 }; 8378 8379 out-ports { 8380 port { 8381 llcc_tpda_out: endpoint { 8382 remote-endpoint = <&ddr_funnel1_in0>; 8383 }; 8384 }; 8385 }; 8386 }; 8387 8388 funnel@10d13000 { 8389 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 8390 reg = <0x0 0x10d13000 0x0 0x1000>; 8391 8392 clocks = <&aoss_qmp>; 8393 clock-names = "apb_pclk"; 8394 8395 in-ports { 8396 port { 8397 ddr_funnel1_in0: endpoint { 8398 remote-endpoint = <&llcc_tpda_out>; 8399 }; 8400 }; 8401 }; 8402 8403 out-ports { 8404 port { 8405 ddr_funnel1_out: endpoint { 8406 remote-endpoint = <&ddr_funnel0_in6>; 8407 }; 8408 }; 8409 }; 8410 }; 8411 8412 apps_smmu: iommu@15000000 { 8413 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 8414 reg = <0 0x15000000 0 0x100000>; 8415 8416 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 8417 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 8418 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 8419 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 8420 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 8421 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 8422 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 8423 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 8424 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 8425 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 8426 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 8427 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 8428 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 8429 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 8430 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 8431 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 8432 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 8433 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 8434 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 8435 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 8436 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 8437 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 8438 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 8439 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 8440 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 8441 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 8442 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 8443 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 8444 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 8445 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 8446 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 8447 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 8448 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 8449 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 8450 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 8451 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 8452 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 8453 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 8454 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 8455 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 8456 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 8457 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 8458 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 8459 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 8460 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 8461 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 8462 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 8463 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 8464 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 8465 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 8466 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 8467 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 8468 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 8469 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 8470 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 8471 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 8472 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 8473 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 8474 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 8475 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 8476 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 8477 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 8478 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 8479 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 8480 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 8481 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 8482 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 8483 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 8484 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 8485 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 8486 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 8487 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 8488 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 8489 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 8490 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 8491 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 8492 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 8493 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 8494 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 8495 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 8496 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 8497 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 8498 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 8499 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 8500 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 8501 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 8502 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 8503 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 8504 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 8505 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 8506 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 8507 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 8508 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 8509 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 8510 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 8511 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 8512 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 8513 8514 #iommu-cells = <2>; 8515 #global-interrupts = <1>; 8516 8517 dma-coherent; 8518 }; 8519 8520 pcie_smmu: iommu@15400000 { 8521 compatible = "arm,smmu-v3"; 8522 reg = <0 0x15400000 0 0x80000>; 8523 #iommu-cells = <1>; 8524 interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 8525 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 8526 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>; 8527 interrupt-names = "eventq", 8528 "gerror", 8529 "cmdq-sync"; 8530 dma-coherent; 8531 status = "reserved"; /* Controlled by Gunyah. */ 8532 }; 8533 8534 intc: interrupt-controller@17000000 { 8535 compatible = "arm,gic-v3"; 8536 reg = <0 0x17000000 0 0x10000>, /* GICD */ 8537 <0 0x17080000 0 0x300000>; /* GICR * 12 */ 8538 8539 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 8540 8541 #interrupt-cells = <3>; 8542 interrupt-controller; 8543 8544 #redistributor-regions = <1>; 8545 redistributor-stride = <0x0 0x40000>; 8546 8547 #address-cells = <2>; 8548 #size-cells = <2>; 8549 ranges; 8550 8551 gic_its: msi-controller@17040000 { 8552 compatible = "arm,gic-v3-its"; 8553 reg = <0 0x17040000 0 0x40000>; 8554 8555 msi-controller; 8556 #msi-cells = <1>; 8557 }; 8558 }; 8559 8560 apss_watchdog: watchdog@17410000 { 8561 compatible = "qcom,apss-wdt-x1e80100", "qcom,kpss-wdt"; 8562 reg = <0x0 0x17410000 0x0 0x1000>; 8563 clocks = <&sleep_clk>; 8564 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 8565 status = "reserved"; /* Reserved by Gunyah */ 8566 }; 8567 8568 cpucp_mbox: mailbox@17430000 { 8569 compatible = "qcom,x1e80100-cpucp-mbox"; 8570 reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>; 8571 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 8572 #mbox-cells = <1>; 8573 }; 8574 8575 apps_rsc: rsc@17500000 { 8576 compatible = "qcom,rpmh-rsc"; 8577 reg = <0 0x17500000 0 0x10000>, 8578 <0 0x17510000 0 0x10000>, 8579 <0 0x17520000 0 0x10000>; 8580 reg-names = "drv-0", "drv-1", "drv-2"; 8581 8582 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 8583 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 8584 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 8585 qcom,tcs-offset = <0xd00>; 8586 qcom,drv-id = <2>; 8587 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 8588 <WAKE_TCS 2>, <CONTROL_TCS 0>; 8589 8590 label = "apps_rsc"; 8591 power-domains = <&system_pd>; 8592 8593 apps_bcm_voter: bcm-voter { 8594 compatible = "qcom,bcm-voter"; 8595 }; 8596 8597 rpmhcc: clock-controller { 8598 compatible = "qcom,x1e80100-rpmh-clk"; 8599 8600 clocks = <&xo_board>; 8601 clock-names = "xo"; 8602 8603 #clock-cells = <1>; 8604 }; 8605 8606 rpmhpd: power-controller { 8607 compatible = "qcom,x1e80100-rpmhpd"; 8608 8609 operating-points-v2 = <&rpmhpd_opp_table>; 8610 8611 #power-domain-cells = <1>; 8612 8613 rpmhpd_opp_table: opp-table { 8614 compatible = "operating-points-v2"; 8615 8616 rpmhpd_opp_ret: opp-16 { 8617 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 8618 }; 8619 8620 rpmhpd_opp_min_svs: opp-48 { 8621 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 8622 }; 8623 8624 rpmhpd_opp_low_svs_d2: opp-52 { 8625 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 8626 }; 8627 8628 rpmhpd_opp_low_svs_d1: opp-56 { 8629 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 8630 }; 8631 8632 rpmhpd_opp_low_svs_d0: opp-60 { 8633 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 8634 }; 8635 8636 rpmhpd_opp_low_svs: opp-64 { 8637 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 8638 }; 8639 8640 rpmhpd_opp_low_svs_l1: opp-80 { 8641 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 8642 }; 8643 8644 rpmhpd_opp_svs: opp-128 { 8645 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 8646 }; 8647 8648 rpmhpd_opp_svs_l0: opp-144 { 8649 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 8650 }; 8651 8652 rpmhpd_opp_svs_l1: opp-192 { 8653 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 8654 }; 8655 8656 rpmhpd_opp_nom: opp-256 { 8657 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 8658 }; 8659 8660 rpmhpd_opp_nom_l1: opp-320 { 8661 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 8662 }; 8663 8664 rpmhpd_opp_nom_l2: opp-336 { 8665 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 8666 }; 8667 8668 rpmhpd_opp_turbo: opp-384 { 8669 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 8670 }; 8671 8672 rpmhpd_opp_turbo_l1: opp-416 { 8673 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 8674 }; 8675 }; 8676 }; 8677 }; 8678 8679 timer@17800000 { 8680 compatible = "arm,armv7-timer-mem"; 8681 reg = <0 0x17800000 0 0x1000>; 8682 8683 #address-cells = <2>; 8684 #size-cells = <1>; 8685 ranges = <0 0 0 0 0x20000000>; 8686 8687 frame@17801000 { 8688 reg = <0 0x17801000 0x1000>, 8689 <0 0x17802000 0x1000>; 8690 8691 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 8692 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 8693 8694 frame-number = <0>; 8695 }; 8696 8697 frame@17803000 { 8698 reg = <0 0x17803000 0x1000>; 8699 8700 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 8701 8702 frame-number = <1>; 8703 8704 status = "disabled"; 8705 }; 8706 8707 frame@17805000 { 8708 reg = <0 0x17805000 0x1000>; 8709 8710 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 8711 8712 frame-number = <2>; 8713 8714 status = "disabled"; 8715 }; 8716 8717 frame@17807000 { 8718 reg = <0 0x17807000 0x1000>; 8719 8720 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 8721 8722 frame-number = <3>; 8723 8724 status = "disabled"; 8725 }; 8726 8727 frame@17809000 { 8728 reg = <0 0x17809000 0x1000>; 8729 8730 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 8731 8732 frame-number = <4>; 8733 8734 status = "disabled"; 8735 }; 8736 8737 frame@1780b000 { 8738 reg = <0 0x1780b000 0x1000>; 8739 8740 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 8741 8742 frame-number = <5>; 8743 8744 status = "disabled"; 8745 }; 8746 8747 frame@1780d000 { 8748 reg = <0 0x1780d000 0x1000>; 8749 8750 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 8751 8752 frame-number = <6>; 8753 8754 status = "disabled"; 8755 }; 8756 }; 8757 8758 sram: sram@18b4e000 { 8759 compatible = "mmio-sram"; 8760 reg = <0x0 0x18b4e000 0x0 0x400>; 8761 8762 #address-cells = <1>; 8763 #size-cells = <1>; 8764 ranges = <0x0 0x0 0x18b4e000 0x400>; 8765 8766 cpu_scp_lpri0: scp-sram-section@0 { 8767 compatible = "arm,scmi-shmem"; 8768 reg = <0x0 0x200>; 8769 }; 8770 8771 cpu_scp_lpri1: scp-sram-section@200 { 8772 compatible = "arm,scmi-shmem"; 8773 reg = <0x200 0x200>; 8774 }; 8775 }; 8776 8777 sbsa_watchdog: watchdog@1c840000 { 8778 compatible = "arm,sbsa-gwdt"; 8779 reg = <0 0x1c840000 0 0x1000>, 8780 <0 0x1c850000 0 0x1000>; 8781 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 8782 }; 8783 8784 qfprom: efuse@221c8000 { 8785 compatible = "qcom,x1e80100-qfprom", "qcom,qfprom"; 8786 reg = <0 0x221c8000 0 0x1000>; 8787 #address-cells = <1>; 8788 #size-cells = <1>; 8789 8790 gpu_speed_bin: gpu-speed-bin@119 { 8791 reg = <0x119 0x2>; 8792 bits = <7 8>; 8793 }; 8794 }; 8795 8796 pmu@24091000 { 8797 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 8798 reg = <0 0x24091000 0 0x1000>; 8799 8800 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 8801 8802 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 8803 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 8804 8805 operating-points-v2 = <&llcc_bwmon_opp_table>; 8806 8807 llcc_bwmon_opp_table: opp-table { 8808 compatible = "operating-points-v2"; 8809 8810 opp-0 { 8811 opp-peak-kBps = <800000>; 8812 }; 8813 8814 opp-1 { 8815 opp-peak-kBps = <2188000>; 8816 }; 8817 8818 opp-2 { 8819 opp-peak-kBps = <3072000>; 8820 }; 8821 8822 opp-3 { 8823 opp-peak-kBps = <6220800>; 8824 }; 8825 8826 opp-4 { 8827 opp-peak-kBps = <6835200>; 8828 }; 8829 8830 opp-5 { 8831 opp-peak-kBps = <8371200>; 8832 }; 8833 8834 opp-6 { 8835 opp-peak-kBps = <10944000>; 8836 }; 8837 8838 opp-7 { 8839 opp-peak-kBps = <12748800>; 8840 }; 8841 8842 opp-8 { 8843 opp-peak-kBps = <14745600>; 8844 }; 8845 8846 opp-9 { 8847 opp-peak-kBps = <16896000>; 8848 }; 8849 }; 8850 }; 8851 8852 /* cluster0 */ 8853 bwmon_cluster0: pmu@240b3400 { 8854 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8855 reg = <0 0x240b3400 0 0x600>; 8856 8857 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8858 8859 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8860 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8861 8862 operating-points-v2 = <&cpu_bwmon_opp_table>; 8863 }; 8864 8865 /* cluster2 */ 8866 bwmon_cluster2: pmu@240b5400 { 8867 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8868 reg = <0 0x240b5400 0 0x600>; 8869 8870 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8871 8872 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8873 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8874 8875 operating-points-v2 = <&cpu_bwmon_opp_table>; 8876 8877 cpu_bwmon_opp_table: opp-table { 8878 compatible = "operating-points-v2"; 8879 8880 opp-0 { 8881 opp-peak-kBps = <4800000>; 8882 }; 8883 8884 opp-1 { 8885 opp-peak-kBps = <7464000>; 8886 }; 8887 8888 opp-2 { 8889 opp-peak-kBps = <9600000>; 8890 }; 8891 8892 opp-3 { 8893 opp-peak-kBps = <12896000>; 8894 }; 8895 8896 opp-4 { 8897 opp-peak-kBps = <14928000>; 8898 }; 8899 8900 opp-5 { 8901 opp-peak-kBps = <17064000>; 8902 }; 8903 }; 8904 }; 8905 8906 /* cluster1 */ 8907 pmu@240b6400 { 8908 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8909 reg = <0 0x240b6400 0 0x600>; 8910 8911 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8912 8913 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8914 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8915 8916 operating-points-v2 = <&cpu_bwmon_opp_table>; 8917 }; 8918 8919 system-cache-controller@25000000 { 8920 compatible = "qcom,x1e80100-llcc"; 8921 reg = <0 0x25000000 0 0x200000>, 8922 <0 0x25200000 0 0x200000>, 8923 <0 0x25400000 0 0x200000>, 8924 <0 0x25600000 0 0x200000>, 8925 <0 0x25800000 0 0x200000>, 8926 <0 0x25a00000 0 0x200000>, 8927 <0 0x25c00000 0 0x200000>, 8928 <0 0x25e00000 0 0x200000>, 8929 <0 0x26000000 0 0x200000>, 8930 <0 0x26200000 0 0x200000>; 8931 reg-names = "llcc0_base", 8932 "llcc1_base", 8933 "llcc2_base", 8934 "llcc3_base", 8935 "llcc4_base", 8936 "llcc5_base", 8937 "llcc6_base", 8938 "llcc7_base", 8939 "llcc_broadcast_base", 8940 "llcc_broadcast_and_base"; 8941 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 8942 }; 8943 8944 remoteproc_cdsp: remoteproc@32300000 { 8945 compatible = "qcom,x1e80100-cdsp-pas"; 8946 reg = <0x0 0x32300000 0x0 0x10000>; 8947 8948 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 8949 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 8950 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 8951 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 8952 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 8953 interrupt-names = "wdog", 8954 "fatal", 8955 "ready", 8956 "handover", 8957 "stop-ack"; 8958 8959 clocks = <&rpmhcc RPMH_CXO_CLK>; 8960 clock-names = "xo"; 8961 8962 power-domains = <&rpmhpd RPMHPD_CX>, 8963 <&rpmhpd RPMHPD_MXC>, 8964 <&rpmhpd RPMHPD_NSP>; 8965 power-domain-names = "cx", 8966 "mxc", 8967 "nsp"; 8968 8969 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 8970 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 8971 8972 memory-region = <&cdsp_mem>, 8973 <&q6_cdsp_dtb_mem>; 8974 8975 qcom,qmp = <&aoss_qmp>; 8976 8977 qcom,smem-states = <&smp2p_cdsp_out 0>; 8978 qcom,smem-state-names = "stop"; 8979 8980 status = "disabled"; 8981 8982 glink-edge { 8983 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 8984 IPCC_MPROC_SIGNAL_GLINK_QMP 8985 IRQ_TYPE_EDGE_RISING>; 8986 mboxes = <&ipcc IPCC_CLIENT_CDSP 8987 IPCC_MPROC_SIGNAL_GLINK_QMP>; 8988 8989 label = "cdsp"; 8990 qcom,remote-pid = <5>; 8991 8992 fastrpc { 8993 compatible = "qcom,fastrpc"; 8994 qcom,glink-channels = "fastrpcglink-apps-dsp"; 8995 label = "cdsp"; 8996 qcom,non-secure-domain; 8997 #address-cells = <1>; 8998 #size-cells = <0>; 8999 9000 compute-cb@1 { 9001 compatible = "qcom,fastrpc-compute-cb"; 9002 reg = <1>; 9003 iommus = <&apps_smmu 0x0c01 0x20>; 9004 dma-coherent; 9005 }; 9006 9007 compute-cb@2 { 9008 compatible = "qcom,fastrpc-compute-cb"; 9009 reg = <2>; 9010 iommus = <&apps_smmu 0x0c02 0x20>; 9011 dma-coherent; 9012 }; 9013 9014 compute-cb@3 { 9015 compatible = "qcom,fastrpc-compute-cb"; 9016 reg = <3>; 9017 iommus = <&apps_smmu 0x0c03 0x20>; 9018 dma-coherent; 9019 }; 9020 9021 compute-cb@4 { 9022 compatible = "qcom,fastrpc-compute-cb"; 9023 reg = <4>; 9024 iommus = <&apps_smmu 0x0c04 0x20>; 9025 dma-coherent; 9026 }; 9027 9028 compute-cb@5 { 9029 compatible = "qcom,fastrpc-compute-cb"; 9030 reg = <5>; 9031 iommus = <&apps_smmu 0x0c05 0x20>; 9032 dma-coherent; 9033 }; 9034 9035 compute-cb@6 { 9036 compatible = "qcom,fastrpc-compute-cb"; 9037 reg = <6>; 9038 iommus = <&apps_smmu 0x0c06 0x20>; 9039 dma-coherent; 9040 }; 9041 9042 compute-cb@7 { 9043 compatible = "qcom,fastrpc-compute-cb"; 9044 reg = <7>; 9045 iommus = <&apps_smmu 0x0c07 0x20>; 9046 dma-coherent; 9047 }; 9048 9049 compute-cb@8 { 9050 compatible = "qcom,fastrpc-compute-cb"; 9051 reg = <8>; 9052 iommus = <&apps_smmu 0x0c08 0x20>; 9053 dma-coherent; 9054 }; 9055 9056 /* note: compute-cb@9 is secure */ 9057 9058 compute-cb@10 { 9059 compatible = "qcom,fastrpc-compute-cb"; 9060 reg = <10>; 9061 iommus = <&apps_smmu 0x0c0c 0x20>; 9062 dma-coherent; 9063 }; 9064 9065 compute-cb@11 { 9066 compatible = "qcom,fastrpc-compute-cb"; 9067 reg = <11>; 9068 iommus = <&apps_smmu 0x0c0d 0x20>; 9069 dma-coherent; 9070 }; 9071 9072 compute-cb@12 { 9073 compatible = "qcom,fastrpc-compute-cb"; 9074 reg = <12>; 9075 iommus = <&apps_smmu 0x0c0e 0x20>; 9076 dma-coherent; 9077 }; 9078 9079 compute-cb@13 { 9080 compatible = "qcom,fastrpc-compute-cb"; 9081 reg = <13>; 9082 iommus = <&apps_smmu 0x0c0f 0x20>; 9083 dma-coherent; 9084 }; 9085 }; 9086 }; 9087 }; 9088 }; 9089 9090 timer { 9091 compatible = "arm,armv8-timer"; 9092 9093 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 9094 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 9095 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 9096 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 9097 }; 9098 9099 thermal_zones: thermal-zones { 9100 aoss0-thermal { 9101 thermal-sensors = <&tsens0 0>; 9102 9103 trips { 9104 trip-point0 { 9105 temperature = <90000>; 9106 hysteresis = <2000>; 9107 type = "hot"; 9108 }; 9109 9110 aoss0-critical { 9111 temperature = <115000>; 9112 hysteresis = <1000>; 9113 type = "critical"; 9114 }; 9115 }; 9116 }; 9117 9118 cpu0-0-top-thermal { 9119 thermal-sensors = <&tsens0 1>; 9120 9121 trips { 9122 cpu-critical { 9123 temperature = <115000>; 9124 hysteresis = <1000>; 9125 type = "critical"; 9126 }; 9127 }; 9128 }; 9129 9130 cpu0-0-btm-thermal { 9131 thermal-sensors = <&tsens0 2>; 9132 9133 trips { 9134 cpu-critical { 9135 temperature = <115000>; 9136 hysteresis = <1000>; 9137 type = "critical"; 9138 }; 9139 }; 9140 }; 9141 9142 cpu0-1-top-thermal { 9143 thermal-sensors = <&tsens0 3>; 9144 9145 trips { 9146 cpu-critical { 9147 temperature = <115000>; 9148 hysteresis = <1000>; 9149 type = "critical"; 9150 }; 9151 }; 9152 }; 9153 9154 cpu0-1-btm-thermal { 9155 thermal-sensors = <&tsens0 4>; 9156 9157 trips { 9158 cpu-critical { 9159 temperature = <115000>; 9160 hysteresis = <1000>; 9161 type = "critical"; 9162 }; 9163 }; 9164 }; 9165 9166 cpu0-2-top-thermal { 9167 thermal-sensors = <&tsens0 5>; 9168 9169 trips { 9170 cpu-critical { 9171 temperature = <115000>; 9172 hysteresis = <1000>; 9173 type = "critical"; 9174 }; 9175 }; 9176 }; 9177 9178 cpu0-2-btm-thermal { 9179 thermal-sensors = <&tsens0 6>; 9180 9181 trips { 9182 cpu-critical { 9183 temperature = <115000>; 9184 hysteresis = <1000>; 9185 type = "critical"; 9186 }; 9187 }; 9188 }; 9189 9190 cpu0-3-top-thermal { 9191 thermal-sensors = <&tsens0 7>; 9192 9193 trips { 9194 cpu-critical { 9195 temperature = <115000>; 9196 hysteresis = <1000>; 9197 type = "critical"; 9198 }; 9199 }; 9200 }; 9201 9202 cpu0-3-btm-thermal { 9203 thermal-sensors = <&tsens0 8>; 9204 9205 trips { 9206 cpu-critical { 9207 temperature = <115000>; 9208 hysteresis = <1000>; 9209 type = "critical"; 9210 }; 9211 }; 9212 }; 9213 9214 cpuss0-top-thermal { 9215 thermal-sensors = <&tsens0 9>; 9216 9217 trips { 9218 cpuss2-critical { 9219 temperature = <115000>; 9220 hysteresis = <1000>; 9221 type = "critical"; 9222 }; 9223 }; 9224 }; 9225 9226 cpuss0-btm-thermal { 9227 thermal-sensors = <&tsens0 10>; 9228 9229 trips { 9230 cpuss2-critical { 9231 temperature = <115000>; 9232 hysteresis = <1000>; 9233 type = "critical"; 9234 }; 9235 }; 9236 }; 9237 9238 mem-thermal { 9239 thermal-sensors = <&tsens0 11>; 9240 9241 trips { 9242 trip-point0 { 9243 temperature = <90000>; 9244 hysteresis = <2000>; 9245 type = "hot"; 9246 }; 9247 9248 mem-critical { 9249 temperature = <115000>; 9250 hysteresis = <0>; 9251 type = "critical"; 9252 }; 9253 }; 9254 }; 9255 9256 video-thermal { 9257 thermal-sensors = <&tsens0 12>; 9258 9259 trips { 9260 trip-point0 { 9261 temperature = <90000>; 9262 hysteresis = <2000>; 9263 type = "hot"; 9264 }; 9265 9266 video-critical { 9267 temperature = <115000>; 9268 hysteresis = <1000>; 9269 type = "critical"; 9270 }; 9271 }; 9272 }; 9273 9274 aoss1-thermal { 9275 thermal-sensors = <&tsens1 0>; 9276 9277 trips { 9278 trip-point0 { 9279 temperature = <90000>; 9280 hysteresis = <2000>; 9281 type = "hot"; 9282 }; 9283 9284 aoss0-critical { 9285 temperature = <115000>; 9286 hysteresis = <1000>; 9287 type = "critical"; 9288 }; 9289 }; 9290 }; 9291 9292 cpu1-0-top-thermal { 9293 thermal-sensors = <&tsens1 1>; 9294 9295 trips { 9296 cpu-critical { 9297 temperature = <115000>; 9298 hysteresis = <1000>; 9299 type = "critical"; 9300 }; 9301 }; 9302 }; 9303 9304 cpu1-0-btm-thermal { 9305 thermal-sensors = <&tsens1 2>; 9306 9307 trips { 9308 cpu-critical { 9309 temperature = <115000>; 9310 hysteresis = <1000>; 9311 type = "critical"; 9312 }; 9313 }; 9314 }; 9315 9316 cpu1-1-top-thermal { 9317 thermal-sensors = <&tsens1 3>; 9318 9319 trips { 9320 cpu-critical { 9321 temperature = <115000>; 9322 hysteresis = <1000>; 9323 type = "critical"; 9324 }; 9325 }; 9326 }; 9327 9328 cpu1-1-btm-thermal { 9329 thermal-sensors = <&tsens1 4>; 9330 9331 trips { 9332 cpu-critical { 9333 temperature = <115000>; 9334 hysteresis = <1000>; 9335 type = "critical"; 9336 }; 9337 }; 9338 }; 9339 9340 cpu1-2-top-thermal { 9341 thermal-sensors = <&tsens1 5>; 9342 9343 trips { 9344 cpu-critical { 9345 temperature = <115000>; 9346 hysteresis = <1000>; 9347 type = "critical"; 9348 }; 9349 }; 9350 }; 9351 9352 cpu1-2-btm-thermal { 9353 thermal-sensors = <&tsens1 6>; 9354 9355 trips { 9356 cpu-critical { 9357 temperature = <115000>; 9358 hysteresis = <1000>; 9359 type = "critical"; 9360 }; 9361 }; 9362 }; 9363 9364 cpu1-3-top-thermal { 9365 thermal-sensors = <&tsens1 7>; 9366 9367 trips { 9368 cpu-critical { 9369 temperature = <115000>; 9370 hysteresis = <1000>; 9371 type = "critical"; 9372 }; 9373 }; 9374 }; 9375 9376 cpu1-3-btm-thermal { 9377 thermal-sensors = <&tsens1 8>; 9378 9379 trips { 9380 cpu-critical { 9381 temperature = <115000>; 9382 hysteresis = <1000>; 9383 type = "critical"; 9384 }; 9385 }; 9386 }; 9387 9388 cpuss1-top-thermal { 9389 thermal-sensors = <&tsens1 9>; 9390 9391 trips { 9392 cpuss2-critical { 9393 temperature = <115000>; 9394 hysteresis = <1000>; 9395 type = "critical"; 9396 }; 9397 }; 9398 }; 9399 9400 cpuss1-btm-thermal { 9401 thermal-sensors = <&tsens1 10>; 9402 9403 trips { 9404 cpuss2-critical { 9405 temperature = <115000>; 9406 hysteresis = <1000>; 9407 type = "critical"; 9408 }; 9409 }; 9410 }; 9411 9412 aoss2-thermal { 9413 thermal-sensors = <&tsens2 0>; 9414 9415 trips { 9416 trip-point0 { 9417 temperature = <90000>; 9418 hysteresis = <2000>; 9419 type = "hot"; 9420 }; 9421 9422 aoss0-critical { 9423 temperature = <115000>; 9424 hysteresis = <1000>; 9425 type = "critical"; 9426 }; 9427 }; 9428 }; 9429 9430 thermal_cpu2_0_top: cpu2-0-top-thermal { 9431 thermal-sensors = <&tsens2 1>; 9432 9433 trips { 9434 cpu-critical { 9435 temperature = <115000>; 9436 hysteresis = <1000>; 9437 type = "critical"; 9438 }; 9439 }; 9440 }; 9441 9442 thermal_cpu2_0_btm: cpu2-0-btm-thermal { 9443 thermal-sensors = <&tsens2 2>; 9444 9445 trips { 9446 cpu-critical { 9447 temperature = <115000>; 9448 hysteresis = <1000>; 9449 type = "critical"; 9450 }; 9451 }; 9452 }; 9453 9454 thermal_cpu2_1_top: cpu2-1-top-thermal { 9455 thermal-sensors = <&tsens2 3>; 9456 9457 trips { 9458 cpu-critical { 9459 temperature = <115000>; 9460 hysteresis = <1000>; 9461 type = "critical"; 9462 }; 9463 }; 9464 }; 9465 9466 thermal_cpu2_1_btm: cpu2-1-btm-thermal { 9467 thermal-sensors = <&tsens2 4>; 9468 9469 trips { 9470 cpu-critical { 9471 temperature = <115000>; 9472 hysteresis = <1000>; 9473 type = "critical"; 9474 }; 9475 }; 9476 }; 9477 9478 thermal_cpu2_2_top: cpu2-2-top-thermal { 9479 thermal-sensors = <&tsens2 5>; 9480 9481 trips { 9482 cpu-critical { 9483 temperature = <115000>; 9484 hysteresis = <1000>; 9485 type = "critical"; 9486 }; 9487 }; 9488 }; 9489 9490 thermal_cpu2_2_btm: cpu2-2-btm-thermal { 9491 thermal-sensors = <&tsens2 6>; 9492 9493 trips { 9494 cpu-critical { 9495 temperature = <115000>; 9496 hysteresis = <1000>; 9497 type = "critical"; 9498 }; 9499 }; 9500 }; 9501 9502 thermal_cpu2_3_top: cpu2-3-top-thermal { 9503 thermal-sensors = <&tsens2 7>; 9504 9505 trips { 9506 cpu-critical { 9507 temperature = <115000>; 9508 hysteresis = <1000>; 9509 type = "critical"; 9510 }; 9511 }; 9512 }; 9513 9514 thermal_cpu2_3_btm: cpu2-3-btm-thermal { 9515 thermal-sensors = <&tsens2 8>; 9516 9517 trips { 9518 cpu-critical { 9519 temperature = <115000>; 9520 hysteresis = <1000>; 9521 type = "critical"; 9522 }; 9523 }; 9524 }; 9525 9526 thermal_cpuss2_top: cpuss2-top-thermal { 9527 thermal-sensors = <&tsens2 9>; 9528 9529 trips { 9530 cpuss2-critical { 9531 temperature = <115000>; 9532 hysteresis = <1000>; 9533 type = "critical"; 9534 }; 9535 }; 9536 }; 9537 9538 thermal_cpuss2_btm: cpuss2-btm-thermal { 9539 thermal-sensors = <&tsens2 10>; 9540 9541 trips { 9542 cpuss2-critical { 9543 temperature = <115000>; 9544 hysteresis = <1000>; 9545 type = "critical"; 9546 }; 9547 }; 9548 }; 9549 9550 thermal_aoss3: aoss3-thermal { 9551 thermal-sensors = <&tsens3 0>; 9552 9553 trips { 9554 trip-point0 { 9555 temperature = <90000>; 9556 hysteresis = <2000>; 9557 type = "hot"; 9558 }; 9559 9560 aoss0-critical { 9561 temperature = <115000>; 9562 hysteresis = <1000>; 9563 type = "critical"; 9564 }; 9565 }; 9566 }; 9567 9568 thermal_nsp0: nsp0-thermal { 9569 thermal-sensors = <&tsens3 1>; 9570 9571 trips { 9572 trip-point0 { 9573 temperature = <90000>; 9574 hysteresis = <2000>; 9575 type = "hot"; 9576 }; 9577 9578 nsp0-critical { 9579 temperature = <115000>; 9580 hysteresis = <1000>; 9581 type = "critical"; 9582 }; 9583 }; 9584 }; 9585 9586 thermal_nsp1: nsp1-thermal { 9587 thermal-sensors = <&tsens3 2>; 9588 9589 trips { 9590 trip-point0 { 9591 temperature = <90000>; 9592 hysteresis = <2000>; 9593 type = "hot"; 9594 }; 9595 9596 nsp1-critical { 9597 temperature = <115000>; 9598 hysteresis = <1000>; 9599 type = "critical"; 9600 }; 9601 }; 9602 }; 9603 9604 thermal_nsp2: nsp2-thermal { 9605 thermal-sensors = <&tsens3 3>; 9606 9607 trips { 9608 trip-point0 { 9609 temperature = <90000>; 9610 hysteresis = <2000>; 9611 type = "hot"; 9612 }; 9613 9614 nsp2-critical { 9615 temperature = <115000>; 9616 hysteresis = <1000>; 9617 type = "critical"; 9618 }; 9619 }; 9620 }; 9621 9622 thermal_nsp3: nsp3-thermal { 9623 thermal-sensors = <&tsens3 4>; 9624 9625 trips { 9626 trip-point0 { 9627 temperature = <90000>; 9628 hysteresis = <2000>; 9629 type = "hot"; 9630 }; 9631 9632 nsp3-critical { 9633 temperature = <115000>; 9634 hysteresis = <1000>; 9635 type = "critical"; 9636 }; 9637 }; 9638 }; 9639 9640 thermal_gpuss_0: gpuss-0-thermal { 9641 polling-delay-passive = <200>; 9642 9643 thermal-sensors = <&tsens3 5>; 9644 9645 cooling-maps { 9646 map0 { 9647 trip = <&gpuss0_alert0>; 9648 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9649 }; 9650 }; 9651 9652 trips { 9653 gpuss0_alert0: trip-point0 { 9654 temperature = <95000>; 9655 hysteresis = <1000>; 9656 type = "passive"; 9657 }; 9658 9659 gpu-critical { 9660 temperature = <115000>; 9661 hysteresis = <1000>; 9662 type = "critical"; 9663 }; 9664 }; 9665 }; 9666 9667 thermal_gpuss_1: gpuss-1-thermal { 9668 polling-delay-passive = <200>; 9669 9670 thermal-sensors = <&tsens3 6>; 9671 9672 cooling-maps { 9673 map0 { 9674 trip = <&gpuss1_alert0>; 9675 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9676 }; 9677 }; 9678 9679 trips { 9680 gpuss1_alert0: trip-point0 { 9681 temperature = <95000>; 9682 hysteresis = <1000>; 9683 type = "passive"; 9684 }; 9685 9686 gpu-critical { 9687 temperature = <115000>; 9688 hysteresis = <1000>; 9689 type = "critical"; 9690 }; 9691 }; 9692 }; 9693 9694 thermal_gpuss_2: gpuss-2-thermal { 9695 polling-delay-passive = <200>; 9696 9697 thermal-sensors = <&tsens3 7>; 9698 9699 cooling-maps { 9700 map0 { 9701 trip = <&gpuss2_alert0>; 9702 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9703 }; 9704 }; 9705 9706 trips { 9707 gpuss2_alert0: trip-point0 { 9708 temperature = <95000>; 9709 hysteresis = <1000>; 9710 type = "passive"; 9711 }; 9712 9713 gpu-critical { 9714 temperature = <115000>; 9715 hysteresis = <1000>; 9716 type = "critical"; 9717 }; 9718 }; 9719 }; 9720 9721 thermal_gpuss_3: gpuss-3-thermal { 9722 polling-delay-passive = <200>; 9723 9724 thermal-sensors = <&tsens3 8>; 9725 9726 cooling-maps { 9727 map0 { 9728 trip = <&gpuss3_alert0>; 9729 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9730 }; 9731 }; 9732 9733 trips { 9734 gpuss3_alert0: trip-point0 { 9735 temperature = <95000>; 9736 hysteresis = <1000>; 9737 type = "passive"; 9738 }; 9739 9740 gpu-critical { 9741 temperature = <115000>; 9742 hysteresis = <1000>; 9743 type = "critical"; 9744 }; 9745 }; 9746 }; 9747 9748 thermal_gpuss_4: gpuss-4-thermal { 9749 polling-delay-passive = <200>; 9750 9751 thermal-sensors = <&tsens3 9>; 9752 9753 cooling-maps { 9754 map0 { 9755 trip = <&gpuss4_alert0>; 9756 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9757 }; 9758 }; 9759 9760 trips { 9761 gpuss4_alert0: trip-point0 { 9762 temperature = <95000>; 9763 hysteresis = <1000>; 9764 type = "passive"; 9765 }; 9766 9767 gpu-critical { 9768 temperature = <115000>; 9769 hysteresis = <1000>; 9770 type = "critical"; 9771 }; 9772 }; 9773 }; 9774 9775 thermal_gpuss_5: gpuss-5-thermal { 9776 polling-delay-passive = <200>; 9777 9778 thermal-sensors = <&tsens3 10>; 9779 9780 cooling-maps { 9781 map0 { 9782 trip = <&gpuss5_alert0>; 9783 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9784 }; 9785 }; 9786 9787 trips { 9788 gpuss5_alert0: trip-point0 { 9789 temperature = <95000>; 9790 hysteresis = <1000>; 9791 type = "passive"; 9792 }; 9793 9794 gpu-critical { 9795 temperature = <115000>; 9796 hysteresis = <1000>; 9797 type = "critical"; 9798 }; 9799 }; 9800 }; 9801 9802 thermal_gpuss_6: gpuss-6-thermal { 9803 polling-delay-passive = <200>; 9804 9805 thermal-sensors = <&tsens3 11>; 9806 9807 cooling-maps { 9808 map0 { 9809 trip = <&gpuss6_alert0>; 9810 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9811 }; 9812 }; 9813 9814 trips { 9815 gpuss6_alert0: trip-point0 { 9816 temperature = <95000>; 9817 hysteresis = <1000>; 9818 type = "passive"; 9819 }; 9820 9821 gpu-critical { 9822 temperature = <115000>; 9823 hysteresis = <1000>; 9824 type = "critical"; 9825 }; 9826 }; 9827 }; 9828 9829 thermal_gpuss_7: gpuss-7-thermal { 9830 polling-delay-passive = <200>; 9831 9832 thermal-sensors = <&tsens3 12>; 9833 9834 cooling-maps { 9835 map0 { 9836 trip = <&gpuss7_alert0>; 9837 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9838 }; 9839 }; 9840 9841 trips { 9842 gpuss7_alert0: trip-point0 { 9843 temperature = <95000>; 9844 hysteresis = <1000>; 9845 type = "passive"; 9846 }; 9847 9848 gpu-critical { 9849 temperature = <115000>; 9850 hysteresis = <1000>; 9851 type = "critical"; 9852 }; 9853 }; 9854 }; 9855 9856 thermal_camera0: camera0-thermal { 9857 thermal-sensors = <&tsens3 13>; 9858 9859 trips { 9860 trip-point0 { 9861 temperature = <90000>; 9862 hysteresis = <2000>; 9863 type = "hot"; 9864 }; 9865 9866 camera0-critical { 9867 temperature = <115000>; 9868 hysteresis = <1000>; 9869 type = "critical"; 9870 }; 9871 }; 9872 }; 9873 9874 thermal_camera1: camera1-thermal { 9875 thermal-sensors = <&tsens3 14>; 9876 9877 trips { 9878 trip-point0 { 9879 temperature = <90000>; 9880 hysteresis = <2000>; 9881 type = "hot"; 9882 }; 9883 9884 camera0-critical { 9885 temperature = <115000>; 9886 hysteresis = <1000>; 9887 type = "critical"; 9888 }; 9889 }; 9890 }; 9891 }; 9892}; 9893