1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 8#include <dt-bindings/clock/qcom,sm8450-videocc.h> 9#include <dt-bindings/clock/qcom,x1e80100-dispcc.h> 10#include <dt-bindings/clock/qcom,x1e80100-gcc.h> 11#include <dt-bindings/clock/qcom,x1e80100-gpucc.h> 12#include <dt-bindings/clock/qcom,x1e80100-tcsr.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 24#include <dt-bindings/thermal/thermal.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 chosen { }; 33 34 clocks { 35 xo_board: xo-board { 36 compatible = "fixed-clock"; 37 clock-frequency = <76800000>; 38 #clock-cells = <0>; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 clock-frequency = <32764>; 44 #clock-cells = <0>; 45 }; 46 47 bi_tcxo_div2: bi-tcxo-div2-clk { 48 compatible = "fixed-factor-clock"; 49 #clock-cells = <0>; 50 51 clocks = <&rpmhcc RPMH_CXO_CLK>; 52 clock-mult = <1>; 53 clock-div = <2>; 54 }; 55 56 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 57 compatible = "fixed-factor-clock"; 58 #clock-cells = <0>; 59 60 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 61 clock-mult = <1>; 62 clock-div = <2>; 63 }; 64 }; 65 66 cpus { 67 #address-cells = <2>; 68 #size-cells = <0>; 69 70 cpu0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "qcom,oryon"; 73 reg = <0x0 0x0>; 74 enable-method = "psci"; 75 next-level-cache = <&l2_0>; 76 power-domains = <&cpu_pd0>, <&scmi_dvfs 0>; 77 power-domain-names = "psci", "perf"; 78 79 l2_0: l2-cache { 80 compatible = "cache"; 81 cache-level = <2>; 82 cache-unified; 83 }; 84 }; 85 86 cpu1: cpu@100 { 87 device_type = "cpu"; 88 compatible = "qcom,oryon"; 89 reg = <0x0 0x100>; 90 enable-method = "psci"; 91 next-level-cache = <&l2_0>; 92 power-domains = <&cpu_pd1>, <&scmi_dvfs 0>; 93 power-domain-names = "psci", "perf"; 94 }; 95 96 cpu2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "qcom,oryon"; 99 reg = <0x0 0x200>; 100 enable-method = "psci"; 101 next-level-cache = <&l2_0>; 102 power-domains = <&cpu_pd2>, <&scmi_dvfs 0>; 103 power-domain-names = "psci", "perf"; 104 }; 105 106 cpu3: cpu@300 { 107 device_type = "cpu"; 108 compatible = "qcom,oryon"; 109 reg = <0x0 0x300>; 110 enable-method = "psci"; 111 next-level-cache = <&l2_0>; 112 power-domains = <&cpu_pd3>, <&scmi_dvfs 0>; 113 power-domain-names = "psci", "perf"; 114 }; 115 116 cpu4: cpu@10000 { 117 device_type = "cpu"; 118 compatible = "qcom,oryon"; 119 reg = <0x0 0x10000>; 120 enable-method = "psci"; 121 next-level-cache = <&l2_1>; 122 power-domains = <&cpu_pd4>, <&scmi_dvfs 1>; 123 power-domain-names = "psci", "perf"; 124 125 l2_1: l2-cache { 126 compatible = "cache"; 127 cache-level = <2>; 128 cache-unified; 129 }; 130 }; 131 132 cpu5: cpu@10100 { 133 device_type = "cpu"; 134 compatible = "qcom,oryon"; 135 reg = <0x0 0x10100>; 136 enable-method = "psci"; 137 next-level-cache = <&l2_1>; 138 power-domains = <&cpu_pd5>, <&scmi_dvfs 1>; 139 power-domain-names = "psci", "perf"; 140 }; 141 142 cpu6: cpu@10200 { 143 device_type = "cpu"; 144 compatible = "qcom,oryon"; 145 reg = <0x0 0x10200>; 146 enable-method = "psci"; 147 next-level-cache = <&l2_1>; 148 power-domains = <&cpu_pd6>, <&scmi_dvfs 1>; 149 power-domain-names = "psci", "perf"; 150 }; 151 152 cpu7: cpu@10300 { 153 device_type = "cpu"; 154 compatible = "qcom,oryon"; 155 reg = <0x0 0x10300>; 156 enable-method = "psci"; 157 next-level-cache = <&l2_1>; 158 power-domains = <&cpu_pd7>, <&scmi_dvfs 1>; 159 power-domain-names = "psci", "perf"; 160 }; 161 162 cpu8: cpu@20000 { 163 device_type = "cpu"; 164 compatible = "qcom,oryon"; 165 reg = <0x0 0x20000>; 166 enable-method = "psci"; 167 next-level-cache = <&l2_2>; 168 power-domains = <&cpu_pd8>, <&scmi_dvfs 2>; 169 power-domain-names = "psci", "perf"; 170 171 l2_2: l2-cache { 172 compatible = "cache"; 173 cache-level = <2>; 174 cache-unified; 175 }; 176 }; 177 178 cpu9: cpu@20100 { 179 device_type = "cpu"; 180 compatible = "qcom,oryon"; 181 reg = <0x0 0x20100>; 182 enable-method = "psci"; 183 next-level-cache = <&l2_2>; 184 power-domains = <&cpu_pd9>, <&scmi_dvfs 2>; 185 power-domain-names = "psci", "perf"; 186 }; 187 188 cpu10: cpu@20200 { 189 device_type = "cpu"; 190 compatible = "qcom,oryon"; 191 reg = <0x0 0x20200>; 192 enable-method = "psci"; 193 next-level-cache = <&l2_2>; 194 power-domains = <&cpu_pd10>, <&scmi_dvfs 2>; 195 power-domain-names = "psci", "perf"; 196 }; 197 198 cpu11: cpu@20300 { 199 device_type = "cpu"; 200 compatible = "qcom,oryon"; 201 reg = <0x0 0x20300>; 202 enable-method = "psci"; 203 next-level-cache = <&l2_2>; 204 power-domains = <&cpu_pd11>, <&scmi_dvfs 2>; 205 power-domain-names = "psci", "perf"; 206 }; 207 208 cpu-map { 209 cluster0 { 210 core0 { 211 cpu = <&cpu0>; 212 }; 213 214 core1 { 215 cpu = <&cpu1>; 216 }; 217 218 core2 { 219 cpu = <&cpu2>; 220 }; 221 222 core3 { 223 cpu = <&cpu3>; 224 }; 225 }; 226 227 cluster1 { 228 core0 { 229 cpu = <&cpu4>; 230 }; 231 232 core1 { 233 cpu = <&cpu5>; 234 }; 235 236 core2 { 237 cpu = <&cpu6>; 238 }; 239 240 core3 { 241 cpu = <&cpu7>; 242 }; 243 }; 244 245 cpu_map_cluster2: cluster2 { 246 core0 { 247 cpu = <&cpu8>; 248 }; 249 250 core1 { 251 cpu = <&cpu9>; 252 }; 253 254 core2 { 255 cpu = <&cpu10>; 256 }; 257 258 core3 { 259 cpu = <&cpu11>; 260 }; 261 }; 262 }; 263 264 idle-states { 265 entry-method = "psci"; 266 267 cluster_c4: cpu-sleep-0 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "ret"; 270 arm,psci-suspend-param = <0x00000004>; 271 entry-latency-us = <180>; 272 exit-latency-us = <500>; 273 min-residency-us = <600>; 274 }; 275 }; 276 277 domain-idle-states { 278 cluster_cl4: cluster-sleep-0 { 279 compatible = "domain-idle-state"; 280 arm,psci-suspend-param = <0x01000044>; 281 entry-latency-us = <350>; 282 exit-latency-us = <500>; 283 min-residency-us = <2500>; 284 }; 285 286 cluster_cl5: cluster-sleep-1 { 287 compatible = "domain-idle-state"; 288 arm,psci-suspend-param = <0x01000054>; 289 entry-latency-us = <2200>; 290 exit-latency-us = <4000>; 291 min-residency-us = <7000>; 292 }; 293 }; 294 }; 295 296 dummy-sink { 297 compatible = "arm,coresight-dummy-sink"; 298 299 in-ports { 300 port { 301 eud_in: endpoint { 302 remote-endpoint = <&swao_rep_out1>; 303 }; 304 }; 305 }; 306 }; 307 308 firmware { 309 scm: scm { 310 compatible = "qcom,scm-x1e80100", "qcom,scm"; 311 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 312 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 313 qcom,dload-mode = <&tcsr 0x19000>; 314 }; 315 316 scmi { 317 compatible = "arm,scmi"; 318 mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>; 319 mbox-names = "tx", "rx"; 320 shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; 321 322 #address-cells = <1>; 323 #size-cells = <0>; 324 325 scmi_dvfs: protocol@13 { 326 reg = <0x13>; 327 #power-domain-cells = <1>; 328 }; 329 }; 330 }; 331 332 clk_virt: interconnect-0 { 333 compatible = "qcom,x1e80100-clk-virt"; 334 #interconnect-cells = <2>; 335 qcom,bcm-voters = <&apps_bcm_voter>; 336 }; 337 338 mc_virt: interconnect-1 { 339 compatible = "qcom,x1e80100-mc-virt"; 340 #interconnect-cells = <2>; 341 qcom,bcm-voters = <&apps_bcm_voter>; 342 }; 343 344 memory@80000000 { 345 device_type = "memory"; 346 /* We expect the bootloader to fill in the size */ 347 reg = <0 0x80000000 0 0>; 348 }; 349 350 pmu { 351 compatible = "arm,armv8-pmuv3"; 352 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 353 }; 354 355 psci { 356 compatible = "arm,psci-1.0"; 357 method = "smc"; 358 359 cpu_pd0: power-domain-cpu0 { 360 #power-domain-cells = <0>; 361 power-domains = <&cluster_pd0>; 362 domain-idle-states = <&cluster_c4>; 363 }; 364 365 cpu_pd1: power-domain-cpu1 { 366 #power-domain-cells = <0>; 367 power-domains = <&cluster_pd0>; 368 domain-idle-states = <&cluster_c4>; 369 }; 370 371 cpu_pd2: power-domain-cpu2 { 372 #power-domain-cells = <0>; 373 power-domains = <&cluster_pd0>; 374 domain-idle-states = <&cluster_c4>; 375 }; 376 377 cpu_pd3: power-domain-cpu3 { 378 #power-domain-cells = <0>; 379 power-domains = <&cluster_pd0>; 380 domain-idle-states = <&cluster_c4>; 381 }; 382 383 cpu_pd4: power-domain-cpu4 { 384 #power-domain-cells = <0>; 385 power-domains = <&cluster_pd1>; 386 domain-idle-states = <&cluster_c4>; 387 }; 388 389 cpu_pd5: power-domain-cpu5 { 390 #power-domain-cells = <0>; 391 power-domains = <&cluster_pd1>; 392 domain-idle-states = <&cluster_c4>; 393 }; 394 395 cpu_pd6: power-domain-cpu6 { 396 #power-domain-cells = <0>; 397 power-domains = <&cluster_pd1>; 398 domain-idle-states = <&cluster_c4>; 399 }; 400 401 cpu_pd7: power-domain-cpu7 { 402 #power-domain-cells = <0>; 403 power-domains = <&cluster_pd1>; 404 domain-idle-states = <&cluster_c4>; 405 }; 406 407 cpu_pd8: power-domain-cpu8 { 408 #power-domain-cells = <0>; 409 power-domains = <&cluster_pd2>; 410 domain-idle-states = <&cluster_c4>; 411 }; 412 413 cpu_pd9: power-domain-cpu9 { 414 #power-domain-cells = <0>; 415 power-domains = <&cluster_pd2>; 416 domain-idle-states = <&cluster_c4>; 417 }; 418 419 cpu_pd10: power-domain-cpu10 { 420 #power-domain-cells = <0>; 421 power-domains = <&cluster_pd2>; 422 domain-idle-states = <&cluster_c4>; 423 }; 424 425 cpu_pd11: power-domain-cpu11 { 426 #power-domain-cells = <0>; 427 power-domains = <&cluster_pd2>; 428 domain-idle-states = <&cluster_c4>; 429 }; 430 431 cluster_pd0: power-domain-cpu-cluster0 { 432 #power-domain-cells = <0>; 433 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 434 power-domains = <&system_pd>; 435 }; 436 437 cluster_pd1: power-domain-cpu-cluster1 { 438 #power-domain-cells = <0>; 439 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 440 power-domains = <&system_pd>; 441 }; 442 443 cluster_pd2: power-domain-cpu-cluster2 { 444 #power-domain-cells = <0>; 445 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 446 power-domains = <&system_pd>; 447 }; 448 449 system_pd: power-domain-system { 450 #power-domain-cells = <0>; 451 /* TODO: system-wide idle states */ 452 }; 453 }; 454 455 reserved-memory { 456 #address-cells = <2>; 457 #size-cells = <2>; 458 ranges; 459 460 gunyah_hyp_mem: gunyah-hyp@80000000 { 461 reg = <0x0 0x80000000 0x0 0x800000>; 462 no-map; 463 }; 464 465 hyp_elf_package_mem: hyp-elf-package@80800000 { 466 reg = <0x0 0x80800000 0x0 0x200000>; 467 no-map; 468 }; 469 470 ncc_mem: ncc@80a00000 { 471 reg = <0x0 0x80a00000 0x0 0x400000>; 472 no-map; 473 }; 474 475 cpucp_log_mem: cpucp-log@80e00000 { 476 reg = <0x0 0x80e00000 0x0 0x40000>; 477 no-map; 478 }; 479 480 cpucp_mem: cpucp@80e40000 { 481 reg = <0x0 0x80e40000 0x0 0x540000>; 482 no-map; 483 }; 484 485 reserved-region@81380000 { 486 reg = <0x0 0x81380000 0x0 0x80000>; 487 no-map; 488 }; 489 490 tags_mem: tags-region@81400000 { 491 reg = <0x0 0x81400000 0x0 0x1a0000>; 492 no-map; 493 }; 494 495 xbl_dtlog_mem: xbl-dtlog@81a00000 { 496 reg = <0x0 0x81a00000 0x0 0x40000>; 497 no-map; 498 }; 499 500 xbl_ramdump_mem: xbl-ramdump@81a40000 { 501 reg = <0x0 0x81a40000 0x0 0x1c0000>; 502 no-map; 503 }; 504 505 aop_image_mem: aop-image@81c00000 { 506 reg = <0x0 0x81c00000 0x0 0x60000>; 507 no-map; 508 }; 509 510 aop_cmd_db_mem: aop-cmd-db@81c60000 { 511 compatible = "qcom,cmd-db"; 512 reg = <0x0 0x81c60000 0x0 0x20000>; 513 no-map; 514 }; 515 516 aop_config_mem: aop-config@81c80000 { 517 reg = <0x0 0x81c80000 0x0 0x20000>; 518 no-map; 519 }; 520 521 tme_crash_dump_mem: tme-crash-dump@81ca0000 { 522 reg = <0x0 0x81ca0000 0x0 0x40000>; 523 no-map; 524 }; 525 526 tme_log_mem: tme-log@81ce0000 { 527 reg = <0x0 0x81ce0000 0x0 0x4000>; 528 no-map; 529 }; 530 531 uefi_log_mem: uefi-log@81ce4000 { 532 reg = <0x0 0x81ce4000 0x0 0x10000>; 533 no-map; 534 }; 535 536 secdata_apss_mem: secdata-apss@81cff000 { 537 reg = <0x0 0x81cff000 0x0 0x1000>; 538 no-map; 539 }; 540 541 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 542 reg = <0x0 0x81e00000 0x0 0x100000>; 543 no-map; 544 }; 545 546 gpu_prr_mem: gpu-prr@81f00000 { 547 reg = <0x0 0x81f00000 0x0 0x10000>; 548 no-map; 549 }; 550 551 tpm_control_mem: tpm-control@81f10000 { 552 reg = <0x0 0x81f10000 0x0 0x10000>; 553 no-map; 554 }; 555 556 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 { 557 reg = <0x0 0x81f20000 0x0 0x10000>; 558 no-map; 559 }; 560 561 pld_pep_mem: pld-pep@81f30000 { 562 reg = <0x0 0x81f30000 0x0 0x6000>; 563 no-map; 564 }; 565 566 pld_gmu_mem: pld-gmu@81f36000 { 567 reg = <0x0 0x81f36000 0x0 0x1000>; 568 no-map; 569 }; 570 571 pld_pdp_mem: pld-pdp@81f37000 { 572 reg = <0x0 0x81f37000 0x0 0x1000>; 573 no-map; 574 }; 575 576 tz_stat_mem: tz-stat@82700000 { 577 reg = <0x0 0x82700000 0x0 0x100000>; 578 no-map; 579 }; 580 581 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 { 582 reg = <0x0 0x82800000 0x0 0xc00000>; 583 no-map; 584 }; 585 586 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 { 587 reg = <0x0 0x84b00000 0x0 0x800000>; 588 no-map; 589 }; 590 591 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 { 592 reg = <0x0 0x85300000 0x0 0x80000>; 593 no-map; 594 }; 595 596 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 { 597 reg = <0x0 0x866c0000 0x0 0x40000>; 598 no-map; 599 }; 600 601 spss_region_mem: spss-region@86700000 { 602 reg = <0x0 0x86700000 0x0 0x400000>; 603 no-map; 604 }; 605 606 adsp_boot_mem: adsp-boot@86b00000 { 607 reg = <0x0 0x86b00000 0x0 0xc00000>; 608 no-map; 609 }; 610 611 video_mem: video@87700000 { 612 reg = <0x0 0x87700000 0x0 0x700000>; 613 no-map; 614 }; 615 616 adspslpi_mem: adspslpi@87e00000 { 617 reg = <0x0 0x87e00000 0x0 0x3a00000>; 618 no-map; 619 }; 620 621 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 { 622 reg = <0x0 0x8b800000 0x0 0x80000>; 623 no-map; 624 }; 625 626 cdsp_mem: cdsp@8b900000 { 627 reg = <0x0 0x8b900000 0x0 0x2000000>; 628 no-map; 629 }; 630 631 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 { 632 reg = <0x0 0x8d900000 0x0 0x80000>; 633 no-map; 634 }; 635 636 gpu_microcode_mem: gpu-microcode@8d9fe000 { 637 reg = <0x0 0x8d9fe000 0x0 0x2000>; 638 no-map; 639 }; 640 641 cvp_mem: cvp@8da00000 { 642 reg = <0x0 0x8da00000 0x0 0x700000>; 643 no-map; 644 }; 645 646 camera_mem: camera@8e100000 { 647 reg = <0x0 0x8e100000 0x0 0x800000>; 648 no-map; 649 }; 650 651 av1_encoder_mem: av1-encoder@8e900000 { 652 reg = <0x0 0x8e900000 0x0 0x700000>; 653 no-map; 654 }; 655 656 reserved-region@8f000000 { 657 reg = <0x0 0x8f000000 0x0 0xa00000>; 658 no-map; 659 }; 660 661 wpss_mem: wpss@8fa00000 { 662 reg = <0x0 0x8fa00000 0x0 0x1900000>; 663 no-map; 664 }; 665 666 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 { 667 reg = <0x0 0x91300000 0x0 0x80000>; 668 no-map; 669 }; 670 671 xbl_sc_mem: xbl-sc@d8000000 { 672 reg = <0x0 0xd8000000 0x0 0x40000>; 673 no-map; 674 }; 675 676 reserved-region@d8040000 { 677 reg = <0x0 0xd8040000 0x0 0xa0000>; 678 no-map; 679 }; 680 681 qtee_mem: qtee@d80e0000 { 682 reg = <0x0 0xd80e0000 0x0 0x520000>; 683 no-map; 684 }; 685 686 ta_mem: ta@d8600000 { 687 reg = <0x0 0xd8600000 0x0 0x8a00000>; 688 no-map; 689 }; 690 691 tags_mem1: tags@e1000000 { 692 reg = <0x0 0xe1000000 0x0 0x26a0000>; 693 no-map; 694 }; 695 696 llcc_lpi_mem: llcc-lpi@ff800000 { 697 reg = <0x0 0xff800000 0x0 0x600000>; 698 no-map; 699 }; 700 701 smem_mem: smem@ffe00000 { 702 compatible = "qcom,smem"; 703 reg = <0x0 0xffe00000 0x0 0x200000>; 704 hwlocks = <&tcsr_mutex 3>; 705 no-map; 706 }; 707 }; 708 709 qup_opp_table_100mhz: opp-table-qup100mhz { 710 compatible = "operating-points-v2"; 711 712 opp-75000000 { 713 opp-hz = /bits/ 64 <75000000>; 714 required-opps = <&rpmhpd_opp_low_svs>; 715 }; 716 717 opp-100000000 { 718 opp-hz = /bits/ 64 <100000000>; 719 required-opps = <&rpmhpd_opp_svs>; 720 }; 721 }; 722 723 qup_opp_table_120mhz: opp-table-qup120mhz { 724 compatible = "operating-points-v2"; 725 726 opp-75000000 { 727 opp-hz = /bits/ 64 <75000000>; 728 required-opps = <&rpmhpd_opp_low_svs>; 729 }; 730 731 opp-120000000 { 732 opp-hz = /bits/ 64 <120000000>; 733 required-opps = <&rpmhpd_opp_svs>; 734 }; 735 }; 736 737 smp2p-adsp { 738 compatible = "qcom,smp2p"; 739 740 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 741 IPCC_MPROC_SIGNAL_SMP2P 742 IRQ_TYPE_EDGE_RISING>; 743 744 mboxes = <&ipcc IPCC_CLIENT_LPASS 745 IPCC_MPROC_SIGNAL_SMP2P>; 746 747 qcom,smem = <443>, <429>; 748 qcom,local-pid = <0>; 749 qcom,remote-pid = <2>; 750 751 smp2p_adsp_out: master-kernel { 752 qcom,entry-name = "master-kernel"; 753 #qcom,smem-state-cells = <1>; 754 }; 755 756 smp2p_adsp_in: slave-kernel { 757 qcom,entry-name = "slave-kernel"; 758 interrupt-controller; 759 #interrupt-cells = <2>; 760 }; 761 }; 762 763 smp2p-cdsp { 764 compatible = "qcom,smp2p"; 765 766 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 767 IPCC_MPROC_SIGNAL_SMP2P 768 IRQ_TYPE_EDGE_RISING>; 769 770 mboxes = <&ipcc IPCC_CLIENT_CDSP 771 IPCC_MPROC_SIGNAL_SMP2P>; 772 773 qcom,smem = <94>, <432>; 774 qcom,local-pid = <0>; 775 qcom,remote-pid = <5>; 776 777 smp2p_cdsp_out: master-kernel { 778 qcom,entry-name = "master-kernel"; 779 #qcom,smem-state-cells = <1>; 780 }; 781 782 smp2p_cdsp_in: slave-kernel { 783 qcom,entry-name = "slave-kernel"; 784 interrupt-controller; 785 #interrupt-cells = <2>; 786 }; 787 }; 788 789 soc: soc@0 { 790 compatible = "simple-bus"; 791 792 #address-cells = <2>; 793 #size-cells = <2>; 794 dma-ranges = <0 0 0 0 0x100 0>; 795 ranges = <0 0 0 0 0x100 0>; 796 797 gcc: clock-controller@100000 { 798 compatible = "qcom,x1e80100-gcc"; 799 reg = <0 0x00100000 0 0x200000>; 800 801 clocks = <&bi_tcxo_div2>, 802 <&sleep_clk>, 803 <&pcie3_phy>, 804 <&pcie4_phy>, 805 <&pcie5_phy>, 806 <&pcie6a_phy>, 807 <0>, 808 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 809 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 810 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 811 <0>, 812 <0>, 813 <0>, 814 <0>, 815 <0>, 816 <0>, 817 <0>, 818 <0>, 819 <0>, 820 <0>, 821 <0>, 822 <0>, 823 <0>, 824 <0>, 825 <0>, 826 <0>, 827 <0>, 828 <0>, 829 <0>, 830 <0>, 831 <0>, 832 <0>, 833 <0>, 834 <0>, 835 <0>, 836 <0>, 837 <0>, 838 <0>, 839 <0>, 840 <0>; 841 842 power-domains = <&rpmhpd RPMHPD_CX>; 843 #clock-cells = <1>; 844 #reset-cells = <1>; 845 #power-domain-cells = <1>; 846 }; 847 848 ipcc: mailbox@408000 { 849 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; 850 reg = <0 0x00408000 0 0x1000>; 851 852 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 853 interrupt-controller; 854 #interrupt-cells = <3>; 855 856 #mbox-cells = <2>; 857 }; 858 859 gpi_dma2: dma-controller@800000 { 860 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 861 reg = <0 0x00800000 0 0x60000>; 862 863 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 875 876 dma-channels = <12>; 877 dma-channel-mask = <0x3e>; 878 #dma-cells = <3>; 879 880 iommus = <&apps_smmu 0x436 0x0>; 881 882 status = "disabled"; 883 }; 884 885 qupv3_2: geniqup@8c0000 { 886 compatible = "qcom,geni-se-qup"; 887 reg = <0 0x008c0000 0 0x2000>; 888 889 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 890 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 891 clock-names = "m-ahb", 892 "s-ahb"; 893 894 iommus = <&apps_smmu 0x423 0x0>; 895 896 #address-cells = <2>; 897 #size-cells = <2>; 898 ranges; 899 900 status = "disabled"; 901 902 i2c16: i2c@880000 { 903 compatible = "qcom,geni-i2c"; 904 reg = <0 0x00880000 0 0x4000>; 905 906 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 907 908 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 909 clock-names = "se"; 910 911 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 912 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 913 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 914 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 915 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 916 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 917 interconnect-names = "qup-core", 918 "qup-config", 919 "qup-memory"; 920 921 power-domains = <&rpmhpd RPMHPD_CX>; 922 required-opps = <&rpmhpd_opp_low_svs>; 923 924 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 925 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 926 dma-names = "tx", 927 "rx"; 928 929 pinctrl-0 = <&qup_i2c16_data_clk>; 930 pinctrl-names = "default"; 931 932 #address-cells = <1>; 933 #size-cells = <0>; 934 935 status = "disabled"; 936 }; 937 938 spi16: spi@880000 { 939 compatible = "qcom,geni-spi"; 940 reg = <0 0x00880000 0 0x4000>; 941 942 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 943 944 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 945 clock-names = "se"; 946 947 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 948 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 949 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 950 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 951 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 952 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 953 interconnect-names = "qup-core", 954 "qup-config", 955 "qup-memory"; 956 957 power-domains = <&rpmhpd RPMHPD_CX>; 958 operating-points-v2 = <&qup_opp_table_120mhz>; 959 960 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 961 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 962 dma-names = "tx", 963 "rx"; 964 965 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 966 pinctrl-names = "default"; 967 968 #address-cells = <1>; 969 #size-cells = <0>; 970 971 status = "disabled"; 972 }; 973 974 i2c17: i2c@884000 { 975 compatible = "qcom,geni-i2c"; 976 reg = <0 0x00884000 0 0x4000>; 977 978 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 979 980 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 981 clock-names = "se"; 982 983 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 984 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 985 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 986 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 987 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 988 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 989 interconnect-names = "qup-core", 990 "qup-config", 991 "qup-memory"; 992 993 power-domains = <&rpmhpd RPMHPD_CX>; 994 required-opps = <&rpmhpd_opp_low_svs>; 995 996 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 997 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 998 dma-names = "tx", 999 "rx"; 1000 1001 pinctrl-0 = <&qup_i2c17_data_clk>; 1002 pinctrl-names = "default"; 1003 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 1007 status = "disabled"; 1008 }; 1009 1010 spi17: spi@884000 { 1011 compatible = "qcom,geni-spi"; 1012 reg = <0 0x00884000 0 0x4000>; 1013 1014 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 1015 1016 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1017 clock-names = "se"; 1018 1019 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1020 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1021 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1022 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1023 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1024 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1025 interconnect-names = "qup-core", 1026 "qup-config", 1027 "qup-memory"; 1028 1029 power-domains = <&rpmhpd RPMHPD_CX>; 1030 operating-points-v2 = <&qup_opp_table_120mhz>; 1031 1032 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1033 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1034 dma-names = "tx", 1035 "rx"; 1036 1037 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 1038 pinctrl-names = "default"; 1039 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 1043 status = "disabled"; 1044 }; 1045 1046 i2c18: i2c@888000 { 1047 compatible = "qcom,geni-i2c"; 1048 reg = <0 0x00888000 0 0x4000>; 1049 1050 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1051 1052 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1053 clock-names = "se"; 1054 1055 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1056 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1057 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1058 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1059 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1060 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1061 interconnect-names = "qup-core", 1062 "qup-config", 1063 "qup-memory"; 1064 1065 power-domains = <&rpmhpd RPMHPD_CX>; 1066 required-opps = <&rpmhpd_opp_low_svs>; 1067 1068 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1069 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1070 dma-names = "tx", 1071 "rx"; 1072 1073 pinctrl-0 = <&qup_i2c18_data_clk>; 1074 pinctrl-names = "default"; 1075 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 1079 status = "disabled"; 1080 }; 1081 1082 spi18: spi@888000 { 1083 compatible = "qcom,geni-spi"; 1084 reg = <0 0x00888000 0 0x4000>; 1085 1086 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1087 1088 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1089 clock-names = "se"; 1090 1091 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1092 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1093 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1094 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1095 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1096 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1097 interconnect-names = "qup-core", 1098 "qup-config", 1099 "qup-memory"; 1100 1101 power-domains = <&rpmhpd RPMHPD_CX>; 1102 operating-points-v2 = <&qup_opp_table_100mhz>; 1103 1104 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1105 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1106 dma-names = "tx", 1107 "rx"; 1108 1109 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1110 pinctrl-names = "default"; 1111 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 1115 status = "disabled"; 1116 }; 1117 1118 i2c19: i2c@88c000 { 1119 compatible = "qcom,geni-i2c"; 1120 reg = <0 0x0088c000 0 0x4000>; 1121 1122 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1123 1124 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1125 clock-names = "se"; 1126 1127 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1128 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1129 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1130 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1131 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1132 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1133 interconnect-names = "qup-core", 1134 "qup-config", 1135 "qup-memory"; 1136 1137 power-domains = <&rpmhpd RPMHPD_CX>; 1138 required-opps = <&rpmhpd_opp_low_svs>; 1139 1140 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1141 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1142 dma-names = "tx", 1143 "rx"; 1144 1145 pinctrl-0 = <&qup_i2c19_data_clk>; 1146 pinctrl-names = "default"; 1147 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 1151 status = "disabled"; 1152 }; 1153 1154 spi19: spi@88c000 { 1155 compatible = "qcom,geni-spi"; 1156 reg = <0 0x0088c000 0 0x4000>; 1157 1158 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1159 1160 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1161 clock-names = "se"; 1162 1163 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1164 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1165 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1166 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1167 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1168 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1169 interconnect-names = "qup-core", 1170 "qup-config", 1171 "qup-memory"; 1172 1173 power-domains = <&rpmhpd RPMHPD_CX>; 1174 operating-points-v2 = <&qup_opp_table_100mhz>; 1175 1176 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1177 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1178 dma-names = "tx", 1179 "rx"; 1180 1181 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1182 pinctrl-names = "default"; 1183 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 1187 status = "disabled"; 1188 }; 1189 1190 i2c20: i2c@890000 { 1191 compatible = "qcom,geni-i2c"; 1192 reg = <0 0x00890000 0 0x4000>; 1193 1194 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1195 1196 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1197 clock-names = "se"; 1198 1199 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1200 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1201 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1202 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1203 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1204 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1205 interconnect-names = "qup-core", 1206 "qup-config", 1207 "qup-memory"; 1208 1209 power-domains = <&rpmhpd RPMHPD_CX>; 1210 required-opps = <&rpmhpd_opp_low_svs>; 1211 1212 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1213 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1214 dma-names = "tx", 1215 "rx"; 1216 1217 pinctrl-0 = <&qup_i2c20_data_clk>; 1218 pinctrl-names = "default"; 1219 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 1223 status = "disabled"; 1224 }; 1225 1226 spi20: spi@890000 { 1227 compatible = "qcom,geni-spi"; 1228 reg = <0 0x00890000 0 0x4000>; 1229 1230 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1231 1232 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1233 clock-names = "se"; 1234 1235 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1236 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1237 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1238 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1239 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1240 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1241 interconnect-names = "qup-core", 1242 "qup-config", 1243 "qup-memory"; 1244 1245 power-domains = <&rpmhpd RPMHPD_CX>; 1246 operating-points-v2 = <&qup_opp_table_100mhz>; 1247 1248 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1249 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1250 dma-names = "tx", 1251 "rx"; 1252 1253 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1254 pinctrl-names = "default"; 1255 1256 #address-cells = <1>; 1257 #size-cells = <0>; 1258 1259 status = "disabled"; 1260 }; 1261 1262 i2c21: i2c@894000 { 1263 compatible = "qcom,geni-i2c"; 1264 reg = <0 0x00894000 0 0x4000>; 1265 1266 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1267 1268 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1269 clock-names = "se"; 1270 1271 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1272 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1273 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1274 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1275 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1276 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1277 interconnect-names = "qup-core", 1278 "qup-config", 1279 "qup-memory"; 1280 1281 power-domains = <&rpmhpd RPMHPD_CX>; 1282 required-opps = <&rpmhpd_opp_low_svs>; 1283 1284 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1285 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1286 dma-names = "tx", 1287 "rx"; 1288 1289 pinctrl-0 = <&qup_i2c21_data_clk>; 1290 pinctrl-names = "default"; 1291 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 1295 status = "disabled"; 1296 }; 1297 1298 spi21: spi@894000 { 1299 compatible = "qcom,geni-spi"; 1300 reg = <0 0x00894000 0 0x4000>; 1301 1302 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1303 1304 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1305 clock-names = "se"; 1306 1307 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1308 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1309 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1310 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1311 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1312 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1313 interconnect-names = "qup-core", 1314 "qup-config", 1315 "qup-memory"; 1316 1317 power-domains = <&rpmhpd RPMHPD_CX>; 1318 operating-points-v2 = <&qup_opp_table_100mhz>; 1319 1320 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1321 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1322 dma-names = "tx", 1323 "rx"; 1324 1325 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1326 pinctrl-names = "default"; 1327 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 1331 status = "disabled"; 1332 }; 1333 1334 uart21: serial@894000 { 1335 compatible = "qcom,geni-uart"; 1336 reg = <0 0x00894000 0 0x4000>; 1337 1338 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1339 1340 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1341 clock-names = "se"; 1342 1343 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1344 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1345 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1346 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 1347 interconnect-names = "qup-core", 1348 "qup-config"; 1349 1350 power-domains = <&rpmhpd RPMHPD_CX>; 1351 operating-points-v2 = <&qup_opp_table_100mhz>; 1352 1353 pinctrl-0 = <&qup_uart21_default>; 1354 pinctrl-names = "default"; 1355 1356 status = "disabled"; 1357 }; 1358 1359 i2c22: i2c@898000 { 1360 compatible = "qcom,geni-i2c"; 1361 reg = <0 0x00898000 0 0x4000>; 1362 1363 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1364 1365 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1366 clock-names = "se"; 1367 1368 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1369 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1370 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1371 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1372 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1373 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1374 interconnect-names = "qup-core", 1375 "qup-config", 1376 "qup-memory"; 1377 1378 power-domains = <&rpmhpd RPMHPD_CX>; 1379 required-opps = <&rpmhpd_opp_low_svs>; 1380 1381 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1382 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1383 dma-names = "tx", 1384 "rx"; 1385 1386 pinctrl-0 = <&qup_i2c22_data_clk>; 1387 pinctrl-names = "default"; 1388 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 1392 status = "disabled"; 1393 }; 1394 1395 spi22: spi@898000 { 1396 compatible = "qcom,geni-spi"; 1397 reg = <0 0x00898000 0 0x4000>; 1398 1399 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1400 1401 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1402 clock-names = "se"; 1403 1404 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1405 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1406 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1407 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1408 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1409 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1410 interconnect-names = "qup-core", 1411 "qup-config", 1412 "qup-memory"; 1413 1414 power-domains = <&rpmhpd RPMHPD_CX>; 1415 operating-points-v2 = <&qup_opp_table_100mhz>; 1416 1417 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1418 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1419 dma-names = "tx", 1420 "rx"; 1421 1422 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1423 pinctrl-names = "default"; 1424 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 1428 status = "disabled"; 1429 }; 1430 1431 i2c23: i2c@89c000 { 1432 compatible = "qcom,geni-i2c"; 1433 reg = <0 0x0089c000 0 0x4000>; 1434 1435 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1436 1437 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1438 clock-names = "se"; 1439 1440 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1441 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1442 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1443 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1444 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1445 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1446 interconnect-names = "qup-core", 1447 "qup-config", 1448 "qup-memory"; 1449 1450 power-domains = <&rpmhpd RPMHPD_CX>; 1451 required-opps = <&rpmhpd_opp_low_svs>; 1452 1453 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1454 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1455 dma-names = "tx", 1456 "rx"; 1457 1458 pinctrl-0 = <&qup_i2c23_data_clk>; 1459 pinctrl-names = "default"; 1460 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 1464 status = "disabled"; 1465 }; 1466 1467 spi23: spi@89c000 { 1468 compatible = "qcom,geni-spi"; 1469 reg = <0 0x0089c000 0 0x4000>; 1470 1471 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1472 1473 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1474 clock-names = "se"; 1475 1476 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1477 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1478 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1479 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1480 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1481 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1482 interconnect-names = "qup-core", 1483 "qup-config", 1484 "qup-memory"; 1485 1486 power-domains = <&rpmhpd RPMHPD_CX>; 1487 operating-points-v2 = <&qup_opp_table_100mhz>; 1488 1489 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1490 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1491 dma-names = "tx", 1492 "rx"; 1493 1494 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1495 pinctrl-names = "default"; 1496 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 1500 status = "disabled"; 1501 }; 1502 }; 1503 1504 gpi_dma1: dma-controller@a00000 { 1505 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1506 reg = <0 0x00a00000 0 0x60000>; 1507 1508 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 1520 1521 dma-channels = <12>; 1522 dma-channel-mask = <0x3e>; 1523 #dma-cells = <3>; 1524 1525 iommus = <&apps_smmu 0x136 0x0>; 1526 1527 status = "disabled"; 1528 }; 1529 1530 qupv3_1: geniqup@ac0000 { 1531 compatible = "qcom,geni-se-qup"; 1532 reg = <0 0x00ac0000 0 0x2000>; 1533 1534 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1535 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1536 clock-names = "m-ahb", 1537 "s-ahb"; 1538 1539 iommus = <&apps_smmu 0x123 0x0>; 1540 1541 #address-cells = <2>; 1542 #size-cells = <2>; 1543 ranges; 1544 1545 status = "disabled"; 1546 1547 i2c8: i2c@a80000 { 1548 compatible = "qcom,geni-i2c"; 1549 reg = <0 0x00a80000 0 0x4000>; 1550 1551 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1552 1553 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1554 clock-names = "se"; 1555 1556 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1557 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1558 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1559 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1560 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1561 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1562 interconnect-names = "qup-core", 1563 "qup-config", 1564 "qup-memory"; 1565 1566 power-domains = <&rpmhpd RPMHPD_CX>; 1567 required-opps = <&rpmhpd_opp_low_svs>; 1568 1569 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1570 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1571 dma-names = "tx", 1572 "rx"; 1573 1574 pinctrl-0 = <&qup_i2c8_data_clk>; 1575 pinctrl-names = "default"; 1576 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 1580 status = "disabled"; 1581 }; 1582 1583 spi8: spi@a80000 { 1584 compatible = "qcom,geni-spi"; 1585 reg = <0 0x00a80000 0 0x4000>; 1586 1587 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1588 1589 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1590 clock-names = "se"; 1591 1592 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1593 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1594 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1595 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1596 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1597 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1598 interconnect-names = "qup-core", 1599 "qup-config", 1600 "qup-memory"; 1601 1602 power-domains = <&rpmhpd RPMHPD_CX>; 1603 operating-points-v2 = <&qup_opp_table_120mhz>; 1604 1605 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1606 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1607 dma-names = "tx", 1608 "rx"; 1609 1610 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1611 pinctrl-names = "default"; 1612 1613 #address-cells = <1>; 1614 #size-cells = <0>; 1615 1616 status = "disabled"; 1617 }; 1618 1619 i2c9: i2c@a84000 { 1620 compatible = "qcom,geni-i2c"; 1621 reg = <0 0x00a84000 0 0x4000>; 1622 1623 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1624 1625 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1626 clock-names = "se"; 1627 1628 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1629 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1630 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1631 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1632 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1633 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1634 interconnect-names = "qup-core", 1635 "qup-config", 1636 "qup-memory"; 1637 1638 power-domains = <&rpmhpd RPMHPD_CX>; 1639 required-opps = <&rpmhpd_opp_low_svs>; 1640 1641 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1642 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1643 dma-names = "tx", 1644 "rx"; 1645 1646 pinctrl-0 = <&qup_i2c9_data_clk>; 1647 pinctrl-names = "default"; 1648 1649 #address-cells = <1>; 1650 #size-cells = <0>; 1651 1652 status = "disabled"; 1653 }; 1654 1655 spi9: spi@a84000 { 1656 compatible = "qcom,geni-spi"; 1657 reg = <0 0x00a84000 0 0x4000>; 1658 1659 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1660 1661 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1662 clock-names = "se"; 1663 1664 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1665 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1666 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1667 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1668 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1669 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1670 interconnect-names = "qup-core", 1671 "qup-config", 1672 "qup-memory"; 1673 1674 power-domains = <&rpmhpd RPMHPD_CX>; 1675 operating-points-v2 = <&qup_opp_table_120mhz>; 1676 1677 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1678 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1679 dma-names = "tx", 1680 "rx"; 1681 1682 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1683 pinctrl-names = "default"; 1684 1685 #address-cells = <1>; 1686 #size-cells = <0>; 1687 1688 status = "disabled"; 1689 }; 1690 1691 i2c10: i2c@a88000 { 1692 compatible = "qcom,geni-i2c"; 1693 reg = <0 0x00a88000 0 0x4000>; 1694 1695 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1696 1697 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1698 clock-names = "se"; 1699 1700 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1701 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1702 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1703 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1704 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1705 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1706 interconnect-names = "qup-core", 1707 "qup-config", 1708 "qup-memory"; 1709 1710 power-domains = <&rpmhpd RPMHPD_CX>; 1711 required-opps = <&rpmhpd_opp_low_svs>; 1712 1713 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1714 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1715 dma-names = "tx", 1716 "rx"; 1717 1718 pinctrl-0 = <&qup_i2c10_data_clk>; 1719 pinctrl-names = "default"; 1720 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 1724 status = "disabled"; 1725 }; 1726 1727 spi10: spi@a88000 { 1728 compatible = "qcom,geni-spi"; 1729 reg = <0 0x00a88000 0 0x4000>; 1730 1731 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1732 1733 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1734 clock-names = "se"; 1735 1736 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1737 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1738 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1739 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1740 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1741 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1742 interconnect-names = "qup-core", 1743 "qup-config", 1744 "qup-memory"; 1745 1746 power-domains = <&rpmhpd RPMHPD_CX>; 1747 operating-points-v2 = <&qup_opp_table_100mhz>; 1748 1749 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1750 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1751 dma-names = "tx", 1752 "rx"; 1753 1754 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1755 pinctrl-names = "default"; 1756 1757 #address-cells = <1>; 1758 #size-cells = <0>; 1759 1760 status = "disabled"; 1761 }; 1762 1763 i2c11: i2c@a8c000 { 1764 compatible = "qcom,geni-i2c"; 1765 reg = <0 0x00a8c000 0 0x4000>; 1766 1767 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1768 1769 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1770 clock-names = "se"; 1771 1772 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1773 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1774 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1775 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1776 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1777 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1778 interconnect-names = "qup-core", 1779 "qup-config", 1780 "qup-memory"; 1781 1782 power-domains = <&rpmhpd RPMHPD_CX>; 1783 required-opps = <&rpmhpd_opp_low_svs>; 1784 1785 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1786 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1787 dma-names = "tx", 1788 "rx"; 1789 1790 pinctrl-0 = <&qup_i2c11_data_clk>; 1791 pinctrl-names = "default"; 1792 1793 #address-cells = <1>; 1794 #size-cells = <0>; 1795 1796 status = "disabled"; 1797 }; 1798 1799 spi11: spi@a8c000 { 1800 compatible = "qcom,geni-spi"; 1801 reg = <0 0x00a8c000 0 0x4000>; 1802 1803 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1804 1805 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1806 clock-names = "se"; 1807 1808 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1809 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1810 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1811 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1812 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1813 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1814 interconnect-names = "qup-core", 1815 "qup-config", 1816 "qup-memory"; 1817 1818 power-domains = <&rpmhpd RPMHPD_CX>; 1819 operating-points-v2 = <&qup_opp_table_100mhz>; 1820 1821 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1822 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1823 dma-names = "tx", 1824 "rx"; 1825 1826 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1827 pinctrl-names = "default"; 1828 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 1832 status = "disabled"; 1833 }; 1834 1835 i2c12: i2c@a90000 { 1836 compatible = "qcom,geni-i2c"; 1837 reg = <0 0x00a90000 0 0x4000>; 1838 1839 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1840 1841 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1842 clock-names = "se"; 1843 1844 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1845 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1846 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1847 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1848 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1849 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1850 interconnect-names = "qup-core", 1851 "qup-config", 1852 "qup-memory"; 1853 1854 power-domains = <&rpmhpd RPMHPD_CX>; 1855 required-opps = <&rpmhpd_opp_low_svs>; 1856 1857 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1858 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1859 dma-names = "tx", 1860 "rx"; 1861 1862 pinctrl-0 = <&qup_i2c12_data_clk>; 1863 pinctrl-names = "default"; 1864 1865 #address-cells = <1>; 1866 #size-cells = <0>; 1867 1868 status = "disabled"; 1869 }; 1870 1871 spi12: spi@a90000 { 1872 compatible = "qcom,geni-spi"; 1873 reg = <0 0x00a90000 0 0x4000>; 1874 1875 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1876 1877 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1878 clock-names = "se"; 1879 1880 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1881 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1882 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1883 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1884 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1885 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1886 interconnect-names = "qup-core", 1887 "qup-config", 1888 "qup-memory"; 1889 1890 power-domains = <&rpmhpd RPMHPD_CX>; 1891 operating-points-v2 = <&qup_opp_table_100mhz>; 1892 1893 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1894 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1895 dma-names = "tx", 1896 "rx"; 1897 1898 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1899 pinctrl-names = "default"; 1900 1901 #address-cells = <1>; 1902 #size-cells = <0>; 1903 1904 status = "disabled"; 1905 }; 1906 1907 i2c13: i2c@a94000 { 1908 compatible = "qcom,geni-i2c"; 1909 reg = <0 0x00a94000 0 0x4000>; 1910 1911 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1912 1913 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1914 clock-names = "se"; 1915 1916 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1917 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1918 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1919 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1920 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1921 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1922 interconnect-names = "qup-core", 1923 "qup-config", 1924 "qup-memory"; 1925 1926 power-domains = <&rpmhpd RPMHPD_CX>; 1927 required-opps = <&rpmhpd_opp_low_svs>; 1928 1929 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1930 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1931 dma-names = "tx", 1932 "rx"; 1933 1934 pinctrl-0 = <&qup_i2c13_data_clk>; 1935 pinctrl-names = "default"; 1936 1937 #address-cells = <1>; 1938 #size-cells = <0>; 1939 1940 status = "disabled"; 1941 }; 1942 1943 spi13: spi@a94000 { 1944 compatible = "qcom,geni-spi"; 1945 reg = <0 0x00a94000 0 0x4000>; 1946 1947 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1948 1949 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1950 clock-names = "se"; 1951 1952 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1953 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1954 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1955 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1956 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1957 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1958 interconnect-names = "qup-core", 1959 "qup-config", 1960 "qup-memory"; 1961 1962 power-domains = <&rpmhpd RPMHPD_CX>; 1963 operating-points-v2 = <&qup_opp_table_100mhz>; 1964 1965 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1966 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1967 dma-names = "tx", 1968 "rx"; 1969 1970 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1971 pinctrl-names = "default"; 1972 1973 #address-cells = <1>; 1974 #size-cells = <0>; 1975 1976 status = "disabled"; 1977 }; 1978 1979 i2c14: i2c@a98000 { 1980 compatible = "qcom,geni-i2c"; 1981 reg = <0 0x00a98000 0 0x4000>; 1982 1983 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1984 1985 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1986 clock-names = "se"; 1987 1988 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1989 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1990 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1991 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1992 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1993 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1994 interconnect-names = "qup-core", 1995 "qup-config", 1996 "qup-memory"; 1997 1998 power-domains = <&rpmhpd RPMHPD_CX>; 1999 required-opps = <&rpmhpd_opp_low_svs>; 2000 2001 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2002 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2003 dma-names = "tx", 2004 "rx"; 2005 2006 pinctrl-0 = <&qup_i2c14_data_clk>; 2007 pinctrl-names = "default"; 2008 2009 #address-cells = <1>; 2010 #size-cells = <0>; 2011 2012 status = "disabled"; 2013 }; 2014 2015 spi14: spi@a98000 { 2016 compatible = "qcom,geni-spi"; 2017 reg = <0 0x00a98000 0 0x4000>; 2018 2019 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 2020 2021 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2022 clock-names = "se"; 2023 2024 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2025 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2026 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2027 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2028 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2029 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2030 interconnect-names = "qup-core", 2031 "qup-config", 2032 "qup-memory"; 2033 2034 power-domains = <&rpmhpd RPMHPD_CX>; 2035 operating-points-v2 = <&qup_opp_table_100mhz>; 2036 2037 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2038 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2039 dma-names = "tx", 2040 "rx"; 2041 2042 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2043 pinctrl-names = "default"; 2044 2045 #address-cells = <1>; 2046 #size-cells = <0>; 2047 2048 status = "disabled"; 2049 }; 2050 2051 uart14: serial@a98000 { 2052 compatible = "qcom,geni-uart"; 2053 reg = <0 0x00a98000 0 0x4000>; 2054 2055 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 2056 2057 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2058 clock-names = "se"; 2059 2060 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2061 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2062 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2063 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2064 interconnect-names = "qup-core", 2065 "qup-config"; 2066 2067 power-domains = <&rpmhpd RPMHPD_CX>; 2068 operating-points-v2 = <&qup_opp_table_100mhz>; 2069 2070 pinctrl-0 = <&qup_uart14_default>; 2071 pinctrl-names = "default"; 2072 2073 status = "disabled"; 2074 }; 2075 2076 i2c15: i2c@a9c000 { 2077 compatible = "qcom,geni-i2c"; 2078 reg = <0 0x00a9c000 0 0x4000>; 2079 2080 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 2081 2082 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2083 clock-names = "se"; 2084 2085 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2086 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2087 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2088 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2089 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2090 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2091 interconnect-names = "qup-core", 2092 "qup-config", 2093 "qup-memory"; 2094 2095 power-domains = <&rpmhpd RPMHPD_CX>; 2096 required-opps = <&rpmhpd_opp_low_svs>; 2097 2098 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2099 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2100 dma-names = "tx", 2101 "rx"; 2102 2103 pinctrl-0 = <&qup_i2c15_data_clk>; 2104 pinctrl-names = "default"; 2105 2106 #address-cells = <1>; 2107 #size-cells = <0>; 2108 2109 status = "disabled"; 2110 }; 2111 2112 spi15: spi@a9c000 { 2113 compatible = "qcom,geni-spi"; 2114 reg = <0 0x00a9c000 0 0x4000>; 2115 2116 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 2117 2118 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2119 clock-names = "se"; 2120 2121 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2122 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2123 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2124 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2125 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2126 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2127 interconnect-names = "qup-core", 2128 "qup-config", 2129 "qup-memory"; 2130 2131 power-domains = <&rpmhpd RPMHPD_CX>; 2132 operating-points-v2 = <&qup_opp_table_100mhz>; 2133 2134 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2135 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2136 dma-names = "tx", 2137 "rx"; 2138 2139 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2140 pinctrl-names = "default"; 2141 2142 #address-cells = <1>; 2143 #size-cells = <0>; 2144 2145 status = "disabled"; 2146 }; 2147 }; 2148 2149 gpi_dma0: dma-controller@b00000 { 2150 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 2151 reg = <0 0x00b00000 0 0x60000>; 2152 2153 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 2158 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 2159 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 2160 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 2162 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 2163 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 2165 2166 dma-channels = <12>; 2167 dma-channel-mask = <0x3e>; 2168 #dma-cells = <3>; 2169 2170 iommus = <&apps_smmu 0x456 0x0>; 2171 2172 status = "disabled"; 2173 }; 2174 2175 qupv3_0: geniqup@bc0000 { 2176 compatible = "qcom,geni-se-qup"; 2177 reg = <0 0x00bc0000 0 0x2000>; 2178 2179 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 2180 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 2181 clock-names = "m-ahb", 2182 "s-ahb"; 2183 2184 iommus = <&apps_smmu 0x443 0x0>; 2185 #address-cells = <2>; 2186 #size-cells = <2>; 2187 ranges; 2188 2189 status = "disabled"; 2190 2191 i2c0: i2c@b80000 { 2192 compatible = "qcom,geni-i2c"; 2193 reg = <0 0x00b80000 0 0x4000>; 2194 2195 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2196 2197 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2198 clock-names = "se"; 2199 2200 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2201 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2202 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2203 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2204 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2205 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2206 interconnect-names = "qup-core", 2207 "qup-config", 2208 "qup-memory"; 2209 2210 power-domains = <&rpmhpd RPMHPD_CX>; 2211 required-opps = <&rpmhpd_opp_low_svs>; 2212 2213 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 2214 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 2215 dma-names = "tx", 2216 "rx"; 2217 2218 pinctrl-0 = <&qup_i2c0_data_clk>; 2219 pinctrl-names = "default"; 2220 2221 #address-cells = <1>; 2222 #size-cells = <0>; 2223 2224 status = "disabled"; 2225 }; 2226 2227 spi0: spi@b80000 { 2228 compatible = "qcom,geni-spi"; 2229 reg = <0 0x00b80000 0 0x4000>; 2230 2231 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2232 2233 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2234 clock-names = "se"; 2235 2236 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2237 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2238 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2239 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2240 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2241 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2242 interconnect-names = "qup-core", 2243 "qup-config", 2244 "qup-memory"; 2245 2246 power-domains = <&rpmhpd RPMHPD_CX>; 2247 operating-points-v2 = <&qup_opp_table_120mhz>; 2248 2249 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 2250 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 2251 dma-names = "tx", 2252 "rx"; 2253 2254 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 2255 pinctrl-names = "default"; 2256 2257 #address-cells = <1>; 2258 #size-cells = <0>; 2259 2260 status = "disabled"; 2261 }; 2262 2263 i2c1: i2c@b84000 { 2264 compatible = "qcom,geni-i2c"; 2265 reg = <0 0x00b84000 0 0x4000>; 2266 2267 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2268 2269 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2270 clock-names = "se"; 2271 2272 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2273 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2274 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2275 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2276 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2277 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2278 interconnect-names = "qup-core", 2279 "qup-config", 2280 "qup-memory"; 2281 2282 power-domains = <&rpmhpd RPMHPD_CX>; 2283 required-opps = <&rpmhpd_opp_low_svs>; 2284 2285 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 2286 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 2287 dma-names = "tx", 2288 "rx"; 2289 2290 pinctrl-0 = <&qup_i2c1_data_clk>; 2291 pinctrl-names = "default"; 2292 2293 #address-cells = <1>; 2294 #size-cells = <0>; 2295 2296 status = "disabled"; 2297 }; 2298 2299 spi1: spi@b84000 { 2300 compatible = "qcom,geni-spi"; 2301 reg = <0 0x00b84000 0 0x4000>; 2302 2303 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2304 2305 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2306 clock-names = "se"; 2307 2308 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2309 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2310 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2311 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2312 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2313 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2314 interconnect-names = "qup-core", 2315 "qup-config", 2316 "qup-memory"; 2317 2318 power-domains = <&rpmhpd RPMHPD_CX>; 2319 operating-points-v2 = <&qup_opp_table_120mhz>; 2320 2321 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 2322 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 2323 dma-names = "tx", 2324 "rx"; 2325 2326 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 2327 pinctrl-names = "default"; 2328 2329 #address-cells = <1>; 2330 #size-cells = <0>; 2331 2332 status = "disabled"; 2333 }; 2334 2335 i2c2: i2c@b88000 { 2336 compatible = "qcom,geni-i2c"; 2337 reg = <0 0x00b88000 0 0x4000>; 2338 2339 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2340 2341 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2342 clock-names = "se"; 2343 2344 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2345 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2346 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2347 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2348 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2349 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2350 interconnect-names = "qup-core", 2351 "qup-config", 2352 "qup-memory"; 2353 2354 power-domains = <&rpmhpd RPMHPD_CX>; 2355 required-opps = <&rpmhpd_opp_low_svs>; 2356 2357 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 2358 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 2359 dma-names = "tx", 2360 "rx"; 2361 2362 pinctrl-0 = <&qup_i2c2_data_clk>; 2363 pinctrl-names = "default"; 2364 2365 #address-cells = <1>; 2366 #size-cells = <0>; 2367 2368 status = "disabled"; 2369 }; 2370 2371 uart2: serial@b88000 { 2372 compatible = "qcom,geni-uart"; 2373 reg = <0 0x00b88000 0 0x4000>; 2374 2375 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2376 2377 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2378 clock-names = "se"; 2379 2380 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2381 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2382 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2383 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2384 interconnect-names = "qup-core", 2385 "qup-config"; 2386 2387 power-domains = <&rpmhpd RPMHPD_CX>; 2388 operating-points-v2 = <&qup_opp_table_100mhz>; 2389 2390 pinctrl-0 = <&qup_uart2_default>; 2391 pinctrl-names = "default"; 2392 2393 status = "disabled"; 2394 }; 2395 2396 spi2: spi@b88000 { 2397 compatible = "qcom,geni-spi"; 2398 reg = <0 0x00b88000 0 0x4000>; 2399 2400 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2401 2402 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2403 clock-names = "se"; 2404 2405 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2406 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2407 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2408 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2409 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2410 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2411 interconnect-names = "qup-core", 2412 "qup-config", 2413 "qup-memory"; 2414 2415 power-domains = <&rpmhpd RPMHPD_CX>; 2416 operating-points-v2 = <&qup_opp_table_100mhz>; 2417 2418 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2419 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2420 dma-names = "tx", 2421 "rx"; 2422 2423 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2424 pinctrl-names = "default"; 2425 2426 #address-cells = <1>; 2427 #size-cells = <0>; 2428 2429 status = "disabled"; 2430 }; 2431 2432 i2c3: i2c@b8c000 { 2433 compatible = "qcom,geni-i2c"; 2434 reg = <0 0x00b8c000 0 0x4000>; 2435 2436 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2437 2438 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2439 clock-names = "se"; 2440 2441 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2442 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2443 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2444 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2445 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2446 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2447 interconnect-names = "qup-core", 2448 "qup-config", 2449 "qup-memory"; 2450 2451 power-domains = <&rpmhpd RPMHPD_CX>; 2452 required-opps = <&rpmhpd_opp_low_svs>; 2453 2454 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2455 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2456 dma-names = "tx", 2457 "rx"; 2458 2459 pinctrl-0 = <&qup_i2c3_data_clk>; 2460 pinctrl-names = "default"; 2461 2462 #address-cells = <1>; 2463 #size-cells = <0>; 2464 2465 status = "disabled"; 2466 }; 2467 2468 spi3: spi@b8c000 { 2469 compatible = "qcom,geni-spi"; 2470 reg = <0 0x00b8c000 0 0x4000>; 2471 2472 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2473 2474 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2475 clock-names = "se"; 2476 2477 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2478 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2479 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2480 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2481 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2482 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2483 interconnect-names = "qup-core", 2484 "qup-config", 2485 "qup-memory"; 2486 2487 power-domains = <&rpmhpd RPMHPD_CX>; 2488 operating-points-v2 = <&qup_opp_table_100mhz>; 2489 2490 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2491 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2492 dma-names = "tx", 2493 "rx"; 2494 2495 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2496 pinctrl-names = "default"; 2497 2498 #address-cells = <1>; 2499 #size-cells = <0>; 2500 2501 status = "disabled"; 2502 }; 2503 2504 i2c4: i2c@b90000 { 2505 compatible = "qcom,geni-i2c"; 2506 reg = <0 0x00b90000 0 0x4000>; 2507 2508 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2509 2510 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2511 clock-names = "se"; 2512 2513 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2514 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2515 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2516 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2517 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2518 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2519 interconnect-names = "qup-core", 2520 "qup-config", 2521 "qup-memory"; 2522 2523 power-domains = <&rpmhpd RPMHPD_CX>; 2524 required-opps = <&rpmhpd_opp_low_svs>; 2525 2526 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2527 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2528 dma-names = "tx", 2529 "rx"; 2530 2531 pinctrl-0 = <&qup_i2c4_data_clk>; 2532 pinctrl-names = "default"; 2533 2534 #address-cells = <1>; 2535 #size-cells = <0>; 2536 2537 status = "disabled"; 2538 }; 2539 2540 spi4: spi@b90000 { 2541 compatible = "qcom,geni-spi"; 2542 reg = <0 0x00b90000 0 0x4000>; 2543 2544 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2545 2546 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2547 clock-names = "se"; 2548 2549 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2550 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2551 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2552 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2553 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2554 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2555 interconnect-names = "qup-core", 2556 "qup-config", 2557 "qup-memory"; 2558 2559 power-domains = <&rpmhpd RPMHPD_CX>; 2560 operating-points-v2 = <&qup_opp_table_100mhz>; 2561 2562 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2563 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2564 dma-names = "tx", 2565 "rx"; 2566 2567 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2568 pinctrl-names = "default"; 2569 2570 #address-cells = <1>; 2571 #size-cells = <0>; 2572 2573 status = "disabled"; 2574 }; 2575 2576 i2c5: i2c@b94000 { 2577 compatible = "qcom,geni-i2c"; 2578 reg = <0 0x00b94000 0 0x4000>; 2579 2580 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2581 2582 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2583 clock-names = "se"; 2584 2585 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2586 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2587 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2588 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2589 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2590 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2591 interconnect-names = "qup-core", 2592 "qup-config", 2593 "qup-memory"; 2594 2595 power-domains = <&rpmhpd RPMHPD_CX>; 2596 required-opps = <&rpmhpd_opp_low_svs>; 2597 2598 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2599 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2600 dma-names = "tx", 2601 "rx"; 2602 2603 pinctrl-0 = <&qup_i2c5_data_clk>; 2604 pinctrl-names = "default"; 2605 2606 #address-cells = <1>; 2607 #size-cells = <0>; 2608 2609 status = "disabled"; 2610 }; 2611 2612 spi5: spi@b94000 { 2613 compatible = "qcom,geni-spi"; 2614 reg = <0 0x00b94000 0 0x4000>; 2615 2616 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2617 2618 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2619 clock-names = "se"; 2620 2621 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2622 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2623 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2624 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2625 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2626 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2627 interconnect-names = "qup-core", 2628 "qup-config", 2629 "qup-memory"; 2630 2631 power-domains = <&rpmhpd RPMHPD_CX>; 2632 operating-points-v2 = <&qup_opp_table_100mhz>; 2633 2634 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2635 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2636 dma-names = "tx", 2637 "rx"; 2638 2639 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2640 pinctrl-names = "default"; 2641 2642 #address-cells = <1>; 2643 #size-cells = <0>; 2644 2645 status = "disabled"; 2646 }; 2647 2648 i2c6: i2c@b98000 { 2649 compatible = "qcom,geni-i2c"; 2650 reg = <0 0x00b98000 0 0x4000>; 2651 2652 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2653 2654 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2655 clock-names = "se"; 2656 2657 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2658 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2659 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2660 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2661 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2662 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2663 interconnect-names = "qup-core", 2664 "qup-config", 2665 "qup-memory"; 2666 2667 power-domains = <&rpmhpd RPMHPD_CX>; 2668 required-opps = <&rpmhpd_opp_low_svs>; 2669 2670 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2671 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2672 dma-names = "tx", 2673 "rx"; 2674 2675 pinctrl-0 = <&qup_i2c6_data_clk>; 2676 pinctrl-names = "default"; 2677 2678 #address-cells = <1>; 2679 #size-cells = <0>; 2680 2681 status = "disabled"; 2682 }; 2683 2684 spi6: spi@b98000 { 2685 compatible = "qcom,geni-spi"; 2686 reg = <0 0x00b98000 0 0x4000>; 2687 2688 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2689 2690 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2691 clock-names = "se"; 2692 2693 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2694 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2695 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2696 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2697 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2698 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2699 interconnect-names = "qup-core", 2700 "qup-config", 2701 "qup-memory"; 2702 2703 power-domains = <&rpmhpd RPMHPD_CX>; 2704 operating-points-v2 = <&qup_opp_table_100mhz>; 2705 2706 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2707 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2708 dma-names = "tx", 2709 "rx"; 2710 2711 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2712 pinctrl-names = "default"; 2713 2714 #address-cells = <1>; 2715 #size-cells = <0>; 2716 2717 status = "disabled"; 2718 }; 2719 2720 i2c7: i2c@b9c000 { 2721 compatible = "qcom,geni-i2c"; 2722 reg = <0 0x00b9c000 0 0x4000>; 2723 2724 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2725 2726 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2727 clock-names = "se"; 2728 2729 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2730 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2731 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2732 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2733 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2734 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2735 interconnect-names = "qup-core", 2736 "qup-config", 2737 "qup-memory"; 2738 2739 power-domains = <&rpmhpd RPMHPD_CX>; 2740 required-opps = <&rpmhpd_opp_low_svs>; 2741 2742 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2743 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2744 dma-names = "tx", 2745 "rx"; 2746 2747 pinctrl-0 = <&qup_i2c7_data_clk>; 2748 pinctrl-names = "default"; 2749 2750 #address-cells = <1>; 2751 #size-cells = <0>; 2752 2753 status = "disabled"; 2754 }; 2755 2756 spi7: spi@b9c000 { 2757 compatible = "qcom,geni-spi"; 2758 reg = <0 0x00b9c000 0 0x4000>; 2759 2760 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2761 2762 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2763 clock-names = "se"; 2764 2765 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2766 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2767 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2768 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2769 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2770 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2771 interconnect-names = "qup-core", 2772 "qup-config", 2773 "qup-memory"; 2774 2775 power-domains = <&rpmhpd RPMHPD_CX>; 2776 operating-points-v2 = <&qup_opp_table_100mhz>; 2777 2778 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2779 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2780 dma-names = "tx", 2781 "rx"; 2782 2783 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2784 pinctrl-names = "default"; 2785 2786 #address-cells = <1>; 2787 #size-cells = <0>; 2788 2789 status = "disabled"; 2790 }; 2791 }; 2792 2793 tsens0: thermal-sensor@c271000 { 2794 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2795 reg = <0 0x0c271000 0 0x1000>, 2796 <0 0x0c222000 0 0x1000>; 2797 2798 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2799 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2800 interrupt-names = "uplow", 2801 "critical"; 2802 2803 #qcom,sensors = <16>; 2804 2805 #thermal-sensor-cells = <1>; 2806 }; 2807 2808 tsens1: thermal-sensor@c272000 { 2809 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2810 reg = <0 0x0c272000 0 0x1000>, 2811 <0 0x0c223000 0 0x1000>; 2812 2813 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2814 <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2815 interrupt-names = "uplow", 2816 "critical"; 2817 2818 #qcom,sensors = <16>; 2819 2820 #thermal-sensor-cells = <1>; 2821 }; 2822 2823 tsens2: thermal-sensor@c273000 { 2824 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2825 reg = <0 0x0c273000 0 0x1000>, 2826 <0 0x0c224000 0 0x1000>; 2827 2828 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>, 2829 <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; 2830 interrupt-names = "uplow", 2831 "critical"; 2832 2833 #qcom,sensors = <16>; 2834 2835 #thermal-sensor-cells = <1>; 2836 }; 2837 2838 tsens3: thermal-sensor@c274000 { 2839 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2840 reg = <0 0x0c274000 0 0x1000>, 2841 <0 0x0c225000 0 0x1000>; 2842 2843 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>, 2844 <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; 2845 interrupt-names = "uplow", 2846 "critical"; 2847 2848 #qcom,sensors = <16>; 2849 2850 #thermal-sensor-cells = <1>; 2851 }; 2852 2853 usb_1_ss0_hsphy: phy@fd3000 { 2854 compatible = "qcom,x1e80100-snps-eusb2-phy", 2855 "qcom,sm8550-snps-eusb2-phy"; 2856 reg = <0 0x00fd3000 0 0x154>; 2857 #phy-cells = <0>; 2858 2859 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2860 clock-names = "ref"; 2861 2862 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2863 2864 status = "disabled"; 2865 }; 2866 2867 usb_1_ss0_qmpphy: phy@fd5000 { 2868 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2869 reg = <0 0x00fd5000 0 0x4000>; 2870 2871 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2872 <&rpmhcc RPMH_CXO_CLK>, 2873 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2874 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2875 clock-names = "aux", 2876 "ref", 2877 "com_aux", 2878 "usb3_pipe"; 2879 2880 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2881 2882 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2883 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>; 2884 reset-names = "phy", 2885 "common"; 2886 2887 #clock-cells = <1>; 2888 #phy-cells = <1>; 2889 2890 mode-switch; 2891 orientation-switch; 2892 2893 status = "disabled"; 2894 2895 ports { 2896 #address-cells = <1>; 2897 #size-cells = <0>; 2898 2899 port@0 { 2900 reg = <0>; 2901 2902 usb_1_ss0_qmpphy_out: endpoint { 2903 }; 2904 }; 2905 2906 port@1 { 2907 reg = <1>; 2908 2909 usb_1_ss0_qmpphy_usb_ss_in: endpoint { 2910 remote-endpoint = <&usb_1_ss0_dwc3_ss>; 2911 }; 2912 }; 2913 2914 port@2 { 2915 reg = <2>; 2916 2917 usb_1_ss0_qmpphy_dp_in: endpoint { 2918 remote-endpoint = <&mdss_dp0_out>; 2919 }; 2920 }; 2921 }; 2922 }; 2923 2924 usb_1_ss1_hsphy: phy@fd9000 { 2925 compatible = "qcom,x1e80100-snps-eusb2-phy", 2926 "qcom,sm8550-snps-eusb2-phy"; 2927 reg = <0 0x00fd9000 0 0x154>; 2928 #phy-cells = <0>; 2929 2930 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2931 clock-names = "ref"; 2932 2933 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2934 2935 status = "disabled"; 2936 }; 2937 2938 usb_1_ss1_qmpphy: phy@fda000 { 2939 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2940 reg = <0 0x00fda000 0 0x4000>; 2941 2942 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2943 <&tcsr TCSR_USB4_1_CLKREF_EN>, 2944 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2945 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2946 clock-names = "aux", 2947 "ref", 2948 "com_aux", 2949 "usb3_pipe"; 2950 2951 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2952 2953 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2954 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>; 2955 reset-names = "phy", 2956 "common"; 2957 2958 #clock-cells = <1>; 2959 #phy-cells = <1>; 2960 2961 mode-switch; 2962 orientation-switch; 2963 2964 status = "disabled"; 2965 2966 ports { 2967 #address-cells = <1>; 2968 #size-cells = <0>; 2969 2970 port@0 { 2971 reg = <0>; 2972 2973 usb_1_ss1_qmpphy_out: endpoint { 2974 }; 2975 }; 2976 2977 port@1 { 2978 reg = <1>; 2979 2980 usb_1_ss1_qmpphy_usb_ss_in: endpoint { 2981 remote-endpoint = <&usb_1_ss1_dwc3_ss>; 2982 }; 2983 }; 2984 2985 port@2 { 2986 reg = <2>; 2987 2988 usb_1_ss1_qmpphy_dp_in: endpoint { 2989 remote-endpoint = <&mdss_dp1_out>; 2990 }; 2991 }; 2992 }; 2993 }; 2994 2995 usb_1_ss2_hsphy: phy@fde000 { 2996 compatible = "qcom,x1e80100-snps-eusb2-phy", 2997 "qcom,sm8550-snps-eusb2-phy"; 2998 reg = <0 0x00fde000 0 0x154>; 2999 #phy-cells = <0>; 3000 3001 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 3002 clock-names = "ref"; 3003 3004 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 3005 3006 status = "disabled"; 3007 }; 3008 3009 usb_1_ss2_qmpphy: phy@fdf000 { 3010 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 3011 reg = <0 0x00fdf000 0 0x4000>; 3012 3013 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 3014 <&tcsr TCSR_USB4_2_CLKREF_EN>, 3015 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 3016 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 3017 clock-names = "aux", 3018 "ref", 3019 "com_aux", 3020 "usb3_pipe"; 3021 3022 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 3023 3024 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 3025 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>; 3026 reset-names = "phy", 3027 "common"; 3028 3029 #clock-cells = <1>; 3030 #phy-cells = <1>; 3031 3032 mode-switch; 3033 orientation-switch; 3034 3035 status = "disabled"; 3036 3037 ports { 3038 #address-cells = <1>; 3039 #size-cells = <0>; 3040 3041 port@0 { 3042 reg = <0>; 3043 3044 usb_1_ss2_qmpphy_out: endpoint { 3045 }; 3046 }; 3047 3048 port@1 { 3049 reg = <1>; 3050 3051 usb_1_ss2_qmpphy_usb_ss_in: endpoint { 3052 remote-endpoint = <&usb_1_ss2_dwc3_ss>; 3053 }; 3054 }; 3055 3056 port@2 { 3057 reg = <2>; 3058 3059 usb_1_ss2_qmpphy_dp_in: endpoint { 3060 remote-endpoint = <&mdss_dp2_out>; 3061 }; 3062 }; 3063 }; 3064 }; 3065 3066 rng: rng@10c3000 { 3067 compatible = "qcom,x1e80100-trng", "qcom,trng"; 3068 reg = <0x0 0x010c3000 0x0 0x1000>; 3069 }; 3070 3071 cnoc_main: interconnect@1500000 { 3072 compatible = "qcom,x1e80100-cnoc-main"; 3073 reg = <0 0x01500000 0 0x14400>; 3074 3075 qcom,bcm-voters = <&apps_bcm_voter>; 3076 3077 #interconnect-cells = <2>; 3078 }; 3079 3080 config_noc: interconnect@1600000 { 3081 compatible = "qcom,x1e80100-cnoc-cfg"; 3082 reg = <0 0x01600000 0 0x6600>; 3083 3084 qcom,bcm-voters = <&apps_bcm_voter>; 3085 3086 #interconnect-cells = <2>; 3087 }; 3088 3089 system_noc: interconnect@1680000 { 3090 compatible = "qcom,x1e80100-system-noc"; 3091 reg = <0 0x01680000 0 0x1c080>; 3092 3093 qcom,bcm-voters = <&apps_bcm_voter>; 3094 3095 #interconnect-cells = <2>; 3096 }; 3097 3098 pcie_south_anoc: interconnect@16c0000 { 3099 compatible = "qcom,x1e80100-pcie-south-anoc"; 3100 reg = <0 0x016c0000 0 0xd080>; 3101 3102 qcom,bcm-voters = <&apps_bcm_voter>; 3103 3104 #interconnect-cells = <2>; 3105 }; 3106 3107 pcie_center_anoc: interconnect@16d0000 { 3108 compatible = "qcom,x1e80100-pcie-center-anoc"; 3109 reg = <0 0x016d0000 0 0x7000>; 3110 3111 qcom,bcm-voters = <&apps_bcm_voter>; 3112 3113 #interconnect-cells = <2>; 3114 }; 3115 3116 aggre1_noc: interconnect@16e0000 { 3117 compatible = "qcom,x1e80100-aggre1-noc"; 3118 reg = <0 0x016e0000 0 0x14400>; 3119 3120 qcom,bcm-voters = <&apps_bcm_voter>; 3121 3122 #interconnect-cells = <2>; 3123 }; 3124 3125 aggre2_noc: interconnect@1700000 { 3126 compatible = "qcom,x1e80100-aggre2-noc"; 3127 reg = <0 0x01700000 0 0x1c400>; 3128 3129 qcom,bcm-voters = <&apps_bcm_voter>; 3130 3131 #interconnect-cells = <2>; 3132 }; 3133 3134 pcie_north_anoc: interconnect@1740000 { 3135 compatible = "qcom,x1e80100-pcie-north-anoc"; 3136 reg = <0 0x01740000 0 0x9080>; 3137 3138 qcom,bcm-voters = <&apps_bcm_voter>; 3139 3140 #interconnect-cells = <2>; 3141 }; 3142 3143 usb_center_anoc: interconnect@1750000 { 3144 compatible = "qcom,x1e80100-usb-center-anoc"; 3145 reg = <0 0x01750000 0 0x8800>; 3146 3147 qcom,bcm-voters = <&apps_bcm_voter>; 3148 3149 #interconnect-cells = <2>; 3150 }; 3151 3152 usb_north_anoc: interconnect@1760000 { 3153 compatible = "qcom,x1e80100-usb-north-anoc"; 3154 reg = <0 0x01760000 0 0x7080>; 3155 3156 qcom,bcm-voters = <&apps_bcm_voter>; 3157 3158 #interconnect-cells = <2>; 3159 }; 3160 3161 usb_south_anoc: interconnect@1770000 { 3162 compatible = "qcom,x1e80100-usb-south-anoc"; 3163 reg = <0 0x01770000 0 0xf080>; 3164 3165 qcom,bcm-voters = <&apps_bcm_voter>; 3166 3167 #interconnect-cells = <2>; 3168 }; 3169 3170 mmss_noc: interconnect@1780000 { 3171 compatible = "qcom,x1e80100-mmss-noc"; 3172 reg = <0 0x01780000 0 0x5b800>; 3173 3174 qcom,bcm-voters = <&apps_bcm_voter>; 3175 3176 #interconnect-cells = <2>; 3177 }; 3178 3179 pcie3: pcie@1bd0000 { 3180 device_type = "pci"; 3181 compatible = "qcom,pcie-x1e80100"; 3182 reg = <0x0 0x01bd0000 0x0 0x3000>, 3183 <0x0 0x78000000 0x0 0xf20>, 3184 <0x0 0x78000f40 0x0 0xa8>, 3185 <0x0 0x78001000 0x0 0x1000>, 3186 <0x0 0x78100000 0x0 0x100000>, 3187 <0x0 0x01bd3000 0x0 0x1000>; 3188 reg-names = "parf", 3189 "dbi", 3190 "elbi", 3191 "atu", 3192 "config", 3193 "mhi"; 3194 #address-cells = <3>; 3195 #size-cells = <2>; 3196 ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>, 3197 <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>, 3198 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; 3199 bus-range = <0x00 0xff>; 3200 3201 dma-coherent; 3202 3203 linux,pci-domain = <3>; 3204 num-lanes = <8>; 3205 3206 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 3207 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 3208 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3209 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 3210 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 3211 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 3212 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 3213 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 3214 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 3215 interrupt-names = "msi0", 3216 "msi1", 3217 "msi2", 3218 "msi3", 3219 "msi4", 3220 "msi5", 3221 "msi6", 3222 "msi7", 3223 "global"; 3224 3225 #interrupt-cells = <1>; 3226 interrupt-map-mask = <0 0 0 0x7>; 3227 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 3228 <0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 3229 <0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 3230 <0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3231 3232 clocks = <&gcc GCC_PCIE_3_AUX_CLK>, 3233 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 3234 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 3235 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 3236 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, 3237 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3238 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3239 clock-names = "aux", 3240 "cfg", 3241 "bus_master", 3242 "bus_slave", 3243 "slave_q2a", 3244 "noc_aggr", 3245 "cnoc_sf_axi"; 3246 3247 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 3248 assigned-clock-rates = <19200000>; 3249 3250 interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS 3251 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3252 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3253 &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ACTIVE_ONLY>; 3254 interconnect-names = "pcie-mem", 3255 "cpu-pcie"; 3256 3257 resets = <&gcc GCC_PCIE_3_BCR>, 3258 <&gcc GCC_PCIE_3_LINK_DOWN_BCR>; 3259 reset-names = "pci", 3260 "link_down"; 3261 3262 power-domains = <&gcc GCC_PCIE_3_GDSC>; 3263 3264 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 3265 0x5555 0x5555 0x5555 0x5555>; 3266 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; 3267 3268 operating-points-v2 = <&pcie3_opp_table>; 3269 3270 status = "disabled"; 3271 3272 pcie3_opp_table: opp-table { 3273 compatible = "operating-points-v2"; 3274 3275 /* 2.5GT/s x1 */ 3276 opp-2500000-1 { 3277 opp-hz = /bits/ 64 <2500000>; 3278 required-opps = <&rpmhpd_opp_low_svs>; 3279 opp-peak-kBps = <250000 1>; 3280 opp-level = <1>; 3281 }; 3282 3283 /* 2.5 GT/s x2 */ 3284 opp-5000000-1 { 3285 opp-hz = /bits/ 64 <5000000>; 3286 required-opps = <&rpmhpd_opp_low_svs>; 3287 opp-peak-kBps = <500000 1>; 3288 opp-level = <1>; 3289 }; 3290 3291 /* 2.5 GT/s x4 */ 3292 opp-10000000-1 { 3293 opp-hz = /bits/ 64 <10000000>; 3294 required-opps = <&rpmhpd_opp_low_svs>; 3295 opp-peak-kBps = <1000000 1>; 3296 opp-level = <1>; 3297 }; 3298 3299 /* 2.5 GT/s x8 */ 3300 opp-20000000-1 { 3301 opp-hz = /bits/ 64 <20000000>; 3302 required-opps = <&rpmhpd_opp_low_svs>; 3303 opp-peak-kBps = <2000000 1>; 3304 opp-level = <1>; 3305 }; 3306 3307 /* 5 GT/s x1 */ 3308 opp-5000000-2 { 3309 opp-hz = /bits/ 64 <5000000>; 3310 required-opps = <&rpmhpd_opp_low_svs>; 3311 opp-peak-kBps = <500000 1>; 3312 opp-level = <2>; 3313 }; 3314 3315 /* 5 GT/s x2 */ 3316 opp-10000000-2 { 3317 opp-hz = /bits/ 64 <10000000>; 3318 required-opps = <&rpmhpd_opp_low_svs>; 3319 opp-peak-kBps = <1000000 1>; 3320 opp-level = <2>; 3321 }; 3322 3323 /* 5 GT/s x4 */ 3324 opp-20000000-2 { 3325 opp-hz = /bits/ 64 <20000000>; 3326 required-opps = <&rpmhpd_opp_low_svs>; 3327 opp-peak-kBps = <2000000 1>; 3328 opp-level = <2>; 3329 }; 3330 3331 /* 5 GT/s x8 */ 3332 opp-40000000-2 { 3333 opp-hz = /bits/ 64 <40000000>; 3334 required-opps = <&rpmhpd_opp_low_svs>; 3335 opp-peak-kBps = <4000000 1>; 3336 opp-level = <2>; 3337 }; 3338 3339 /* 8 GT/s x1 */ 3340 opp-8000000-3 { 3341 opp-hz = /bits/ 64 <8000000>; 3342 required-opps = <&rpmhpd_opp_svs>; 3343 opp-peak-kBps = <984500 1>; 3344 opp-level = <3>; 3345 }; 3346 3347 /* 8 GT/s x2 */ 3348 opp-16000000-3 { 3349 opp-hz = /bits/ 64 <16000000>; 3350 required-opps = <&rpmhpd_opp_svs>; 3351 opp-peak-kBps = <1969000 1>; 3352 opp-level = <3>; 3353 }; 3354 3355 /* 8 GT/s x4 */ 3356 opp-32000000-3 { 3357 opp-hz = /bits/ 64 <32000000>; 3358 required-opps = <&rpmhpd_opp_svs>; 3359 opp-peak-kBps = <3938000 1>; 3360 opp-level = <3>; 3361 }; 3362 3363 /* 8 GT/s x8 */ 3364 opp-64000000-3 { 3365 opp-hz = /bits/ 64 <64000000>; 3366 required-opps = <&rpmhpd_opp_svs>; 3367 opp-peak-kBps = <7876000 1>; 3368 opp-level = <3>; 3369 }; 3370 3371 /* 16 GT/s x1 */ 3372 opp-16000000-4 { 3373 opp-hz = /bits/ 64 <16000000>; 3374 required-opps = <&rpmhpd_opp_svs>; 3375 opp-peak-kBps = <1969000 1>; 3376 opp-level = <4>; 3377 }; 3378 3379 /* 16 GT/s x2 */ 3380 opp-32000000-4 { 3381 opp-hz = /bits/ 64 <32000000>; 3382 required-opps = <&rpmhpd_opp_svs>; 3383 opp-peak-kBps = <3938000 1>; 3384 opp-level = <4>; 3385 }; 3386 3387 /* 16 GT/s x4 */ 3388 opp-64000000-4 { 3389 opp-hz = /bits/ 64 <64000000>; 3390 required-opps = <&rpmhpd_opp_svs>; 3391 opp-peak-kBps = <7876000 1>; 3392 opp-level = <4>; 3393 }; 3394 3395 /* 16 GT/s x8 */ 3396 opp-128000000-4 { 3397 opp-hz = /bits/ 64 <128000000>; 3398 required-opps = <&rpmhpd_opp_svs>; 3399 opp-peak-kBps = <15753000 1>; 3400 opp-level = <4>; 3401 }; 3402 }; 3403 3404 pcie3_port0: pcie@0 { 3405 device_type = "pci"; 3406 compatible = "pciclass,0604"; 3407 reg = <0x0 0x0 0x0 0x0 0x0>; 3408 bus-range = <0x01 0xff>; 3409 3410 phys = <&pcie3_phy>; 3411 3412 #address-cells = <3>; 3413 #size-cells = <2>; 3414 ranges; 3415 }; 3416 }; 3417 3418 pcie3_phy: phy@1be0000 { 3419 compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy"; 3420 reg = <0 0x01be0000 0 0x10000>; 3421 3422 clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>, 3423 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 3424 <&tcsr TCSR_PCIE_8L_CLKREF_EN>, 3425 <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>, 3426 <&gcc GCC_PCIE_3_PIPE_CLK>, 3427 <&gcc GCC_PCIE_3_PIPEDIV2_CLK>; 3428 clock-names = "aux", 3429 "cfg_ahb", 3430 "ref", 3431 "rchng", 3432 "pipe", 3433 "pipediv2"; 3434 3435 resets = <&gcc GCC_PCIE_3_PHY_BCR>, 3436 <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>; 3437 reset-names = "phy", 3438 "phy_nocsr"; 3439 3440 assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>; 3441 assigned-clock-rates = <100000000>; 3442 3443 power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>; 3444 3445 #clock-cells = <0>; 3446 clock-output-names = "pcie3_pipe_clk"; 3447 3448 #phy-cells = <0>; 3449 3450 status = "disabled"; 3451 }; 3452 3453 pcie6a: pci@1bf8000 { 3454 device_type = "pci"; 3455 compatible = "qcom,pcie-x1e80100"; 3456 reg = <0 0x01bf8000 0 0x3000>, 3457 <0 0x70000000 0 0xf20>, 3458 <0 0x70000f40 0 0xa8>, 3459 <0 0x70001000 0 0x1000>, 3460 <0 0x70100000 0 0x100000>, 3461 <0 0x01bfb000 0 0x1000>; 3462 reg-names = "parf", 3463 "dbi", 3464 "elbi", 3465 "atu", 3466 "config", 3467 "mhi"; 3468 #address-cells = <3>; 3469 #size-cells = <2>; 3470 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, 3471 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 3472 bus-range = <0x00 0xff>; 3473 3474 dma-coherent; 3475 3476 linux,pci-domain = <6>; 3477 num-lanes = <4>; 3478 3479 msi-map = <0x0 &gic_its 0xe0000 0x10000>; 3480 3481 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>; 3490 interrupt-names = "msi0", 3491 "msi1", 3492 "msi2", 3493 "msi3", 3494 "msi4", 3495 "msi5", 3496 "msi6", 3497 "msi7", 3498 "global"; 3499 3500 #interrupt-cells = <1>; 3501 interrupt-map-mask = <0 0 0 0x7>; 3502 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 3503 <0 0 0 2 &intc 0 0 GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 3504 <0 0 0 3 &intc 0 0 GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 3505 <0 0 0 4 &intc 0 0 GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>; 3506 3507 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, 3508 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3509 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>, 3510 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>, 3511 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>, 3512 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>, 3513 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>; 3514 clock-names = "aux", 3515 "cfg", 3516 "bus_master", 3517 "bus_slave", 3518 "slave_q2a", 3519 "noc_aggr", 3520 "cnoc_sf_axi"; 3521 3522 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>; 3523 assigned-clock-rates = <19200000>; 3524 3525 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS 3526 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3527 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3528 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ACTIVE_ONLY>; 3529 interconnect-names = "pcie-mem", 3530 "cpu-pcie"; 3531 3532 resets = <&gcc GCC_PCIE_6A_BCR>, 3533 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; 3534 reset-names = "pci", 3535 "link_down"; 3536 3537 power-domains = <&gcc GCC_PCIE_6A_GDSC>; 3538 required-opps = <&rpmhpd_opp_nom>; 3539 3540 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3541 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3542 3543 status = "disabled"; 3544 3545 pcie6a_port0: pcie@0 { 3546 device_type = "pci"; 3547 reg = <0x0 0x0 0x0 0x0 0x0>; 3548 bus-range = <0x01 0xff>; 3549 3550 phys = <&pcie6a_phy>; 3551 3552 #address-cells = <3>; 3553 #size-cells = <2>; 3554 ranges; 3555 }; 3556 }; 3557 3558 pcie6a_phy: phy@1bfc000 { 3559 compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy"; 3560 reg = <0 0x01bfc000 0 0x2000>, 3561 <0 0x01bfe000 0 0x2000>; 3562 3563 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, 3564 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3565 <&tcsr TCSR_PCIE_4L_CLKREF_EN>, 3566 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, 3567 <&gcc GCC_PCIE_6A_PIPE_CLK>, 3568 <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>; 3569 clock-names = "aux", 3570 "cfg_ahb", 3571 "ref", 3572 "rchng", 3573 "pipe", 3574 "pipediv2"; 3575 3576 resets = <&gcc GCC_PCIE_6A_PHY_BCR>, 3577 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; 3578 reset-names = "phy", 3579 "phy_nocsr"; 3580 3581 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>; 3582 assigned-clock-rates = <100000000>; 3583 3584 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3585 3586 qcom,4ln-config-sel = <&tcsr 0x1a000 0>; 3587 3588 #clock-cells = <0>; 3589 clock-output-names = "pcie6a_pipe_clk"; 3590 3591 #phy-cells = <0>; 3592 3593 status = "disabled"; 3594 }; 3595 3596 pcie5: pci@1c00000 { 3597 device_type = "pci"; 3598 compatible = "qcom,pcie-x1e80100"; 3599 reg = <0 0x01c00000 0 0x3000>, 3600 <0 0x7e000000 0 0xf1d>, 3601 <0 0x7e000f40 0 0xa8>, 3602 <0 0x7e001000 0 0x1000>, 3603 <0 0x7e100000 0 0x100000>, 3604 <0 0x01c03000 0 0x1000>; 3605 reg-names = "parf", 3606 "dbi", 3607 "elbi", 3608 "atu", 3609 "config", 3610 "mhi"; 3611 #address-cells = <3>; 3612 #size-cells = <2>; 3613 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3614 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>; 3615 bus-range = <0x00 0xff>; 3616 3617 dma-coherent; 3618 3619 linux,pci-domain = <5>; 3620 num-lanes = <2>; 3621 3622 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 3630 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 3631 interrupt-names = "msi0", 3632 "msi1", 3633 "msi2", 3634 "msi3", 3635 "msi4", 3636 "msi5", 3637 "msi6", 3638 "msi7", 3639 "global"; 3640 3641 #interrupt-cells = <1>; 3642 interrupt-map-mask = <0 0 0 0x7>; 3643 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 3644 <0 0 0 2 &intc 0 0 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 3645 <0 0 0 3 &intc 0 0 GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 3646 <0 0 0 4 &intc 0 0 GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 3647 3648 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3649 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3650 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 3651 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 3652 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 3653 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3654 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3655 clock-names = "aux", 3656 "cfg", 3657 "bus_master", 3658 "bus_slave", 3659 "slave_q2a", 3660 "noc_aggr", 3661 "cnoc_sf_axi"; 3662 3663 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3664 assigned-clock-rates = <19200000>; 3665 3666 interconnects = <&pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3667 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3668 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3669 &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ACTIVE_ONLY>; 3670 interconnect-names = "pcie-mem", 3671 "cpu-pcie"; 3672 3673 resets = <&gcc GCC_PCIE_5_BCR>, 3674 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3675 reset-names = "pci", 3676 "link_down"; 3677 3678 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3679 required-opps = <&rpmhpd_opp_nom>; 3680 3681 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3682 3683 status = "disabled"; 3684 3685 pcie5_port0: pcie@0 { 3686 device_type = "pci"; 3687 reg = <0x0 0x0 0x0 0x0 0x0>; 3688 bus-range = <0x01 0xff>; 3689 3690 phys = <&pcie5_phy>; 3691 3692 #address-cells = <3>; 3693 #size-cells = <2>; 3694 ranges; 3695 }; 3696 }; 3697 3698 pcie5_phy: phy@1c06000 { 3699 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3700 reg = <0 0x01c06000 0 0x2000>; 3701 3702 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3703 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3704 <&tcsr TCSR_PCIE_2L_5_CLKREF_EN>, 3705 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3706 <&gcc GCC_PCIE_5_PIPE_CLK>, 3707 <&gcc GCC_PCIE_5_PIPEDIV2_CLK>; 3708 clock-names = "aux", 3709 "cfg_ahb", 3710 "ref", 3711 "rchng", 3712 "pipe", 3713 "pipediv2"; 3714 3715 resets = <&gcc GCC_PCIE_5_PHY_BCR>, 3716 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; 3717 reset-names = "phy", 3718 "phy_nocsr"; 3719 3720 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3721 assigned-clock-rates = <100000000>; 3722 3723 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3724 3725 #clock-cells = <0>; 3726 clock-output-names = "pcie5_pipe_clk"; 3727 3728 #phy-cells = <0>; 3729 3730 status = "disabled"; 3731 }; 3732 3733 pcie4: pci@1c08000 { 3734 device_type = "pci"; 3735 compatible = "qcom,pcie-x1e80100"; 3736 reg = <0 0x01c08000 0 0x3000>, 3737 <0 0x7c000000 0 0xf1d>, 3738 <0 0x7c000f40 0 0xa8>, 3739 <0 0x7c001000 0 0x1000>, 3740 <0 0x7c100000 0 0x100000>, 3741 <0 0x01c0b000 0 0x1000>; 3742 reg-names = "parf", 3743 "dbi", 3744 "elbi", 3745 "atu", 3746 "config", 3747 "mhi"; 3748 #address-cells = <3>; 3749 #size-cells = <2>; 3750 ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>, 3751 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>; 3752 bus-range = <0x00 0xff>; 3753 3754 dma-coherent; 3755 3756 linux,pci-domain = <4>; 3757 num-lanes = <2>; 3758 3759 msi-map = <0x0 &gic_its 0xc0000 0x10000>; 3760 3761 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3765 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 3770 interrupt-names = "msi0", 3771 "msi1", 3772 "msi2", 3773 "msi3", 3774 "msi4", 3775 "msi5", 3776 "msi6", 3777 "msi7", 3778 "global"; 3779 3780 #interrupt-cells = <1>; 3781 interrupt-map-mask = <0 0 0 0x7>; 3782 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 3783 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 3784 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 3785 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 3786 3787 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3788 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3789 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 3790 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 3791 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 3792 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3793 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3794 clock-names = "aux", 3795 "cfg", 3796 "bus_master", 3797 "bus_slave", 3798 "slave_q2a", 3799 "noc_aggr", 3800 "cnoc_sf_axi"; 3801 3802 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 3803 assigned-clock-rates = <19200000>; 3804 3805 interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 3806 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3807 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3808 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 3809 interconnect-names = "pcie-mem", 3810 "cpu-pcie"; 3811 3812 resets = <&gcc GCC_PCIE_4_BCR>, 3813 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 3814 reset-names = "pci", 3815 "link_down"; 3816 3817 power-domains = <&gcc GCC_PCIE_4_GDSC>; 3818 required-opps = <&rpmhpd_opp_nom>; 3819 3820 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3821 3822 status = "disabled"; 3823 3824 pcie4_port0: pcie@0 { 3825 device_type = "pci"; 3826 reg = <0x0 0x0 0x0 0x0 0x0>; 3827 bus-range = <0x01 0xff>; 3828 3829 phys = <&pcie4_phy>; 3830 3831 #address-cells = <3>; 3832 #size-cells = <2>; 3833 ranges; 3834 }; 3835 }; 3836 3837 pcie4_phy: phy@1c0e000 { 3838 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3839 reg = <0 0x01c0e000 0 0x2000>; 3840 3841 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3842 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3843 <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>, 3844 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 3845 <&gcc GCC_PCIE_4_PIPE_CLK>, 3846 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 3847 clock-names = "aux", 3848 "cfg_ahb", 3849 "ref", 3850 "rchng", 3851 "pipe", 3852 "pipediv2"; 3853 3854 resets = <&gcc GCC_PCIE_4_PHY_BCR>, 3855 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; 3856 reset-names = "phy", 3857 "phy_nocsr"; 3858 3859 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 3860 assigned-clock-rates = <100000000>; 3861 3862 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 3863 3864 #clock-cells = <0>; 3865 clock-output-names = "pcie4_pipe_clk"; 3866 3867 #phy-cells = <0>; 3868 3869 status = "disabled"; 3870 }; 3871 3872 cryptobam: dma-controller@1dc4000 { 3873 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 3874 reg = <0x0 0x01dc4000 0x0 0x28000>; 3875 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 3876 #dma-cells = <1>; 3877 iommus = <&apps_smmu 0x480 0x0>, 3878 <&apps_smmu 0x481 0x0>; 3879 qcom,ee = <0>; 3880 qcom,controlled-remotely; 3881 num-channels = <20>; 3882 qcom,num-ees = <4>; 3883 }; 3884 3885 crypto: crypto@1dfa000 { 3886 compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce"; 3887 reg = <0x0 0x01dfa000 0x0 0x6000>; 3888 dmas = <&cryptobam 4>, <&cryptobam 5>; 3889 dma-names = "rx", 3890 "tx"; 3891 iommus = <&apps_smmu 0x480 0x0>, 3892 <&apps_smmu 0x481 0x0>; 3893 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 3894 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3895 interconnect-names = "memory"; 3896 }; 3897 3898 tcsr_mutex: hwlock@1f40000 { 3899 compatible = "qcom,tcsr-mutex"; 3900 reg = <0 0x01f40000 0 0x20000>; 3901 #hwlock-cells = <1>; 3902 }; 3903 3904 tcsr: clock-controller@1fc0000 { 3905 compatible = "qcom,x1e80100-tcsr", "syscon"; 3906 reg = <0 0x01fc0000 0 0x30000>; 3907 clocks = <&rpmhcc RPMH_CXO_CLK>; 3908 #clock-cells = <1>; 3909 #reset-cells = <1>; 3910 }; 3911 3912 gpu: gpu@3d00000 { 3913 compatible = "qcom,adreno-43050c01", "qcom,adreno"; 3914 reg = <0x0 0x03d00000 0x0 0x40000>, 3915 <0x0 0x03d9e000 0x0 0x1000>, 3916 <0x0 0x03d61000 0x0 0x800>; 3917 3918 reg-names = "kgsl_3d0_reg_memory", 3919 "cx_mem", 3920 "cx_dbgc"; 3921 3922 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3923 3924 iommus = <&adreno_smmu 0 0x0>, 3925 <&adreno_smmu 1 0x0>; 3926 3927 operating-points-v2 = <&gpu_opp_table>; 3928 3929 qcom,gmu = <&gmu>; 3930 #cooling-cells = <2>; 3931 3932 nvmem-cells = <&gpu_speed_bin>; 3933 nvmem-cell-names = "speed_bin"; 3934 3935 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3936 interconnect-names = "gfx-mem"; 3937 3938 status = "disabled"; 3939 3940 gpu_zap_shader: zap-shader { 3941 memory-region = <&gpu_microcode_mem>; 3942 }; 3943 3944 gpu_opp_table: opp-table { 3945 compatible = "operating-points-v2-adreno", "operating-points-v2"; 3946 3947 opp-1500000000 { 3948 opp-hz = /bits/ 64 <1500000000>; 3949 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>; 3950 opp-peak-kBps = <16500000>; 3951 qcom,opp-acd-level = <0xa82a5ffd>; 3952 opp-supported-hw = <0x03>; 3953 }; 3954 3955 opp-1375000000 { 3956 opp-hz = /bits/ 64 <1375000000>; 3957 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 3958 opp-peak-kBps = <16500000>; 3959 qcom,opp-acd-level = <0xa82a5ffd>; 3960 opp-supported-hw = <0x03>; 3961 }; 3962 3963 opp-1250000000 { 3964 opp-hz = /bits/ 64 <1250000000>; 3965 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 3966 opp-peak-kBps = <16500000>; 3967 qcom,opp-acd-level = <0xa82a5ffd>; 3968 opp-supported-hw = <0x07>; 3969 }; 3970 3971 opp-1175000000 { 3972 opp-hz = /bits/ 64 <1175000000>; 3973 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; 3974 opp-peak-kBps = <14398438>; 3975 qcom,opp-acd-level = <0xa82a5ffd>; 3976 opp-supported-hw = <0x07>; 3977 }; 3978 3979 opp-1100000000-0 { 3980 opp-hz = /bits/ 64 <1100000000>; 3981 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3982 opp-peak-kBps = <14398438>; 3983 qcom,opp-acd-level = <0xa82a5ffd>; 3984 opp-supported-hw = <0x07>; 3985 }; 3986 3987 /* Only applicable for SKUs which has 1100Mhz as Fmax */ 3988 opp-1100000000-1 { 3989 opp-hz = /bits/ 64 <1100000000>; 3990 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3991 opp-peak-kBps = <16500000>; 3992 qcom,opp-acd-level = <0xa82a5ffd>; 3993 opp-supported-hw = <0x08>; 3994 }; 3995 3996 opp-1000000000 { 3997 opp-hz = /bits/ 64 <1000000000>; 3998 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3999 opp-peak-kBps = <14398438>; 4000 qcom,opp-acd-level = <0xa82b5ffd>; 4001 opp-supported-hw = <0x0f>; 4002 }; 4003 4004 opp-925000000 { 4005 opp-hz = /bits/ 64 <925000000>; 4006 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4007 opp-peak-kBps = <14398438>; 4008 qcom,opp-acd-level = <0xa82b5ffd>; 4009 opp-supported-hw = <0x0f>; 4010 }; 4011 4012 opp-800000000 { 4013 opp-hz = /bits/ 64 <800000000>; 4014 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4015 opp-peak-kBps = <12449219>; 4016 qcom,opp-acd-level = <0xa82c5ffd>; 4017 opp-supported-hw = <0x0f>; 4018 }; 4019 4020 opp-744000000 { 4021 opp-hz = /bits/ 64 <744000000>; 4022 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4023 opp-peak-kBps = <10687500>; 4024 qcom,opp-acd-level = <0x882e5ffd>; 4025 opp-supported-hw = <0x0f>; 4026 }; 4027 4028 opp-687000000-0 { 4029 opp-hz = /bits/ 64 <687000000>; 4030 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4031 opp-peak-kBps = <8171875>; 4032 qcom,opp-acd-level = <0x882e5ffd>; 4033 opp-supported-hw = <0x0f>; 4034 }; 4035 4036 /* Only applicable for SKUs which has 687Mhz as Fmax */ 4037 opp-687000000-1 { 4038 opp-hz = /bits/ 64 <687000000>; 4039 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4040 opp-peak-kBps = <16500000>; 4041 qcom,opp-acd-level = <0x882e5ffd>; 4042 opp-supported-hw = <0x10>; 4043 }; 4044 4045 opp-550000000 { 4046 opp-hz = /bits/ 64 <550000000>; 4047 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4048 opp-peak-kBps = <6074219>; 4049 qcom,opp-acd-level = <0xc0285ffd>; 4050 opp-supported-hw = <0x1f>; 4051 }; 4052 4053 opp-390000000 { 4054 opp-hz = /bits/ 64 <390000000>; 4055 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4056 opp-peak-kBps = <3000000>; 4057 qcom,opp-acd-level = <0xc0285ffd>; 4058 opp-supported-hw = <0x1f>; 4059 }; 4060 4061 opp-300000000 { 4062 opp-hz = /bits/ 64 <300000000>; 4063 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4064 opp-peak-kBps = <2136719>; 4065 qcom,opp-acd-level = <0xc02b5ffd>; 4066 opp-supported-hw = <0x1f>; 4067 }; 4068 }; 4069 }; 4070 4071 gmu: gmu@3d6a000 { 4072 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; 4073 reg = <0x0 0x03d6a000 0x0 0x35000>, 4074 <0x0 0x03d50000 0x0 0x10000>, 4075 <0x0 0x0b280000 0x0 0x10000>; 4076 reg-names = "gmu", "rscc", "gmu_pdc"; 4077 4078 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4080 interrupt-names = "hfi", "gmu"; 4081 4082 clocks = <&gpucc GPU_CC_AHB_CLK>, 4083 <&gpucc GPU_CC_CX_GMU_CLK>, 4084 <&gpucc GPU_CC_CXO_CLK>, 4085 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4086 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4087 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4088 <&gpucc GPU_CC_DEMET_CLK>; 4089 clock-names = "ahb", 4090 "gmu", 4091 "cxo", 4092 "axi", 4093 "memnoc", 4094 "hub", 4095 "demet"; 4096 4097 power-domains = <&gpucc GPU_CX_GDSC>, 4098 <&gpucc GPU_GX_GDSC>; 4099 power-domain-names = "cx", 4100 "gx"; 4101 4102 iommus = <&adreno_smmu 5 0x0>; 4103 4104 qcom,qmp = <&aoss_qmp>; 4105 4106 operating-points-v2 = <&gmu_opp_table>; 4107 4108 gmu_opp_table: opp-table { 4109 compatible = "operating-points-v2"; 4110 4111 opp-550000000 { 4112 opp-hz = /bits/ 64 <550000000>; 4113 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4114 }; 4115 4116 opp-220000000 { 4117 opp-hz = /bits/ 64 <220000000>; 4118 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4119 }; 4120 }; 4121 }; 4122 4123 gpucc: clock-controller@3d90000 { 4124 compatible = "qcom,x1e80100-gpucc"; 4125 reg = <0 0x03d90000 0 0xa000>; 4126 clocks = <&bi_tcxo_div2>, 4127 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, 4128 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; 4129 #clock-cells = <1>; 4130 #reset-cells = <1>; 4131 #power-domain-cells = <1>; 4132 }; 4133 4134 adreno_smmu: iommu@3da0000 { 4135 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu", 4136 "qcom,smmu-500", "arm,mmu-500"; 4137 reg = <0x0 0x03da0000 0x0 0x40000>; 4138 #iommu-cells = <2>; 4139 #global-interrupts = <1>; 4140 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 4141 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4142 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4143 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4144 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4145 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4146 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4147 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4148 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4149 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4150 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 4151 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 4152 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4153 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 4154 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 4155 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 4156 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 4157 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 4158 <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, 4159 <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 4160 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 4161 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 4162 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 4163 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 4164 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 4165 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 4166 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4167 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4168 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4169 <&gpucc GPU_CC_AHB_CLK>; 4170 clock-names = "hlos", 4171 "bus", 4172 "iface", 4173 "ahb"; 4174 power-domains = <&gpucc GPU_CX_GDSC>; 4175 dma-coherent; 4176 }; 4177 4178 gem_noc: interconnect@26400000 { 4179 compatible = "qcom,x1e80100-gem-noc"; 4180 reg = <0 0x26400000 0 0x311200>; 4181 4182 qcom,bcm-voters = <&apps_bcm_voter>; 4183 4184 #interconnect-cells = <2>; 4185 }; 4186 4187 nsp_noc: interconnect@320c0000 { 4188 compatible = "qcom,x1e80100-nsp-noc"; 4189 reg = <0 0x320c0000 0 0xe080>; 4190 4191 qcom,bcm-voters = <&apps_bcm_voter>; 4192 4193 #interconnect-cells = <2>; 4194 }; 4195 4196 remoteproc_adsp: remoteproc@6800000 { 4197 compatible = "qcom,x1e80100-adsp-pas"; 4198 reg = <0x0 0x06800000 0x0 0x10000>; 4199 4200 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4201 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4202 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4203 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4204 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4205 interrupt-names = "wdog", 4206 "fatal", 4207 "ready", 4208 "handover", 4209 "stop-ack"; 4210 4211 clocks = <&rpmhcc RPMH_CXO_CLK>; 4212 clock-names = "xo"; 4213 4214 power-domains = <&rpmhpd RPMHPD_LCX>, 4215 <&rpmhpd RPMHPD_LMX>; 4216 power-domain-names = "lcx", 4217 "lmx"; 4218 4219 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 4220 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4221 4222 memory-region = <&adspslpi_mem>, 4223 <&q6_adsp_dtb_mem>; 4224 4225 qcom,qmp = <&aoss_qmp>; 4226 4227 qcom,smem-states = <&smp2p_adsp_out 0>; 4228 qcom,smem-state-names = "stop"; 4229 4230 status = "disabled"; 4231 4232 glink-edge { 4233 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4234 IPCC_MPROC_SIGNAL_GLINK_QMP 4235 IRQ_TYPE_EDGE_RISING>; 4236 mboxes = <&ipcc IPCC_CLIENT_LPASS 4237 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4238 4239 label = "lpass"; 4240 qcom,remote-pid = <2>; 4241 4242 fastrpc { 4243 compatible = "qcom,fastrpc"; 4244 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4245 label = "adsp"; 4246 qcom,non-secure-domain; 4247 #address-cells = <1>; 4248 #size-cells = <0>; 4249 4250 compute-cb@3 { 4251 compatible = "qcom,fastrpc-compute-cb"; 4252 reg = <3>; 4253 iommus = <&apps_smmu 0x1003 0x80>, 4254 <&apps_smmu 0x1063 0x0>; 4255 dma-coherent; 4256 }; 4257 4258 compute-cb@4 { 4259 compatible = "qcom,fastrpc-compute-cb"; 4260 reg = <4>; 4261 iommus = <&apps_smmu 0x1004 0x80>, 4262 <&apps_smmu 0x1064 0x0>; 4263 dma-coherent; 4264 }; 4265 4266 compute-cb@5 { 4267 compatible = "qcom,fastrpc-compute-cb"; 4268 reg = <5>; 4269 iommus = <&apps_smmu 0x1005 0x80>, 4270 <&apps_smmu 0x1065 0x0>; 4271 dma-coherent; 4272 }; 4273 4274 compute-cb@6 { 4275 compatible = "qcom,fastrpc-compute-cb"; 4276 reg = <6>; 4277 iommus = <&apps_smmu 0x1006 0x80>, 4278 <&apps_smmu 0x1066 0x0>; 4279 dma-coherent; 4280 }; 4281 4282 compute-cb@7 { 4283 compatible = "qcom,fastrpc-compute-cb"; 4284 reg = <7>; 4285 iommus = <&apps_smmu 0x1007 0x80>, 4286 <&apps_smmu 0x1067 0x0>; 4287 dma-coherent; 4288 }; 4289 }; 4290 4291 gpr { 4292 compatible = "qcom,gpr"; 4293 qcom,glink-channels = "adsp_apps"; 4294 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4295 qcom,intents = <512 20>; 4296 #address-cells = <1>; 4297 #size-cells = <0>; 4298 4299 q6apm: service@1 { 4300 compatible = "qcom,q6apm"; 4301 reg = <GPR_APM_MODULE_IID>; 4302 #sound-dai-cells = <0>; 4303 qcom,protection-domain = "avs/audio", 4304 "msm/adsp/audio_pd"; 4305 4306 q6apmbedai: bedais { 4307 compatible = "qcom,q6apm-lpass-dais"; 4308 #sound-dai-cells = <1>; 4309 }; 4310 4311 q6apmdai: dais { 4312 compatible = "qcom,q6apm-dais"; 4313 iommus = <&apps_smmu 0x1001 0x80>, 4314 <&apps_smmu 0x1061 0x0>; 4315 }; 4316 }; 4317 4318 q6prm: service@2 { 4319 compatible = "qcom,q6prm"; 4320 reg = <GPR_PRM_MODULE_IID>; 4321 qcom,protection-domain = "avs/audio", 4322 "msm/adsp/audio_pd"; 4323 4324 q6prmcc: clock-controller { 4325 compatible = "qcom,q6prm-lpass-clocks"; 4326 #clock-cells = <2>; 4327 }; 4328 }; 4329 }; 4330 }; 4331 }; 4332 4333 lpass_wsa2macro: codec@6aa0000 { 4334 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4335 reg = <0 0x06aa0000 0 0x1000>; 4336 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4337 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4338 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4339 <&lpass_vamacro>; 4340 clock-names = "mclk", 4341 "macro", 4342 "dcodec", 4343 "fsgen"; 4344 4345 #clock-cells = <0>; 4346 clock-output-names = "wsa2-mclk"; 4347 #sound-dai-cells = <1>; 4348 sound-name-prefix = "WSA2"; 4349 }; 4350 4351 swr3: soundwire@6ab0000 { 4352 compatible = "qcom,soundwire-v2.0.0"; 4353 reg = <0 0x06ab0000 0 0x10000>; 4354 clocks = <&lpass_wsa2macro>; 4355 clock-names = "iface"; 4356 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 4357 label = "WSA2"; 4358 4359 pinctrl-0 = <&wsa2_swr_active>; 4360 pinctrl-names = "default"; 4361 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>; 4362 reset-names = "swr_audio_cgcr"; 4363 4364 qcom,din-ports = <4>; 4365 qcom,dout-ports = <9>; 4366 4367 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4368 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4369 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4370 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4371 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4372 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4373 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4374 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4375 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4376 4377 #address-cells = <2>; 4378 #size-cells = <0>; 4379 #sound-dai-cells = <1>; 4380 status = "disabled"; 4381 }; 4382 4383 lpass_rxmacro: codec@6ac0000 { 4384 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 4385 reg = <0 0x06ac0000 0 0x1000>; 4386 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4387 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4388 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4389 <&lpass_vamacro>; 4390 clock-names = "mclk", 4391 "macro", 4392 "dcodec", 4393 "fsgen"; 4394 4395 #clock-cells = <0>; 4396 clock-output-names = "mclk"; 4397 #sound-dai-cells = <1>; 4398 }; 4399 4400 swr1: soundwire@6ad0000 { 4401 compatible = "qcom,soundwire-v2.0.0"; 4402 reg = <0 0x06ad0000 0 0x10000>; 4403 clocks = <&lpass_rxmacro>; 4404 clock-names = "iface"; 4405 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 4406 label = "RX"; 4407 4408 pinctrl-0 = <&rx_swr_active>; 4409 pinctrl-names = "default"; 4410 4411 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 4412 reset-names = "swr_audio_cgcr"; 4413 qcom,din-ports = <1>; 4414 qcom,dout-ports = <11>; 4415 4416 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4417 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4418 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4419 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4420 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4421 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4422 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4423 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4424 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4425 4426 #address-cells = <2>; 4427 #size-cells = <0>; 4428 #sound-dai-cells = <1>; 4429 status = "disabled"; 4430 }; 4431 4432 lpass_txmacro: codec@6ae0000 { 4433 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 4434 reg = <0 0x06ae0000 0 0x1000>; 4435 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4436 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4437 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4438 <&lpass_vamacro>; 4439 clock-names = "mclk", 4440 "macro", 4441 "dcodec", 4442 "fsgen"; 4443 4444 #clock-cells = <0>; 4445 clock-output-names = "mclk"; 4446 #sound-dai-cells = <1>; 4447 }; 4448 4449 lpass_wsamacro: codec@6b00000 { 4450 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4451 reg = <0 0x06b00000 0 0x1000>; 4452 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4453 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4454 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4455 <&lpass_vamacro>; 4456 clock-names = "mclk", 4457 "macro", 4458 "dcodec", 4459 "fsgen"; 4460 4461 #clock-cells = <0>; 4462 clock-output-names = "mclk"; 4463 #sound-dai-cells = <1>; 4464 sound-name-prefix = "WSA"; 4465 }; 4466 4467 swr0: soundwire@6b10000 { 4468 compatible = "qcom,soundwire-v2.0.0"; 4469 reg = <0 0x06b10000 0 0x10000>; 4470 clocks = <&lpass_wsamacro>; 4471 clock-names = "iface"; 4472 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 4473 label = "WSA"; 4474 4475 pinctrl-0 = <&wsa_swr_active>; 4476 pinctrl-names = "default"; 4477 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 4478 reset-names = "swr_audio_cgcr"; 4479 4480 qcom,din-ports = <4>; 4481 qcom,dout-ports = <9>; 4482 4483 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4484 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4485 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4486 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4487 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4488 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4489 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4490 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4491 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4492 4493 #address-cells = <2>; 4494 #size-cells = <0>; 4495 #sound-dai-cells = <1>; 4496 status = "disabled"; 4497 }; 4498 4499 lpass_audiocc: clock-controller@6b6c000 { 4500 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc"; 4501 reg = <0 0x06b6c000 0 0x1000>; 4502 #clock-cells = <1>; 4503 #reset-cells = <1>; 4504 }; 4505 4506 swr2: soundwire@6d30000 { 4507 compatible = "qcom,soundwire-v2.0.0"; 4508 reg = <0 0x06d30000 0 0x10000>; 4509 clocks = <&lpass_txmacro>; 4510 clock-names = "iface"; 4511 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 4512 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 4513 interrupt-names = "core", "wakeup"; 4514 label = "TX"; 4515 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 4516 reset-names = "swr_audio_cgcr"; 4517 4518 pinctrl-0 = <&tx_swr_active>; 4519 pinctrl-names = "default"; 4520 4521 qcom,din-ports = <4>; 4522 qcom,dout-ports = <1>; 4523 4524 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>; 4525 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>; 4526 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>; 4527 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4528 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4529 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4530 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4531 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4532 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>; 4533 4534 #address-cells = <2>; 4535 #size-cells = <0>; 4536 #sound-dai-cells = <1>; 4537 status = "disabled"; 4538 }; 4539 4540 lpass_vamacro: codec@6d44000 { 4541 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 4542 reg = <0 0x06d44000 0 0x1000>; 4543 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4544 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4545 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4546 clock-names = "mclk", 4547 "macro", 4548 "dcodec"; 4549 4550 #clock-cells = <0>; 4551 clock-output-names = "fsgen"; 4552 #sound-dai-cells = <1>; 4553 }; 4554 4555 lpass_tlmm: pinctrl@6e80000 { 4556 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl"; 4557 reg = <0 0x06e80000 0 0x20000>, 4558 <0 0x07250000 0 0x10000>; 4559 4560 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4561 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4562 clock-names = "core", "audio"; 4563 4564 gpio-controller; 4565 #gpio-cells = <2>; 4566 gpio-ranges = <&lpass_tlmm 0 0 23>; 4567 4568 tx_swr_active: tx-swr-active-state { 4569 clk-pins { 4570 pins = "gpio0"; 4571 function = "swr_tx_clk"; 4572 drive-strength = <2>; 4573 slew-rate = <1>; 4574 bias-disable; 4575 }; 4576 4577 data-pins { 4578 pins = "gpio1", "gpio2"; 4579 function = "swr_tx_data"; 4580 drive-strength = <2>; 4581 slew-rate = <1>; 4582 bias-bus-hold; 4583 }; 4584 }; 4585 4586 rx_swr_active: rx-swr-active-state { 4587 clk-pins { 4588 pins = "gpio3"; 4589 function = "swr_rx_clk"; 4590 drive-strength = <2>; 4591 slew-rate = <1>; 4592 bias-disable; 4593 }; 4594 4595 data-pins { 4596 pins = "gpio4", "gpio5"; 4597 function = "swr_rx_data"; 4598 drive-strength = <2>; 4599 slew-rate = <1>; 4600 bias-bus-hold; 4601 }; 4602 }; 4603 4604 dmic01_default: dmic01-default-state { 4605 clk-pins { 4606 pins = "gpio6"; 4607 function = "dmic1_clk"; 4608 drive-strength = <8>; 4609 output-high; 4610 }; 4611 4612 data-pins { 4613 pins = "gpio7"; 4614 function = "dmic1_data"; 4615 drive-strength = <8>; 4616 input-enable; 4617 }; 4618 }; 4619 4620 dmic23_default: dmic23-default-state { 4621 clk-pins { 4622 pins = "gpio8"; 4623 function = "dmic2_clk"; 4624 drive-strength = <8>; 4625 output-high; 4626 }; 4627 4628 data-pins { 4629 pins = "gpio9"; 4630 function = "dmic2_data"; 4631 drive-strength = <8>; 4632 input-enable; 4633 }; 4634 }; 4635 4636 wsa_swr_active: wsa-swr-active-state { 4637 clk-pins { 4638 pins = "gpio10"; 4639 function = "wsa_swr_clk"; 4640 drive-strength = <2>; 4641 slew-rate = <1>; 4642 bias-disable; 4643 }; 4644 4645 data-pins { 4646 pins = "gpio11"; 4647 function = "wsa_swr_data"; 4648 drive-strength = <2>; 4649 slew-rate = <1>; 4650 bias-bus-hold; 4651 }; 4652 }; 4653 4654 wsa2_swr_active: wsa2-swr-active-state { 4655 clk-pins { 4656 pins = "gpio15"; 4657 function = "wsa2_swr_clk"; 4658 drive-strength = <2>; 4659 slew-rate = <1>; 4660 bias-disable; 4661 }; 4662 4663 data-pins { 4664 pins = "gpio16"; 4665 function = "wsa2_swr_data"; 4666 drive-strength = <2>; 4667 slew-rate = <1>; 4668 bias-bus-hold; 4669 }; 4670 }; 4671 }; 4672 4673 lpasscc: clock-controller@6ea0000 { 4674 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc"; 4675 reg = <0 0x06ea0000 0 0x12000>; 4676 #clock-cells = <1>; 4677 #reset-cells = <1>; 4678 }; 4679 4680 lpass_ag_noc: interconnect@7e40000 { 4681 compatible = "qcom,x1e80100-lpass-ag-noc"; 4682 reg = <0 0x07e40000 0 0xe080>; 4683 4684 qcom,bcm-voters = <&apps_bcm_voter>; 4685 4686 #interconnect-cells = <2>; 4687 }; 4688 4689 lpass_lpiaon_noc: interconnect@7400000 { 4690 compatible = "qcom,x1e80100-lpass-lpiaon-noc"; 4691 reg = <0 0x07400000 0 0x19080>; 4692 4693 qcom,bcm-voters = <&apps_bcm_voter>; 4694 4695 #interconnect-cells = <2>; 4696 }; 4697 4698 lpass_lpicx_noc: interconnect@7430000 { 4699 compatible = "qcom,x1e80100-lpass-lpicx-noc"; 4700 reg = <0 0x07430000 0 0x3a200>; 4701 4702 qcom,bcm-voters = <&apps_bcm_voter>; 4703 4704 #interconnect-cells = <2>; 4705 }; 4706 4707 sdhc_2: mmc@8804000 { 4708 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; 4709 reg = <0 0x08804000 0 0x1000>; 4710 4711 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4712 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4713 interrupt-names = "hc_irq", "pwr_irq"; 4714 4715 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4716 <&gcc GCC_SDCC2_APPS_CLK>, 4717 <&rpmhcc RPMH_CXO_CLK>; 4718 clock-names = "iface", "core", "xo"; 4719 iommus = <&apps_smmu 0x520 0>; 4720 qcom,dll-config = <0x0007642c>; 4721 qcom,ddr-config = <0x80040868>; 4722 power-domains = <&rpmhpd RPMHPD_CX>; 4723 operating-points-v2 = <&sdhc2_opp_table>; 4724 4725 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 4726 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4727 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4728 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4729 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 4730 bus-width = <4>; 4731 dma-coherent; 4732 4733 status = "disabled"; 4734 4735 sdhc2_opp_table: opp-table { 4736 compatible = "operating-points-v2"; 4737 4738 opp-19200000 { 4739 opp-hz = /bits/ 64 <19200000>; 4740 required-opps = <&rpmhpd_opp_min_svs>; 4741 }; 4742 4743 opp-50000000 { 4744 opp-hz = /bits/ 64 <50000000>; 4745 required-opps = <&rpmhpd_opp_low_svs>; 4746 }; 4747 4748 opp-100000000 { 4749 opp-hz = /bits/ 64 <100000000>; 4750 required-opps = <&rpmhpd_opp_svs>; 4751 }; 4752 4753 opp-202000000 { 4754 opp-hz = /bits/ 64 <202000000>; 4755 required-opps = <&rpmhpd_opp_svs_l1>; 4756 }; 4757 }; 4758 }; 4759 4760 sdhc_4: mmc@8844000 { 4761 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; 4762 reg = <0 0x08844000 0 0x1000>; 4763 4764 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 4765 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 4766 interrupt-names = "hc_irq", "pwr_irq"; 4767 4768 clocks = <&gcc GCC_SDCC4_AHB_CLK>, 4769 <&gcc GCC_SDCC4_APPS_CLK>, 4770 <&rpmhcc RPMH_CXO_CLK>; 4771 clock-names = "iface", "core", "xo"; 4772 iommus = <&apps_smmu 0x160 0>; 4773 qcom,dll-config = <0x0007642c>; 4774 qcom,ddr-config = <0x80040868>; 4775 power-domains = <&rpmhpd RPMHPD_CX>; 4776 operating-points-v2 = <&sdhc4_opp_table>; 4777 4778 interconnects = <&aggre2_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS 4779 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4780 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4781 &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 4782 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 4783 bus-width = <4>; 4784 dma-coherent; 4785 4786 status = "disabled"; 4787 4788 sdhc4_opp_table: opp-table { 4789 compatible = "operating-points-v2"; 4790 4791 opp-19200000 { 4792 opp-hz = /bits/ 64 <19200000>; 4793 required-opps = <&rpmhpd_opp_min_svs>; 4794 }; 4795 4796 opp-50000000 { 4797 opp-hz = /bits/ 64 <50000000>; 4798 required-opps = <&rpmhpd_opp_low_svs>; 4799 }; 4800 4801 opp-100000000 { 4802 opp-hz = /bits/ 64 <100000000>; 4803 required-opps = <&rpmhpd_opp_svs>; 4804 }; 4805 4806 opp-202000000 { 4807 opp-hz = /bits/ 64 <202000000>; 4808 required-opps = <&rpmhpd_opp_svs_l1>; 4809 }; 4810 }; 4811 }; 4812 4813 usb_2_hsphy: phy@88e0000 { 4814 compatible = "qcom,x1e80100-snps-eusb2-phy", 4815 "qcom,sm8550-snps-eusb2-phy"; 4816 reg = <0 0x088e0000 0 0x154>; 4817 #phy-cells = <0>; 4818 4819 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 4820 clock-names = "ref"; 4821 4822 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 4823 4824 status = "disabled"; 4825 }; 4826 4827 usb_mp_hsphy0: phy@88e1000 { 4828 compatible = "qcom,x1e80100-snps-eusb2-phy", 4829 "qcom,sm8550-snps-eusb2-phy"; 4830 reg = <0 0x088e1000 0 0x154>; 4831 #phy-cells = <0>; 4832 4833 clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>; 4834 clock-names = "ref"; 4835 4836 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 4837 4838 status = "disabled"; 4839 }; 4840 4841 usb_mp_hsphy1: phy@88e2000 { 4842 compatible = "qcom,x1e80100-snps-eusb2-phy", 4843 "qcom,sm8550-snps-eusb2-phy"; 4844 reg = <0 0x088e2000 0 0x154>; 4845 #phy-cells = <0>; 4846 4847 clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>; 4848 clock-names = "ref"; 4849 4850 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 4851 4852 status = "disabled"; 4853 }; 4854 4855 usb_mp_qmpphy0: phy@88e3000 { 4856 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4857 reg = <0 0x088e3000 0 0x2000>; 4858 4859 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4860 <&rpmhcc RPMH_CXO_CLK>, 4861 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4862 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 4863 clock-names = "aux", 4864 "ref", 4865 "com_aux", 4866 "pipe"; 4867 4868 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 4869 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 4870 reset-names = "phy", 4871 "phy_phy"; 4872 4873 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 4874 4875 #clock-cells = <0>; 4876 clock-output-names = "usb_mp_phy0_pipe_clk"; 4877 4878 #phy-cells = <0>; 4879 4880 status = "disabled"; 4881 }; 4882 4883 usb_mp_qmpphy1: phy@88e5000 { 4884 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4885 reg = <0 0x088e5000 0 0x2000>; 4886 4887 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4888 <&rpmhcc RPMH_CXO_CLK>, 4889 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4890 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 4891 clock-names = "aux", 4892 "ref", 4893 "com_aux", 4894 "pipe"; 4895 4896 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 4897 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 4898 reset-names = "phy", 4899 "phy_phy"; 4900 4901 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 4902 4903 #clock-cells = <0>; 4904 clock-output-names = "usb_mp_phy1_pipe_clk"; 4905 4906 #phy-cells = <0>; 4907 4908 status = "disabled"; 4909 }; 4910 4911 usb_1_ss2: usb@a0f8800 { 4912 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4913 reg = <0 0x0a0f8800 0 0x400>; 4914 4915 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 4916 <&gcc GCC_USB30_TERT_MASTER_CLK>, 4917 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 4918 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 4919 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4920 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4921 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4922 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4923 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4924 clock-names = "cfg_noc", 4925 "core", 4926 "iface", 4927 "sleep", 4928 "mock_utmi", 4929 "noc_aggr", 4930 "noc_aggr_north", 4931 "noc_aggr_south", 4932 "noc_sys"; 4933 4934 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4935 <&gcc GCC_USB30_TERT_MASTER_CLK>; 4936 assigned-clock-rates = <19200000>, 4937 <200000000>; 4938 4939 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 4940 <&pdc 58 IRQ_TYPE_EDGE_BOTH>, 4941 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 4942 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>; 4943 interrupt-names = "pwr_event", 4944 "dp_hs_phy_irq", 4945 "dm_hs_phy_irq", 4946 "ss_phy_irq"; 4947 4948 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 4949 required-opps = <&rpmhpd_opp_nom>; 4950 4951 resets = <&gcc GCC_USB30_TERT_BCR>; 4952 4953 interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS 4954 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4955 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4956 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4957 interconnect-names = "usb-ddr", 4958 "apps-usb"; 4959 4960 wakeup-source; 4961 4962 #address-cells = <2>; 4963 #size-cells = <2>; 4964 ranges; 4965 4966 status = "disabled"; 4967 4968 usb_1_ss2_dwc3: usb@a000000 { 4969 compatible = "snps,dwc3"; 4970 reg = <0 0x0a000000 0 0xcd00>; 4971 4972 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 4973 4974 iommus = <&apps_smmu 0x14a0 0x0>; 4975 4976 phys = <&usb_1_ss2_hsphy>, 4977 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; 4978 phy-names = "usb2-phy", 4979 "usb3-phy"; 4980 4981 snps,dis_u2_susphy_quirk; 4982 snps,dis_enblslpm_quirk; 4983 snps,usb3_lpm_capable; 4984 snps,dis-u1-entry-quirk; 4985 snps,dis-u2-entry-quirk; 4986 4987 dma-coherent; 4988 4989 ports { 4990 #address-cells = <1>; 4991 #size-cells = <0>; 4992 4993 port@0 { 4994 reg = <0>; 4995 4996 usb_1_ss2_dwc3_hs: endpoint { 4997 }; 4998 }; 4999 5000 port@1 { 5001 reg = <1>; 5002 5003 usb_1_ss2_dwc3_ss: endpoint { 5004 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; 5005 }; 5006 }; 5007 }; 5008 }; 5009 }; 5010 5011 usb_2: usb@a2f8800 { 5012 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 5013 reg = <0 0x0a2f8800 0 0x400>; 5014 #address-cells = <2>; 5015 #size-cells = <2>; 5016 ranges; 5017 5018 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 5019 <&gcc GCC_USB20_MASTER_CLK>, 5020 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 5021 <&gcc GCC_USB20_SLEEP_CLK>, 5022 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 5023 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5024 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5025 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5026 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5027 clock-names = "cfg_noc", 5028 "core", 5029 "iface", 5030 "sleep", 5031 "mock_utmi", 5032 "noc_aggr", 5033 "noc_aggr_north", 5034 "noc_aggr_south", 5035 "noc_sys"; 5036 5037 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 5038 <&gcc GCC_USB20_MASTER_CLK>; 5039 assigned-clock-rates = <19200000>, <200000000>; 5040 5041 interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 5042 <&pdc 50 IRQ_TYPE_EDGE_BOTH>, 5043 <&pdc 49 IRQ_TYPE_EDGE_BOTH>; 5044 interrupt-names = "pwr_event", 5045 "dp_hs_phy_irq", 5046 "dm_hs_phy_irq"; 5047 5048 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 5049 required-opps = <&rpmhpd_opp_nom>; 5050 5051 resets = <&gcc GCC_USB20_PRIM_BCR>; 5052 5053 interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 5054 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5055 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5056 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; 5057 interconnect-names = "usb-ddr", 5058 "apps-usb"; 5059 5060 qcom,select-utmi-as-pipe-clk; 5061 wakeup-source; 5062 5063 status = "disabled"; 5064 5065 usb_2_dwc3: usb@a200000 { 5066 compatible = "snps,dwc3"; 5067 reg = <0 0x0a200000 0 0xcd00>; 5068 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 5069 iommus = <&apps_smmu 0x14e0 0x0>; 5070 phys = <&usb_2_hsphy>; 5071 phy-names = "usb2-phy"; 5072 maximum-speed = "high-speed"; 5073 snps,dis-u1-entry-quirk; 5074 snps,dis-u2-entry-quirk; 5075 5076 dma-coherent; 5077 5078 port { 5079 usb_2_dwc3_hs: endpoint { 5080 }; 5081 }; 5082 }; 5083 }; 5084 5085 usb_mp: usb@a4f8800 { 5086 compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3"; 5087 reg = <0 0x0a4f8800 0 0x400>; 5088 5089 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 5090 <&gcc GCC_USB30_MP_MASTER_CLK>, 5091 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 5092 <&gcc GCC_USB30_MP_SLEEP_CLK>, 5093 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 5094 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5095 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5096 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5097 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5098 clock-names = "cfg_noc", 5099 "core", 5100 "iface", 5101 "sleep", 5102 "mock_utmi", 5103 "noc_aggr", 5104 "noc_aggr_north", 5105 "noc_aggr_south", 5106 "noc_sys"; 5107 5108 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 5109 <&gcc GCC_USB30_MP_MASTER_CLK>; 5110 assigned-clock-rates = <19200000>, 5111 <200000000>; 5112 5113 interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 5114 <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 5115 <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 5116 <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 5117 <&pdc 52 IRQ_TYPE_EDGE_BOTH>, 5118 <&pdc 51 IRQ_TYPE_EDGE_BOTH>, 5119 <&pdc 54 IRQ_TYPE_EDGE_BOTH>, 5120 <&pdc 53 IRQ_TYPE_EDGE_BOTH>, 5121 <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, 5122 <&pdc 56 IRQ_TYPE_LEVEL_HIGH>; 5123 interrupt-names = "pwr_event_1", "pwr_event_2", 5124 "hs_phy_1", "hs_phy_2", 5125 "dp_hs_phy_1", "dm_hs_phy_1", 5126 "dp_hs_phy_2", "dm_hs_phy_2", 5127 "ss_phy_1", "ss_phy_2"; 5128 5129 power-domains = <&gcc GCC_USB30_MP_GDSC>; 5130 required-opps = <&rpmhpd_opp_nom>; 5131 5132 resets = <&gcc GCC_USB30_MP_BCR>; 5133 5134 interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS 5135 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5136 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5137 &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ACTIVE_ONLY>; 5138 interconnect-names = "usb-ddr", 5139 "apps-usb"; 5140 5141 wakeup-source; 5142 5143 #address-cells = <2>; 5144 #size-cells = <2>; 5145 ranges; 5146 5147 status = "disabled"; 5148 5149 usb_mp_dwc3: usb@a400000 { 5150 compatible = "snps,dwc3"; 5151 reg = <0 0x0a400000 0 0xcd00>; 5152 5153 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 5154 5155 iommus = <&apps_smmu 0x1400 0x0>; 5156 5157 phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>, 5158 <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>; 5159 phy-names = "usb2-0", "usb3-0", 5160 "usb2-1", "usb3-1"; 5161 dr_mode = "host"; 5162 5163 snps,dis_u2_susphy_quirk; 5164 snps,dis_enblslpm_quirk; 5165 snps,usb3_lpm_capable; 5166 snps,dis-u1-entry-quirk; 5167 snps,dis-u2-entry-quirk; 5168 5169 dma-coherent; 5170 }; 5171 }; 5172 5173 usb_1_ss0: usb@a6f8800 { 5174 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 5175 reg = <0 0x0a6f8800 0 0x400>; 5176 5177 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5178 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5179 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5180 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5181 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5182 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5183 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>, 5184 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>, 5185 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5186 clock-names = "cfg_noc", 5187 "core", 5188 "iface", 5189 "sleep", 5190 "mock_utmi", 5191 "noc_aggr", 5192 "noc_aggr_north", 5193 "noc_aggr_south", 5194 "noc_sys"; 5195 5196 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5197 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5198 assigned-clock-rates = <19200000>, 5199 <200000000>; 5200 5201 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 5202 <&pdc 61 IRQ_TYPE_EDGE_BOTH>, 5203 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 5204 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 5205 interrupt-names = "pwr_event", 5206 "dp_hs_phy_irq", 5207 "dm_hs_phy_irq", 5208 "ss_phy_irq"; 5209 5210 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 5211 required-opps = <&rpmhpd_opp_nom>; 5212 5213 resets = <&gcc GCC_USB30_PRIM_BCR>; 5214 5215 wakeup-source; 5216 5217 #address-cells = <2>; 5218 #size-cells = <2>; 5219 ranges; 5220 5221 status = "disabled"; 5222 5223 usb_1_ss0_dwc3: usb@a600000 { 5224 compatible = "snps,dwc3"; 5225 reg = <0 0x0a600000 0 0xcd00>; 5226 5227 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 5228 5229 iommus = <&apps_smmu 0x1420 0x0>; 5230 5231 phys = <&usb_1_ss0_hsphy>, 5232 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; 5233 phy-names = "usb2-phy", 5234 "usb3-phy"; 5235 5236 snps,dis_u2_susphy_quirk; 5237 snps,dis_enblslpm_quirk; 5238 snps,usb3_lpm_capable; 5239 snps,dis-u1-entry-quirk; 5240 snps,dis-u2-entry-quirk; 5241 5242 dma-coherent; 5243 5244 ports { 5245 #address-cells = <1>; 5246 #size-cells = <0>; 5247 5248 port@0 { 5249 reg = <0>; 5250 5251 usb_1_ss0_dwc3_hs: endpoint { 5252 }; 5253 }; 5254 5255 port@1 { 5256 reg = <1>; 5257 5258 usb_1_ss0_dwc3_ss: endpoint { 5259 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; 5260 }; 5261 }; 5262 }; 5263 }; 5264 }; 5265 5266 usb_1_ss1: usb@a8f8800 { 5267 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 5268 reg = <0 0x0a8f8800 0 0x400>; 5269 5270 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 5271 <&gcc GCC_USB30_SEC_MASTER_CLK>, 5272 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 5273 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 5274 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5275 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5276 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5277 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5278 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5279 clock-names = "cfg_noc", 5280 "core", 5281 "iface", 5282 "sleep", 5283 "mock_utmi", 5284 "noc_aggr", 5285 "noc_aggr_north", 5286 "noc_aggr_south", 5287 "noc_sys"; 5288 5289 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5290 <&gcc GCC_USB30_SEC_MASTER_CLK>; 5291 assigned-clock-rates = <19200000>, 5292 <200000000>; 5293 5294 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 5295 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 5296 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 5297 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; 5298 interrupt-names = "pwr_event", 5299 "dp_hs_phy_irq", 5300 "dm_hs_phy_irq", 5301 "ss_phy_irq"; 5302 5303 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 5304 required-opps = <&rpmhpd_opp_nom>; 5305 5306 resets = <&gcc GCC_USB30_SEC_BCR>; 5307 5308 interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS 5309 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5310 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5311 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5312 interconnect-names = "usb-ddr", 5313 "apps-usb"; 5314 5315 wakeup-source; 5316 5317 #address-cells = <2>; 5318 #size-cells = <2>; 5319 ranges; 5320 5321 status = "disabled"; 5322 5323 usb_1_ss1_dwc3: usb@a800000 { 5324 compatible = "snps,dwc3"; 5325 reg = <0 0x0a800000 0 0xcd00>; 5326 5327 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 5328 5329 iommus = <&apps_smmu 0x1460 0x0>; 5330 5331 phys = <&usb_1_ss1_hsphy>, 5332 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; 5333 phy-names = "usb2-phy", 5334 "usb3-phy"; 5335 5336 snps,dis_u2_susphy_quirk; 5337 snps,dis_enblslpm_quirk; 5338 snps,usb3_lpm_capable; 5339 snps,dis-u1-entry-quirk; 5340 snps,dis-u2-entry-quirk; 5341 5342 dma-coherent; 5343 5344 ports { 5345 #address-cells = <1>; 5346 #size-cells = <0>; 5347 5348 port@0 { 5349 reg = <0>; 5350 5351 usb_1_ss1_dwc3_hs: endpoint { 5352 }; 5353 }; 5354 5355 port@1 { 5356 reg = <1>; 5357 5358 usb_1_ss1_dwc3_ss: endpoint { 5359 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; 5360 }; 5361 }; 5362 }; 5363 }; 5364 }; 5365 5366 iris: video-codec@aa00000 { 5367 compatible = "qcom,x1e80100-iris", "qcom,sm8550-iris"; 5368 5369 reg = <0 0x0aa00000 0 0xf0000>; 5370 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 5371 5372 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 5373 <&videocc VIDEO_CC_MVS0_GDSC>, 5374 <&rpmhpd RPMHPD_MXC>, 5375 <&rpmhpd RPMHPD_MMCX>; 5376 power-domain-names = "venus", 5377 "vcodec0", 5378 "mxc", 5379 "mmcx"; 5380 operating-points-v2 = <&iris_opp_table>; 5381 5382 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 5383 <&videocc VIDEO_CC_MVS0C_CLK>, 5384 <&videocc VIDEO_CC_MVS0_CLK>; 5385 clock-names = "iface", 5386 "core", 5387 "vcodec0_core"; 5388 5389 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5390 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5391 <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS 5392 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5393 interconnect-names = "cpu-cfg", 5394 "video-mem"; 5395 5396 memory-region = <&video_mem>; 5397 5398 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 5399 reset-names = "bus"; 5400 5401 iommus = <&apps_smmu 0x1940 0>, 5402 <&apps_smmu 0x1947 0>; 5403 dma-coherent; 5404 5405 /* 5406 * IRIS firmware is signed by vendors, only 5407 * enable on boards where the proper signed firmware 5408 * is available. 5409 */ 5410 status = "disabled"; 5411 5412 iris_opp_table: opp-table { 5413 compatible = "operating-points-v2"; 5414 5415 opp-192000000 { 5416 opp-hz = /bits/ 64 <192000000>; 5417 required-opps = <&rpmhpd_opp_low_svs_d1>, 5418 <&rpmhpd_opp_low_svs_d1>; 5419 }; 5420 5421 opp-240000000 { 5422 opp-hz = /bits/ 64 <240000000>; 5423 required-opps = <&rpmhpd_opp_svs>, 5424 <&rpmhpd_opp_low_svs>; 5425 }; 5426 5427 opp-338000000 { 5428 opp-hz = /bits/ 64 <338000000>; 5429 required-opps = <&rpmhpd_opp_svs>, 5430 <&rpmhpd_opp_svs>; 5431 }; 5432 5433 opp-366000000 { 5434 opp-hz = /bits/ 64 <366000000>; 5435 required-opps = <&rpmhpd_opp_svs_l1>, 5436 <&rpmhpd_opp_svs_l1>; 5437 }; 5438 5439 opp-444000000 { 5440 opp-hz = /bits/ 64 <444000000>; 5441 required-opps = <&rpmhpd_opp_nom>, 5442 <&rpmhpd_opp_nom>; 5443 }; 5444 5445 opp-481000000 { 5446 opp-hz = /bits/ 64 <481000000>; 5447 required-opps = <&rpmhpd_opp_turbo>, 5448 <&rpmhpd_opp_turbo>; 5449 }; 5450 }; 5451 }; 5452 5453 videocc: clock-controller@aaf0000 { 5454 compatible = "qcom,x1e80100-videocc"; 5455 reg = <0 0x0aaf0000 0 0x10000>; 5456 clocks = <&bi_tcxo_div2>, 5457 <&gcc GCC_VIDEO_AHB_CLK>; 5458 power-domains = <&rpmhpd RPMHPD_MMCX>, 5459 <&rpmhpd RPMHPD_MXC>; 5460 required-opps = <&rpmhpd_opp_low_svs>, 5461 <&rpmhpd_opp_low_svs>; 5462 #clock-cells = <1>; 5463 #reset-cells = <1>; 5464 #power-domain-cells = <1>; 5465 }; 5466 5467 mdss: display-subsystem@ae00000 { 5468 compatible = "qcom,x1e80100-mdss"; 5469 reg = <0 0x0ae00000 0 0x1000>; 5470 reg-names = "mdss"; 5471 5472 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 5473 5474 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5475 <&gcc GCC_DISP_HF_AXI_CLK>, 5476 <&dispcc DISP_CC_MDSS_MDP_CLK>; 5477 5478 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 5479 5480 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 5481 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 5482 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 5483 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5484 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5485 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5486 interconnect-names = "mdp0-mem", 5487 "mdp1-mem", 5488 "cpu-cfg"; 5489 5490 power-domains = <&dispcc MDSS_GDSC>; 5491 5492 iommus = <&apps_smmu 0x1c00 0x2>; 5493 5494 interrupt-controller; 5495 #interrupt-cells = <1>; 5496 5497 #address-cells = <2>; 5498 #size-cells = <2>; 5499 ranges; 5500 5501 status = "disabled"; 5502 5503 mdss_mdp: display-controller@ae01000 { 5504 compatible = "qcom,x1e80100-dpu"; 5505 reg = <0 0x0ae01000 0 0x8f000>, 5506 <0 0x0aeb0000 0 0x2008>; 5507 reg-names = "mdp", 5508 "vbif"; 5509 5510 interrupts-extended = <&mdss 0>; 5511 5512 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5513 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5514 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 5515 <&dispcc DISP_CC_MDSS_MDP_CLK>, 5516 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5517 clock-names = "nrt_bus", 5518 "iface", 5519 "lut", 5520 "core", 5521 "vsync"; 5522 5523 operating-points-v2 = <&mdp_opp_table>; 5524 5525 power-domains = <&rpmhpd RPMHPD_MMCX>; 5526 5527 ports { 5528 #address-cells = <1>; 5529 #size-cells = <0>; 5530 5531 port@0 { 5532 reg = <0>; 5533 5534 mdss_intf0_out: endpoint { 5535 remote-endpoint = <&mdss_dp0_in>; 5536 }; 5537 }; 5538 5539 port@4 { 5540 reg = <4>; 5541 5542 mdss_intf4_out: endpoint { 5543 remote-endpoint = <&mdss_dp1_in>; 5544 }; 5545 }; 5546 5547 port@5 { 5548 reg = <5>; 5549 5550 mdss_intf5_out: endpoint { 5551 remote-endpoint = <&mdss_dp3_in>; 5552 }; 5553 }; 5554 5555 port@6 { 5556 reg = <6>; 5557 5558 mdss_intf6_out: endpoint { 5559 remote-endpoint = <&mdss_dp2_in>; 5560 }; 5561 }; 5562 }; 5563 5564 mdp_opp_table: opp-table { 5565 compatible = "operating-points-v2"; 5566 5567 opp-200000000 { 5568 opp-hz = /bits/ 64 <200000000>; 5569 required-opps = <&rpmhpd_opp_low_svs>; 5570 }; 5571 5572 opp-325000000 { 5573 opp-hz = /bits/ 64 <325000000>; 5574 required-opps = <&rpmhpd_opp_svs>; 5575 }; 5576 5577 opp-375000000 { 5578 opp-hz = /bits/ 64 <375000000>; 5579 required-opps = <&rpmhpd_opp_svs_l1>; 5580 }; 5581 5582 opp-514000000 { 5583 opp-hz = /bits/ 64 <514000000>; 5584 required-opps = <&rpmhpd_opp_nom>; 5585 }; 5586 5587 opp-575000000 { 5588 opp-hz = /bits/ 64 <575000000>; 5589 required-opps = <&rpmhpd_opp_nom_l1>; 5590 }; 5591 }; 5592 }; 5593 5594 mdss_dp0: displayport-controller@ae90000 { 5595 compatible = "qcom,x1e80100-dp"; 5596 reg = <0 0x0ae90000 0 0x200>, 5597 <0 0x0ae90200 0 0x200>, 5598 <0 0x0ae90400 0 0xc00>, 5599 <0 0x0ae91000 0 0x400>, 5600 <0 0x0ae91400 0 0x400>; 5601 5602 interrupts-extended = <&mdss 12>; 5603 5604 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5605 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 5606 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 5607 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5608 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5609 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 5610 clock-names = "core_iface", 5611 "core_aux", 5612 "ctrl_link", 5613 "ctrl_link_iface", 5614 "stream_pixel", 5615 "stream_1_pixel"; 5616 5617 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5618 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5619 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 5620 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5621 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5622 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5623 5624 operating-points-v2 = <&mdss_dp0_opp_table>; 5625 5626 power-domains = <&rpmhpd RPMHPD_MMCX>; 5627 5628 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; 5629 phy-names = "dp"; 5630 5631 #sound-dai-cells = <0>; 5632 sound-name-prefix = "DisplayPort0"; 5633 5634 status = "disabled"; 5635 5636 ports { 5637 #address-cells = <1>; 5638 #size-cells = <0>; 5639 5640 port@0 { 5641 reg = <0>; 5642 5643 mdss_dp0_in: endpoint { 5644 remote-endpoint = <&mdss_intf0_out>; 5645 }; 5646 }; 5647 5648 port@1 { 5649 reg = <1>; 5650 5651 mdss_dp0_out: endpoint { 5652 data-lanes = <0 1 2 3>; 5653 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; 5654 }; 5655 }; 5656 }; 5657 5658 mdss_dp0_opp_table: opp-table { 5659 compatible = "operating-points-v2"; 5660 5661 opp-160000000 { 5662 opp-hz = /bits/ 64 <160000000>; 5663 required-opps = <&rpmhpd_opp_low_svs>; 5664 }; 5665 5666 opp-270000000 { 5667 opp-hz = /bits/ 64 <270000000>; 5668 required-opps = <&rpmhpd_opp_svs>; 5669 }; 5670 5671 opp-540000000 { 5672 opp-hz = /bits/ 64 <540000000>; 5673 required-opps = <&rpmhpd_opp_svs_l1>; 5674 }; 5675 5676 opp-810000000 { 5677 opp-hz = /bits/ 64 <810000000>; 5678 required-opps = <&rpmhpd_opp_nom>; 5679 }; 5680 }; 5681 }; 5682 5683 mdss_dp1: displayport-controller@ae98000 { 5684 compatible = "qcom,x1e80100-dp"; 5685 reg = <0 0x0ae98000 0 0x200>, 5686 <0 0x0ae98200 0 0x200>, 5687 <0 0x0ae98400 0 0xc00>, 5688 <0 0x0ae99000 0 0x400>, 5689 <0 0x0ae99400 0 0x400>; 5690 5691 interrupts-extended = <&mdss 13>; 5692 5693 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5694 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 5695 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 5696 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5697 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 5698 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 5699 clock-names = "core_iface", 5700 "core_aux", 5701 "ctrl_link", 5702 "ctrl_link_iface", 5703 "stream_pixel", 5704 "stream_1_pixel"; 5705 5706 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5707 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 5708 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 5709 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5710 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5711 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5712 5713 operating-points-v2 = <&mdss_dp1_opp_table>; 5714 5715 power-domains = <&rpmhpd RPMHPD_MMCX>; 5716 5717 phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; 5718 phy-names = "dp"; 5719 5720 #sound-dai-cells = <0>; 5721 sound-name-prefix = "DisplayPort1"; 5722 5723 status = "disabled"; 5724 5725 ports { 5726 #address-cells = <1>; 5727 #size-cells = <0>; 5728 5729 port@0 { 5730 reg = <0>; 5731 5732 mdss_dp1_in: endpoint { 5733 remote-endpoint = <&mdss_intf4_out>; 5734 }; 5735 }; 5736 5737 port@1 { 5738 reg = <1>; 5739 5740 mdss_dp1_out: endpoint { 5741 data-lanes = <0 1 2 3>; 5742 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; 5743 }; 5744 }; 5745 }; 5746 5747 mdss_dp1_opp_table: opp-table { 5748 compatible = "operating-points-v2"; 5749 5750 opp-160000000 { 5751 opp-hz = /bits/ 64 <160000000>; 5752 required-opps = <&rpmhpd_opp_low_svs>; 5753 }; 5754 5755 opp-270000000 { 5756 opp-hz = /bits/ 64 <270000000>; 5757 required-opps = <&rpmhpd_opp_svs>; 5758 }; 5759 5760 opp-540000000 { 5761 opp-hz = /bits/ 64 <540000000>; 5762 required-opps = <&rpmhpd_opp_svs_l1>; 5763 }; 5764 5765 opp-810000000 { 5766 opp-hz = /bits/ 64 <810000000>; 5767 required-opps = <&rpmhpd_opp_nom>; 5768 }; 5769 }; 5770 }; 5771 5772 mdss_dp2: displayport-controller@ae9a000 { 5773 compatible = "qcom,x1e80100-dp"; 5774 reg = <0 0x0ae9a000 0 0x200>, 5775 <0 0x0ae9a200 0 0x200>, 5776 <0 0x0ae9a400 0 0xc00>, 5777 <0 0x0ae9b000 0 0x400>, 5778 <0 0x0ae9b400 0 0x400>; 5779 5780 interrupts-extended = <&mdss 14>; 5781 5782 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5783 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5784 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 5785 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5786 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 5787 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 5788 clock-names = "core_iface", 5789 "core_aux", 5790 "ctrl_link", 5791 "ctrl_link_iface", 5792 "stream_pixel", 5793 "stream_1_pixel"; 5794 5795 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5796 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 5797 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 5798 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5799 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5800 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5801 5802 operating-points-v2 = <&mdss_dp2_opp_table>; 5803 5804 power-domains = <&rpmhpd RPMHPD_MMCX>; 5805 5806 phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>; 5807 phy-names = "dp"; 5808 5809 #sound-dai-cells = <0>; 5810 sound-name-prefix = "DisplayPort2"; 5811 5812 status = "disabled"; 5813 5814 ports { 5815 #address-cells = <1>; 5816 #size-cells = <0>; 5817 5818 port@0 { 5819 reg = <0>; 5820 mdss_dp2_in: endpoint { 5821 remote-endpoint = <&mdss_intf6_out>; 5822 }; 5823 }; 5824 5825 port@1 { 5826 reg = <1>; 5827 5828 mdss_dp2_out: endpoint { 5829 data-lanes = <0 1 2 3>; 5830 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; 5831 }; 5832 }; 5833 }; 5834 5835 mdss_dp2_opp_table: opp-table { 5836 compatible = "operating-points-v2"; 5837 5838 opp-160000000 { 5839 opp-hz = /bits/ 64 <160000000>; 5840 required-opps = <&rpmhpd_opp_low_svs>; 5841 }; 5842 5843 opp-270000000 { 5844 opp-hz = /bits/ 64 <270000000>; 5845 required-opps = <&rpmhpd_opp_svs>; 5846 }; 5847 5848 opp-540000000 { 5849 opp-hz = /bits/ 64 <540000000>; 5850 required-opps = <&rpmhpd_opp_svs_l1>; 5851 }; 5852 5853 opp-810000000 { 5854 opp-hz = /bits/ 64 <810000000>; 5855 required-opps = <&rpmhpd_opp_nom>; 5856 }; 5857 }; 5858 }; 5859 5860 mdss_dp3: displayport-controller@aea0000 { 5861 compatible = "qcom,x1e80100-dp"; 5862 reg = <0 0x0aea0000 0 0x200>, 5863 <0 0x0aea0200 0 0x200>, 5864 <0 0x0aea0400 0 0xc00>, 5865 <0 0x0aea1000 0 0x400>, 5866 <0 0x0aea1400 0 0x400>; 5867 5868 interrupts-extended = <&mdss 15>; 5869 5870 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5871 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5872 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 5873 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5874 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5875 clock-names = "core_iface", 5876 "core_aux", 5877 "ctrl_link", 5878 "ctrl_link_iface", 5879 "stream_pixel"; 5880 5881 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5882 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5883 assigned-clock-parents = <&mdss_dp3_phy 0>, 5884 <&mdss_dp3_phy 1>; 5885 5886 operating-points-v2 = <&mdss_dp3_opp_table>; 5887 5888 power-domains = <&rpmhpd RPMHPD_MMCX>; 5889 5890 phys = <&mdss_dp3_phy>; 5891 phy-names = "dp"; 5892 5893 #sound-dai-cells = <0>; 5894 sound-name-prefix = "DisplayPort3"; 5895 5896 status = "disabled"; 5897 5898 ports { 5899 #address-cells = <1>; 5900 #size-cells = <0>; 5901 5902 port@0 { 5903 reg = <0>; 5904 5905 mdss_dp3_in: endpoint { 5906 remote-endpoint = <&mdss_intf5_out>; 5907 }; 5908 }; 5909 5910 port@1 { 5911 reg = <1>; 5912 5913 mdss_dp3_out: endpoint { 5914 }; 5915 }; 5916 }; 5917 5918 mdss_dp3_opp_table: opp-table { 5919 compatible = "operating-points-v2"; 5920 5921 opp-160000000 { 5922 opp-hz = /bits/ 64 <160000000>; 5923 required-opps = <&rpmhpd_opp_low_svs>; 5924 }; 5925 5926 opp-270000000 { 5927 opp-hz = /bits/ 64 <270000000>; 5928 required-opps = <&rpmhpd_opp_svs>; 5929 }; 5930 5931 opp-540000000 { 5932 opp-hz = /bits/ 64 <540000000>; 5933 required-opps = <&rpmhpd_opp_svs_l1>; 5934 }; 5935 5936 opp-810000000 { 5937 opp-hz = /bits/ 64 <810000000>; 5938 required-opps = <&rpmhpd_opp_nom>; 5939 }; 5940 }; 5941 }; 5942 5943 }; 5944 5945 mdss_dp2_phy: phy@aec2a00 { 5946 compatible = "qcom,x1e80100-dp-phy"; 5947 reg = <0 0x0aec2a00 0 0x19c>, 5948 <0 0x0aec2200 0 0xec>, 5949 <0 0x0aec2600 0 0xec>, 5950 <0 0x0aec2000 0 0x1c8>; 5951 5952 clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5953 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5954 <&tcsr TCSR_EDP_CLKREF_EN>; 5955 clock-names = "aux", 5956 "cfg_ahb", 5957 "ref"; 5958 5959 power-domains = <&rpmhpd RPMHPD_MX>; 5960 5961 #clock-cells = <1>; 5962 #phy-cells = <0>; 5963 5964 status = "disabled"; 5965 }; 5966 5967 mdss_dp3_phy: phy@aec5a00 { 5968 compatible = "qcom,x1e80100-dp-phy"; 5969 reg = <0 0x0aec5a00 0 0x19c>, 5970 <0 0x0aec5200 0 0xec>, 5971 <0 0x0aec5600 0 0xec>, 5972 <0 0x0aec5000 0 0x1c8>; 5973 5974 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5975 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5976 <&tcsr TCSR_EDP_CLKREF_EN>; 5977 clock-names = "aux", 5978 "cfg_ahb", 5979 "ref"; 5980 5981 power-domains = <&rpmhpd RPMHPD_MX>; 5982 5983 #clock-cells = <1>; 5984 #phy-cells = <0>; 5985 5986 status = "disabled"; 5987 }; 5988 5989 dispcc: clock-controller@af00000 { 5990 compatible = "qcom,x1e80100-dispcc"; 5991 reg = <0 0x0af00000 0 0x20000>; 5992 clocks = <&bi_tcxo_div2>, 5993 <&bi_tcxo_ao_div2>, 5994 <&gcc GCC_DISP_AHB_CLK>, 5995 <&sleep_clk>, 5996 <0>, /* dsi0 */ 5997 <0>, 5998 <0>, /* dsi1 */ 5999 <0>, 6000 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 6001 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 6002 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 6003 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 6004 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 6005 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 6006 <&mdss_dp3_phy 0>, /* dp3 */ 6007 <&mdss_dp3_phy 1>; 6008 power-domains = <&rpmhpd RPMHPD_MMCX>; 6009 required-opps = <&rpmhpd_opp_low_svs>; 6010 #clock-cells = <1>; 6011 #reset-cells = <1>; 6012 #power-domain-cells = <1>; 6013 }; 6014 6015 pdc: interrupt-controller@b220000 { 6016 compatible = "qcom,x1e80100-pdc", "qcom,pdc"; 6017 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 6018 6019 qcom,pdc-ranges = <0 480 42>, <42 251 5>, 6020 <47 522 52>, <99 609 32>, 6021 <131 717 12>, <143 816 19>; 6022 #interrupt-cells = <2>; 6023 interrupt-parent = <&intc>; 6024 interrupt-controller; 6025 }; 6026 6027 aoss_qmp: power-management@c300000 { 6028 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp"; 6029 reg = <0 0x0c300000 0 0x400>; 6030 interrupt-parent = <&ipcc>; 6031 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 6032 IRQ_TYPE_EDGE_RISING>; 6033 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 6034 6035 #clock-cells = <0>; 6036 }; 6037 6038 sram@c3f0000 { 6039 compatible = "qcom,rpmh-stats"; 6040 reg = <0 0x0c3f0000 0 0x400>; 6041 }; 6042 6043 spmi: arbiter@c400000 { 6044 compatible = "qcom,x1e80100-spmi-pmic-arb"; 6045 reg = <0 0x0c400000 0 0x3000>, 6046 <0 0x0c500000 0 0x400000>, 6047 <0 0x0c440000 0 0x80000>; 6048 reg-names = "core", "chnls", "obsrvr"; 6049 6050 qcom,ee = <0>; 6051 qcom,channel = <0>; 6052 6053 #address-cells = <2>; 6054 #size-cells = <2>; 6055 ranges; 6056 6057 spmi_bus0: spmi@c42d000 { 6058 reg = <0 0x0c42d000 0 0x4000>, 6059 <0 0x0c4c0000 0 0x10000>; 6060 reg-names = "cnfg", "intr"; 6061 6062 interrupt-names = "periph_irq"; 6063 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 6064 interrupt-controller; 6065 #interrupt-cells = <4>; 6066 6067 #address-cells = <2>; 6068 #size-cells = <0>; 6069 }; 6070 6071 spmi_bus1: spmi@c432000 { 6072 reg = <0 0x0c432000 0 0x4000>, 6073 <0 0x0c4d0000 0 0x10000>; 6074 reg-names = "cnfg", "intr"; 6075 6076 interrupt-names = "periph_irq"; 6077 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 6078 interrupt-controller; 6079 #interrupt-cells = <4>; 6080 6081 #address-cells = <2>; 6082 #size-cells = <0>; 6083 }; 6084 }; 6085 6086 tlmm: pinctrl@f100000 { 6087 compatible = "qcom,x1e80100-tlmm"; 6088 reg = <0 0x0f100000 0 0xf00000>; 6089 6090 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 6091 6092 gpio-controller; 6093 #gpio-cells = <2>; 6094 6095 interrupt-controller; 6096 #interrupt-cells = <2>; 6097 6098 gpio-ranges = <&tlmm 0 0 239>; 6099 wakeup-parent = <&pdc>; 6100 6101 edp0_hpd_default: edp0-hpd-default-state { 6102 pins = "gpio119"; 6103 function = "edp0_hot"; 6104 bias-disable; 6105 }; 6106 6107 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 6108 /* SDA, SCL */ 6109 pins = "gpio0", "gpio1"; 6110 function = "qup0_se0"; 6111 drive-strength = <2>; 6112 bias-pull-up = <2200>; 6113 }; 6114 6115 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 6116 /* SDA, SCL */ 6117 pins = "gpio4", "gpio5"; 6118 function = "qup0_se1"; 6119 drive-strength = <2>; 6120 bias-pull-up = <2200>; 6121 }; 6122 6123 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 6124 /* SDA, SCL */ 6125 pins = "gpio8", "gpio9"; 6126 function = "qup0_se2"; 6127 drive-strength = <2>; 6128 bias-pull-up = <2200>; 6129 }; 6130 6131 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 6132 /* SDA, SCL */ 6133 pins = "gpio12", "gpio13"; 6134 function = "qup0_se3"; 6135 drive-strength = <2>; 6136 bias-pull-up = <2200>; 6137 }; 6138 6139 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 6140 /* SDA, SCL */ 6141 pins = "gpio16", "gpio17"; 6142 function = "qup0_se4"; 6143 drive-strength = <2>; 6144 bias-pull-up = <2200>; 6145 }; 6146 6147 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 6148 /* SDA, SCL */ 6149 pins = "gpio20", "gpio21"; 6150 function = "qup0_se5"; 6151 drive-strength = <2>; 6152 bias-pull-up = <2200>; 6153 }; 6154 6155 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 6156 /* SDA, SCL */ 6157 pins = "gpio24", "gpio25"; 6158 function = "qup0_se6"; 6159 drive-strength = <2>; 6160 bias-pull-up = <2200>; 6161 }; 6162 6163 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 6164 /* SDA, SCL */ 6165 pins = "gpio14", "gpio15"; 6166 function = "qup0_se7"; 6167 drive-strength = <2>; 6168 bias-pull-up = <2200>; 6169 }; 6170 6171 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 6172 /* SDA, SCL */ 6173 pins = "gpio32", "gpio33"; 6174 function = "qup1_se0"; 6175 drive-strength = <2>; 6176 bias-pull-up = <2200>; 6177 }; 6178 6179 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 6180 /* SDA, SCL */ 6181 pins = "gpio36", "gpio37"; 6182 function = "qup1_se1"; 6183 drive-strength = <2>; 6184 bias-pull-up = <2200>; 6185 }; 6186 6187 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 6188 /* SDA, SCL */ 6189 pins = "gpio40", "gpio41"; 6190 function = "qup1_se2"; 6191 drive-strength = <2>; 6192 bias-pull-up = <2200>; 6193 }; 6194 6195 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 6196 /* SDA, SCL */ 6197 pins = "gpio44", "gpio45"; 6198 function = "qup1_se3"; 6199 drive-strength = <2>; 6200 bias-pull-up = <2200>; 6201 }; 6202 6203 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 6204 /* SDA, SCL */ 6205 pins = "gpio48", "gpio49"; 6206 function = "qup1_se4"; 6207 drive-strength = <2>; 6208 bias-pull-up = <2200>; 6209 }; 6210 6211 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 6212 /* SDA, SCL */ 6213 pins = "gpio52", "gpio53"; 6214 function = "qup1_se5"; 6215 drive-strength = <2>; 6216 bias-pull-up = <2200>; 6217 }; 6218 6219 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 6220 /* SDA, SCL */ 6221 pins = "gpio56", "gpio57"; 6222 function = "qup1_se6"; 6223 drive-strength = <2>; 6224 bias-pull-up = <2200>; 6225 }; 6226 6227 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 6228 /* SDA, SCL */ 6229 pins = "gpio54", "gpio55"; 6230 function = "qup1_se7"; 6231 drive-strength = <2>; 6232 bias-pull-up = <2200>; 6233 }; 6234 6235 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 6236 /* SDA, SCL */ 6237 pins = "gpio64", "gpio65"; 6238 function = "qup2_se0"; 6239 drive-strength = <2>; 6240 bias-pull-up = <2200>; 6241 }; 6242 6243 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 6244 /* SDA, SCL */ 6245 pins = "gpio68", "gpio69"; 6246 function = "qup2_se1"; 6247 drive-strength = <2>; 6248 bias-pull-up = <2200>; 6249 }; 6250 6251 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 6252 /* SDA, SCL */ 6253 pins = "gpio72", "gpio73"; 6254 function = "qup2_se2"; 6255 drive-strength = <2>; 6256 bias-pull-up = <2200>; 6257 }; 6258 6259 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 6260 /* SDA, SCL */ 6261 pins = "gpio76", "gpio77"; 6262 function = "qup2_se3"; 6263 drive-strength = <2>; 6264 bias-pull-up = <2200>; 6265 }; 6266 6267 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 6268 /* SDA, SCL */ 6269 pins = "gpio80", "gpio81"; 6270 function = "qup2_se4"; 6271 drive-strength = <2>; 6272 bias-pull-up = <2200>; 6273 }; 6274 6275 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 6276 /* SDA, SCL */ 6277 pins = "gpio84", "gpio85"; 6278 function = "qup2_se5"; 6279 drive-strength = <2>; 6280 bias-pull-up = <2200>; 6281 }; 6282 6283 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 6284 /* SDA, SCL */ 6285 pins = "gpio88", "gpio89"; 6286 function = "qup2_se6"; 6287 drive-strength = <2>; 6288 bias-pull-up = <2200>; 6289 }; 6290 6291 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 6292 /* SDA, SCL */ 6293 pins = "gpio86", "gpio87"; 6294 function = "qup2_se7"; 6295 drive-strength = <2>; 6296 bias-pull-up = <2200>; 6297 }; 6298 6299 qup_spi0_cs: qup-spi0-cs-state { 6300 pins = "gpio3"; 6301 function = "qup0_se0"; 6302 drive-strength = <6>; 6303 bias-disable; 6304 }; 6305 6306 qup_spi0_data_clk: qup-spi0-data-clk-state { 6307 /* MISO, MOSI, CLK */ 6308 pins = "gpio0", "gpio1", "gpio2"; 6309 function = "qup0_se0"; 6310 drive-strength = <6>; 6311 bias-disable; 6312 }; 6313 6314 qup_spi1_cs: qup-spi1-cs-state { 6315 pins = "gpio7"; 6316 function = "qup0_se1"; 6317 drive-strength = <6>; 6318 bias-disable; 6319 }; 6320 6321 qup_spi1_data_clk: qup-spi1-data-clk-state { 6322 /* MISO, MOSI, CLK */ 6323 pins = "gpio4", "gpio5", "gpio6"; 6324 function = "qup0_se1"; 6325 drive-strength = <6>; 6326 bias-disable; 6327 }; 6328 6329 qup_spi2_cs: qup-spi2-cs-state { 6330 pins = "gpio11"; 6331 function = "qup0_se2"; 6332 drive-strength = <6>; 6333 bias-disable; 6334 }; 6335 6336 qup_spi2_data_clk: qup-spi2-data-clk-state { 6337 /* MISO, MOSI, CLK */ 6338 pins = "gpio8", "gpio9", "gpio10"; 6339 function = "qup0_se2"; 6340 drive-strength = <6>; 6341 bias-disable; 6342 }; 6343 6344 qup_spi3_cs: qup-spi3-cs-state { 6345 pins = "gpio15"; 6346 function = "qup0_se3"; 6347 drive-strength = <6>; 6348 bias-disable; 6349 }; 6350 6351 qup_spi3_data_clk: qup-spi3-data-clk-state { 6352 /* MISO, MOSI, CLK */ 6353 pins = "gpio12", "gpio13", "gpio14"; 6354 function = "qup0_se3"; 6355 drive-strength = <6>; 6356 bias-disable; 6357 }; 6358 6359 qup_spi4_cs: qup-spi4-cs-state { 6360 pins = "gpio19"; 6361 function = "qup0_se4"; 6362 drive-strength = <6>; 6363 bias-disable; 6364 }; 6365 6366 qup_spi4_data_clk: qup-spi4-data-clk-state { 6367 /* MISO, MOSI, CLK */ 6368 pins = "gpio16", "gpio17", "gpio18"; 6369 function = "qup0_se4"; 6370 drive-strength = <6>; 6371 bias-disable; 6372 }; 6373 6374 qup_spi5_cs: qup-spi5-cs-state { 6375 pins = "gpio23"; 6376 function = "qup0_se5"; 6377 drive-strength = <6>; 6378 bias-disable; 6379 }; 6380 6381 qup_spi5_data_clk: qup-spi5-data-clk-state { 6382 /* MISO, MOSI, CLK */ 6383 pins = "gpio20", "gpio21", "gpio22"; 6384 function = "qup0_se5"; 6385 drive-strength = <6>; 6386 bias-disable; 6387 }; 6388 6389 qup_spi6_cs: qup-spi6-cs-state { 6390 pins = "gpio27"; 6391 function = "qup0_se6"; 6392 drive-strength = <6>; 6393 bias-disable; 6394 }; 6395 6396 qup_spi6_data_clk: qup-spi6-data-clk-state { 6397 /* MISO, MOSI, CLK */ 6398 pins = "gpio24", "gpio25", "gpio26"; 6399 function = "qup0_se6"; 6400 drive-strength = <6>; 6401 bias-disable; 6402 }; 6403 6404 qup_spi7_cs: qup-spi7-cs-state { 6405 pins = "gpio13"; 6406 function = "qup0_se7"; 6407 drive-strength = <6>; 6408 bias-disable; 6409 }; 6410 6411 qup_spi7_data_clk: qup-spi7-data-clk-state { 6412 /* MISO, MOSI, CLK */ 6413 pins = "gpio14", "gpio15", "gpio12"; 6414 function = "qup0_se7"; 6415 drive-strength = <6>; 6416 bias-disable; 6417 }; 6418 6419 qup_spi8_cs: qup-spi8-cs-state { 6420 pins = "gpio35"; 6421 function = "qup1_se0"; 6422 drive-strength = <6>; 6423 bias-disable; 6424 }; 6425 6426 qup_spi8_data_clk: qup-spi8-data-clk-state { 6427 /* MISO, MOSI, CLK */ 6428 pins = "gpio32", "gpio33", "gpio34"; 6429 function = "qup1_se0"; 6430 drive-strength = <6>; 6431 bias-disable; 6432 }; 6433 6434 qup_spi9_cs: qup-spi9-cs-state { 6435 pins = "gpio39"; 6436 function = "qup1_se1"; 6437 drive-strength = <6>; 6438 bias-disable; 6439 }; 6440 6441 qup_spi9_data_clk: qup-spi9-data-clk-state { 6442 /* MISO, MOSI, CLK */ 6443 pins = "gpio36", "gpio37", "gpio38"; 6444 function = "qup1_se1"; 6445 drive-strength = <6>; 6446 bias-disable; 6447 }; 6448 6449 qup_spi10_cs: qup-spi10-cs-state { 6450 pins = "gpio43"; 6451 function = "qup1_se2"; 6452 drive-strength = <6>; 6453 bias-disable; 6454 }; 6455 6456 qup_spi10_data_clk: qup-spi10-data-clk-state { 6457 /* MISO, MOSI, CLK */ 6458 pins = "gpio40", "gpio41", "gpio42"; 6459 function = "qup1_se2"; 6460 drive-strength = <6>; 6461 bias-disable; 6462 }; 6463 6464 qup_spi11_cs: qup-spi11-cs-state { 6465 pins = "gpio47"; 6466 function = "qup1_se3"; 6467 drive-strength = <6>; 6468 bias-disable; 6469 }; 6470 6471 qup_spi11_data_clk: qup-spi11-data-clk-state { 6472 /* MISO, MOSI, CLK */ 6473 pins = "gpio44", "gpio45", "gpio46"; 6474 function = "qup1_se3"; 6475 drive-strength = <6>; 6476 bias-disable; 6477 }; 6478 6479 qup_spi12_cs: qup-spi12-cs-state { 6480 pins = "gpio51"; 6481 function = "qup1_se4"; 6482 drive-strength = <6>; 6483 bias-disable; 6484 }; 6485 6486 qup_spi12_data_clk: qup-spi12-data-clk-state { 6487 /* MISO, MOSI, CLK */ 6488 pins = "gpio48", "gpio49", "gpio50"; 6489 function = "qup1_se4"; 6490 drive-strength = <6>; 6491 bias-disable; 6492 }; 6493 6494 qup_spi13_cs: qup-spi13-cs-state { 6495 pins = "gpio55"; 6496 function = "qup1_se5"; 6497 drive-strength = <6>; 6498 bias-disable; 6499 }; 6500 6501 qup_spi13_data_clk: qup-spi13-data-clk-state { 6502 /* MISO, MOSI, CLK */ 6503 pins = "gpio52", "gpio53", "gpio54"; 6504 function = "qup1_se5"; 6505 drive-strength = <6>; 6506 bias-disable; 6507 }; 6508 6509 qup_spi14_cs: qup-spi14-cs-state { 6510 pins = "gpio59"; 6511 function = "qup1_se6"; 6512 drive-strength = <6>; 6513 bias-disable; 6514 }; 6515 6516 qup_spi14_data_clk: qup-spi14-data-clk-state { 6517 /* MISO, MOSI, CLK */ 6518 pins = "gpio56", "gpio57", "gpio58"; 6519 function = "qup1_se6"; 6520 drive-strength = <6>; 6521 bias-disable; 6522 }; 6523 6524 qup_spi15_cs: qup-spi15-cs-state { 6525 pins = "gpio53"; 6526 function = "qup1_se7"; 6527 drive-strength = <6>; 6528 bias-disable; 6529 }; 6530 6531 qup_spi15_data_clk: qup-spi15-data-clk-state { 6532 /* MISO, MOSI, CLK */ 6533 pins = "gpio54", "gpio55", "gpio52"; 6534 function = "qup1_se7"; 6535 drive-strength = <6>; 6536 bias-disable; 6537 }; 6538 6539 qup_spi16_cs: qup-spi16-cs-state { 6540 pins = "gpio67"; 6541 function = "qup2_se0"; 6542 drive-strength = <6>; 6543 bias-disable; 6544 }; 6545 6546 qup_spi16_data_clk: qup-spi16-data-clk-state { 6547 /* MISO, MOSI, CLK */ 6548 pins = "gpio64", "gpio65", "gpio66"; 6549 function = "qup2_se0"; 6550 drive-strength = <6>; 6551 bias-disable; 6552 }; 6553 6554 qup_spi17_cs: qup-spi17-cs-state { 6555 pins = "gpio71"; 6556 function = "qup2_se1"; 6557 drive-strength = <6>; 6558 bias-disable; 6559 }; 6560 6561 qup_spi17_data_clk: qup-spi17-data-clk-state { 6562 /* MISO, MOSI, CLK */ 6563 pins = "gpio68", "gpio69", "gpio70"; 6564 function = "qup2_se1"; 6565 drive-strength = <6>; 6566 bias-disable; 6567 }; 6568 6569 qup_spi18_cs: qup-spi18-cs-state { 6570 pins = "gpio75"; 6571 function = "qup2_se2"; 6572 drive-strength = <6>; 6573 bias-disable; 6574 }; 6575 6576 qup_spi18_data_clk: qup-spi18-data-clk-state { 6577 /* MISO, MOSI, CLK */ 6578 pins = "gpio72", "gpio73", "gpio74"; 6579 function = "qup2_se2"; 6580 drive-strength = <6>; 6581 bias-disable; 6582 }; 6583 6584 qup_spi19_cs: qup-spi19-cs-state { 6585 pins = "gpio79"; 6586 function = "qup2_se3"; 6587 drive-strength = <6>; 6588 bias-disable; 6589 }; 6590 6591 qup_spi19_data_clk: qup-spi19-data-clk-state { 6592 /* MISO, MOSI, CLK */ 6593 pins = "gpio76", "gpio77", "gpio78"; 6594 function = "qup2_se3"; 6595 drive-strength = <6>; 6596 bias-disable; 6597 }; 6598 6599 qup_spi20_cs: qup-spi20-cs-state { 6600 pins = "gpio83"; 6601 function = "qup2_se4"; 6602 drive-strength = <6>; 6603 bias-disable; 6604 }; 6605 6606 qup_spi20_data_clk: qup-spi20-data-clk-state { 6607 /* MISO, MOSI, CLK */ 6608 pins = "gpio80", "gpio81", "gpio82"; 6609 function = "qup2_se4"; 6610 drive-strength = <6>; 6611 bias-disable; 6612 }; 6613 6614 qup_spi21_cs: qup-spi21-cs-state { 6615 pins = "gpio87"; 6616 function = "qup2_se5"; 6617 drive-strength = <6>; 6618 bias-disable; 6619 }; 6620 6621 qup_spi21_data_clk: qup-spi21-data-clk-state { 6622 /* MISO, MOSI, CLK */ 6623 pins = "gpio84", "gpio85", "gpio86"; 6624 function = "qup2_se5"; 6625 drive-strength = <6>; 6626 bias-disable; 6627 }; 6628 6629 qup_spi22_cs: qup-spi22-cs-state { 6630 pins = "gpio91"; 6631 function = "qup2_se6"; 6632 drive-strength = <6>; 6633 bias-disable; 6634 }; 6635 6636 qup_spi22_data_clk: qup-spi22-data-clk-state { 6637 /* MISO, MOSI, CLK */ 6638 pins = "gpio88", "gpio89", "gpio90"; 6639 function = "qup2_se6"; 6640 drive-strength = <6>; 6641 bias-disable; 6642 }; 6643 6644 qup_spi23_cs: qup-spi23-cs-state { 6645 pins = "gpio85"; 6646 function = "qup2_se7"; 6647 drive-strength = <6>; 6648 bias-disable; 6649 }; 6650 6651 qup_spi23_data_clk: qup-spi23-data-clk-state { 6652 /* MISO, MOSI, CLK */ 6653 pins = "gpio86", "gpio87", "gpio84"; 6654 function = "qup2_se7"; 6655 drive-strength = <6>; 6656 bias-disable; 6657 }; 6658 6659 qup_uart2_default: qup-uart2-default-state { 6660 cts-pins { 6661 pins = "gpio8"; 6662 function = "qup0_se2"; 6663 drive-strength = <2>; 6664 bias-disable; 6665 }; 6666 6667 rts-pins { 6668 pins = "gpio9"; 6669 function = "qup0_se2"; 6670 drive-strength = <2>; 6671 bias-disable; 6672 }; 6673 6674 tx-pins { 6675 pins = "gpio10"; 6676 function = "qup0_se2"; 6677 drive-strength = <2>; 6678 bias-disable; 6679 }; 6680 6681 rx-pins { 6682 pins = "gpio11"; 6683 function = "qup0_se2"; 6684 drive-strength = <2>; 6685 bias-disable; 6686 }; 6687 }; 6688 6689 qup_uart14_default: qup-uart14-default-state { 6690 cts-pins { 6691 pins = "gpio56"; 6692 function = "qup1_se6"; 6693 bias-bus-hold; 6694 }; 6695 6696 rts-pins { 6697 pins = "gpio57"; 6698 function = "qup1_se6"; 6699 drive-strength = <2>; 6700 bias-disable; 6701 }; 6702 6703 tx-pins { 6704 pins = "gpio58"; 6705 function = "qup1_se6"; 6706 drive-strength = <2>; 6707 bias-disable; 6708 }; 6709 6710 rx-pins { 6711 pins = "gpio59"; 6712 function = "qup1_se6"; 6713 bias-pull-up; 6714 }; 6715 }; 6716 6717 qup_uart21_default: qup-uart21-default-state { 6718 tx-pins { 6719 pins = "gpio86"; 6720 function = "qup2_se5"; 6721 drive-strength = <2>; 6722 bias-disable; 6723 }; 6724 6725 rx-pins { 6726 pins = "gpio87"; 6727 function = "qup2_se5"; 6728 drive-strength = <2>; 6729 bias-disable; 6730 }; 6731 }; 6732 6733 sdc2_default: sdc2-default-state { 6734 clk-pins { 6735 pins = "sdc2_clk"; 6736 drive-strength = <16>; 6737 bias-disable; 6738 }; 6739 6740 cmd-pins { 6741 pins = "sdc2_cmd"; 6742 drive-strength = <10>; 6743 bias-pull-up; 6744 }; 6745 6746 data-pins { 6747 pins = "sdc2_data"; 6748 drive-strength = <10>; 6749 bias-pull-up; 6750 }; 6751 }; 6752 6753 sdc2_sleep: sdc2-sleep-state { 6754 clk-pins { 6755 pins = "sdc2_clk"; 6756 drive-strength = <2>; 6757 bias-disable; 6758 }; 6759 6760 cmd-pins { 6761 pins = "sdc2_cmd"; 6762 drive-strength = <2>; 6763 bias-pull-up; 6764 }; 6765 6766 data-pins { 6767 pins = "sdc2_data"; 6768 drive-strength = <2>; 6769 bias-pull-up; 6770 }; 6771 }; 6772 }; 6773 6774 stm@10002000 { 6775 compatible = "arm,coresight-stm", "arm,primecell"; 6776 reg = <0x0 0x10002000 0x0 0x1000>, 6777 <0x0 0x16280000 0x0 0x180000>; 6778 reg-names = "stm-base", 6779 "stm-stimulus-base"; 6780 6781 clocks = <&aoss_qmp>; 6782 clock-names = "apb_pclk"; 6783 6784 out-ports { 6785 port { 6786 stm_out: endpoint { 6787 remote-endpoint = <&funnel0_in7>; 6788 }; 6789 }; 6790 }; 6791 }; 6792 6793 tpdm@10003000 { 6794 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6795 reg = <0x0 0x10003000 0x0 0x1000>; 6796 6797 clocks = <&aoss_qmp>; 6798 clock-names = "apb_pclk"; 6799 6800 qcom,cmb-element-bits = <32>; 6801 qcom,cmb-msrs-num = <32>; 6802 status = "disabled"; 6803 6804 out-ports { 6805 port { 6806 dcc_tpdm_out: endpoint { 6807 remote-endpoint = <&qdss_tpda_in0>; 6808 }; 6809 }; 6810 }; 6811 }; 6812 6813 tpda@10004000 { 6814 compatible = "qcom,coresight-tpda", "arm,primecell"; 6815 reg = <0x0 0x10004000 0x0 0x1000>; 6816 6817 clocks = <&aoss_qmp>; 6818 clock-names = "apb_pclk"; 6819 6820 in-ports { 6821 #address-cells = <1>; 6822 #size-cells = <0>; 6823 6824 port@0 { 6825 reg = <0>; 6826 6827 qdss_tpda_in0: endpoint { 6828 remote-endpoint = <&dcc_tpdm_out>; 6829 }; 6830 }; 6831 6832 port@1 { 6833 reg = <1>; 6834 6835 qdss_tpda_in1: endpoint { 6836 remote-endpoint = <&qdss_tpdm_out>; 6837 }; 6838 }; 6839 }; 6840 6841 out-ports { 6842 port { 6843 qdss_tpda_out: endpoint { 6844 remote-endpoint = <&funnel0_in6>; 6845 }; 6846 }; 6847 }; 6848 }; 6849 6850 tpdm@1000f000 { 6851 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6852 reg = <0x0 0x1000f000 0x0 0x1000>; 6853 6854 clocks = <&aoss_qmp>; 6855 clock-names = "apb_pclk"; 6856 6857 qcom,cmb-element-bits = <32>; 6858 qcom,cmb-msrs-num = <32>; 6859 6860 out-ports { 6861 port { 6862 qdss_tpdm_out: endpoint { 6863 remote-endpoint = <&qdss_tpda_in1>; 6864 }; 6865 }; 6866 }; 6867 }; 6868 6869 funnel@10041000 { 6870 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6871 reg = <0x0 0x10041000 0x0 0x1000>; 6872 6873 clocks = <&aoss_qmp>; 6874 clock-names = "apb_pclk"; 6875 6876 in-ports { 6877 #address-cells = <1>; 6878 #size-cells = <0>; 6879 6880 port@6 { 6881 reg = <6>; 6882 6883 funnel0_in6: endpoint { 6884 remote-endpoint = <&qdss_tpda_out>; 6885 }; 6886 }; 6887 6888 port@7 { 6889 reg = <7>; 6890 6891 funnel0_in7: endpoint { 6892 remote-endpoint = <&stm_out>; 6893 }; 6894 }; 6895 }; 6896 6897 out-ports { 6898 port { 6899 funnel0_out: endpoint { 6900 remote-endpoint = <&qdss_funnel_in0>; 6901 }; 6902 }; 6903 }; 6904 }; 6905 6906 funnel@10042000 { 6907 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6908 reg = <0x0 0x10042000 0x0 0x1000>; 6909 6910 clocks = <&aoss_qmp>; 6911 clock-names = "apb_pclk"; 6912 6913 in-ports { 6914 #address-cells = <1>; 6915 #size-cells = <0>; 6916 6917 port@2 { 6918 reg = <2>; 6919 6920 funnel1_in2: endpoint { 6921 remote-endpoint = <&tmess_funnel_out>; 6922 }; 6923 }; 6924 6925 port@5 { 6926 reg = <5>; 6927 6928 funnel1_in5: endpoint { 6929 remote-endpoint = <&dlst_funnel_out>; 6930 }; 6931 }; 6932 6933 port@6 { 6934 reg = <6>; 6935 6936 funnel1_in6: endpoint { 6937 remote-endpoint = <&dlct1_funnel_out>; 6938 }; 6939 }; 6940 }; 6941 6942 out-ports { 6943 port { 6944 funnel1_out: endpoint { 6945 remote-endpoint = <&qdss_funnel_in1>; 6946 }; 6947 }; 6948 }; 6949 }; 6950 6951 funnel@10045000 { 6952 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6953 reg = <0x0 0x10045000 0x0 0x1000>; 6954 6955 clocks = <&aoss_qmp>; 6956 clock-names = "apb_pclk"; 6957 6958 in-ports { 6959 #address-cells = <1>; 6960 #size-cells = <0>; 6961 6962 port@0 { 6963 reg = <0>; 6964 6965 qdss_funnel_in0: endpoint { 6966 remote-endpoint = <&funnel0_out>; 6967 }; 6968 }; 6969 6970 port@1 { 6971 reg = <1>; 6972 6973 qdss_funnel_in1: endpoint { 6974 remote-endpoint = <&funnel1_out>; 6975 }; 6976 }; 6977 }; 6978 6979 out-ports { 6980 port { 6981 qdss_funnel_out: endpoint { 6982 remote-endpoint = <&aoss_funnel_in7>; 6983 }; 6984 }; 6985 }; 6986 }; 6987 6988 tpdm@10800000 { 6989 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6990 reg = <0x0 0x10800000 0x0 0x1000>; 6991 6992 clocks = <&aoss_qmp>; 6993 clock-names = "apb_pclk"; 6994 6995 qcom,cmb-element-bits = <64>; 6996 qcom,cmb-msrs-num = <32>; 6997 6998 out-ports { 6999 port { 7000 mxa_tpdm_out: endpoint { 7001 remote-endpoint = <&dlct2_tpda_in15>; 7002 }; 7003 }; 7004 }; 7005 }; 7006 7007 tpdm@1082c000 { 7008 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7009 reg = <0x0 0x1082c000 0x0 0x1000>; 7010 7011 clocks = <&aoss_qmp>; 7012 clock-names = "apb_pclk"; 7013 7014 qcom,dsb-element-bits = <32>; 7015 qcom,dsb-msrs-num = <32>; 7016 7017 out-ports { 7018 port { 7019 gcc_tpdm_out: endpoint { 7020 remote-endpoint = <&dlct1_tpda_in21>; 7021 }; 7022 }; 7023 }; 7024 }; 7025 7026 tpdm@10841000 { 7027 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7028 reg = <0x0 0x10841000 0x0 0x1000>; 7029 7030 clocks = <&aoss_qmp>; 7031 clock-names = "apb_pclk"; 7032 7033 qcom,cmb-element-bits = <32>; 7034 qcom,cmb-msrs-num = <32>; 7035 7036 out-ports { 7037 port { 7038 prng_tpdm_out: endpoint { 7039 remote-endpoint = <&dlct1_tpda_in19>; 7040 }; 7041 }; 7042 }; 7043 }; 7044 7045 tpdm@10844000 { 7046 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7047 reg = <0x0 0x10844000 0x0 0x1000>; 7048 7049 clocks = <&aoss_qmp>; 7050 clock-names = "apb_pclk"; 7051 7052 qcom,dsb-element-bits = <32>; 7053 qcom,dsb-msrs-num = <32>; 7054 7055 out-ports { 7056 port { 7057 lpass_cx_tpdm_out: endpoint { 7058 remote-endpoint = <&lpass_cx_funnel_in0>; 7059 }; 7060 }; 7061 }; 7062 }; 7063 7064 funnel@10846000 { 7065 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7066 reg = <0x0 0x10846000 0x0 0x1000>; 7067 7068 clocks = <&aoss_qmp>; 7069 clock-names = "apb_pclk"; 7070 7071 in-ports { 7072 port { 7073 lpass_cx_funnel_in0: endpoint { 7074 remote-endpoint = <&lpass_cx_tpdm_out>; 7075 }; 7076 }; 7077 }; 7078 7079 out-ports { 7080 port { 7081 lpass_cx_funnel_out: endpoint { 7082 remote-endpoint = <&dlct1_tpda_in4>; 7083 }; 7084 }; 7085 }; 7086 }; 7087 7088 cti@1098b000 { 7089 compatible = "arm,coresight-cti", "arm,primecell"; 7090 reg = <0x0 0x1098b000 0x0 0x1000>; 7091 7092 clocks = <&aoss_qmp>; 7093 clock-names = "apb_pclk"; 7094 }; 7095 7096 tpdm@109d0000 { 7097 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7098 reg = <0x0 0x109d0000 0x0 0x1000>; 7099 7100 clocks = <&aoss_qmp>; 7101 clock-names = "apb_pclk"; 7102 7103 qcom,dsb-element-bits = <32>; 7104 qcom,dsb-msrs-num = <32>; 7105 status = "disabled"; 7106 7107 out-ports { 7108 port { 7109 qm_tpdm_out: endpoint { 7110 remote-endpoint = <&dlct1_tpda_in20>; 7111 }; 7112 }; 7113 }; 7114 }; 7115 7116 tpdm@10ac0000 { 7117 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7118 reg = <0x0 0x10ac0000 0x0 0x1000>; 7119 7120 clocks = <&aoss_qmp>; 7121 clock-names = "apb_pclk"; 7122 7123 qcom,dsb-element-bits = <32>; 7124 qcom,dsb-msrs-num = <32>; 7125 status = "disabled"; 7126 7127 out-ports { 7128 port { 7129 dlst_tpdm0_out: endpoint { 7130 remote-endpoint = <&dlst_tpda_in8>; 7131 }; 7132 }; 7133 }; 7134 }; 7135 7136 tpdm@10ac1000 { 7137 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7138 reg = <0x0 0x10ac1000 0x0 0x1000>; 7139 7140 clocks = <&aoss_qmp>; 7141 clock-names = "apb_pclk"; 7142 7143 qcom,cmb-element-bits = <64>; 7144 qcom,cmb-msrs-num = <32>; 7145 7146 out-ports { 7147 port { 7148 dlst_tpdm1_out: endpoint { 7149 remote-endpoint = <&dlst_tpda_in9>; 7150 }; 7151 }; 7152 }; 7153 }; 7154 7155 tpda@10ac4000 { 7156 compatible = "qcom,coresight-tpda", "arm,primecell"; 7157 reg = <0x0 0x10ac4000 0x0 0x1000>; 7158 7159 clocks = <&aoss_qmp>; 7160 clock-names = "apb_pclk"; 7161 7162 in-ports { 7163 #address-cells = <1>; 7164 #size-cells = <0>; 7165 7166 port@8 { 7167 reg = <8>; 7168 7169 dlst_tpda_in8: endpoint { 7170 remote-endpoint = <&dlst_tpdm0_out>; 7171 }; 7172 }; 7173 7174 port@9 { 7175 reg = <9>; 7176 7177 dlst_tpda_in9: endpoint { 7178 remote-endpoint = <&dlst_tpdm1_out>; 7179 }; 7180 }; 7181 }; 7182 7183 out-ports { 7184 port { 7185 dlst_tpda_out: endpoint { 7186 remote-endpoint = <&dlst_funnel_in0>; 7187 }; 7188 }; 7189 }; 7190 }; 7191 7192 funnel@10ac5000 { 7193 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7194 reg = <0x0 0x10ac5000 0x0 0x1000>; 7195 7196 clocks = <&aoss_qmp>; 7197 clock-names = "apb_pclk"; 7198 7199 in-ports { 7200 port { 7201 dlst_funnel_in0: endpoint { 7202 remote-endpoint = <&dlst_tpda_out>; 7203 }; 7204 }; 7205 }; 7206 7207 out-ports { 7208 port { 7209 dlst_funnel_out: endpoint { 7210 remote-endpoint = <&funnel1_in5>; 7211 }; 7212 }; 7213 }; 7214 }; 7215 7216 funnel@10b04000 { 7217 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7218 reg = <0x0 0x10b04000 0x0 0x1000>; 7219 7220 clocks = <&aoss_qmp>; 7221 clock-names = "apb_pclk"; 7222 7223 in-ports { 7224 #address-cells = <1>; 7225 #size-cells = <0>; 7226 7227 port@3 { 7228 reg = <3>; 7229 7230 aoss_funnel_in3: endpoint { 7231 remote-endpoint = <&ddr_lpi_funnel_out>; 7232 }; 7233 }; 7234 7235 port@6 { 7236 reg = <6>; 7237 7238 aoss_funnel_in6: endpoint { 7239 remote-endpoint = <&aoss_tpda_out>; 7240 }; 7241 }; 7242 7243 port@7 { 7244 reg = <7>; 7245 7246 aoss_funnel_in7: endpoint { 7247 remote-endpoint = <&qdss_funnel_out>; 7248 }; 7249 }; 7250 }; 7251 7252 out-ports { 7253 port { 7254 aoss_funnel_out: endpoint { 7255 remote-endpoint = <&etf0_in>; 7256 }; 7257 }; 7258 }; 7259 }; 7260 7261 etf0: tmc@10b05000 { 7262 compatible = "arm,coresight-tmc", "arm,primecell"; 7263 reg = <0x0 0x10b05000 0x0 0x1000>; 7264 7265 clocks = <&aoss_qmp>; 7266 clock-names = "apb_pclk"; 7267 7268 in-ports { 7269 port { 7270 etf0_in: endpoint { 7271 remote-endpoint = <&aoss_funnel_out>; 7272 }; 7273 }; 7274 }; 7275 7276 out-ports { 7277 port { 7278 etf0_out: endpoint { 7279 remote-endpoint = <&swao_rep_in>; 7280 }; 7281 }; 7282 }; 7283 }; 7284 7285 replicator@10b06000 { 7286 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 7287 reg = <0x0 0x10b06000 0x0 0x1000>; 7288 7289 clocks = <&aoss_qmp>; 7290 clock-names = "apb_pclk"; 7291 7292 in-ports { 7293 port { 7294 swao_rep_in: endpoint { 7295 remote-endpoint = <&etf0_out>; 7296 }; 7297 }; 7298 }; 7299 7300 out-ports { 7301 port { 7302 swao_rep_out1: endpoint { 7303 remote-endpoint = <&eud_in>; 7304 }; 7305 }; 7306 }; 7307 }; 7308 7309 tpda@10b08000 { 7310 compatible = "qcom,coresight-tpda", "arm,primecell"; 7311 reg = <0x0 0x10b08000 0x0 0x1000>; 7312 7313 clocks = <&aoss_qmp>; 7314 clock-names = "apb_pclk"; 7315 7316 in-ports { 7317 #address-cells = <1>; 7318 #size-cells = <0>; 7319 7320 port@0 { 7321 reg = <0>; 7322 7323 aoss_tpda_in0: endpoint { 7324 remote-endpoint = <&aoss_tpdm0_out>; 7325 }; 7326 }; 7327 7328 port@1 { 7329 reg = <1>; 7330 7331 aoss_tpda_in1: endpoint { 7332 remote-endpoint = <&aoss_tpdm1_out>; 7333 }; 7334 }; 7335 7336 port@2 { 7337 reg = <2>; 7338 7339 aoss_tpda_in2: endpoint { 7340 remote-endpoint = <&aoss_tpdm2_out>; 7341 }; 7342 }; 7343 7344 port@3 { 7345 reg = <3>; 7346 7347 aoss_tpda_in3: endpoint { 7348 remote-endpoint = <&aoss_tpdm3_out>; 7349 }; 7350 }; 7351 7352 port@4 { 7353 reg = <4>; 7354 7355 aoss_tpda_in4: endpoint { 7356 remote-endpoint = <&aoss_tpdm4_out>; 7357 }; 7358 }; 7359 }; 7360 7361 out-ports { 7362 port { 7363 aoss_tpda_out: endpoint { 7364 remote-endpoint = <&aoss_funnel_in6>; 7365 }; 7366 }; 7367 }; 7368 }; 7369 7370 tpdm@10b09000 { 7371 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7372 reg = <0x0 0x10b09000 0x0 0x1000>; 7373 7374 clocks = <&aoss_qmp>; 7375 clock-names = "apb_pclk"; 7376 7377 qcom,cmb-element-bits = <64>; 7378 qcom,cmb-msrs-num = <32>; 7379 7380 out-ports { 7381 port { 7382 aoss_tpdm0_out: endpoint { 7383 remote-endpoint = <&aoss_tpda_in0>; 7384 }; 7385 }; 7386 }; 7387 }; 7388 7389 tpdm@10b0a000 { 7390 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7391 reg = <0x0 0x10b0a000 0x0 0x1000>; 7392 7393 clocks = <&aoss_qmp>; 7394 clock-names = "apb_pclk"; 7395 7396 qcom,cmb-element-bits = <64>; 7397 qcom,cmb-msrs-num = <32>; 7398 7399 out-ports { 7400 port { 7401 aoss_tpdm1_out: endpoint { 7402 remote-endpoint = <&aoss_tpda_in1>; 7403 }; 7404 }; 7405 }; 7406 }; 7407 7408 tpdm@10b0b000 { 7409 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7410 reg = <0x0 0x10b0b000 0x0 0x1000>; 7411 7412 clocks = <&aoss_qmp>; 7413 clock-names = "apb_pclk"; 7414 7415 qcom,cmb-element-bits = <64>; 7416 qcom,cmb-msrs-num = <32>; 7417 7418 out-ports { 7419 port { 7420 aoss_tpdm2_out: endpoint { 7421 remote-endpoint = <&aoss_tpda_in2>; 7422 }; 7423 }; 7424 }; 7425 }; 7426 7427 tpdm@10b0c000 { 7428 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7429 reg = <0x0 0x10b0c000 0x0 0x1000>; 7430 7431 clocks = <&aoss_qmp>; 7432 clock-names = "apb_pclk"; 7433 7434 qcom,cmb-element-bits = <64>; 7435 qcom,cmb-msrs-num = <32>; 7436 7437 out-ports { 7438 port { 7439 aoss_tpdm3_out: endpoint { 7440 remote-endpoint = <&aoss_tpda_in3>; 7441 }; 7442 }; 7443 }; 7444 }; 7445 7446 tpdm@10b0d000 { 7447 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7448 reg = <0x0 0x10b0d000 0x0 0x1000>; 7449 7450 clocks = <&aoss_qmp>; 7451 clock-names = "apb_pclk"; 7452 7453 qcom,dsb-element-bits = <32>; 7454 qcom,dsb-msrs-num = <32>; 7455 7456 out-ports { 7457 port { 7458 aoss_tpdm4_out: endpoint { 7459 remote-endpoint = <&aoss_tpda_in4>; 7460 }; 7461 }; 7462 }; 7463 }; 7464 7465 tpdm@10b20000 { 7466 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7467 reg = <0x0 0x10b20000 0x0 0x1000>; 7468 7469 clocks = <&aoss_qmp>; 7470 clock-names = "apb_pclk"; 7471 7472 qcom,dsb-element-bits = <32>; 7473 qcom,dsb-msrs-num = <32>; 7474 status = "disabled"; 7475 7476 out-ports { 7477 port { 7478 lpicc_tpdm_out: endpoint { 7479 remote-endpoint = <&ddr_lpi_tpda_in>; 7480 }; 7481 }; 7482 }; 7483 }; 7484 7485 tpda@10b23000 { 7486 compatible = "qcom,coresight-tpda", "arm,primecell"; 7487 reg = <0x0 0x10b23000 0x0 0x1000>; 7488 7489 clocks = <&aoss_qmp>; 7490 clock-names = "apb_pclk"; 7491 status = "disabled"; 7492 7493 in-ports { 7494 port { 7495 ddr_lpi_tpda_in: endpoint { 7496 remote-endpoint = <&lpicc_tpdm_out>; 7497 }; 7498 }; 7499 }; 7500 7501 out-ports { 7502 port { 7503 ddr_lpi_tpda_out: endpoint { 7504 remote-endpoint = <&ddr_lpi_funnel_in0>; 7505 }; 7506 }; 7507 }; 7508 }; 7509 7510 funnel@10b24000 { 7511 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7512 reg = <0x0 0x10b24000 0x0 0x1000>; 7513 7514 clocks = <&aoss_qmp>; 7515 clock-names = "apb_pclk"; 7516 status = "disabled"; 7517 7518 in-ports { 7519 port { 7520 ddr_lpi_funnel_in0: endpoint { 7521 remote-endpoint = <&ddr_lpi_tpda_out>; 7522 }; 7523 }; 7524 }; 7525 7526 out-ports { 7527 port { 7528 ddr_lpi_funnel_out: endpoint { 7529 remote-endpoint = <&aoss_funnel_in3>; 7530 }; 7531 }; 7532 }; 7533 }; 7534 7535 tpdm@10c08000 { 7536 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7537 reg = <0x0 0x10c08000 0x0 0x1000>; 7538 7539 clocks = <&aoss_qmp>; 7540 clock-names = "apb_pclk"; 7541 7542 qcom,dsb-element-bits = <32>; 7543 qcom,dsb-msrs-num = <32>; 7544 7545 out-ports { 7546 port { 7547 mm_tpdm_out: endpoint { 7548 remote-endpoint = <&mm_funnel_in4>; 7549 }; 7550 }; 7551 }; 7552 }; 7553 7554 funnel@10c0b000 { 7555 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7556 reg = <0x0 0x10c0b000 0x0 0x1000>; 7557 7558 clocks = <&aoss_qmp>; 7559 clock-names = "apb_pclk"; 7560 7561 in-ports { 7562 #address-cells = <1>; 7563 #size-cells = <0>; 7564 7565 port@4 { 7566 reg = <4>; 7567 7568 mm_funnel_in4: endpoint { 7569 remote-endpoint = <&mm_tpdm_out>; 7570 }; 7571 }; 7572 }; 7573 7574 out-ports { 7575 port { 7576 mm_funnel_out: endpoint { 7577 remote-endpoint = <&dlct2_tpda_in4>; 7578 }; 7579 }; 7580 }; 7581 }; 7582 7583 tpdm@10c28000 { 7584 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7585 reg = <0x0 0x10c28000 0x0 0x1000>; 7586 7587 clocks = <&aoss_qmp>; 7588 clock-names = "apb_pclk"; 7589 7590 qcom,dsb-element-bits = <32>; 7591 qcom,dsb-msrs-num = <32>; 7592 7593 out-ports { 7594 port { 7595 dlct1_tpdm_out: endpoint { 7596 remote-endpoint = <&dlct1_tpda_in26>; 7597 }; 7598 }; 7599 }; 7600 }; 7601 7602 tpdm@10c29000 { 7603 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7604 reg = <0x0 0x10c29000 0x0 0x1000>; 7605 7606 clocks = <&aoss_qmp>; 7607 clock-names = "apb_pclk"; 7608 7609 qcom,cmb-element-bits = <64>; 7610 qcom,cmb-msrs-num = <32>; 7611 7612 out-ports { 7613 port { 7614 ipcc_tpdm_out: endpoint { 7615 remote-endpoint = <&dlct1_tpda_in27>; 7616 }; 7617 }; 7618 }; 7619 }; 7620 7621 tpda@10c2b000 { 7622 compatible = "qcom,coresight-tpda", "arm,primecell"; 7623 reg = <0x0 0x10c2b000 0x0 0x1000>; 7624 7625 clocks = <&aoss_qmp>; 7626 clock-names = "apb_pclk"; 7627 7628 in-ports { 7629 #address-cells = <1>; 7630 #size-cells = <0>; 7631 7632 port@4 { 7633 reg = <4>; 7634 7635 dlct1_tpda_in4: endpoint { 7636 remote-endpoint = <&lpass_cx_funnel_out>; 7637 }; 7638 }; 7639 7640 port@13 { 7641 reg = <19>; 7642 7643 dlct1_tpda_in19: endpoint { 7644 remote-endpoint = <&prng_tpdm_out>; 7645 }; 7646 }; 7647 7648 port@14 { 7649 reg = <20>; 7650 7651 dlct1_tpda_in20: endpoint { 7652 remote-endpoint = <&qm_tpdm_out>; 7653 }; 7654 }; 7655 7656 port@15 { 7657 reg = <21>; 7658 7659 dlct1_tpda_in21: endpoint { 7660 remote-endpoint = <&gcc_tpdm_out>; 7661 }; 7662 }; 7663 7664 port@1a { 7665 reg = <26>; 7666 7667 dlct1_tpda_in26: endpoint { 7668 remote-endpoint = <&dlct1_tpdm_out>; 7669 }; 7670 }; 7671 7672 port@1b { 7673 reg = <27>; 7674 7675 dlct1_tpda_in27: endpoint { 7676 remote-endpoint = <&ipcc_tpdm_out>; 7677 }; 7678 }; 7679 }; 7680 7681 out-ports { 7682 port { 7683 dlct1_tpda_out: endpoint { 7684 remote-endpoint = <&dlct1_funnel_in0>; 7685 }; 7686 }; 7687 }; 7688 }; 7689 7690 funnel@10c2c000 { 7691 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7692 reg = <0x0 0x10c2c000 0x0 0x1000>; 7693 7694 clocks = <&aoss_qmp>; 7695 clock-names = "apb_pclk"; 7696 7697 in-ports { 7698 #address-cells = <1>; 7699 #size-cells = <0>; 7700 7701 port@0 { 7702 reg = <0>; 7703 7704 dlct1_funnel_in0: endpoint { 7705 remote-endpoint = <&dlct1_tpda_out>; 7706 }; 7707 }; 7708 7709 port@4 { 7710 reg = <4>; 7711 7712 dlct1_funnel_in4: endpoint { 7713 remote-endpoint = <&dlct2_funnel_out>; 7714 }; 7715 }; 7716 7717 port@5 { 7718 reg = <5>; 7719 7720 dlct1_funnel_in5: endpoint { 7721 remote-endpoint = <&ddr_funnel0_out>; 7722 }; 7723 }; 7724 }; 7725 7726 out-ports { 7727 port { 7728 dlct1_funnel_out: endpoint { 7729 remote-endpoint = <&funnel1_in6>; 7730 }; 7731 }; 7732 }; 7733 }; 7734 7735 tpdm@10c38000 { 7736 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7737 reg = <0x0 0x10c38000 0x0 0x1000>; 7738 7739 clocks = <&aoss_qmp>; 7740 clock-names = "apb_pclk"; 7741 7742 qcom,cmb-element-bits = <64>; 7743 qcom,cmb-msrs-num = <32>; 7744 7745 out-ports { 7746 port { 7747 dlct2_tpdm0_out: endpoint { 7748 remote-endpoint = <&dlct2_tpda_in16>; 7749 }; 7750 }; 7751 }; 7752 }; 7753 7754 tpdm@10c39000 { 7755 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7756 reg = <0x0 0x10c39000 0x0 0x1000>; 7757 7758 clocks = <&aoss_qmp>; 7759 clock-names = "apb_pclk"; 7760 7761 qcom,cmb-element-bits = <64>; 7762 qcom,cmb-msrs-num = <32>; 7763 7764 out-ports { 7765 port { 7766 dlct2_tpdm1_out: endpoint { 7767 remote-endpoint = <&dlct2_tpda_in17>; 7768 }; 7769 }; 7770 }; 7771 }; 7772 7773 tpda@10c3c000 { 7774 compatible = "qcom,coresight-tpda", "arm,primecell"; 7775 reg = <0x0 0x10c3c000 0x0 0x1000>; 7776 7777 clocks = <&aoss_qmp>; 7778 clock-names = "apb_pclk"; 7779 7780 in-ports { 7781 #address-cells = <1>; 7782 #size-cells = <0>; 7783 7784 port@4 { 7785 reg = <4>; 7786 7787 dlct2_tpda_in4: endpoint { 7788 remote-endpoint = <&mm_funnel_out>; 7789 }; 7790 }; 7791 7792 port@f { 7793 reg = <15>; 7794 7795 dlct2_tpda_in15: endpoint { 7796 remote-endpoint = <&mxa_tpdm_out>; 7797 }; 7798 }; 7799 7800 port@10 { 7801 reg = <16>; 7802 7803 dlct2_tpda_in16: endpoint { 7804 remote-endpoint = <&dlct2_tpdm0_out>; 7805 }; 7806 }; 7807 7808 port@11 { 7809 reg = <17>; 7810 7811 dlct2_tpda_in17: endpoint { 7812 remote-endpoint = <&dlct2_tpdm1_out>; 7813 }; 7814 }; 7815 }; 7816 7817 out-ports { 7818 port { 7819 dlct2_tpda_out: endpoint { 7820 remote-endpoint = <&dlct2_funnel_in0>; 7821 }; 7822 }; 7823 }; 7824 }; 7825 7826 funnel@10c3d000 { 7827 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7828 reg = <0x0 0x10c3d000 0x0 0x1000>; 7829 7830 clocks = <&aoss_qmp>; 7831 clock-names = "apb_pclk"; 7832 7833 in-ports { 7834 port { 7835 dlct2_funnel_in0: endpoint { 7836 remote-endpoint = <&dlct2_tpda_out>; 7837 }; 7838 }; 7839 }; 7840 7841 out-ports { 7842 port { 7843 dlct2_funnel_out: endpoint { 7844 remote-endpoint = <&dlct1_funnel_in4>; 7845 }; 7846 }; 7847 }; 7848 }; 7849 7850 tpdm@10cc1000 { 7851 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7852 reg = <0x0 0x10cc1000 0x0 0x1000>; 7853 7854 clocks = <&aoss_qmp>; 7855 clock-names = "apb_pclk"; 7856 7857 qcom,cmb-element-bits = <64>; 7858 qcom,cmb-msrs-num = <32>; 7859 qcom,dsb-element-bits = <32>; 7860 qcom,dsb-msrs-num = <32>; 7861 status = "disabled"; 7862 7863 out-ports { 7864 port { 7865 tmess_tpdm1_out: endpoint { 7866 remote-endpoint = <&tmess_tpda_in2>; 7867 }; 7868 }; 7869 }; 7870 }; 7871 7872 tpda@10cc4000 { 7873 compatible = "qcom,coresight-tpda", "arm,primecell"; 7874 reg = <0x0 0x10cc4000 0x0 0x1000>; 7875 7876 clocks = <&aoss_qmp>; 7877 clock-names = "apb_pclk"; 7878 7879 in-ports { 7880 #address-cells = <1>; 7881 #size-cells = <0>; 7882 7883 port@2 { 7884 reg = <2>; 7885 7886 tmess_tpda_in2: endpoint { 7887 remote-endpoint = <&tmess_tpdm1_out>; 7888 }; 7889 }; 7890 }; 7891 7892 out-ports { 7893 port { 7894 tmess_tpda_out: endpoint { 7895 remote-endpoint = <&tmess_funnel_in0>; 7896 }; 7897 }; 7898 }; 7899 }; 7900 7901 funnel@10cc5000 { 7902 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7903 reg = <0x0 0x10cc5000 0x0 0x1000>; 7904 7905 clocks = <&aoss_qmp>; 7906 clock-names = "apb_pclk"; 7907 7908 in-ports { 7909 port { 7910 tmess_funnel_in0: endpoint { 7911 remote-endpoint = <&tmess_tpda_out>; 7912 }; 7913 }; 7914 }; 7915 7916 out-ports { 7917 port { 7918 tmess_funnel_out: endpoint { 7919 remote-endpoint = <&funnel1_in2>; 7920 }; 7921 }; 7922 }; 7923 }; 7924 7925 funnel@10d04000 { 7926 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7927 reg = <0x0 0x10d04000 0x0 0x1000>; 7928 7929 clocks = <&aoss_qmp>; 7930 clock-names = "apb_pclk"; 7931 7932 in-ports { 7933 #address-cells = <1>; 7934 #size-cells = <0>; 7935 7936 port@6 { 7937 reg = <6>; 7938 7939 ddr_funnel0_in6: endpoint { 7940 remote-endpoint = <&ddr_funnel1_out>; 7941 }; 7942 }; 7943 }; 7944 7945 out-ports { 7946 port { 7947 ddr_funnel0_out: endpoint { 7948 remote-endpoint = <&dlct1_funnel_in5>; 7949 }; 7950 }; 7951 }; 7952 }; 7953 7954 tpdm@10d08000 { 7955 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7956 reg = <0x0 0x10d08000 0x0 0x1000>; 7957 7958 clocks = <&aoss_qmp>; 7959 clock-names = "apb_pclk"; 7960 7961 qcom,cmb-element-bits = <32>; 7962 qcom,cmb-msrs-num = <32>; 7963 7964 out-ports { 7965 port { 7966 llcc0_tpdm_out: endpoint { 7967 remote-endpoint = <&llcc_tpda_in0>; 7968 }; 7969 }; 7970 }; 7971 }; 7972 7973 tpdm@10d09000 { 7974 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7975 reg = <0x0 0x10d09000 0x0 0x1000>; 7976 7977 clocks = <&aoss_qmp>; 7978 clock-names = "apb_pclk"; 7979 7980 qcom,cmb-element-bits = <32>; 7981 qcom,cmb-msrs-num = <32>; 7982 7983 out-ports { 7984 port { 7985 llcc1_tpdm_out: endpoint { 7986 remote-endpoint = <&llcc_tpda_in1>; 7987 }; 7988 }; 7989 }; 7990 }; 7991 7992 tpdm@10d0a000 { 7993 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7994 reg = <0x0 0x10d0a000 0x0 0x1000>; 7995 7996 clocks = <&aoss_qmp>; 7997 clock-names = "apb_pclk"; 7998 7999 qcom,cmb-element-bits = <32>; 8000 qcom,cmb-msrs-num = <32>; 8001 8002 out-ports { 8003 port { 8004 llcc2_tpdm_out: endpoint { 8005 remote-endpoint = <&llcc_tpda_in2>; 8006 }; 8007 }; 8008 }; 8009 }; 8010 8011 tpdm@10d0b000 { 8012 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8013 reg = <0x0 0x10d0b000 0x0 0x1000>; 8014 8015 clocks = <&aoss_qmp>; 8016 clock-names = "apb_pclk"; 8017 8018 qcom,cmb-element-bits = <32>; 8019 qcom,cmb-msrs-num = <32>; 8020 8021 out-ports { 8022 port { 8023 llcc3_tpdm_out: endpoint { 8024 remote-endpoint = <&llcc_tpda_in3>; 8025 }; 8026 }; 8027 }; 8028 }; 8029 8030 tpdm@10d0c000 { 8031 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8032 reg = <0x0 0x10d0c000 0x0 0x1000>; 8033 8034 clocks = <&aoss_qmp>; 8035 clock-names = "apb_pclk"; 8036 8037 qcom,cmb-element-bits = <32>; 8038 qcom,cmb-msrs-num = <32>; 8039 8040 out-ports { 8041 port { 8042 llcc4_tpdm_out: endpoint { 8043 remote-endpoint = <&llcc_tpda_in4>; 8044 }; 8045 }; 8046 }; 8047 }; 8048 8049 tpdm@10d0d000 { 8050 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8051 reg = <0x0 0x10d0d000 0x0 0x1000>; 8052 8053 clocks = <&aoss_qmp>; 8054 clock-names = "apb_pclk"; 8055 8056 qcom,cmb-element-bits = <32>; 8057 qcom,cmb-msrs-num = <32>; 8058 8059 out-ports { 8060 port { 8061 llcc5_tpdm_out: endpoint { 8062 remote-endpoint = <&llcc_tpda_in5>; 8063 }; 8064 }; 8065 }; 8066 }; 8067 8068 tpdm@10d0e000 { 8069 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8070 reg = <0x0 0x10d0e000 0x0 0x1000>; 8071 8072 clocks = <&aoss_qmp>; 8073 clock-names = "apb_pclk"; 8074 8075 qcom,cmb-element-bits = <32>; 8076 qcom,cmb-msrs-num = <32>; 8077 8078 out-ports { 8079 port { 8080 llcc6_tpdm_out: endpoint { 8081 remote-endpoint = <&llcc_tpda_in6>; 8082 }; 8083 }; 8084 }; 8085 }; 8086 8087 tpdm@10d0f000 { 8088 compatible = "qcom,coresight-tpdm", "arm,primecell"; 8089 reg = <0x0 0x10d0f000 0x0 0x1000>; 8090 8091 clocks = <&aoss_qmp>; 8092 clock-names = "apb_pclk"; 8093 8094 qcom,cmb-element-bits = <32>; 8095 qcom,cmb-msrs-num = <32>; 8096 8097 out-ports { 8098 port { 8099 llcc7_tpdm_out: endpoint { 8100 remote-endpoint = <&llcc_tpda_in7>; 8101 }; 8102 }; 8103 }; 8104 }; 8105 8106 tpda@10d12000 { 8107 compatible = "qcom,coresight-tpda", "arm,primecell"; 8108 reg = <0x0 0x10d12000 0x0 0x1000>; 8109 8110 clocks = <&aoss_qmp>; 8111 clock-names = "apb_pclk"; 8112 8113 in-ports { 8114 #address-cells = <1>; 8115 #size-cells = <0>; 8116 8117 port@0 { 8118 reg = <0>; 8119 8120 llcc_tpda_in0: endpoint { 8121 remote-endpoint = <&llcc0_tpdm_out>; 8122 }; 8123 }; 8124 8125 port@1 { 8126 reg = <1>; 8127 8128 llcc_tpda_in1: endpoint { 8129 remote-endpoint = <&llcc1_tpdm_out>; 8130 }; 8131 }; 8132 8133 port@2 { 8134 reg = <2>; 8135 8136 llcc_tpda_in2: endpoint { 8137 remote-endpoint = <&llcc2_tpdm_out>; 8138 }; 8139 }; 8140 8141 port@3 { 8142 reg = <3>; 8143 8144 llcc_tpda_in3: endpoint { 8145 remote-endpoint = <&llcc3_tpdm_out>; 8146 }; 8147 }; 8148 8149 port@4 { 8150 reg = <4>; 8151 8152 llcc_tpda_in4: endpoint { 8153 remote-endpoint = <&llcc4_tpdm_out>; 8154 }; 8155 }; 8156 8157 port@5 { 8158 reg = <5>; 8159 8160 llcc_tpda_in5: endpoint { 8161 remote-endpoint = <&llcc5_tpdm_out>; 8162 }; 8163 }; 8164 8165 port@6 { 8166 reg = <6>; 8167 8168 llcc_tpda_in6: endpoint { 8169 remote-endpoint = <&llcc6_tpdm_out>; 8170 }; 8171 }; 8172 8173 port@7 { 8174 reg = <7>; 8175 8176 llcc_tpda_in7: endpoint { 8177 remote-endpoint = <&llcc7_tpdm_out>; 8178 }; 8179 }; 8180 }; 8181 8182 out-ports { 8183 port { 8184 llcc_tpda_out: endpoint { 8185 remote-endpoint = <&ddr_funnel1_in0>; 8186 }; 8187 }; 8188 }; 8189 }; 8190 8191 funnel@10d13000 { 8192 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 8193 reg = <0x0 0x10d13000 0x0 0x1000>; 8194 8195 clocks = <&aoss_qmp>; 8196 clock-names = "apb_pclk"; 8197 8198 in-ports { 8199 port { 8200 ddr_funnel1_in0: endpoint { 8201 remote-endpoint = <&llcc_tpda_out>; 8202 }; 8203 }; 8204 }; 8205 8206 out-ports { 8207 port { 8208 ddr_funnel1_out: endpoint { 8209 remote-endpoint = <&ddr_funnel0_in6>; 8210 }; 8211 }; 8212 }; 8213 }; 8214 8215 apps_smmu: iommu@15000000 { 8216 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 8217 reg = <0 0x15000000 0 0x100000>; 8218 8219 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 8220 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 8221 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 8222 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 8223 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 8224 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 8225 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 8226 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 8227 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 8228 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 8229 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 8230 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 8231 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 8232 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 8233 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 8234 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 8235 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 8236 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 8237 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 8238 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 8239 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 8240 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 8241 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 8242 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 8243 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 8244 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 8245 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 8246 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 8247 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 8248 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 8249 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 8250 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 8251 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 8252 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 8253 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 8254 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 8255 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 8256 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 8257 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 8258 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 8259 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 8260 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 8261 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 8262 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 8263 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 8264 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 8265 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 8266 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 8267 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 8268 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 8269 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 8270 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 8271 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 8272 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 8273 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 8274 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 8275 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 8276 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 8277 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 8278 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 8279 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 8280 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 8281 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 8282 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 8283 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 8284 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 8285 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 8286 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 8287 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 8288 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 8289 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 8290 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 8291 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 8292 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 8293 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 8294 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 8295 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 8296 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 8297 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 8298 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 8299 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 8300 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 8301 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 8302 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 8303 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 8304 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 8305 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 8306 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 8307 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 8308 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 8309 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 8310 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 8311 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 8312 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 8313 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 8314 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 8315 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 8316 8317 #iommu-cells = <2>; 8318 #global-interrupts = <1>; 8319 8320 dma-coherent; 8321 }; 8322 8323 pcie_smmu: iommu@15400000 { 8324 compatible = "arm,smmu-v3"; 8325 reg = <0 0x15400000 0 0x80000>; 8326 #iommu-cells = <1>; 8327 interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 8328 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 8329 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>; 8330 interrupt-names = "eventq", 8331 "gerror", 8332 "cmdq-sync"; 8333 dma-coherent; 8334 status = "reserved"; /* Controlled by Gunyah. */ 8335 }; 8336 8337 intc: interrupt-controller@17000000 { 8338 compatible = "arm,gic-v3"; 8339 reg = <0 0x17000000 0 0x10000>, /* GICD */ 8340 <0 0x17080000 0 0x300000>; /* GICR * 12 */ 8341 8342 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 8343 8344 #interrupt-cells = <3>; 8345 interrupt-controller; 8346 8347 #redistributor-regions = <1>; 8348 redistributor-stride = <0x0 0x40000>; 8349 8350 #address-cells = <2>; 8351 #size-cells = <2>; 8352 ranges; 8353 8354 gic_its: msi-controller@17040000 { 8355 compatible = "arm,gic-v3-its"; 8356 reg = <0 0x17040000 0 0x40000>; 8357 8358 msi-controller; 8359 #msi-cells = <1>; 8360 }; 8361 }; 8362 8363 apss_watchdog: watchdog@17410000 { 8364 compatible = "qcom,apss-wdt-x1e80100", "qcom,kpss-wdt"; 8365 reg = <0x0 0x17410000 0x0 0x1000>; 8366 clocks = <&sleep_clk>; 8367 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 8368 status = "reserved"; /* Reserved by Gunyah */ 8369 }; 8370 8371 cpucp_mbox: mailbox@17430000 { 8372 compatible = "qcom,x1e80100-cpucp-mbox"; 8373 reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>; 8374 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 8375 #mbox-cells = <1>; 8376 }; 8377 8378 apps_rsc: rsc@17500000 { 8379 compatible = "qcom,rpmh-rsc"; 8380 reg = <0 0x17500000 0 0x10000>, 8381 <0 0x17510000 0 0x10000>, 8382 <0 0x17520000 0 0x10000>; 8383 reg-names = "drv-0", "drv-1", "drv-2"; 8384 8385 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 8386 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 8387 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 8388 qcom,tcs-offset = <0xd00>; 8389 qcom,drv-id = <2>; 8390 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 8391 <WAKE_TCS 2>, <CONTROL_TCS 0>; 8392 8393 label = "apps_rsc"; 8394 power-domains = <&system_pd>; 8395 8396 apps_bcm_voter: bcm-voter { 8397 compatible = "qcom,bcm-voter"; 8398 }; 8399 8400 rpmhcc: clock-controller { 8401 compatible = "qcom,x1e80100-rpmh-clk"; 8402 8403 clocks = <&xo_board>; 8404 clock-names = "xo"; 8405 8406 #clock-cells = <1>; 8407 }; 8408 8409 rpmhpd: power-controller { 8410 compatible = "qcom,x1e80100-rpmhpd"; 8411 8412 operating-points-v2 = <&rpmhpd_opp_table>; 8413 8414 #power-domain-cells = <1>; 8415 8416 rpmhpd_opp_table: opp-table { 8417 compatible = "operating-points-v2"; 8418 8419 rpmhpd_opp_ret: opp-16 { 8420 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 8421 }; 8422 8423 rpmhpd_opp_min_svs: opp-48 { 8424 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 8425 }; 8426 8427 rpmhpd_opp_low_svs_d2: opp-52 { 8428 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 8429 }; 8430 8431 rpmhpd_opp_low_svs_d1: opp-56 { 8432 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 8433 }; 8434 8435 rpmhpd_opp_low_svs_d0: opp-60 { 8436 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 8437 }; 8438 8439 rpmhpd_opp_low_svs: opp-64 { 8440 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 8441 }; 8442 8443 rpmhpd_opp_low_svs_l1: opp-80 { 8444 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 8445 }; 8446 8447 rpmhpd_opp_svs: opp-128 { 8448 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 8449 }; 8450 8451 rpmhpd_opp_svs_l0: opp-144 { 8452 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 8453 }; 8454 8455 rpmhpd_opp_svs_l1: opp-192 { 8456 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 8457 }; 8458 8459 rpmhpd_opp_nom: opp-256 { 8460 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 8461 }; 8462 8463 rpmhpd_opp_nom_l1: opp-320 { 8464 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 8465 }; 8466 8467 rpmhpd_opp_nom_l2: opp-336 { 8468 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 8469 }; 8470 8471 rpmhpd_opp_turbo: opp-384 { 8472 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 8473 }; 8474 8475 rpmhpd_opp_turbo_l1: opp-416 { 8476 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 8477 }; 8478 }; 8479 }; 8480 }; 8481 8482 timer@17800000 { 8483 compatible = "arm,armv7-timer-mem"; 8484 reg = <0 0x17800000 0 0x1000>; 8485 8486 #address-cells = <2>; 8487 #size-cells = <1>; 8488 ranges = <0 0 0 0 0x20000000>; 8489 8490 frame@17801000 { 8491 reg = <0 0x17801000 0x1000>, 8492 <0 0x17802000 0x1000>; 8493 8494 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 8495 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 8496 8497 frame-number = <0>; 8498 }; 8499 8500 frame@17803000 { 8501 reg = <0 0x17803000 0x1000>; 8502 8503 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 8504 8505 frame-number = <1>; 8506 8507 status = "disabled"; 8508 }; 8509 8510 frame@17805000 { 8511 reg = <0 0x17805000 0x1000>; 8512 8513 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 8514 8515 frame-number = <2>; 8516 8517 status = "disabled"; 8518 }; 8519 8520 frame@17807000 { 8521 reg = <0 0x17807000 0x1000>; 8522 8523 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 8524 8525 frame-number = <3>; 8526 8527 status = "disabled"; 8528 }; 8529 8530 frame@17809000 { 8531 reg = <0 0x17809000 0x1000>; 8532 8533 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 8534 8535 frame-number = <4>; 8536 8537 status = "disabled"; 8538 }; 8539 8540 frame@1780b000 { 8541 reg = <0 0x1780b000 0x1000>; 8542 8543 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 8544 8545 frame-number = <5>; 8546 8547 status = "disabled"; 8548 }; 8549 8550 frame@1780d000 { 8551 reg = <0 0x1780d000 0x1000>; 8552 8553 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 8554 8555 frame-number = <6>; 8556 8557 status = "disabled"; 8558 }; 8559 }; 8560 8561 sram: sram@18b4e000 { 8562 compatible = "mmio-sram"; 8563 reg = <0x0 0x18b4e000 0x0 0x400>; 8564 8565 #address-cells = <1>; 8566 #size-cells = <1>; 8567 ranges = <0x0 0x0 0x18b4e000 0x400>; 8568 8569 cpu_scp_lpri0: scp-sram-section@0 { 8570 compatible = "arm,scmi-shmem"; 8571 reg = <0x0 0x200>; 8572 }; 8573 8574 cpu_scp_lpri1: scp-sram-section@200 { 8575 compatible = "arm,scmi-shmem"; 8576 reg = <0x200 0x200>; 8577 }; 8578 }; 8579 8580 sbsa_watchdog: watchdog@1c840000 { 8581 compatible = "arm,sbsa-gwdt"; 8582 reg = <0 0x1c840000 0 0x1000>, 8583 <0 0x1c850000 0 0x1000>; 8584 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 8585 }; 8586 8587 qfprom: efuse@221c8000 { 8588 compatible = "qcom,x1e80100-qfprom", "qcom,qfprom"; 8589 reg = <0 0x221c8000 0 0x1000>; 8590 #address-cells = <1>; 8591 #size-cells = <1>; 8592 8593 gpu_speed_bin: gpu-speed-bin@119 { 8594 reg = <0x119 0x2>; 8595 bits = <7 8>; 8596 }; 8597 }; 8598 8599 pmu@24091000 { 8600 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 8601 reg = <0 0x24091000 0 0x1000>; 8602 8603 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 8604 8605 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 8606 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 8607 8608 operating-points-v2 = <&llcc_bwmon_opp_table>; 8609 8610 llcc_bwmon_opp_table: opp-table { 8611 compatible = "operating-points-v2"; 8612 8613 opp-0 { 8614 opp-peak-kBps = <800000>; 8615 }; 8616 8617 opp-1 { 8618 opp-peak-kBps = <2188000>; 8619 }; 8620 8621 opp-2 { 8622 opp-peak-kBps = <3072000>; 8623 }; 8624 8625 opp-3 { 8626 opp-peak-kBps = <6220800>; 8627 }; 8628 8629 opp-4 { 8630 opp-peak-kBps = <6835200>; 8631 }; 8632 8633 opp-5 { 8634 opp-peak-kBps = <8371200>; 8635 }; 8636 8637 opp-6 { 8638 opp-peak-kBps = <10944000>; 8639 }; 8640 8641 opp-7 { 8642 opp-peak-kBps = <12748800>; 8643 }; 8644 8645 opp-8 { 8646 opp-peak-kBps = <14745600>; 8647 }; 8648 8649 opp-9 { 8650 opp-peak-kBps = <16896000>; 8651 }; 8652 }; 8653 }; 8654 8655 /* cluster0 */ 8656 bwmon_cluster0: pmu@240b3400 { 8657 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8658 reg = <0 0x240b3400 0 0x600>; 8659 8660 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8661 8662 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8663 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8664 8665 operating-points-v2 = <&cpu_bwmon_opp_table>; 8666 }; 8667 8668 /* cluster2 */ 8669 bwmon_cluster2: pmu@240b5400 { 8670 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8671 reg = <0 0x240b5400 0 0x600>; 8672 8673 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8674 8675 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8676 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8677 8678 operating-points-v2 = <&cpu_bwmon_opp_table>; 8679 8680 cpu_bwmon_opp_table: opp-table { 8681 compatible = "operating-points-v2"; 8682 8683 opp-0 { 8684 opp-peak-kBps = <4800000>; 8685 }; 8686 8687 opp-1 { 8688 opp-peak-kBps = <7464000>; 8689 }; 8690 8691 opp-2 { 8692 opp-peak-kBps = <9600000>; 8693 }; 8694 8695 opp-3 { 8696 opp-peak-kBps = <12896000>; 8697 }; 8698 8699 opp-4 { 8700 opp-peak-kBps = <14928000>; 8701 }; 8702 8703 opp-5 { 8704 opp-peak-kBps = <17064000>; 8705 }; 8706 }; 8707 }; 8708 8709 /* cluster1 */ 8710 pmu@240b6400 { 8711 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8712 reg = <0 0x240b6400 0 0x600>; 8713 8714 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8715 8716 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8717 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8718 8719 operating-points-v2 = <&cpu_bwmon_opp_table>; 8720 }; 8721 8722 system-cache-controller@25000000 { 8723 compatible = "qcom,x1e80100-llcc"; 8724 reg = <0 0x25000000 0 0x200000>, 8725 <0 0x25200000 0 0x200000>, 8726 <0 0x25400000 0 0x200000>, 8727 <0 0x25600000 0 0x200000>, 8728 <0 0x25800000 0 0x200000>, 8729 <0 0x25a00000 0 0x200000>, 8730 <0 0x25c00000 0 0x200000>, 8731 <0 0x25e00000 0 0x200000>, 8732 <0 0x26000000 0 0x200000>, 8733 <0 0x26200000 0 0x200000>; 8734 reg-names = "llcc0_base", 8735 "llcc1_base", 8736 "llcc2_base", 8737 "llcc3_base", 8738 "llcc4_base", 8739 "llcc5_base", 8740 "llcc6_base", 8741 "llcc7_base", 8742 "llcc_broadcast_base", 8743 "llcc_broadcast_and_base"; 8744 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 8745 }; 8746 8747 remoteproc_cdsp: remoteproc@32300000 { 8748 compatible = "qcom,x1e80100-cdsp-pas"; 8749 reg = <0x0 0x32300000 0x0 0x10000>; 8750 8751 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 8752 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 8753 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 8754 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 8755 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 8756 interrupt-names = "wdog", 8757 "fatal", 8758 "ready", 8759 "handover", 8760 "stop-ack"; 8761 8762 clocks = <&rpmhcc RPMH_CXO_CLK>; 8763 clock-names = "xo"; 8764 8765 power-domains = <&rpmhpd RPMHPD_CX>, 8766 <&rpmhpd RPMHPD_MXC>, 8767 <&rpmhpd RPMHPD_NSP>; 8768 power-domain-names = "cx", 8769 "mxc", 8770 "nsp"; 8771 8772 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 8773 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 8774 8775 memory-region = <&cdsp_mem>, 8776 <&q6_cdsp_dtb_mem>; 8777 8778 qcom,qmp = <&aoss_qmp>; 8779 8780 qcom,smem-states = <&smp2p_cdsp_out 0>; 8781 qcom,smem-state-names = "stop"; 8782 8783 status = "disabled"; 8784 8785 glink-edge { 8786 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 8787 IPCC_MPROC_SIGNAL_GLINK_QMP 8788 IRQ_TYPE_EDGE_RISING>; 8789 mboxes = <&ipcc IPCC_CLIENT_CDSP 8790 IPCC_MPROC_SIGNAL_GLINK_QMP>; 8791 8792 label = "cdsp"; 8793 qcom,remote-pid = <5>; 8794 8795 fastrpc { 8796 compatible = "qcom,fastrpc"; 8797 qcom,glink-channels = "fastrpcglink-apps-dsp"; 8798 label = "cdsp"; 8799 qcom,non-secure-domain; 8800 #address-cells = <1>; 8801 #size-cells = <0>; 8802 8803 compute-cb@1 { 8804 compatible = "qcom,fastrpc-compute-cb"; 8805 reg = <1>; 8806 iommus = <&apps_smmu 0x0c01 0x20>; 8807 dma-coherent; 8808 }; 8809 8810 compute-cb@2 { 8811 compatible = "qcom,fastrpc-compute-cb"; 8812 reg = <2>; 8813 iommus = <&apps_smmu 0x0c02 0x20>; 8814 dma-coherent; 8815 }; 8816 8817 compute-cb@3 { 8818 compatible = "qcom,fastrpc-compute-cb"; 8819 reg = <3>; 8820 iommus = <&apps_smmu 0x0c03 0x20>; 8821 dma-coherent; 8822 }; 8823 8824 compute-cb@4 { 8825 compatible = "qcom,fastrpc-compute-cb"; 8826 reg = <4>; 8827 iommus = <&apps_smmu 0x0c04 0x20>; 8828 dma-coherent; 8829 }; 8830 8831 compute-cb@5 { 8832 compatible = "qcom,fastrpc-compute-cb"; 8833 reg = <5>; 8834 iommus = <&apps_smmu 0x0c05 0x20>; 8835 dma-coherent; 8836 }; 8837 8838 compute-cb@6 { 8839 compatible = "qcom,fastrpc-compute-cb"; 8840 reg = <6>; 8841 iommus = <&apps_smmu 0x0c06 0x20>; 8842 dma-coherent; 8843 }; 8844 8845 compute-cb@7 { 8846 compatible = "qcom,fastrpc-compute-cb"; 8847 reg = <7>; 8848 iommus = <&apps_smmu 0x0c07 0x20>; 8849 dma-coherent; 8850 }; 8851 8852 compute-cb@8 { 8853 compatible = "qcom,fastrpc-compute-cb"; 8854 reg = <8>; 8855 iommus = <&apps_smmu 0x0c08 0x20>; 8856 dma-coherent; 8857 }; 8858 8859 /* note: compute-cb@9 is secure */ 8860 8861 compute-cb@10 { 8862 compatible = "qcom,fastrpc-compute-cb"; 8863 reg = <10>; 8864 iommus = <&apps_smmu 0x0c0c 0x20>; 8865 dma-coherent; 8866 }; 8867 8868 compute-cb@11 { 8869 compatible = "qcom,fastrpc-compute-cb"; 8870 reg = <11>; 8871 iommus = <&apps_smmu 0x0c0d 0x20>; 8872 dma-coherent; 8873 }; 8874 8875 compute-cb@12 { 8876 compatible = "qcom,fastrpc-compute-cb"; 8877 reg = <12>; 8878 iommus = <&apps_smmu 0x0c0e 0x20>; 8879 dma-coherent; 8880 }; 8881 8882 compute-cb@13 { 8883 compatible = "qcom,fastrpc-compute-cb"; 8884 reg = <13>; 8885 iommus = <&apps_smmu 0x0c0f 0x20>; 8886 dma-coherent; 8887 }; 8888 }; 8889 }; 8890 }; 8891 }; 8892 8893 timer { 8894 compatible = "arm,armv8-timer"; 8895 8896 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 8897 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 8898 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 8899 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 8900 }; 8901 8902 thermal_zones: thermal-zones { 8903 aoss0-thermal { 8904 thermal-sensors = <&tsens0 0>; 8905 8906 trips { 8907 trip-point0 { 8908 temperature = <90000>; 8909 hysteresis = <2000>; 8910 type = "hot"; 8911 }; 8912 8913 aoss0-critical { 8914 temperature = <115000>; 8915 hysteresis = <1000>; 8916 type = "critical"; 8917 }; 8918 }; 8919 }; 8920 8921 cpu0-0-top-thermal { 8922 thermal-sensors = <&tsens0 1>; 8923 8924 trips { 8925 cpu-critical { 8926 temperature = <115000>; 8927 hysteresis = <1000>; 8928 type = "critical"; 8929 }; 8930 }; 8931 }; 8932 8933 cpu0-0-btm-thermal { 8934 thermal-sensors = <&tsens0 2>; 8935 8936 trips { 8937 cpu-critical { 8938 temperature = <115000>; 8939 hysteresis = <1000>; 8940 type = "critical"; 8941 }; 8942 }; 8943 }; 8944 8945 cpu0-1-top-thermal { 8946 thermal-sensors = <&tsens0 3>; 8947 8948 trips { 8949 cpu-critical { 8950 temperature = <115000>; 8951 hysteresis = <1000>; 8952 type = "critical"; 8953 }; 8954 }; 8955 }; 8956 8957 cpu0-1-btm-thermal { 8958 thermal-sensors = <&tsens0 4>; 8959 8960 trips { 8961 cpu-critical { 8962 temperature = <115000>; 8963 hysteresis = <1000>; 8964 type = "critical"; 8965 }; 8966 }; 8967 }; 8968 8969 cpu0-2-top-thermal { 8970 thermal-sensors = <&tsens0 5>; 8971 8972 trips { 8973 cpu-critical { 8974 temperature = <115000>; 8975 hysteresis = <1000>; 8976 type = "critical"; 8977 }; 8978 }; 8979 }; 8980 8981 cpu0-2-btm-thermal { 8982 thermal-sensors = <&tsens0 6>; 8983 8984 trips { 8985 cpu-critical { 8986 temperature = <115000>; 8987 hysteresis = <1000>; 8988 type = "critical"; 8989 }; 8990 }; 8991 }; 8992 8993 cpu0-3-top-thermal { 8994 thermal-sensors = <&tsens0 7>; 8995 8996 trips { 8997 cpu-critical { 8998 temperature = <115000>; 8999 hysteresis = <1000>; 9000 type = "critical"; 9001 }; 9002 }; 9003 }; 9004 9005 cpu0-3-btm-thermal { 9006 thermal-sensors = <&tsens0 8>; 9007 9008 trips { 9009 cpu-critical { 9010 temperature = <115000>; 9011 hysteresis = <1000>; 9012 type = "critical"; 9013 }; 9014 }; 9015 }; 9016 9017 cpuss0-top-thermal { 9018 thermal-sensors = <&tsens0 9>; 9019 9020 trips { 9021 cpuss2-critical { 9022 temperature = <115000>; 9023 hysteresis = <1000>; 9024 type = "critical"; 9025 }; 9026 }; 9027 }; 9028 9029 cpuss0-btm-thermal { 9030 thermal-sensors = <&tsens0 10>; 9031 9032 trips { 9033 cpuss2-critical { 9034 temperature = <115000>; 9035 hysteresis = <1000>; 9036 type = "critical"; 9037 }; 9038 }; 9039 }; 9040 9041 mem-thermal { 9042 thermal-sensors = <&tsens0 11>; 9043 9044 trips { 9045 trip-point0 { 9046 temperature = <90000>; 9047 hysteresis = <2000>; 9048 type = "hot"; 9049 }; 9050 9051 mem-critical { 9052 temperature = <115000>; 9053 hysteresis = <0>; 9054 type = "critical"; 9055 }; 9056 }; 9057 }; 9058 9059 video-thermal { 9060 thermal-sensors = <&tsens0 12>; 9061 9062 trips { 9063 trip-point0 { 9064 temperature = <90000>; 9065 hysteresis = <2000>; 9066 type = "hot"; 9067 }; 9068 9069 video-critical { 9070 temperature = <115000>; 9071 hysteresis = <1000>; 9072 type = "critical"; 9073 }; 9074 }; 9075 }; 9076 9077 aoss1-thermal { 9078 thermal-sensors = <&tsens1 0>; 9079 9080 trips { 9081 trip-point0 { 9082 temperature = <90000>; 9083 hysteresis = <2000>; 9084 type = "hot"; 9085 }; 9086 9087 aoss0-critical { 9088 temperature = <115000>; 9089 hysteresis = <1000>; 9090 type = "critical"; 9091 }; 9092 }; 9093 }; 9094 9095 cpu1-0-top-thermal { 9096 thermal-sensors = <&tsens1 1>; 9097 9098 trips { 9099 cpu-critical { 9100 temperature = <115000>; 9101 hysteresis = <1000>; 9102 type = "critical"; 9103 }; 9104 }; 9105 }; 9106 9107 cpu1-0-btm-thermal { 9108 thermal-sensors = <&tsens1 2>; 9109 9110 trips { 9111 cpu-critical { 9112 temperature = <115000>; 9113 hysteresis = <1000>; 9114 type = "critical"; 9115 }; 9116 }; 9117 }; 9118 9119 cpu1-1-top-thermal { 9120 thermal-sensors = <&tsens1 3>; 9121 9122 trips { 9123 cpu-critical { 9124 temperature = <115000>; 9125 hysteresis = <1000>; 9126 type = "critical"; 9127 }; 9128 }; 9129 }; 9130 9131 cpu1-1-btm-thermal { 9132 thermal-sensors = <&tsens1 4>; 9133 9134 trips { 9135 cpu-critical { 9136 temperature = <115000>; 9137 hysteresis = <1000>; 9138 type = "critical"; 9139 }; 9140 }; 9141 }; 9142 9143 cpu1-2-top-thermal { 9144 thermal-sensors = <&tsens1 5>; 9145 9146 trips { 9147 cpu-critical { 9148 temperature = <115000>; 9149 hysteresis = <1000>; 9150 type = "critical"; 9151 }; 9152 }; 9153 }; 9154 9155 cpu1-2-btm-thermal { 9156 thermal-sensors = <&tsens1 6>; 9157 9158 trips { 9159 cpu-critical { 9160 temperature = <115000>; 9161 hysteresis = <1000>; 9162 type = "critical"; 9163 }; 9164 }; 9165 }; 9166 9167 cpu1-3-top-thermal { 9168 thermal-sensors = <&tsens1 7>; 9169 9170 trips { 9171 cpu-critical { 9172 temperature = <115000>; 9173 hysteresis = <1000>; 9174 type = "critical"; 9175 }; 9176 }; 9177 }; 9178 9179 cpu1-3-btm-thermal { 9180 thermal-sensors = <&tsens1 8>; 9181 9182 trips { 9183 cpu-critical { 9184 temperature = <115000>; 9185 hysteresis = <1000>; 9186 type = "critical"; 9187 }; 9188 }; 9189 }; 9190 9191 cpuss1-top-thermal { 9192 thermal-sensors = <&tsens1 9>; 9193 9194 trips { 9195 cpuss2-critical { 9196 temperature = <115000>; 9197 hysteresis = <1000>; 9198 type = "critical"; 9199 }; 9200 }; 9201 }; 9202 9203 cpuss1-btm-thermal { 9204 thermal-sensors = <&tsens1 10>; 9205 9206 trips { 9207 cpuss2-critical { 9208 temperature = <115000>; 9209 hysteresis = <1000>; 9210 type = "critical"; 9211 }; 9212 }; 9213 }; 9214 9215 aoss2-thermal { 9216 thermal-sensors = <&tsens2 0>; 9217 9218 trips { 9219 trip-point0 { 9220 temperature = <90000>; 9221 hysteresis = <2000>; 9222 type = "hot"; 9223 }; 9224 9225 aoss0-critical { 9226 temperature = <115000>; 9227 hysteresis = <1000>; 9228 type = "critical"; 9229 }; 9230 }; 9231 }; 9232 9233 cpu2-0-top-thermal { 9234 thermal-sensors = <&tsens2 1>; 9235 9236 trips { 9237 cpu-critical { 9238 temperature = <115000>; 9239 hysteresis = <1000>; 9240 type = "critical"; 9241 }; 9242 }; 9243 }; 9244 9245 cpu2-0-btm-thermal { 9246 thermal-sensors = <&tsens2 2>; 9247 9248 trips { 9249 cpu-critical { 9250 temperature = <115000>; 9251 hysteresis = <1000>; 9252 type = "critical"; 9253 }; 9254 }; 9255 }; 9256 9257 cpu2-1-top-thermal { 9258 thermal-sensors = <&tsens2 3>; 9259 9260 trips { 9261 cpu-critical { 9262 temperature = <115000>; 9263 hysteresis = <1000>; 9264 type = "critical"; 9265 }; 9266 }; 9267 }; 9268 9269 cpu2-1-btm-thermal { 9270 thermal-sensors = <&tsens2 4>; 9271 9272 trips { 9273 cpu-critical { 9274 temperature = <115000>; 9275 hysteresis = <1000>; 9276 type = "critical"; 9277 }; 9278 }; 9279 }; 9280 9281 cpu2-2-top-thermal { 9282 thermal-sensors = <&tsens2 5>; 9283 9284 trips { 9285 cpu-critical { 9286 temperature = <115000>; 9287 hysteresis = <1000>; 9288 type = "critical"; 9289 }; 9290 }; 9291 }; 9292 9293 cpu2-2-btm-thermal { 9294 thermal-sensors = <&tsens2 6>; 9295 9296 trips { 9297 cpu-critical { 9298 temperature = <115000>; 9299 hysteresis = <1000>; 9300 type = "critical"; 9301 }; 9302 }; 9303 }; 9304 9305 cpu2-3-top-thermal { 9306 thermal-sensors = <&tsens2 7>; 9307 9308 trips { 9309 cpu-critical { 9310 temperature = <115000>; 9311 hysteresis = <1000>; 9312 type = "critical"; 9313 }; 9314 }; 9315 }; 9316 9317 cpu2-3-btm-thermal { 9318 thermal-sensors = <&tsens2 8>; 9319 9320 trips { 9321 cpu-critical { 9322 temperature = <115000>; 9323 hysteresis = <1000>; 9324 type = "critical"; 9325 }; 9326 }; 9327 }; 9328 9329 cpuss2-top-thermal { 9330 thermal-sensors = <&tsens2 9>; 9331 9332 trips { 9333 cpuss2-critical { 9334 temperature = <115000>; 9335 hysteresis = <1000>; 9336 type = "critical"; 9337 }; 9338 }; 9339 }; 9340 9341 cpuss2-btm-thermal { 9342 thermal-sensors = <&tsens2 10>; 9343 9344 trips { 9345 cpuss2-critical { 9346 temperature = <115000>; 9347 hysteresis = <1000>; 9348 type = "critical"; 9349 }; 9350 }; 9351 }; 9352 9353 aoss3-thermal { 9354 thermal-sensors = <&tsens3 0>; 9355 9356 trips { 9357 trip-point0 { 9358 temperature = <90000>; 9359 hysteresis = <2000>; 9360 type = "hot"; 9361 }; 9362 9363 aoss0-critical { 9364 temperature = <115000>; 9365 hysteresis = <1000>; 9366 type = "critical"; 9367 }; 9368 }; 9369 }; 9370 9371 nsp0-thermal { 9372 thermal-sensors = <&tsens3 1>; 9373 9374 trips { 9375 trip-point0 { 9376 temperature = <90000>; 9377 hysteresis = <2000>; 9378 type = "hot"; 9379 }; 9380 9381 nsp0-critical { 9382 temperature = <115000>; 9383 hysteresis = <1000>; 9384 type = "critical"; 9385 }; 9386 }; 9387 }; 9388 9389 nsp1-thermal { 9390 thermal-sensors = <&tsens3 2>; 9391 9392 trips { 9393 trip-point0 { 9394 temperature = <90000>; 9395 hysteresis = <2000>; 9396 type = "hot"; 9397 }; 9398 9399 nsp1-critical { 9400 temperature = <115000>; 9401 hysteresis = <1000>; 9402 type = "critical"; 9403 }; 9404 }; 9405 }; 9406 9407 nsp2-thermal { 9408 thermal-sensors = <&tsens3 3>; 9409 9410 trips { 9411 trip-point0 { 9412 temperature = <90000>; 9413 hysteresis = <2000>; 9414 type = "hot"; 9415 }; 9416 9417 nsp2-critical { 9418 temperature = <115000>; 9419 hysteresis = <1000>; 9420 type = "critical"; 9421 }; 9422 }; 9423 }; 9424 9425 nsp3-thermal { 9426 thermal-sensors = <&tsens3 4>; 9427 9428 trips { 9429 trip-point0 { 9430 temperature = <90000>; 9431 hysteresis = <2000>; 9432 type = "hot"; 9433 }; 9434 9435 nsp3-critical { 9436 temperature = <115000>; 9437 hysteresis = <1000>; 9438 type = "critical"; 9439 }; 9440 }; 9441 }; 9442 9443 gpuss-0-thermal { 9444 polling-delay-passive = <200>; 9445 9446 thermal-sensors = <&tsens3 5>; 9447 9448 cooling-maps { 9449 map0 { 9450 trip = <&gpuss0_alert0>; 9451 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9452 }; 9453 }; 9454 9455 trips { 9456 gpuss0_alert0: trip-point0 { 9457 temperature = <95000>; 9458 hysteresis = <1000>; 9459 type = "passive"; 9460 }; 9461 9462 gpu-critical { 9463 temperature = <115000>; 9464 hysteresis = <1000>; 9465 type = "critical"; 9466 }; 9467 }; 9468 }; 9469 9470 gpuss-1-thermal { 9471 polling-delay-passive = <200>; 9472 9473 thermal-sensors = <&tsens3 6>; 9474 9475 cooling-maps { 9476 map0 { 9477 trip = <&gpuss1_alert0>; 9478 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9479 }; 9480 }; 9481 9482 trips { 9483 gpuss1_alert0: trip-point0 { 9484 temperature = <95000>; 9485 hysteresis = <1000>; 9486 type = "passive"; 9487 }; 9488 9489 gpu-critical { 9490 temperature = <115000>; 9491 hysteresis = <1000>; 9492 type = "critical"; 9493 }; 9494 }; 9495 }; 9496 9497 gpuss-2-thermal { 9498 polling-delay-passive = <200>; 9499 9500 thermal-sensors = <&tsens3 7>; 9501 9502 cooling-maps { 9503 map0 { 9504 trip = <&gpuss2_alert0>; 9505 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9506 }; 9507 }; 9508 9509 trips { 9510 gpuss2_alert0: trip-point0 { 9511 temperature = <95000>; 9512 hysteresis = <1000>; 9513 type = "passive"; 9514 }; 9515 9516 gpu-critical { 9517 temperature = <115000>; 9518 hysteresis = <1000>; 9519 type = "critical"; 9520 }; 9521 }; 9522 }; 9523 9524 gpuss-3-thermal { 9525 polling-delay-passive = <200>; 9526 9527 thermal-sensors = <&tsens3 8>; 9528 9529 cooling-maps { 9530 map0 { 9531 trip = <&gpuss3_alert0>; 9532 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9533 }; 9534 }; 9535 9536 trips { 9537 gpuss3_alert0: trip-point0 { 9538 temperature = <95000>; 9539 hysteresis = <1000>; 9540 type = "passive"; 9541 }; 9542 9543 gpu-critical { 9544 temperature = <115000>; 9545 hysteresis = <1000>; 9546 type = "critical"; 9547 }; 9548 }; 9549 }; 9550 9551 gpuss-4-thermal { 9552 polling-delay-passive = <200>; 9553 9554 thermal-sensors = <&tsens3 9>; 9555 9556 cooling-maps { 9557 map0 { 9558 trip = <&gpuss4_alert0>; 9559 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9560 }; 9561 }; 9562 9563 trips { 9564 gpuss4_alert0: trip-point0 { 9565 temperature = <95000>; 9566 hysteresis = <1000>; 9567 type = "passive"; 9568 }; 9569 9570 gpu-critical { 9571 temperature = <115000>; 9572 hysteresis = <1000>; 9573 type = "critical"; 9574 }; 9575 }; 9576 }; 9577 9578 gpuss-5-thermal { 9579 polling-delay-passive = <200>; 9580 9581 thermal-sensors = <&tsens3 10>; 9582 9583 cooling-maps { 9584 map0 { 9585 trip = <&gpuss5_alert0>; 9586 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9587 }; 9588 }; 9589 9590 trips { 9591 gpuss5_alert0: trip-point0 { 9592 temperature = <95000>; 9593 hysteresis = <1000>; 9594 type = "passive"; 9595 }; 9596 9597 gpu-critical { 9598 temperature = <115000>; 9599 hysteresis = <1000>; 9600 type = "critical"; 9601 }; 9602 }; 9603 }; 9604 9605 gpuss-6-thermal { 9606 polling-delay-passive = <200>; 9607 9608 thermal-sensors = <&tsens3 11>; 9609 9610 cooling-maps { 9611 map0 { 9612 trip = <&gpuss6_alert0>; 9613 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9614 }; 9615 }; 9616 9617 trips { 9618 gpuss6_alert0: trip-point0 { 9619 temperature = <95000>; 9620 hysteresis = <1000>; 9621 type = "passive"; 9622 }; 9623 9624 gpu-critical { 9625 temperature = <115000>; 9626 hysteresis = <1000>; 9627 type = "critical"; 9628 }; 9629 }; 9630 }; 9631 9632 gpuss-7-thermal { 9633 polling-delay-passive = <200>; 9634 9635 thermal-sensors = <&tsens3 12>; 9636 9637 cooling-maps { 9638 map0 { 9639 trip = <&gpuss7_alert0>; 9640 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9641 }; 9642 }; 9643 9644 trips { 9645 gpuss7_alert0: trip-point0 { 9646 temperature = <95000>; 9647 hysteresis = <1000>; 9648 type = "passive"; 9649 }; 9650 9651 gpu-critical { 9652 temperature = <115000>; 9653 hysteresis = <1000>; 9654 type = "critical"; 9655 }; 9656 }; 9657 }; 9658 9659 camera0-thermal { 9660 thermal-sensors = <&tsens3 13>; 9661 9662 trips { 9663 trip-point0 { 9664 temperature = <90000>; 9665 hysteresis = <2000>; 9666 type = "hot"; 9667 }; 9668 9669 camera0-critical { 9670 temperature = <115000>; 9671 hysteresis = <1000>; 9672 type = "critical"; 9673 }; 9674 }; 9675 }; 9676 9677 camera1-thermal { 9678 thermal-sensors = <&tsens3 14>; 9679 9680 trips { 9681 trip-point0 { 9682 temperature = <90000>; 9683 hysteresis = <2000>; 9684 type = "hot"; 9685 }; 9686 9687 camera0-critical { 9688 temperature = <115000>; 9689 hysteresis = <1000>; 9690 type = "critical"; 9691 }; 9692 }; 9693 }; 9694 }; 9695}; 9696