1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2023, Linaro Ltd 4 * 5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-qcm2290.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-qcm2290.h> 11#include <dt-bindings/clock/qcom,qcm2290-gpucc.h> 12#include <dt-bindings/clock/qcom,rpmcc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/interconnect/qcom,qcm2290.h> 18#include <dt-bindings/interconnect/qcom,rpm-icc.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/soc/qcom,apr.h> 21#include <dt-bindings/sound/qcom,q6asm.h> 22#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 clock-frequency = <32764>; 41 #clock-cells = <0>; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x0 0x0>; 53 clocks = <&cpufreq_hw 0>; 54 capacity-dmips-mhz = <1024>; 55 dynamic-power-coefficient = <100>; 56 enable-method = "psci"; 57 next-level-cache = <&l2_0>; 58 qcom,freq-domain = <&cpufreq_hw 0>; 59 power-domains = <&cpu_pd0>; 60 power-domain-names = "psci"; 61 l2_0: l2-cache { 62 compatible = "cache"; 63 cache-level = <2>; 64 cache-unified; 65 }; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x0 0x1>; 72 clocks = <&cpufreq_hw 0>; 73 capacity-dmips-mhz = <1024>; 74 dynamic-power-coefficient = <100>; 75 enable-method = "psci"; 76 next-level-cache = <&l2_0>; 77 qcom,freq-domain = <&cpufreq_hw 0>; 78 power-domains = <&cpu_pd1>; 79 power-domain-names = "psci"; 80 }; 81 82 cpu2: cpu@2 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x0 0x2>; 86 clocks = <&cpufreq_hw 0>; 87 capacity-dmips-mhz = <1024>; 88 dynamic-power-coefficient = <100>; 89 enable-method = "psci"; 90 next-level-cache = <&l2_0>; 91 qcom,freq-domain = <&cpufreq_hw 0>; 92 power-domains = <&cpu_pd2>; 93 power-domain-names = "psci"; 94 }; 95 96 cpu3: cpu@3 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x0 0x3>; 100 clocks = <&cpufreq_hw 0>; 101 capacity-dmips-mhz = <1024>; 102 dynamic-power-coefficient = <100>; 103 enable-method = "psci"; 104 next-level-cache = <&l2_0>; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 power-domains = <&cpu_pd3>; 107 power-domain-names = "psci"; 108 }; 109 110 cpu-map { 111 cluster0 { 112 core0 { 113 cpu = <&cpu0>; 114 }; 115 116 core1 { 117 cpu = <&cpu1>; 118 }; 119 120 core2 { 121 cpu = <&cpu2>; 122 }; 123 124 core3 { 125 cpu = <&cpu3>; 126 }; 127 }; 128 }; 129 130 domain-idle-states { 131 cluster_sleep: cluster-sleep-0 { 132 compatible = "domain-idle-state"; 133 arm,psci-suspend-param = <0x41000043>; 134 entry-latency-us = <800>; 135 exit-latency-us = <2118>; 136 min-residency-us = <7376>; 137 }; 138 }; 139 140 idle-states { 141 entry-method = "psci"; 142 143 cpu_sleep: cpu-sleep-0 { 144 compatible = "arm,idle-state"; 145 idle-state-name = "power-collapse"; 146 arm,psci-suspend-param = <0x40000003>; 147 entry-latency-us = <290>; 148 exit-latency-us = <376>; 149 min-residency-us = <1182>; 150 local-timer-stop; 151 }; 152 }; 153 }; 154 155 firmware { 156 scm: scm { 157 compatible = "qcom,scm-qcm2290", "qcom,scm"; 158 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 159 clock-names = "core"; 160 qcom,dload-mode = <&tcsr_regs 0x13000>; 161 #reset-cells = <1>; 162 interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG 163 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 164 }; 165 }; 166 167 memory@40000000 { 168 device_type = "memory"; 169 /* We expect the bootloader to fill in the size */ 170 reg = <0 0x40000000 0 0>; 171 }; 172 173 pmu { 174 compatible = "arm,cortex-a53-pmu"; 175 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 176 }; 177 178 psci { 179 compatible = "arm,psci-1.0"; 180 method = "smc"; 181 182 cpu_pd0: power-domain-cpu0 { 183 #power-domain-cells = <0>; 184 power-domains = <&cluster_pd>; 185 domain-idle-states = <&cpu_sleep>; 186 }; 187 188 cpu_pd1: power-domain-cpu1 { 189 #power-domain-cells = <0>; 190 power-domains = <&cluster_pd>; 191 domain-idle-states = <&cpu_sleep>; 192 }; 193 194 cpu_pd2: power-domain-cpu2 { 195 #power-domain-cells = <0>; 196 power-domains = <&cluster_pd>; 197 domain-idle-states = <&cpu_sleep>; 198 }; 199 200 cpu_pd3: power-domain-cpu3 { 201 #power-domain-cells = <0>; 202 power-domains = <&cluster_pd>; 203 domain-idle-states = <&cpu_sleep>; 204 }; 205 206 cluster_pd: power-domain-cpu-cluster { 207 #power-domain-cells = <0>; 208 power-domains = <&mpm>; 209 domain-idle-states = <&cluster_sleep>; 210 }; 211 }; 212 213 rpm: remoteproc { 214 compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc"; 215 216 glink-edge { 217 compatible = "qcom,glink-rpm"; 218 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 219 qcom,rpm-msg-ram = <&rpm_msg_ram>; 220 mboxes = <&apcs_glb 0>; 221 222 rpm_requests: rpm-requests { 223 compatible = "qcom,rpm-qcm2290", "qcom,glink-smd-rpm"; 224 qcom,glink-channels = "rpm_requests"; 225 226 rpmcc: clock-controller { 227 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; 228 clocks = <&xo_board>; 229 clock-names = "xo"; 230 #clock-cells = <1>; 231 }; 232 233 rpmpd: power-controller { 234 compatible = "qcom,qcm2290-rpmpd"; 235 #power-domain-cells = <1>; 236 operating-points-v2 = <&rpmpd_opp_table>; 237 238 rpmpd_opp_table: opp-table { 239 compatible = "operating-points-v2"; 240 241 rpmpd_opp_min_svs: opp1 { 242 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 243 }; 244 245 rpmpd_opp_low_svs: opp2 { 246 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 247 }; 248 249 rpmpd_opp_svs: opp3 { 250 opp-level = <RPM_SMD_LEVEL_SVS>; 251 }; 252 253 rpmpd_opp_svs_plus: opp4 { 254 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 255 }; 256 257 rpmpd_opp_nom: opp5 { 258 opp-level = <RPM_SMD_LEVEL_NOM>; 259 }; 260 261 rpmpd_opp_nom_plus: opp6 { 262 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 263 }; 264 265 rpmpd_opp_turbo: opp7 { 266 opp-level = <RPM_SMD_LEVEL_TURBO>; 267 }; 268 269 rpmpd_opp_turbo_plus: opp8 { 270 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 271 }; 272 }; 273 }; 274 }; 275 }; 276 277 mpm: interrupt-controller { 278 compatible = "qcom,mpm"; 279 qcom,rpm-msg-ram = <&apss_mpm>; 280 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 281 mboxes = <&apcs_glb 1>; 282 interrupt-controller; 283 #interrupt-cells = <2>; 284 #power-domain-cells = <0>; 285 interrupt-parent = <&intc>; 286 qcom,mpm-pin-count = <96>; 287 qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ 288 <5 296>, /* Soundwire master_irq */ 289 <12 422>, /* DWC3 ss_phy_irq */ 290 <24 79>, /* Soundwire wake_irq */ 291 <86 183>, /* MPM wake, SPMI */ 292 <90 260>; /* QUSB2_PHY DP+DM */ 293 }; 294 }; 295 296 reserved_memory: reserved-memory { 297 #address-cells = <2>; 298 #size-cells = <2>; 299 ranges; 300 301 hyp_mem: hyp@45700000 { 302 reg = <0x0 0x45700000 0x0 0x600000>; 303 no-map; 304 }; 305 306 xbl_aop_mem: xbl-aop@45e00000 { 307 reg = <0x0 0x45e00000 0x0 0x140000>; 308 no-map; 309 }; 310 311 sec_apps_mem: sec-apps@45fff000 { 312 reg = <0x0 0x45fff000 0x0 0x1000>; 313 no-map; 314 }; 315 316 smem_mem: smem@46000000 { 317 compatible = "qcom,smem"; 318 reg = <0x0 0x46000000 0x0 0x200000>; 319 no-map; 320 321 hwlocks = <&tcsr_mutex 3>; 322 qcom,rpm-msg-ram = <&rpm_msg_ram>; 323 }; 324 325 pil_modem_mem: modem@4ab00000 { 326 reg = <0x0 0x4ab00000 0x0 0x6900000>; 327 no-map; 328 }; 329 330 pil_video_mem: video@51400000 { 331 reg = <0x0 0x51400000 0x0 0x500000>; 332 no-map; 333 }; 334 335 wlan_msa_mem: wlan-msa@51900000 { 336 reg = <0x0 0x51900000 0x0 0x100000>; 337 no-map; 338 }; 339 340 pil_adsp_mem: adsp@51a00000 { 341 reg = <0x0 0x51a00000 0x0 0x1c00000>; 342 no-map; 343 }; 344 345 pil_ipa_fw_mem: ipa-fw@53600000 { 346 reg = <0x0 0x53600000 0x0 0x10000>; 347 no-map; 348 }; 349 350 pil_ipa_gsi_mem: ipa-gsi@53610000 { 351 reg = <0x0 0x53610000 0x0 0x5000>; 352 no-map; 353 }; 354 355 pil_gpu_mem: zap@53615000 { 356 compatible = "shared-dma-pool"; 357 reg = <0x0 0x53615000 0x0 0x2000>; 358 no-map; 359 }; 360 361 cont_splash_memory: framebuffer@5c000000 { 362 reg = <0x0 0x5c000000 0x0 0x00f00000>; 363 no-map; 364 }; 365 366 dfps_data_memory: dpfs-data@5cf00000 { 367 reg = <0x0 0x5cf00000 0x0 0x0100000>; 368 no-map; 369 }; 370 371 removed_mem: reserved@60000000 { 372 reg = <0x0 0x60000000 0x0 0x3900000>; 373 no-map; 374 }; 375 376 rmtfs_mem: memory@89b01000 { 377 compatible = "qcom,rmtfs-mem"; 378 reg = <0x0 0x89b01000 0x0 0x200000>; 379 no-map; 380 381 qcom,client-id = <1>; 382 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 383 }; 384 }; 385 386 smp2p-adsp { 387 compatible = "qcom,smp2p"; 388 qcom,smem = <443>, <429>; 389 390 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 391 392 mboxes = <&apcs_glb 10>; 393 394 qcom,local-pid = <0>; 395 qcom,remote-pid = <2>; 396 397 adsp_smp2p_out: master-kernel { 398 qcom,entry-name = "master-kernel"; 399 #qcom,smem-state-cells = <1>; 400 }; 401 402 adsp_smp2p_in: slave-kernel { 403 qcom,entry-name = "slave-kernel"; 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 }; 407 }; 408 409 smp2p-mpss { 410 compatible = "qcom,smp2p"; 411 qcom,smem = <435>, <428>; 412 413 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 414 415 mboxes = <&apcs_glb 14>; 416 417 qcom,local-pid = <0>; 418 qcom,remote-pid = <1>; 419 420 modem_smp2p_out: master-kernel { 421 qcom,entry-name = "master-kernel"; 422 #qcom,smem-state-cells = <1>; 423 }; 424 425 modem_smp2p_in: slave-kernel { 426 qcom,entry-name = "slave-kernel"; 427 interrupt-controller; 428 #interrupt-cells = <2>; 429 }; 430 431 wlan_smp2p_in: wlan-wpss-to-ap { 432 qcom,entry-name = "wlan"; 433 interrupt-controller; 434 #interrupt-cells = <2>; 435 }; 436 }; 437 438 soc: soc@0 { 439 compatible = "simple-bus"; 440 #address-cells = <2>; 441 #size-cells = <2>; 442 ranges = <0 0 0 0 0x10 0>; 443 dma-ranges = <0 0 0 0 0x10 0>; 444 445 tcsr_mutex: hwlock@340000 { 446 compatible = "qcom,tcsr-mutex"; 447 reg = <0x0 0x00340000 0x0 0x20000>; 448 #hwlock-cells = <1>; 449 }; 450 451 tcsr_regs: syscon@3c0000 { 452 compatible = "qcom,qcm2290-tcsr", "syscon"; 453 reg = <0x0 0x003c0000 0x0 0x40000>; 454 }; 455 456 tlmm: pinctrl@500000 { 457 compatible = "qcom,qcm2290-tlmm"; 458 reg = <0x0 0x00500000 0x0 0x300000>; 459 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 460 gpio-controller; 461 gpio-ranges = <&tlmm 0 0 127>; 462 wakeup-parent = <&mpm>; 463 #gpio-cells = <2>; 464 interrupt-controller; 465 #interrupt-cells = <2>; 466 467 qup_i2c0_default: qup-i2c0-default-state { 468 pins = "gpio0", "gpio1"; 469 function = "qup0"; 470 drive-strength = <2>; 471 bias-pull-up; 472 }; 473 474 qup_i2c1_default: qup-i2c1-default-state { 475 pins = "gpio4", "gpio5"; 476 function = "qup1"; 477 drive-strength = <2>; 478 bias-pull-up; 479 }; 480 481 qup_i2c2_default: qup-i2c2-default-state { 482 pins = "gpio6", "gpio7"; 483 function = "qup2"; 484 drive-strength = <2>; 485 bias-pull-up; 486 }; 487 488 qup_i2c3_default: qup-i2c3-default-state { 489 pins = "gpio8", "gpio9"; 490 function = "qup3"; 491 drive-strength = <2>; 492 bias-pull-up; 493 }; 494 495 qup_i2c4_default: qup-i2c4-default-state { 496 pins = "gpio12", "gpio13"; 497 function = "qup4"; 498 drive-strength = <2>; 499 bias-pull-up; 500 }; 501 502 qup_i2c5_default: qup-i2c5-default-state { 503 pins = "gpio14", "gpio15"; 504 function = "qup5"; 505 drive-strength = <2>; 506 bias-pull-up; 507 }; 508 509 qup_spi0_default: qup-spi0-default-state { 510 pins = "gpio0", "gpio1","gpio2", "gpio3"; 511 function = "qup0"; 512 drive-strength = <2>; 513 bias-pull-up; 514 }; 515 516 qup_spi1_default: qup-spi1-default-state { 517 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 518 function = "qup1"; 519 drive-strength = <2>; 520 bias-pull-up; 521 }; 522 523 qup_spi2_default: qup-spi2-default-state { 524 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 525 function = "qup2"; 526 drive-strength = <2>; 527 bias-pull-up; 528 }; 529 530 qup_spi3_default: qup-spi3-default-state { 531 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 532 function = "qup3"; 533 drive-strength = <2>; 534 bias-pull-up; 535 }; 536 537 qup_spi4_default: qup-spi4-default-state { 538 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 539 function = "qup4"; 540 drive-strength = <2>; 541 bias-pull-up; 542 }; 543 544 qup_spi5_default: qup-spi5-default-state { 545 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 546 function = "qup5"; 547 drive-strength = <2>; 548 bias-pull-up; 549 }; 550 551 qup_uart0_default: qup-uart0-default-state { 552 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 553 function = "qup0"; 554 drive-strength = <2>; 555 bias-disable; 556 }; 557 558 qup_uart1_default: qup-uart1-default-state { 559 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 560 function = "qup1"; 561 drive-strength = <2>; 562 bias-disable; 563 }; 564 565 qup_uart2_default: qup-uart2-default-state { 566 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 567 function = "qup2"; 568 drive-strength = <2>; 569 bias-disable; 570 }; 571 572 qup_uart3_default: qup-uart3-default-state { 573 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 574 function = "qup3"; 575 drive-strength = <2>; 576 bias-disable; 577 }; 578 579 qup_uart4_default: qup-uart4-default-state { 580 pins = "gpio12", "gpio13"; 581 function = "qup4"; 582 drive-strength = <2>; 583 bias-disable; 584 }; 585 586 qup_uart5_default: qup-uart5-default-state { 587 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 588 function = "qup5"; 589 drive-strength = <2>; 590 bias-disable; 591 }; 592 593 cci0_default: cci0-default-state { 594 pins = "gpio22", "gpio23"; 595 function = "cci_i2c"; 596 drive-strength = <2>; 597 bias-disable; 598 }; 599 600 cci1_default: cci1-default-state { 601 pins = "gpio29", "gpio30"; 602 function = "cci_i2c"; 603 drive-strength = <2>; 604 bias-disable; 605 }; 606 607 mclk0_default: mclk0-default-state { 608 pins = "gpio20"; 609 function = "cam_mclk"; 610 drive-strength = <16>; 611 bias-disable; 612 }; 613 614 mclk1_default: mclk1-default-state { 615 pins = "gpio21"; 616 function = "cam_mclk"; 617 drive-strength = <16>; 618 bias-disable; 619 }; 620 621 mclk2_default: mclk2-default-state { 622 pins = "gpio27"; 623 function = "cam_mclk"; 624 drive-strength = <16>; 625 bias-disable; 626 }; 627 628 mclk3_default: mclk3-default-state { 629 pins = "gpio28"; 630 function = "cam_mclk"; 631 drive-strength = <16>; 632 bias-disable; 633 }; 634 635 sdc1_state_on: sdc1-on-state { 636 clk-pins { 637 pins = "sdc1_clk"; 638 drive-strength = <16>; 639 bias-disable; 640 }; 641 642 cmd-pins { 643 pins = "sdc1_cmd"; 644 drive-strength = <10>; 645 bias-pull-up; 646 }; 647 648 data-pins { 649 pins = "sdc1_data"; 650 drive-strength = <10>; 651 bias-pull-up; 652 }; 653 654 rclk-pins { 655 pins = "sdc1_rclk"; 656 bias-pull-down; 657 }; 658 }; 659 660 sdc1_state_off: sdc1-off-state { 661 clk-pins { 662 pins = "sdc1_clk"; 663 drive-strength = <2>; 664 bias-disable; 665 }; 666 667 cmd-pins { 668 pins = "sdc1_cmd"; 669 drive-strength = <2>; 670 bias-pull-up; 671 }; 672 673 data-pins { 674 pins = "sdc1_data"; 675 drive-strength = <2>; 676 bias-pull-up; 677 }; 678 679 rclk-pins { 680 pins = "sdc1_rclk"; 681 bias-pull-down; 682 }; 683 }; 684 685 sdc2_state_on: sdc2-on-state { 686 clk-pins { 687 pins = "sdc2_clk"; 688 drive-strength = <16>; 689 bias-disable; 690 }; 691 692 cmd-pins { 693 pins = "sdc2_cmd"; 694 drive-strength = <10>; 695 bias-pull-up; 696 }; 697 698 data-pins { 699 pins = "sdc2_data"; 700 drive-strength = <10>; 701 bias-pull-up; 702 }; 703 }; 704 705 sdc2_state_off: sdc2-off-state { 706 clk-pins { 707 pins = "sdc2_clk"; 708 drive-strength = <2>; 709 bias-disable; 710 }; 711 712 cmd-pins { 713 pins = "sdc2_cmd"; 714 drive-strength = <2>; 715 bias-pull-up; 716 }; 717 718 data-pins { 719 pins = "sdc2_data"; 720 drive-strength = <2>; 721 bias-pull-up; 722 }; 723 }; 724 }; 725 726 lpass_tlmm: pinctrl@a7c0000 { 727 compatible = "qcom,qcm2290-lpass-lpi-pinctrl", 728 "qcom,sm6115-lpass-lpi-pinctrl"; 729 reg = <0x0 0x0a7c0000 0x0 0x20000>, 730 <0x0 0x0a950000 0x0 0x10000>; 731 732 clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 733 clock-names = "audio"; 734 735 gpio-controller; 736 #gpio-cells = <2>; 737 gpio-ranges = <&lpass_tlmm 0 0 19>; 738 739 lpi_i2s2_active: lpi-i2s2-active-state { 740 sck-pins { 741 pins = "gpio10"; 742 function = "i2s2_clk"; 743 bias-disable; 744 drive-strength = <8>; 745 }; 746 747 ws-pins { 748 pins = "gpio11"; 749 function = "i2s2_ws"; 750 bias-disable; 751 drive-strength = <8>; 752 }; 753 754 data-pins { 755 pins = "gpio12"; 756 function = "i2s2_data"; 757 bias-disable; 758 drive-strength = <8>; 759 }; 760 }; 761 }; 762 763 gcc: clock-controller@1400000 { 764 compatible = "qcom,gcc-qcm2290"; 765 reg = <0x0 0x01400000 0x0 0x1f0000>; 766 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 767 clock-names = "bi_tcxo", "sleep_clk"; 768 #clock-cells = <1>; 769 #reset-cells = <1>; 770 #power-domain-cells = <1>; 771 }; 772 773 usb_hsphy: phy@1613000 { 774 compatible = "qcom,qcm2290-qusb2-phy"; 775 reg = <0x0 0x01613000 0x0 0x180>; 776 777 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 778 <&rpmcc RPM_SMD_XO_CLK_SRC>; 779 clock-names = "cfg_ahb", "ref"; 780 781 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 782 nvmem-cells = <&qusb2_hstx_trim>; 783 #phy-cells = <0>; 784 785 status = "disabled"; 786 }; 787 788 usb_qmpphy: phy@1615000 { 789 compatible = "qcom,qcm2290-qmp-usb3-phy"; 790 reg = <0x0 0x01615000 0x0 0x1000>; 791 792 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 793 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 794 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 795 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 796 clock-names = "cfg_ahb", 797 "ref", 798 "com_aux", 799 "pipe"; 800 801 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 802 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 803 reset-names = "phy", 804 "phy_phy"; 805 806 #clock-cells = <0>; 807 clock-output-names = "usb3_phy_pipe_clk_src"; 808 809 #phy-cells = <0>; 810 orientation-switch; 811 812 qcom,tcsr-reg = <&tcsr_regs 0xb244>; 813 814 status = "disabled"; 815 816 ports { 817 #address-cells = <1>; 818 #size-cells = <0>; 819 820 port@0 { 821 reg = <0>; 822 823 usb_qmpphy_out: endpoint { 824 }; 825 }; 826 827 port@1 { 828 reg = <1>; 829 830 usb_qmpphy_usb_ss_in: endpoint { 831 remote-endpoint = <&usb_dwc3_ss>; 832 }; 833 }; 834 }; 835 }; 836 837 system_noc: interconnect@1880000 { 838 compatible = "qcom,qcm2290-snoc"; 839 reg = <0x0 0x01880000 0x0 0x60200>; 840 #interconnect-cells = <2>; 841 842 qup_virt: interconnect-qup { 843 compatible = "qcom,qcm2290-qup-virt"; 844 #interconnect-cells = <2>; 845 }; 846 847 mmnrt_virt: interconnect-mmnrt { 848 compatible = "qcom,qcm2290-mmnrt-virt"; 849 #interconnect-cells = <2>; 850 }; 851 852 mmrt_virt: interconnect-mmrt { 853 compatible = "qcom,qcm2290-mmrt-virt"; 854 #interconnect-cells = <2>; 855 }; 856 }; 857 858 config_noc: interconnect@1900000 { 859 compatible = "qcom,qcm2290-cnoc"; 860 reg = <0x0 0x01900000 0x0 0x8200>; 861 #interconnect-cells = <2>; 862 }; 863 864 cryptobam: dma-controller@1b04000 { 865 compatible = "qcom,bam-v1.7.0"; 866 reg = <0x0 0x01b04000 0x0 0x24000>; 867 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 869 clock-names = "bam_clk"; 870 #dma-cells = <1>; 871 qcom,ee = <0>; 872 qcom,controlled-remotely; 873 iommus = <&apps_smmu 0x0084 0x11>, 874 <&apps_smmu 0x0086 0x11>; 875 }; 876 877 crypto: crypto@1b3a000 { 878 compatible = "qcom,qcm2290-qce", "qcom,ipq4019-qce", "qcom,qce"; 879 reg = <0x0 0x01b3a000 0x0 0x6000>; 880 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 881 clock-names = "core"; 882 dmas = <&cryptobam 6>, <&cryptobam 7>; 883 dma-names = "rx", "tx"; 884 iommus = <&apps_smmu 0x0084 0x11>, 885 <&apps_smmu 0x0086 0x11>; 886 }; 887 888 qfprom@1b44000 { 889 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; 890 reg = <0x0 0x01b44000 0x0 0x3000>; 891 #address-cells = <1>; 892 #size-cells = <1>; 893 894 qusb2_hstx_trim: hstx-trim@25b { 895 reg = <0x25b 0x1>; 896 bits = <1 4>; 897 }; 898 899 gpu_speed_bin: gpu-speed-bin@2006 { 900 reg = <0x2006 0x2>; 901 bits = <5 8>; 902 }; 903 }; 904 905 pmu@1b8e300 { 906 compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon"; 907 reg = <0x0 0x01b8e300 0x0 0x600>; 908 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 909 910 operating-points-v2 = <&cpu_bwmon_opp_table>; 911 interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 912 &bimc SLAVE_EBI1 RPM_ACTIVE_TAG>; 913 914 cpu_bwmon_opp_table: opp-table { 915 compatible = "operating-points-v2"; 916 917 opp-0 { 918 opp-peak-kBps = <(200 * 4 * 1000)>; 919 }; 920 921 opp-1 { 922 opp-peak-kBps = <(300 * 4 * 1000)>; 923 }; 924 925 opp-2 { 926 opp-peak-kBps = <(451 * 4 * 1000)>; 927 }; 928 929 opp-3 { 930 opp-peak-kBps = <(547 * 4 * 1000)>; 931 }; 932 933 opp-4 { 934 opp-peak-kBps = <(681 * 4 * 1000)>; 935 }; 936 937 opp-5 { 938 opp-peak-kBps = <(768 * 4 * 1000)>; 939 }; 940 941 opp-6 { 942 opp-peak-kBps = <(1017 * 4 * 1000)>; 943 }; 944 945 opp-7 { 946 opp-peak-kBps = <(1353 * 4 * 1000)>; 947 }; 948 949 opp-8 { 950 opp-peak-kBps = <(1555 * 4 * 1000)>; 951 }; 952 953 opp-9 { 954 opp-peak-kBps = <(1804 * 4 * 1000)>; 955 }; 956 }; 957 }; 958 959 spmi_bus: spmi@1c40000 { 960 compatible = "qcom,spmi-pmic-arb"; 961 reg = <0x0 0x01c40000 0x0 0x1100>, 962 <0x0 0x01e00000 0x0 0x2000000>, 963 <0x0 0x03e00000 0x0 0x100000>, 964 <0x0 0x03f00000 0x0 0xa0000>, 965 <0x0 0x01c0a000 0x0 0x26000>; 966 reg-names = "core", 967 "chnls", 968 "obsrvr", 969 "intr", 970 "cnfg"; 971 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; 972 interrupt-names = "periph_irq"; 973 qcom,ee = <0>; 974 qcom,channel = <0>; 975 #address-cells = <2>; 976 #size-cells = <0>; 977 interrupt-controller; 978 #interrupt-cells = <4>; 979 }; 980 981 tsens0: thermal-sensor@4411000 { 982 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; 983 reg = <0x0 0x04411000 0x0 0x1ff>, 984 <0x0 0x04410000 0x0 0x8>; 985 #qcom,sensors = <10>; 986 interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>, 987 <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 988 interrupt-names = "uplow", "critical"; 989 #thermal-sensor-cells = <1>; 990 }; 991 992 rng: rng@4453000 { 993 compatible = "qcom,prng-ee"; 994 reg = <0x0 0x04453000 0x0 0x1000>; 995 clocks = <&rpmcc RPM_SMD_HWKM_CLK>; 996 clock-names = "core"; 997 }; 998 999 bimc: interconnect@4480000 { 1000 compatible = "qcom,qcm2290-bimc"; 1001 reg = <0x0 0x04480000 0x0 0x80000>; 1002 #interconnect-cells = <2>; 1003 }; 1004 1005 rpm_msg_ram: sram@45f0000 { 1006 compatible = "qcom,rpm-msg-ram", "mmio-sram"; 1007 reg = <0x0 0x045f0000 0x0 0x7000>; 1008 #address-cells = <1>; 1009 #size-cells = <1>; 1010 ranges = <0 0x0 0x045f0000 0x7000>; 1011 1012 apss_mpm: sram@1b8 { 1013 reg = <0x1b8 0x48>; 1014 }; 1015 }; 1016 1017 sram@4690000 { 1018 compatible = "qcom,rpm-stats"; 1019 reg = <0x0 0x04690000 0x0 0x10000>; 1020 }; 1021 1022 sdhc_1: mmc@4744000 { 1023 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 1024 reg = <0x0 0x04744000 0x0 0x1000>, 1025 <0x0 0x04745000 0x0 0x1000>, 1026 <0x0 0x04748000 0x0 0x8000>; 1027 reg-names = "hc", 1028 "cqhci", 1029 "ice"; 1030 1031 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1033 interrupt-names = "hc_irq", "pwr_irq"; 1034 1035 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1036 <&gcc GCC_SDCC1_APPS_CLK>, 1037 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1038 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1039 clock-names = "iface", 1040 "core", 1041 "xo", 1042 "ice"; 1043 1044 resets = <&gcc GCC_SDCC1_BCR>; 1045 1046 power-domains = <&rpmpd QCM2290_VDDCX>; 1047 operating-points-v2 = <&sdhc1_opp_table>; 1048 iommus = <&apps_smmu 0xc0 0x0>; 1049 interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG 1050 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1051 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1052 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>; 1053 interconnect-names = "sdhc-ddr", 1054 "cpu-sdhc"; 1055 1056 qcom,dll-config = <0x000f642c>; 1057 qcom,ddr-config = <0x80040868>; 1058 bus-width = <8>; 1059 1060 mmc-ddr-1_8v; 1061 mmc-hs200-1_8v; 1062 mmc-hs400-1_8v; 1063 mmc-hs400-enhanced-strobe; 1064 1065 status = "disabled"; 1066 1067 sdhc1_opp_table: opp-table { 1068 compatible = "operating-points-v2"; 1069 1070 opp-100000000 { 1071 opp-hz = /bits/ 64 <100000000>; 1072 required-opps = <&rpmpd_opp_low_svs>; 1073 opp-peak-kBps = <250000 133320>; 1074 opp-avg-kBps = <102400 65000>; 1075 }; 1076 1077 opp-192000000 { 1078 opp-hz = /bits/ 64 <192000000>; 1079 required-opps = <&rpmpd_opp_low_svs>; 1080 opp-peak-kBps = <800000 300000>; 1081 opp-avg-kBps = <204800 200000>; 1082 }; 1083 1084 opp-384000000 { 1085 opp-hz = /bits/ 64 <384000000>; 1086 required-opps = <&rpmpd_opp_svs_plus>; 1087 opp-peak-kBps = <800000 300000>; 1088 opp-avg-kBps = <204800 200000>; 1089 }; 1090 }; 1091 }; 1092 1093 sdhc_2: mmc@4784000 { 1094 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 1095 reg = <0x0 0x04784000 0x0 0x1000>; 1096 reg-names = "hc"; 1097 1098 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1100 interrupt-names = "hc_irq", "pwr_irq"; 1101 1102 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1103 <&gcc GCC_SDCC2_APPS_CLK>, 1104 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1105 clock-names = "iface", 1106 "core", 1107 "xo"; 1108 1109 resets = <&gcc GCC_SDCC2_BCR>; 1110 1111 power-domains = <&rpmpd QCM2290_VDDCX>; 1112 operating-points-v2 = <&sdhc2_opp_table>; 1113 iommus = <&apps_smmu 0xa0 0x0>; 1114 interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG 1115 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1116 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1117 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>; 1118 interconnect-names = "sdhc-ddr", 1119 "cpu-sdhc"; 1120 1121 qcom,dll-config = <0x0007642c>; 1122 qcom,ddr-config = <0x80040868>; 1123 bus-width = <4>; 1124 1125 status = "disabled"; 1126 1127 sdhc2_opp_table: opp-table { 1128 compatible = "operating-points-v2"; 1129 1130 opp-100000000 { 1131 opp-hz = /bits/ 64 <100000000>; 1132 required-opps = <&rpmpd_opp_low_svs>; 1133 opp-peak-kBps = <250000 133320>; 1134 opp-avg-kBps = <261438 150000>; 1135 }; 1136 1137 opp-202000000 { 1138 opp-hz = /bits/ 64 <202000000>; 1139 required-opps = <&rpmpd_opp_svs_plus>; 1140 opp-peak-kBps = <800000 300000>; 1141 opp-avg-kBps = <261438 300000>; 1142 }; 1143 }; 1144 }; 1145 1146 gpi_dma0: dma-controller@4a00000 { 1147 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; 1148 reg = <0x0 0x04a00000 0x0 0x60000>; 1149 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1159 dma-channels = <10>; 1160 dma-channel-mask = <0x1f>; 1161 iommus = <&apps_smmu 0xf6 0x0>; 1162 #dma-cells = <3>; 1163 status = "disabled"; 1164 }; 1165 1166 qupv3_id_0: geniqup@4ac0000 { 1167 compatible = "qcom,geni-se-qup"; 1168 reg = <0x0 0x04ac0000 0x0 0x2000>; 1169 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1170 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1171 clock-names = "m-ahb", "s-ahb"; 1172 iommus = <&apps_smmu 0xe3 0x0>; 1173 #address-cells = <2>; 1174 #size-cells = <2>; 1175 ranges; 1176 status = "disabled"; 1177 1178 i2c0: i2c@4a80000 { 1179 compatible = "qcom,geni-i2c"; 1180 reg = <0x0 0x04a80000 0x0 0x4000>; 1181 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1182 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1183 clock-names = "se"; 1184 pinctrl-0 = <&qup_i2c0_default>; 1185 pinctrl-names = "default"; 1186 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1187 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1188 dma-names = "tx", "rx"; 1189 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1190 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1191 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1192 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1193 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1194 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1195 interconnect-names = "qup-core", 1196 "qup-config", 1197 "qup-memory"; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 status = "disabled"; 1201 }; 1202 1203 spi0: spi@4a80000 { 1204 compatible = "qcom,geni-spi"; 1205 reg = <0x0 0x04a80000 0x0 0x4000>; 1206 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1207 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1208 clock-names = "se"; 1209 pinctrl-0 = <&qup_spi0_default>; 1210 pinctrl-names = "default"; 1211 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1212 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1213 dma-names = "tx", "rx"; 1214 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1215 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1216 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1217 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1218 interconnect-names = "qup-core", 1219 "qup-config"; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 status = "disabled"; 1223 }; 1224 1225 uart0: serial@4a80000 { 1226 compatible = "qcom,geni-uart"; 1227 reg = <0x0 0x04a80000 0x0 0x4000>; 1228 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1229 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1230 clock-names = "se"; 1231 pinctrl-0 = <&qup_uart0_default>; 1232 pinctrl-names = "default"; 1233 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1234 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1235 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1236 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1237 interconnect-names = "qup-core", 1238 "qup-config"; 1239 status = "disabled"; 1240 }; 1241 1242 i2c1: i2c@4a84000 { 1243 compatible = "qcom,geni-i2c"; 1244 reg = <0x0 0x04a84000 0x0 0x4000>; 1245 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1246 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1247 clock-names = "se"; 1248 pinctrl-0 = <&qup_i2c1_default>; 1249 pinctrl-names = "default"; 1250 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1251 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1252 dma-names = "tx", "rx"; 1253 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1254 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1255 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1256 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1257 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1258 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1259 interconnect-names = "qup-core", 1260 "qup-config", 1261 "qup-memory"; 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 status = "disabled"; 1265 }; 1266 1267 spi1: spi@4a84000 { 1268 compatible = "qcom,geni-spi"; 1269 reg = <0x0 0x04a84000 0x0 0x4000>; 1270 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1271 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1272 clock-names = "se"; 1273 pinctrl-0 = <&qup_spi1_default>; 1274 pinctrl-names = "default"; 1275 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1276 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1277 dma-names = "tx", "rx"; 1278 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1279 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1280 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1281 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1282 interconnect-names = "qup-core", 1283 "qup-config"; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 status = "disabled"; 1287 }; 1288 1289 uart1: serial@4a84000 { 1290 compatible = "qcom,geni-uart"; 1291 reg = <0x0 0x04a84000 0x0 0x4000>; 1292 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1293 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1294 clock-names = "se"; 1295 pinctrl-0 = <&qup_uart1_default>; 1296 pinctrl-names = "default"; 1297 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1298 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1299 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1300 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1301 interconnect-names = "qup-core", 1302 "qup-config"; 1303 status = "disabled"; 1304 }; 1305 1306 i2c2: i2c@4a88000 { 1307 compatible = "qcom,geni-i2c"; 1308 reg = <0x0 0x04a88000 0x0 0x4000>; 1309 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1310 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1311 clock-names = "se"; 1312 pinctrl-0 = <&qup_i2c2_default>; 1313 pinctrl-names = "default"; 1314 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1315 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1316 dma-names = "tx", "rx"; 1317 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1318 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1319 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1320 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1321 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1322 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1323 interconnect-names = "qup-core", 1324 "qup-config", 1325 "qup-memory"; 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 status = "disabled"; 1329 }; 1330 1331 spi2: spi@4a88000 { 1332 compatible = "qcom,geni-spi"; 1333 reg = <0x0 0x04a88000 0x0 0x4000>; 1334 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1335 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1336 clock-names = "se"; 1337 pinctrl-0 = <&qup_spi2_default>; 1338 pinctrl-names = "default"; 1339 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1340 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1341 dma-names = "tx", "rx"; 1342 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1343 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1344 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1345 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1346 interconnect-names = "qup-core", 1347 "qup-config"; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 status = "disabled"; 1351 }; 1352 1353 uart2: serial@4a88000 { 1354 compatible = "qcom,geni-uart"; 1355 reg = <0x0 0x04a88000 0x0 0x4000>; 1356 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1357 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1358 clock-names = "se"; 1359 pinctrl-0 = <&qup_uart2_default>; 1360 pinctrl-names = "default"; 1361 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1362 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1363 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1364 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1365 interconnect-names = "qup-core", 1366 "qup-config"; 1367 status = "disabled"; 1368 }; 1369 1370 i2c3: i2c@4a8c000 { 1371 compatible = "qcom,geni-i2c"; 1372 reg = <0x0 0x04a8c000 0x0 0x4000>; 1373 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1374 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1375 clock-names = "se"; 1376 pinctrl-0 = <&qup_i2c3_default>; 1377 pinctrl-names = "default"; 1378 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1379 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1380 dma-names = "tx", "rx"; 1381 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1382 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1383 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1384 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1385 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1386 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1387 interconnect-names = "qup-core", 1388 "qup-config", 1389 "qup-memory"; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 status = "disabled"; 1393 }; 1394 1395 spi3: spi@4a8c000 { 1396 compatible = "qcom,geni-spi"; 1397 reg = <0x0 0x04a8c000 0x0 0x4000>; 1398 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1399 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1400 clock-names = "se"; 1401 pinctrl-0 = <&qup_spi3_default>; 1402 pinctrl-names = "default"; 1403 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1404 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1405 dma-names = "tx", "rx"; 1406 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1407 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1408 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1409 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1410 interconnect-names = "qup-core", 1411 "qup-config"; 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 status = "disabled"; 1415 }; 1416 1417 uart3: serial@4a8c000 { 1418 compatible = "qcom,geni-uart"; 1419 reg = <0x0 0x04a8c000 0x0 0x4000>; 1420 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1421 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1422 clock-names = "se"; 1423 pinctrl-0 = <&qup_uart3_default>; 1424 pinctrl-names = "default"; 1425 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1426 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1427 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1428 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1429 interconnect-names = "qup-core", 1430 "qup-config"; 1431 status = "disabled"; 1432 }; 1433 1434 i2c4: i2c@4a90000 { 1435 compatible = "qcom,geni-i2c"; 1436 reg = <0x0 0x04a90000 0x0 0x4000>; 1437 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1438 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1439 clock-names = "se"; 1440 pinctrl-0 = <&qup_i2c4_default>; 1441 pinctrl-names = "default"; 1442 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1443 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1444 dma-names = "tx", "rx"; 1445 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1446 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1447 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1448 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1449 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1450 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1451 interconnect-names = "qup-core", 1452 "qup-config", 1453 "qup-memory"; 1454 #address-cells = <1>; 1455 #size-cells = <0>; 1456 status = "disabled"; 1457 }; 1458 1459 spi4: spi@4a90000 { 1460 compatible = "qcom,geni-spi"; 1461 reg = <0x0 0x04a90000 0x0 0x4000>; 1462 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1463 clock-names = "se"; 1464 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1465 pinctrl-names = "default"; 1466 pinctrl-0 = <&qup_spi4_default>; 1467 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1468 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1469 dma-names = "tx", "rx"; 1470 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1471 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1472 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1473 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1474 interconnect-names = "qup-core", 1475 "qup-config"; 1476 #address-cells = <1>; 1477 #size-cells = <0>; 1478 status = "disabled"; 1479 }; 1480 1481 uart4: serial@4a90000 { 1482 compatible = "qcom,geni-uart"; 1483 reg = <0x0 0x04a90000 0x0 0x4000>; 1484 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1485 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1486 clock-names = "se"; 1487 pinctrl-0 = <&qup_uart4_default>; 1488 pinctrl-names = "default"; 1489 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1490 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1491 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1492 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1493 interconnect-names = "qup-core", 1494 "qup-config"; 1495 status = "disabled"; 1496 }; 1497 1498 i2c5: i2c@4a94000 { 1499 compatible = "qcom,geni-i2c"; 1500 reg = <0x0 0x04a94000 0x0 0x4000>; 1501 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1502 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1503 clock-names = "se"; 1504 pinctrl-0 = <&qup_i2c5_default>; 1505 pinctrl-names = "default"; 1506 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1507 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1508 dma-names = "tx", "rx"; 1509 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1510 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1511 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1512 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1513 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1514 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1515 interconnect-names = "qup-core", 1516 "qup-config", 1517 "qup-memory"; 1518 #address-cells = <1>; 1519 #size-cells = <0>; 1520 status = "disabled"; 1521 }; 1522 1523 spi5: spi@4a94000 { 1524 compatible = "qcom,geni-spi"; 1525 reg = <0x0 0x04a94000 0x0 0x4000>; 1526 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1527 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1528 clock-names = "se"; 1529 pinctrl-0 = <&qup_spi5_default>; 1530 pinctrl-names = "default"; 1531 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1532 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1533 dma-names = "tx", "rx"; 1534 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1535 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1536 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1537 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1538 interconnect-names = "qup-core", 1539 "qup-config"; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 status = "disabled"; 1543 }; 1544 1545 uart5: serial@4a94000 { 1546 compatible = "qcom,geni-uart"; 1547 reg = <0x0 0x04a94000 0x0 0x4000>; 1548 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1549 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1550 clock-names = "se"; 1551 pinctrl-0 = <&qup_uart5_default>; 1552 pinctrl-names = "default"; 1553 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1554 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1555 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1556 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1557 interconnect-names = "qup-core", 1558 "qup-config"; 1559 status = "disabled"; 1560 }; 1561 }; 1562 1563 usb: usb@4ef8800 { 1564 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; 1565 reg = <0x0 0x04ef8800 0x0 0x400>; 1566 interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1567 <&mpm 12 IRQ_TYPE_LEVEL_HIGH>; 1568 interrupt-names = "hs_phy_irq", 1569 "ss_phy_irq"; 1570 1571 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1572 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1573 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1574 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1575 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1576 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1577 clock-names = "cfg_noc", 1578 "core", 1579 "iface", 1580 "sleep", 1581 "mock_utmi", 1582 "xo"; 1583 1584 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1585 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1586 assigned-clock-rates = <19200000>, <133333333>; 1587 1588 resets = <&gcc GCC_USB30_PRIM_BCR>; 1589 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1590 /* TODO: USB<->IPA path */ 1591 interconnects = <&system_noc MASTER_USB3_0 RPM_ALWAYS_TAG 1592 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1593 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1594 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; 1595 interconnect-names = "usb-ddr", 1596 "apps-usb"; 1597 wakeup-source; 1598 1599 #address-cells = <2>; 1600 #size-cells = <2>; 1601 ranges; 1602 1603 status = "disabled"; 1604 1605 usb_dwc3: usb@4e00000 { 1606 compatible = "snps,dwc3"; 1607 reg = <0x0 0x04e00000 0x0 0xcd00>; 1608 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1609 phys = <&usb_hsphy>, <&usb_qmpphy>; 1610 phy-names = "usb2-phy", "usb3-phy"; 1611 iommus = <&apps_smmu 0x120 0x0>; 1612 snps,dis_u2_susphy_quirk; 1613 snps,dis_enblslpm_quirk; 1614 snps,has-lpm-erratum; 1615 snps,hird-threshold = /bits/ 8 <0x10>; 1616 snps,usb3_lpm_capable; 1617 snps,parkmode-disable-ss-quirk; 1618 maximum-speed = "super-speed"; 1619 dr_mode = "otg"; 1620 usb-role-switch; 1621 1622 ports { 1623 #address-cells = <1>; 1624 #size-cells = <0>; 1625 1626 port@0 { 1627 reg = <0>; 1628 1629 usb_dwc3_hs: endpoint { 1630 }; 1631 }; 1632 1633 port@1 { 1634 reg = <1>; 1635 1636 usb_dwc3_ss: endpoint { 1637 remote-endpoint = <&usb_qmpphy_usb_ss_in>; 1638 }; 1639 }; 1640 }; 1641 }; 1642 }; 1643 1644 gpu: gpu@5900000 { 1645 compatible = "qcom,adreno-07000200", "qcom,adreno"; 1646 reg = <0x0 0x05900000 0x0 0x40000>, 1647 <0x0 0x0599e000 0x0 0x1000>, 1648 <0x0 0x05961000 0x0 0x800>; 1649 reg-names = "kgsl_3d0_reg_memory", 1650 "cx_mem", 1651 "cx_dbgc"; 1652 1653 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1654 1655 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, 1656 <&gpucc GPU_CC_AHB_CLK>, 1657 <&gcc GCC_BIMC_GPU_AXI_CLK>, 1658 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1659 <&gpucc GPU_CC_CX_GMU_CLK>, 1660 <&gpucc GPU_CC_CXO_CLK>; 1661 clock-names = "core", 1662 "iface", 1663 "mem_iface", 1664 "alt_mem_iface", 1665 "gmu", 1666 "xo"; 1667 1668 interconnects = <&bimc MASTER_GFX3D RPM_ALWAYS_TAG 1669 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1670 interconnect-names = "gfx-mem"; 1671 1672 iommus = <&adreno_smmu 0 1>, 1673 <&adreno_smmu 2 0>; 1674 operating-points-v2 = <&gpu_opp_table>; 1675 power-domains = <&rpmpd QCM2290_VDDCX>; 1676 qcom,gmu = <&gmu_wrapper>; 1677 1678 nvmem-cells = <&gpu_speed_bin>; 1679 nvmem-cell-names = "speed_bin"; 1680 #cooling-cells = <2>; 1681 1682 status = "disabled"; 1683 1684 gpu_zap_shader: zap-shader { 1685 memory-region = <&pil_gpu_mem>; 1686 }; 1687 1688 gpu_opp_table: opp-table { 1689 compatible = "operating-points-v2"; 1690 1691 /* TODO: Scale RPM_SMD_BIMC_GPU_CLK w/ turbo freqs */ 1692 opp-1123200000 { 1693 opp-hz = /bits/ 64 <1123200000>; 1694 required-opps = <&rpmpd_opp_turbo_plus>; 1695 opp-peak-kBps = <6881000>; 1696 opp-supported-hw = <0x3>; 1697 turbo-mode; 1698 }; 1699 1700 opp-1017600000 { 1701 opp-hz = /bits/ 64 <1017600000>; 1702 required-opps = <&rpmpd_opp_turbo>; 1703 opp-peak-kBps = <6881000>; 1704 opp-supported-hw = <0x3>; 1705 turbo-mode; 1706 }; 1707 1708 opp-921600000 { 1709 opp-hz = /bits/ 64 <921600000>; 1710 required-opps = <&rpmpd_opp_nom_plus>; 1711 opp-peak-kBps = <6881000>; 1712 opp-supported-hw = <0x3>; 1713 }; 1714 1715 opp-844800000 { 1716 opp-hz = /bits/ 64 <844800000>; 1717 required-opps = <&rpmpd_opp_nom>; 1718 opp-peak-kBps = <6881000>; 1719 opp-supported-hw = <0x7>; 1720 }; 1721 1722 opp-672000000 { 1723 opp-hz = /bits/ 64 <672000000>; 1724 required-opps = <&rpmpd_opp_svs_plus>; 1725 opp-peak-kBps = <3879000>; 1726 opp-supported-hw = <0xf>; 1727 }; 1728 1729 opp-537600000 { 1730 opp-hz = /bits/ 64 <537600000>; 1731 required-opps = <&rpmpd_opp_svs>; 1732 opp-peak-kBps = <2929000>; 1733 opp-supported-hw = <0xf>; 1734 }; 1735 1736 opp-355200000 { 1737 opp-hz = /bits/ 64 <355200000>; 1738 required-opps = <&rpmpd_opp_low_svs>; 1739 opp-peak-kBps = <1720000>; 1740 opp-supported-hw = <0xf>; 1741 }; 1742 }; 1743 }; 1744 1745 gmu_wrapper: gmu@596a000 { 1746 compatible = "qcom,adreno-gmu-wrapper"; 1747 reg = <0x0 0x0596a000 0x0 0x30000>; 1748 reg-names = "gmu"; 1749 power-domains = <&gpucc GPU_CX_GDSC>, 1750 <&gpucc GPU_GX_GDSC>; 1751 power-domain-names = "cx", 1752 "gx"; 1753 }; 1754 1755 gpucc: clock-controller@5990000 { 1756 compatible = "qcom,qcm2290-gpucc"; 1757 reg = <0x0 0x05990000 0x0 0x9000>; 1758 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1759 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1760 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1761 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1762 power-domains = <&rpmpd QCM2290_VDDCX>; 1763 required-opps = <&rpmpd_opp_low_svs>; 1764 #clock-cells = <1>; 1765 #reset-cells = <1>; 1766 #power-domain-cells = <1>; 1767 }; 1768 1769 adreno_smmu: iommu@59a0000 { 1770 compatible = "qcom,qcm2290-smmu-500", "qcom,adreno-smmu", 1771 "qcom,smmu-500", "arm,mmu-500"; 1772 reg = <0x0 0x059a0000 0x0 0x10000>; 1773 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1782 1783 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1784 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1785 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1786 clock-names = "mem", 1787 "hlos", 1788 "iface"; 1789 1790 power-domains = <&gpucc GPU_CX_GDSC>; 1791 1792 #global-interrupts = <1>; 1793 #iommu-cells = <2>; 1794 }; 1795 1796 cci: cci@5c1b000 { 1797 compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci"; 1798 reg = <0x0 0x5c1b000 0x0 0x1000>; 1799 1800 interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>; 1801 1802 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>; 1803 clock-names = "ahb", "cci"; 1804 assigned-clocks = <&gcc GCC_CAMSS_CCI_0_CLK>; 1805 assigned-clock-rates = <37500000>; 1806 1807 power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; 1808 1809 pinctrl-0 = <&cci0_default &cci1_default>; 1810 pinctrl-names = "default"; 1811 1812 #address-cells = <1>; 1813 #size-cells = <0>; 1814 1815 status = "disabled"; 1816 1817 cci_i2c0: i2c-bus@0 { 1818 reg = <0>; 1819 clock-frequency = <400000>; 1820 #address-cells = <1>; 1821 #size-cells = <0>; 1822 }; 1823 1824 cci_i2c1: i2c-bus@1 { 1825 reg = <1>; 1826 clock-frequency = <400000>; 1827 #address-cells = <1>; 1828 #size-cells = <0>; 1829 }; 1830 }; 1831 1832 camss: camss@5c11000 { 1833 compatible = "qcom,qcm2290-camss"; 1834 1835 reg = <0x0 0x5c11000 0x0 0x1000>, 1836 <0x0 0x5c6e000 0x0 0x1000>, 1837 <0x0 0x5c75000 0x0 0x1000>, 1838 <0x0 0x5c52000 0x0 0x1000>, 1839 <0x0 0x5c53000 0x0 0x1000>, 1840 <0x0 0x5c66000 0x0 0x400>, 1841 <0x0 0x5c68000 0x0 0x400>, 1842 <0x0 0x5c6f000 0x0 0x4000>, 1843 <0x0 0x5c76000 0x0 0x4000>; 1844 reg-names = "top", 1845 "csid0", 1846 "csid1", 1847 "csiphy0", 1848 "csiphy1", 1849 "csitpg0", 1850 "csitpg1", 1851 "vfe0", 1852 "vfe1"; 1853 1854 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 1855 <&gcc GCC_CAMSS_AXI_CLK>, 1856 <&gcc GCC_CAMSS_NRT_AXI_CLK>, 1857 <&gcc GCC_CAMSS_RT_AXI_CLK>, 1858 <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, 1859 <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, 1860 <&gcc GCC_CAMSS_CPHY_0_CLK>, 1861 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1862 <&gcc GCC_CAMSS_CPHY_1_CLK>, 1863 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1864 <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1865 <&gcc GCC_CAMSS_TFE_0_CLK>, 1866 <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, 1867 <&gcc GCC_CAMSS_TFE_1_CLK>, 1868 <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK> ; 1869 clock-names = "ahb", 1870 "axi", 1871 "camnoc_nrt_axi", 1872 "camnoc_rt_axi", 1873 "csi0", 1874 "csi1", 1875 "csiphy0", 1876 "csiphy0_timer", 1877 "csiphy1", 1878 "csiphy1_timer", 1879 "top_ahb", 1880 "vfe0", 1881 "vfe0_cphy_rx", 1882 "vfe1", 1883 "vfe1_cphy_rx"; 1884 1885 interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>, 1886 <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, 1887 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, 1888 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 1889 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1890 <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>, 1891 <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>, 1892 <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; 1893 interrupt-names = "csid0", 1894 "csid1", 1895 "csiphy0", 1896 "csiphy1", 1897 "csitpg0", 1898 "csitpg1", 1899 "vfe0", 1900 "vfe1"; 1901 1902 interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 1903 &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>, 1904 <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG 1905 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1906 <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG 1907 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1908 interconnect-names = "ahb", 1909 "hf_mnoc", 1910 "sf_mnoc"; 1911 1912 iommus = <&apps_smmu 0x400 0x0>, 1913 <&apps_smmu 0x800 0x0>, 1914 <&apps_smmu 0x820 0x0>, 1915 <&apps_smmu 0x840 0x0>; 1916 1917 power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; 1918 1919 status = "disabled"; 1920 1921 ports { 1922 #address-cells = <1>; 1923 #size-cells = <0>; 1924 1925 port@0 { 1926 reg = <0>; 1927 }; 1928 1929 port@1 { 1930 reg = <1>; 1931 }; 1932 }; 1933 }; 1934 1935 mdss: display-subsystem@5e00000 { 1936 compatible = "qcom,qcm2290-mdss"; 1937 reg = <0x0 0x05e00000 0x0 0x1000>; 1938 reg-names = "mdss"; 1939 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1940 interrupt-controller; 1941 #interrupt-cells = <1>; 1942 1943 clocks = <&gcc GCC_DISP_AHB_CLK>, 1944 <&gcc GCC_DISP_HF_AXI_CLK>, 1945 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1946 clock-names = "iface", 1947 "bus", 1948 "core"; 1949 1950 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 1951 1952 power-domains = <&dispcc MDSS_GDSC>; 1953 1954 iommus = <&apps_smmu 0x420 0x2>, 1955 <&apps_smmu 0x421 0x0>; 1956 interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG 1957 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1958 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1959 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; 1960 interconnect-names = "mdp0-mem", 1961 "cpu-cfg"; 1962 1963 #address-cells = <2>; 1964 #size-cells = <2>; 1965 ranges; 1966 1967 status = "disabled"; 1968 1969 mdp: display-controller@5e01000 { 1970 compatible = "qcom,qcm2290-dpu"; 1971 reg = <0x0 0x05e01000 0x0 0x8f000>, 1972 <0x0 0x05eb0000 0x0 0x3000>; 1973 reg-names = "mdp", 1974 "vbif"; 1975 1976 interrupt-parent = <&mdss>; 1977 interrupts = <0>; 1978 1979 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1980 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1981 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1982 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1983 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1984 clock-names = "bus", 1985 "iface", 1986 "core", 1987 "lut", 1988 "vsync"; 1989 1990 operating-points-v2 = <&mdp_opp_table>; 1991 power-domains = <&rpmpd QCM2290_VDDCX>; 1992 1993 ports { 1994 #address-cells = <1>; 1995 #size-cells = <0>; 1996 1997 port@0 { 1998 reg = <0>; 1999 dpu_intf1_out: endpoint { 2000 remote-endpoint = <&mdss_dsi0_in>; 2001 }; 2002 }; 2003 }; 2004 2005 mdp_opp_table: opp-table { 2006 compatible = "operating-points-v2"; 2007 2008 opp-19200000 { 2009 opp-hz = /bits/ 64 <19200000>; 2010 required-opps = <&rpmpd_opp_min_svs>; 2011 }; 2012 2013 opp-192000000 { 2014 opp-hz = /bits/ 64 <192000000>; 2015 required-opps = <&rpmpd_opp_low_svs>; 2016 }; 2017 2018 opp-256000000 { 2019 opp-hz = /bits/ 64 <256000000>; 2020 required-opps = <&rpmpd_opp_svs>; 2021 }; 2022 2023 opp-307200000 { 2024 opp-hz = /bits/ 64 <307200000>; 2025 required-opps = <&rpmpd_opp_svs_plus>; 2026 }; 2027 2028 opp-384000000 { 2029 opp-hz = /bits/ 64 <384000000>; 2030 required-opps = <&rpmpd_opp_nom>; 2031 }; 2032 }; 2033 }; 2034 2035 mdss_dsi0: dsi@5e94000 { 2036 compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2037 reg = <0x0 0x05e94000 0x0 0x400>; 2038 reg-names = "dsi_ctrl"; 2039 2040 interrupt-parent = <&mdss>; 2041 interrupts = <4>; 2042 2043 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2044 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2045 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2046 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2047 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2048 <&gcc GCC_DISP_HF_AXI_CLK>; 2049 clock-names = "byte", 2050 "byte_intf", 2051 "pixel", 2052 "core", 2053 "iface", 2054 "bus"; 2055 2056 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2057 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2058 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2059 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2060 2061 operating-points-v2 = <&dsi_opp_table>; 2062 power-domains = <&rpmpd QCM2290_VDDCX>; 2063 phys = <&mdss_dsi0_phy>; 2064 2065 #address-cells = <1>; 2066 #size-cells = <0>; 2067 2068 status = "disabled"; 2069 2070 dsi_opp_table: opp-table { 2071 compatible = "operating-points-v2"; 2072 2073 opp-19200000 { 2074 opp-hz = /bits/ 64 <19200000>; 2075 required-opps = <&rpmpd_opp_min_svs>; 2076 }; 2077 2078 opp-164000000 { 2079 opp-hz = /bits/ 64 <164000000>; 2080 required-opps = <&rpmpd_opp_low_svs>; 2081 }; 2082 2083 opp-187500000 { 2084 opp-hz = /bits/ 64 <187500000>; 2085 required-opps = <&rpmpd_opp_svs>; 2086 }; 2087 }; 2088 2089 ports { 2090 #address-cells = <1>; 2091 #size-cells = <0>; 2092 2093 port@0 { 2094 reg = <0>; 2095 2096 mdss_dsi0_in: endpoint { 2097 remote-endpoint = <&dpu_intf1_out>; 2098 }; 2099 }; 2100 2101 port@1 { 2102 reg = <1>; 2103 2104 mdss_dsi0_out: endpoint { 2105 }; 2106 }; 2107 }; 2108 }; 2109 2110 mdss_dsi0_phy: phy@5e94400 { 2111 compatible = "qcom,dsi-phy-14nm-2290"; 2112 reg = <0x0 0x05e94400 0x0 0x100>, 2113 <0x0 0x05e94500 0x0 0x300>, 2114 <0x0 0x05e94800 0x0 0x188>; 2115 reg-names = "dsi_phy", 2116 "dsi_phy_lane", 2117 "dsi_pll"; 2118 2119 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2120 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2121 clock-names = "iface", 2122 "ref"; 2123 2124 power-domains = <&rpmpd QCM2290_VDDMX>; 2125 required-opps = <&rpmpd_opp_nom>; 2126 2127 #clock-cells = <1>; 2128 #phy-cells = <0>; 2129 2130 status = "disabled"; 2131 }; 2132 }; 2133 2134 dispcc: clock-controller@5f00000 { 2135 compatible = "qcom,qcm2290-dispcc"; 2136 reg = <0x0 0x05f00000 0x0 0x20000>; 2137 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2138 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 2139 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2140 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 2141 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2142 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2143 clock-names = "bi_tcxo", 2144 "bi_tcxo_ao", 2145 "gcc_disp_gpll0_clk_src", 2146 "gcc_disp_gpll0_div_clk_src", 2147 "dsi0_phy_pll_out_byteclk", 2148 "dsi0_phy_pll_out_dsiclk"; 2149 #power-domain-cells = <1>; 2150 #clock-cells = <1>; 2151 #reset-cells = <1>; 2152 }; 2153 2154 remoteproc_mpss: remoteproc@6080000 { 2155 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; 2156 reg = <0x0 0x06080000 0x0 0x100>; 2157 2158 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 2159 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2160 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2161 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2162 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2163 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2164 interrupt-names = "wdog", 2165 "fatal", 2166 "ready", 2167 "handover", 2168 "stop-ack", 2169 "shutdown-ack"; 2170 2171 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2172 clock-names = "xo"; 2173 2174 power-domains = <&rpmpd QCM2290_VDDCX>; 2175 2176 memory-region = <&pil_modem_mem>; 2177 2178 qcom,smem-states = <&modem_smp2p_out 0>; 2179 qcom,smem-state-names = "stop"; 2180 2181 status = "disabled"; 2182 2183 glink-edge { 2184 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 2185 label = "mpss"; 2186 qcom,remote-pid = <1>; 2187 mboxes = <&apcs_glb 12>; 2188 }; 2189 }; 2190 2191 remoteproc_adsp: remoteproc@ab00000 { 2192 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; 2193 reg = <0x0 0x0ab00000 0x0 0x100>; 2194 2195 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 2196 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2197 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2198 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2199 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2200 interrupt-names = "wdog", 2201 "fatal", 2202 "ready", 2203 "handover", 2204 "stop-ack"; 2205 2206 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2207 clock-names = "xo"; 2208 2209 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, 2210 <&rpmpd QCM2290_VDD_LPI_MX>; 2211 2212 memory-region = <&pil_adsp_mem>; 2213 2214 qcom,smem-states = <&adsp_smp2p_out 0>; 2215 qcom,smem-state-names = "stop"; 2216 2217 status = "disabled"; 2218 2219 glink-edge { 2220 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2221 label = "lpass"; 2222 qcom,remote-pid = <2>; 2223 mboxes = <&apcs_glb 8>; 2224 2225 apr { 2226 compatible = "qcom,apr-v2"; 2227 qcom,glink-channels = "apr_audio_svc"; 2228 qcom,domain = <APR_DOMAIN_ADSP>; 2229 #address-cells = <1>; 2230 #size-cells = <0>; 2231 2232 service@3 { 2233 reg = <APR_SVC_ADSP_CORE>; 2234 compatible = "qcom,q6core"; 2235 qcom,protection-domain = "avs/audio", 2236 "msm/adsp/audio_pd"; 2237 }; 2238 2239 q6afe: service@4 { 2240 compatible = "qcom,q6afe"; 2241 reg = <APR_SVC_AFE>; 2242 qcom,protection-domain = "avs/audio", 2243 "msm/adsp/audio_pd"; 2244 q6afedai: dais { 2245 compatible = "qcom,q6afe-dais"; 2246 #address-cells = <1>; 2247 #size-cells = <0>; 2248 #sound-dai-cells = <1>; 2249 }; 2250 2251 q6afecc: clock-controller { 2252 compatible = "qcom,q6afe-clocks"; 2253 #clock-cells = <2>; 2254 }; 2255 }; 2256 2257 q6asm: service@7 { 2258 compatible = "qcom,q6asm"; 2259 reg = <APR_SVC_ASM>; 2260 qcom,protection-domain = "avs/audio", 2261 "msm/adsp/audio_pd"; 2262 q6asmdai: dais { 2263 compatible = "qcom,q6asm-dais"; 2264 #address-cells = <1>; 2265 #size-cells = <0>; 2266 #sound-dai-cells = <1>; 2267 iommus = <&apps_smmu 0x1c1 0x0>; 2268 2269 dai@0 { 2270 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 2271 }; 2272 2273 dai@1 { 2274 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 2275 }; 2276 2277 dai@2 { 2278 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 2279 }; 2280 }; 2281 }; 2282 2283 q6adm: service@8 { 2284 compatible = "qcom,q6adm"; 2285 reg = <APR_SVC_ADM>; 2286 qcom,protection-domain = "avs/audio", 2287 "msm/adsp/audio_pd"; 2288 q6routing: routing { 2289 compatible = "qcom,q6adm-routing"; 2290 #sound-dai-cells = <0>; 2291 }; 2292 }; 2293 }; 2294 2295 fastrpc { 2296 compatible = "qcom,fastrpc"; 2297 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2298 label = "adsp"; 2299 2300 qcom,non-secure-domain; 2301 2302 #address-cells = <1>; 2303 #size-cells = <0>; 2304 2305 compute-cb@3 { 2306 compatible = "qcom,fastrpc-compute-cb"; 2307 reg = <3>; 2308 iommus = <&apps_smmu 0x1c3 0x0>; 2309 }; 2310 2311 compute-cb@4 { 2312 compatible = "qcom,fastrpc-compute-cb"; 2313 reg = <4>; 2314 iommus = <&apps_smmu 0x1c4 0x0>; 2315 }; 2316 2317 compute-cb@5 { 2318 compatible = "qcom,fastrpc-compute-cb"; 2319 reg = <5>; 2320 iommus = <&apps_smmu 0x1c5 0x0>; 2321 }; 2322 2323 compute-cb@6 { 2324 compatible = "qcom,fastrpc-compute-cb"; 2325 reg = <6>; 2326 iommus = <&apps_smmu 0x1c6 0x0>; 2327 }; 2328 2329 compute-cb@7 { 2330 compatible = "qcom,fastrpc-compute-cb"; 2331 reg = <7>; 2332 iommus = <&apps_smmu 0x1c7 0x0>; 2333 }; 2334 }; 2335 }; 2336 }; 2337 2338 apps_smmu: iommu@c600000 { 2339 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2340 reg = <0x0 0x0c600000 0x0 0x80000>; 2341 #iommu-cells = <2>; 2342 #global-interrupts = <1>; 2343 2344 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2345 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 2346 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2347 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2348 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2349 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2350 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2351 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2352 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2353 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2354 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2355 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2356 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2357 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2358 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2359 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2360 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2361 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2362 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2363 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2364 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2365 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2366 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2367 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2368 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2369 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2370 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2371 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2372 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2373 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2374 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2375 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2376 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2377 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2378 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2379 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2380 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2381 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2382 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2383 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2384 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2385 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2386 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2387 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2388 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2389 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2390 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2391 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2392 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2393 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2394 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2395 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2396 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2398 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2399 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2400 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2401 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2404 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2405 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2406 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2407 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2408 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2409 }; 2410 2411 venus: video-codec@5a00000 { 2412 compatible = "qcom,qcm2290-venus"; 2413 reg = <0 0x5a00000 0 0xf0000>; 2414 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 2415 2416 power-domains = <&gcc GCC_VENUS_GDSC>, 2417 <&gcc GCC_VCODEC0_GDSC>, 2418 <&rpmpd QCM2290_VDDCX>; 2419 power-domain-names = "venus", 2420 "vcodec0", 2421 "cx"; 2422 operating-points-v2 = <&venus_opp_table>; 2423 2424 clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, 2425 <&gcc GCC_VIDEO_AHB_CLK>, 2426 <&gcc GCC_VENUS_CTL_AXI_CLK>, 2427 <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>, 2428 <&gcc GCC_VIDEO_VCODEC0_SYS_CLK>, 2429 <&gcc GCC_VCODEC0_AXI_CLK>; 2430 clock-names = "core", 2431 "iface", 2432 "bus", 2433 "throttle", 2434 "vcodec0_core", 2435 "vcodec0_bus"; 2436 2437 memory-region = <&pil_video_mem>; 2438 iommus = <&apps_smmu 0x860 0x0>, 2439 <&apps_smmu 0x880 0x0>, 2440 <&apps_smmu 0x861 0x04>, 2441 <&apps_smmu 0x863 0x0>, 2442 <&apps_smmu 0x804 0xe0>; 2443 2444 interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG 2445 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 2446 <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 2447 &config_noc SLAVE_VENUS_CFG RPM_ACTIVE_TAG>; 2448 interconnect-names = "video-mem", 2449 "cpu-cfg"; 2450 2451 venus_opp_table: opp-table { 2452 compatible = "operating-points-v2"; 2453 2454 opp-133333333 { 2455 opp-hz = /bits/ 64 <133333333>; 2456 required-opps = <&rpmpd_opp_low_svs>; 2457 }; 2458 2459 opp-240000000 { 2460 opp-hz = /bits/ 64 <240000000>; 2461 required-opps = <&rpmpd_opp_svs>; 2462 }; 2463 }; 2464 }; 2465 2466 wifi: wifi@c800000 { 2467 compatible = "qcom,wcn3990-wifi"; 2468 reg = <0x0 0x0c800000 0x0 0x800000>; 2469 reg-names = "membase"; 2470 memory-region = <&wlan_msa_mem>; 2471 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 2480 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 2481 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2482 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2483 iommus = <&apps_smmu 0x1a0 0x1>; 2484 qcom,msa-fixed-perm; 2485 status = "disabled"; 2486 }; 2487 2488 watchdog@f017000 { 2489 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; 2490 reg = <0x0 0x0f017000 0x0 0x1000>; 2491 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 2492 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 2493 clocks = <&sleep_clk>; 2494 }; 2495 2496 apcs_glb: mailbox@f111000 { 2497 compatible = "qcom,qcm2290-apcs-hmss-global"; 2498 reg = <0x0 0x0f111000 0x0 0x1000>; 2499 #mbox-cells = <1>; 2500 }; 2501 2502 timer@f120000 { 2503 compatible = "arm,armv7-timer-mem"; 2504 reg = <0x0 0x0f120000 0x0 0x1000>; 2505 #address-cells = <1>; 2506 #size-cells = <1>; 2507 ranges = <0 0x0 0x0f121000 0x8000>; 2508 2509 frame@0 { 2510 reg = <0x0 0x1000>, 2511 <0x1000 0x1000>; 2512 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2513 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2514 frame-number = <0>; 2515 }; 2516 2517 frame@2000 { 2518 reg = <0x2000 0x1000>; 2519 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2520 frame-number = <1>; 2521 status = "disabled"; 2522 }; 2523 2524 frame@3000 { 2525 reg = <0x3000 0x1000>; 2526 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2527 frame-number = <2>; 2528 status = "disabled"; 2529 }; 2530 2531 frame@4000 { 2532 reg = <0x4000 0x1000>; 2533 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2534 frame-number = <3>; 2535 status = "disabled"; 2536 }; 2537 2538 frame@5000 { 2539 reg = <0x5000 0x1000>; 2540 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2541 frame-number = <4>; 2542 status = "disabled"; 2543 }; 2544 2545 frame@6000 { 2546 reg = <0x6000 0x1000>; 2547 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2548 frame-number = <5>; 2549 status = "disabled"; 2550 }; 2551 2552 frame@7000 { 2553 reg = <0x7000 0x1000>; 2554 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2555 frame-number = <6>; 2556 status = "disabled"; 2557 }; 2558 }; 2559 2560 intc: interrupt-controller@f200000 { 2561 compatible = "arm,gic-v3"; 2562 reg = <0x0 0x0f200000 0x0 0x10000>, 2563 <0x0 0x0f300000 0x0 0x100000>; 2564 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2565 #interrupt-cells = <3>; 2566 interrupt-controller; 2567 interrupt-parent = <&intc>; 2568 #redistributor-regions = <1>; 2569 redistributor-stride = <0x0 0x20000>; 2570 }; 2571 2572 cpufreq_hw: cpufreq@f521000 { 2573 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; 2574 reg = <0x0 0x0f521000 0x0 0x1000>; 2575 reg-names = "freq-domain0"; 2576 interrupts-extended = <&lmh_cluster 0>; 2577 interrupt-names = "dcvsh-irq-0"; 2578 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2579 clock-names = "xo", "alternate"; 2580 2581 #freq-domain-cells = <1>; 2582 #clock-cells = <1>; 2583 }; 2584 2585 lmh_cluster: lmh@f550800 { 2586 compatible = "qcom,qcm2290-lmh", "qcom,sm8150-lmh"; 2587 reg = <0x0 0x0f550800 0x0 0x400>; 2588 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2589 cpus = <&cpu0>; 2590 qcom,lmh-temp-arm-millicelsius = <65000>; 2591 qcom,lmh-temp-low-millicelsius = <94500>; 2592 qcom,lmh-temp-high-millicelsius = <95000>; 2593 interrupt-controller; 2594 #interrupt-cells = <1>; 2595 }; 2596 }; 2597 2598 thermal-zones { 2599 mapss-thermal { 2600 thermal-sensors = <&tsens0 0>; 2601 2602 trips { 2603 mapss_alert0: trip-point0 { 2604 temperature = <90000>; 2605 hysteresis = <2000>; 2606 type = "passive"; 2607 }; 2608 2609 mapss_alert1: trip-point1 { 2610 temperature = <95000>; 2611 hysteresis = <2000>; 2612 type = "passive"; 2613 }; 2614 2615 mapss_crit: mapss-crit { 2616 temperature = <110000>; 2617 hysteresis = <1000>; 2618 type = "critical"; 2619 }; 2620 }; 2621 }; 2622 2623 video-thermal { 2624 thermal-sensors = <&tsens0 1>; 2625 2626 trips { 2627 video_alert0: trip-point0 { 2628 temperature = <90000>; 2629 hysteresis = <2000>; 2630 type = "passive"; 2631 }; 2632 2633 video_alert1: trip-point1 { 2634 temperature = <95000>; 2635 hysteresis = <2000>; 2636 type = "passive"; 2637 }; 2638 2639 video_crit: video-crit { 2640 temperature = <110000>; 2641 hysteresis = <1000>; 2642 type = "critical"; 2643 }; 2644 }; 2645 }; 2646 2647 wlan-thermal { 2648 thermal-sensors = <&tsens0 2>; 2649 2650 trips { 2651 wlan_alert0: trip-point0 { 2652 temperature = <90000>; 2653 hysteresis = <2000>; 2654 type = "passive"; 2655 }; 2656 2657 wlan_alert1: trip-point1 { 2658 temperature = <95000>; 2659 hysteresis = <2000>; 2660 type = "passive"; 2661 }; 2662 2663 wlan_crit: wlan-crit { 2664 temperature = <110000>; 2665 hysteresis = <1000>; 2666 type = "critical"; 2667 }; 2668 }; 2669 }; 2670 2671 cpuss0-thermal { 2672 thermal-sensors = <&tsens0 3>; 2673 2674 trips { 2675 cpuss0_alert0: trip-point0 { 2676 temperature = <90000>; 2677 hysteresis = <2000>; 2678 type = "passive"; 2679 }; 2680 2681 cpuss0_alert1: trip-point1 { 2682 temperature = <95000>; 2683 hysteresis = <2000>; 2684 type = "passive"; 2685 }; 2686 2687 cpuss0_crit: cpuss0-crit { 2688 temperature = <110000>; 2689 hysteresis = <1000>; 2690 type = "critical"; 2691 }; 2692 }; 2693 }; 2694 2695 cpuss1-thermal { 2696 thermal-sensors = <&tsens0 4>; 2697 2698 trips { 2699 cpuss1_alert0: trip-point0 { 2700 temperature = <90000>; 2701 hysteresis = <2000>; 2702 type = "passive"; 2703 }; 2704 2705 cpuss1_alert1: trip-point1 { 2706 temperature = <95000>; 2707 hysteresis = <2000>; 2708 type = "passive"; 2709 }; 2710 2711 cpuss1_crit: cpuss1-crit { 2712 temperature = <110000>; 2713 hysteresis = <1000>; 2714 type = "critical"; 2715 }; 2716 }; 2717 }; 2718 2719 mdm0-thermal { 2720 thermal-sensors = <&tsens0 5>; 2721 2722 trips { 2723 mdm0_alert0: trip-point0 { 2724 temperature = <90000>; 2725 hysteresis = <2000>; 2726 type = "passive"; 2727 }; 2728 2729 mdm0_alert1: trip-point1 { 2730 temperature = <95000>; 2731 hysteresis = <2000>; 2732 type = "passive"; 2733 }; 2734 2735 mdm0_crit: mdm0-crit { 2736 temperature = <110000>; 2737 hysteresis = <1000>; 2738 type = "critical"; 2739 }; 2740 }; 2741 }; 2742 2743 mdm1-thermal { 2744 thermal-sensors = <&tsens0 6>; 2745 2746 trips { 2747 mdm1_alert0: trip-point0 { 2748 temperature = <90000>; 2749 hysteresis = <2000>; 2750 type = "passive"; 2751 }; 2752 2753 mdm1_alert1: trip-point1 { 2754 temperature = <95000>; 2755 hysteresis = <2000>; 2756 type = "passive"; 2757 }; 2758 2759 mdm1_crit: mdm1-crit { 2760 temperature = <110000>; 2761 hysteresis = <1000>; 2762 type = "critical"; 2763 }; 2764 }; 2765 }; 2766 2767 gpu-thermal { 2768 thermal-sensors = <&tsens0 7>; 2769 2770 trips { 2771 gpu_alert0: trip-point0 { 2772 temperature = <90000>; 2773 hysteresis = <2000>; 2774 type = "passive"; 2775 }; 2776 2777 gpu_alert1: trip-point1 { 2778 temperature = <95000>; 2779 hysteresis = <2000>; 2780 type = "passive"; 2781 }; 2782 2783 gpu_crit: gpu-crit { 2784 temperature = <110000>; 2785 hysteresis = <1000>; 2786 type = "critical"; 2787 }; 2788 }; 2789 }; 2790 2791 hm-center-thermal { 2792 thermal-sensors = <&tsens0 8>; 2793 2794 trips { 2795 hm_center_alert0: trip-point0 { 2796 temperature = <90000>; 2797 hysteresis = <2000>; 2798 type = "passive"; 2799 }; 2800 2801 hm_center_alert1: trip-point1 { 2802 temperature = <95000>; 2803 hysteresis = <2000>; 2804 type = "passive"; 2805 }; 2806 2807 hm_center_crit: hm-center-crit { 2808 temperature = <110000>; 2809 hysteresis = <1000>; 2810 type = "critical"; 2811 }; 2812 }; 2813 }; 2814 2815 camera-thermal { 2816 thermal-sensors = <&tsens0 9>; 2817 2818 trips { 2819 camera_alert0: trip-point0 { 2820 temperature = <90000>; 2821 hysteresis = <2000>; 2822 type = "passive"; 2823 }; 2824 2825 camera_alert1: trip-point1 { 2826 temperature = <95000>; 2827 hysteresis = <2000>; 2828 type = "passive"; 2829 }; 2830 2831 camera_crit: camera-crit { 2832 temperature = <110000>; 2833 hysteresis = <1000>; 2834 type = "critical"; 2835 }; 2836 }; 2837 }; 2838 }; 2839 2840 timer { 2841 compatible = "arm,armv8-timer"; 2842 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2843 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2844 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2845 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2846 }; 2847}; 2848