xref: /linux/arch/arm64/boot/dts/nvidia/tegra264.dtsi (revision d30c1683aaecb93d2ab95685dc4300a33d3cea7a) 
1// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
3#include <dt-bindings/clock/nvidia,tegra264.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mailbox/tegra186-hsp.h>
6#include <dt-bindings/memory/nvidia,tegra264.h>
7#include <dt-bindings/power/nvidia,tegra264-bpmp.h>
8#include <dt-bindings/reset/nvidia,tegra264.h>
9
10/ {
11	compatible = "nvidia,tegra264";
12	interrupt-parent = <&gic>;
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	reserved-memory {
17		#address-cells = <2>;
18		#size-cells = <2>;
19		ranges;
20
21		shmem_bpmp: shmem@86070000 {
22			compatible = "nvidia,tegra264-bpmp-shmem";
23			reg = <0x0 0x86070000 0x0 0x2000>;
24			no-map;
25		};
26	};
27
28	/* SYSTEM MMIO */
29	bus@0 {
30		compatible = "simple-bus";
31
32		#address-cells = <2>;
33		#size-cells = <2>;
34
35		ranges = <0x00 0x00000000 0x00 0x00000000 0x01 0x00000000>;
36
37		misc@100000 {
38			compatible = "nvidia,tegra234-misc";
39			reg = <0x0 0x00100000 0x0 0x0f000>,
40			      <0x0 0x0c140000 0x0 0x10000>;
41		};
42
43		timer@8000000 {
44			compatible = "nvidia,tegra234-timer";
45			reg = <0x0 0x08000000 0x0 0x140000>;
46			interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
47				     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
48				     <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>,
49				     <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>;
50			status = "disabled";
51		};
52
53		aconnect@9000000 {
54			compatible = "nvidia,tegra264-aconnect",
55					"nvidia,tegra210-aconnect";
56			clocks = <&bpmp TEGRA264_CLK_APE>,
57				<&bpmp TEGRA264_CLK_ADSP>;
58			clock-names = "ape", "apb2ape";
59			power-domains = <&bpmp TEGRA264_POWER_DOMAIN_AUD>;
60			status = "disabled";
61
62			#address-cells = <2>;
63			#size-cells = <2>;
64			ranges = <0x0 0x9000000 0x0 0x9000000 0x0 0x2000000>;
65
66			adma: dma-controller@9440000 {
67				compatible = "nvidia,tegra264-adma";
68				reg = <0x0 0x9440000 0x0 0xb0000>;
69				interrupt-parent = <&agic_page0>;
70				interrupts = <GIC_SPI 0x90 IRQ_TYPE_LEVEL_HIGH>,
71					   <GIC_SPI 0x91 IRQ_TYPE_LEVEL_HIGH>,
72					   <GIC_SPI 0x92 IRQ_TYPE_LEVEL_HIGH>,
73					   <GIC_SPI 0x93 IRQ_TYPE_LEVEL_HIGH>,
74					   <GIC_SPI 0x94 IRQ_TYPE_LEVEL_HIGH>,
75					   <GIC_SPI 0x95 IRQ_TYPE_LEVEL_HIGH>,
76					   <GIC_SPI 0x96 IRQ_TYPE_LEVEL_HIGH>,
77					   <GIC_SPI 0x97 IRQ_TYPE_LEVEL_HIGH>,
78					   <GIC_SPI 0x98 IRQ_TYPE_LEVEL_HIGH>,
79					   <GIC_SPI 0x99 IRQ_TYPE_LEVEL_HIGH>,
80					   <GIC_SPI 0x9a IRQ_TYPE_LEVEL_HIGH>,
81					   <GIC_SPI 0x9b IRQ_TYPE_LEVEL_HIGH>,
82					   <GIC_SPI 0x9c IRQ_TYPE_LEVEL_HIGH>,
83					   <GIC_SPI 0x9d IRQ_TYPE_LEVEL_HIGH>,
84					   <GIC_SPI 0x9e IRQ_TYPE_LEVEL_HIGH>,
85					   <GIC_SPI 0x9f IRQ_TYPE_LEVEL_HIGH>,
86					   <GIC_SPI 0xa0 IRQ_TYPE_LEVEL_HIGH>,
87					   <GIC_SPI 0xa1 IRQ_TYPE_LEVEL_HIGH>,
88					   <GIC_SPI 0xa2 IRQ_TYPE_LEVEL_HIGH>,
89					   <GIC_SPI 0xa3 IRQ_TYPE_LEVEL_HIGH>,
90					   <GIC_SPI 0xa4 IRQ_TYPE_LEVEL_HIGH>,
91					   <GIC_SPI 0xa5 IRQ_TYPE_LEVEL_HIGH>,
92					   <GIC_SPI 0xa6 IRQ_TYPE_LEVEL_HIGH>,
93					   <GIC_SPI 0xa7 IRQ_TYPE_LEVEL_HIGH>,
94					   <GIC_SPI 0xa8 IRQ_TYPE_LEVEL_HIGH>,
95					   <GIC_SPI 0xa9 IRQ_TYPE_LEVEL_HIGH>,
96					   <GIC_SPI 0xaa IRQ_TYPE_LEVEL_HIGH>,
97					   <GIC_SPI 0xab IRQ_TYPE_LEVEL_HIGH>,
98					   <GIC_SPI 0xac IRQ_TYPE_LEVEL_HIGH>,
99					   <GIC_SPI 0xad IRQ_TYPE_LEVEL_HIGH>,
100					   <GIC_SPI 0xae IRQ_TYPE_LEVEL_HIGH>,
101					   <GIC_SPI 0xaf IRQ_TYPE_LEVEL_HIGH>,
102					   <GIC_SPI 0xb0 IRQ_TYPE_LEVEL_HIGH>,
103					   <GIC_SPI 0xb1 IRQ_TYPE_LEVEL_HIGH>,
104					   <GIC_SPI 0xb2 IRQ_TYPE_LEVEL_HIGH>,
105					   <GIC_SPI 0xb3 IRQ_TYPE_LEVEL_HIGH>,
106					   <GIC_SPI 0xb4 IRQ_TYPE_LEVEL_HIGH>,
107					   <GIC_SPI 0xb5 IRQ_TYPE_LEVEL_HIGH>,
108					   <GIC_SPI 0xb6 IRQ_TYPE_LEVEL_HIGH>,
109					   <GIC_SPI 0xb7 IRQ_TYPE_LEVEL_HIGH>,
110					   <GIC_SPI 0xb8 IRQ_TYPE_LEVEL_HIGH>,
111					   <GIC_SPI 0xb9 IRQ_TYPE_LEVEL_HIGH>,
112					   <GIC_SPI 0xba IRQ_TYPE_LEVEL_HIGH>,
113					   <GIC_SPI 0xbb IRQ_TYPE_LEVEL_HIGH>,
114					   <GIC_SPI 0xbc IRQ_TYPE_LEVEL_HIGH>,
115					   <GIC_SPI 0xbd IRQ_TYPE_LEVEL_HIGH>,
116					   <GIC_SPI 0xbe IRQ_TYPE_LEVEL_HIGH>,
117					   <GIC_SPI 0xbf IRQ_TYPE_LEVEL_HIGH>,
118					   <GIC_SPI 0xc0 IRQ_TYPE_LEVEL_HIGH>,
119					   <GIC_SPI 0xc1 IRQ_TYPE_LEVEL_HIGH>,
120					   <GIC_SPI 0xc2 IRQ_TYPE_LEVEL_HIGH>,
121					   <GIC_SPI 0xc3 IRQ_TYPE_LEVEL_HIGH>,
122					   <GIC_SPI 0xc4 IRQ_TYPE_LEVEL_HIGH>,
123					   <GIC_SPI 0xc5 IRQ_TYPE_LEVEL_HIGH>,
124					   <GIC_SPI 0xc6 IRQ_TYPE_LEVEL_HIGH>,
125					   <GIC_SPI 0xc7 IRQ_TYPE_LEVEL_HIGH>,
126					   <GIC_SPI 0xc8 IRQ_TYPE_LEVEL_HIGH>,
127					   <GIC_SPI 0xc9 IRQ_TYPE_LEVEL_HIGH>,
128					   <GIC_SPI 0xca IRQ_TYPE_LEVEL_HIGH>,
129					   <GIC_SPI 0xcb IRQ_TYPE_LEVEL_HIGH>,
130					   <GIC_SPI 0xcc IRQ_TYPE_LEVEL_HIGH>,
131					   <GIC_SPI 0xcd IRQ_TYPE_LEVEL_HIGH>,
132					   <GIC_SPI 0xce IRQ_TYPE_LEVEL_HIGH>,
133					   <GIC_SPI 0xcf IRQ_TYPE_LEVEL_HIGH>;
134				#dma-cells = <1>;
135				clocks = <&bpmp TEGRA264_CLK_AHUB>;
136				clock-names = "d_audio";
137				status = "disabled";
138			};
139
140			tegra_ahub: ahub@9630000 {
141				compatible = "nvidia,tegra264-ahub";
142				reg = <0x0 0x9630000 0x0 0x10000>;
143				clocks = <&bpmp TEGRA264_CLK_AHUB>;
144				clock-names = "ahub";
145				assigned-clocks = <&bpmp TEGRA264_CLK_AHUB>;
146				assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON_APE>;
147				status = "disabled";
148
149				#address-cells = <2>;
150				#size-cells = <2>;
151				/* ADMA is under AHUB range, its excluded in the defined range */
152				ranges = <0x0 0x9280000 0x0 0x9280000 0x0 0x1c0000>,
153					<0x0 0x9510000 0x0 0x9510000 0x0 0x370000>;
154
155				tegra_i2s1: i2s@9280000 {
156					compatible = "nvidia,tegra264-i2s";
157					reg = <0x0 0x9280000 0x0 0x10000>;
158					clocks = <&bpmp TEGRA264_CLK_I2S1>,
159					       <&bpmp TEGRA264_CLK_I2S1_SCLK_IN>;
160					clock-names = "i2s", "sync_input";
161					assigned-clocks = <&bpmp TEGRA264_CLK_I2S1>;
162					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
163					assigned-clock-rates = <1536000>;
164					sound-name-prefix = "I2S1";
165					status = "disabled";
166
167					ports {
168						#address-cells = <1>;
169						#size-cells = <0>;
170
171						port@0 {
172							reg = <0>;
173
174							i2s1_cif: endpoint {
175								remote-endpoint = <&xbar_i2s1>;
176							};
177						};
178
179						i2s1_port: port@1 {
180							reg = <1>;
181
182							i2s1_dap: endpoint {
183								dai-format = "i2s";
184								/* placeholder for external codec */
185							};
186						};
187					};
188				};
189
190				tegra_i2s2: i2s@9290000 {
191					compatible = "nvidia,tegra264-i2s";
192					reg = <0x0 0x9290000 0x0 0x10000>;
193					clocks = <&bpmp TEGRA264_CLK_I2S2>,
194						 <&bpmp TEGRA264_CLK_I2S2_SCLK_IN>;
195					clock-names = "i2s", "sync_input";
196					assigned-clocks = <&bpmp TEGRA264_CLK_I2S2>;
197					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
198					assigned-clock-rates = <1536000>;
199					sound-name-prefix = "I2S2";
200					status = "disabled";
201
202					ports {
203						#address-cells = <1>;
204						#size-cells = <0>;
205
206						port@0 {
207							reg = <0>;
208
209							i2s2_cif: endpoint {
210								remote-endpoint = <&xbar_i2s2>;
211							};
212						};
213
214						i2s2_port: port@1 {
215							reg = <1>;
216
217							i2s2_dap: endpoint {
218								dai-format = "i2s";
219								/* placeholder for external codec */
220							};
221						};
222					};
223				};
224
225				tegra_i2s3: i2s@92a0000 {
226					compatible = "nvidia,tegra264-i2s";
227					reg = <0x0 0x92a0000 0x0 0x10000>;
228					clocks = <&bpmp TEGRA264_CLK_I2S3>,
229					       <&bpmp TEGRA264_CLK_I2S3_SCLK_IN>;
230					clock-names = "i2s", "sync_input";
231					assigned-clocks = <&bpmp TEGRA264_CLK_I2S3>;
232					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
233					assigned-clock-rates = <1536000>;
234					sound-name-prefix = "I2S3";
235					status = "disabled";
236
237					ports {
238						#address-cells = <1>;
239						#size-cells = <0>;
240
241						port@0 {
242							reg = <0>;
243
244							i2s3_cif: endpoint {
245								remote-endpoint = <&xbar_i2s3>;
246							};
247						};
248
249						i2s3_port: port@1 {
250							reg = <1>;
251
252							i2s3_dap: endpoint {
253								dai-format = "i2s";
254								/* placeholder for external codec */
255							};
256						};
257					};
258				};
259
260				tegra_i2s4: i2s@92b0000 {
261					compatible = "nvidia,tegra264-i2s";
262					reg = <0x0 0x92b0000 0x0 0x10000>;
263					clocks = <&bpmp TEGRA264_CLK_I2S4>,
264					       <&bpmp TEGRA264_CLK_I2S4_SCLK_IN>;
265					clock-names = "i2s", "sync_input";
266					assigned-clocks = <&bpmp TEGRA264_CLK_I2S4>;
267					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
268					assigned-clock-rates = <1536000>;
269					sound-name-prefix = "I2S4";
270					status = "disabled";
271
272					ports {
273						#address-cells = <1>;
274						#size-cells = <0>;
275
276						port@0 {
277							reg = <0>;
278
279							i2s4_cif: endpoint {
280								remote-endpoint = <&xbar_i2s4>;
281							};
282						};
283
284						i2s4_port: port@1 {
285							reg = <1>;
286
287							i2s4_dap: endpoint {
288								dai-format = "i2s";
289								/* placeholder for external codec */
290							};
291						};
292					};
293				};
294
295				tegra_i2s5: i2s@92c0000 {
296					compatible = "nvidia,tegra264-i2s";
297					reg = <0x0 0x92c0000 0x0 0x10000>;
298					clocks = <&bpmp TEGRA264_CLK_I2S5>,
299					       <&bpmp TEGRA264_CLK_I2S5_SCLK_IN>;
300					clock-names = "i2s", "sync_input";
301					assigned-clocks = <&bpmp TEGRA264_CLK_I2S5>;
302					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
303					assigned-clock-rates = <1536000>;
304					sound-name-prefix = "I2S5";
305					status = "disabled";
306
307					ports {
308						#address-cells = <1>;
309						#size-cells = <0>;
310
311						port@0 {
312							reg = <0>;
313
314							i2s5_cif: endpoint {
315								remote-endpoint = <&xbar_i2s5>;
316							};
317						};
318
319						i2s5_port: port@1 {
320							reg = <1>;
321
322							i2s5_dap: endpoint {
323								dai-format = "i2s";
324								/* placeholder for external codec */
325							};
326						};
327					};
328				};
329
330				tegra_i2s6: i2s@92d0000 {
331					compatible = "nvidia,tegra264-i2s";
332					reg = <0x0 0x92d0000 0x0 0x10000>;
333					clocks = <&bpmp TEGRA264_CLK_I2S6>,
334					       <&bpmp TEGRA264_CLK_I2S6_SCLK_IN>;
335					clock-names = "i2s", "sync_input";
336					assigned-clocks = <&bpmp TEGRA264_CLK_I2S6>;
337					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
338					assigned-clock-rates = <1536000>;
339					sound-name-prefix = "I2S6";
340					status = "disabled";
341
342					ports {
343						#address-cells = <1>;
344						#size-cells = <0>;
345
346						port@0 {
347							reg = <0>;
348
349							i2s6_cif: endpoint {
350								remote-endpoint = <&xbar_i2s6>;
351							};
352						};
353
354						i2s6_port: port@1 {
355							reg = <1>;
356
357							i2s6_dap: endpoint {
358								dai-format = "i2s";
359								/* placeholder for external codec */
360							};
361						};
362					};
363				};
364
365				tegra_i2s7: i2s@92e0000 {
366					compatible = "nvidia,tegra264-i2s";
367					reg = <0x0 0x92e0000 0x0 0x10000>;
368					clocks = <&bpmp TEGRA264_CLK_I2S7>,
369					       <&bpmp TEGRA264_CLK_I2S7_SCLK_IN>;
370					clock-names = "i2s", "sync_input";
371					assigned-clocks = <&bpmp TEGRA264_CLK_I2S7>;
372					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
373					assigned-clock-rates = <1536000>;
374					sound-name-prefix = "I2S7";
375					status = "disabled";
376
377					ports {
378						#address-cells = <1>;
379						#size-cells = <0>;
380
381						port@0 {
382							reg = <0>;
383
384							i2s7_cif: endpoint {
385								remote-endpoint = <&xbar_i2s7>;
386							};
387						};
388
389						i2s7_port: port@1 {
390							reg = <1>;
391
392							i2s7_dap: endpoint {
393								dai-format = "i2s";
394								/* placeholder for external codec */
395							};
396						};
397					};
398				};
399
400				tegra_i2s8: i2s@92f0000 {
401					compatible = "nvidia,tegra264-i2s";
402					reg = <0x0 0x92f0000 0x0 0x10000>;
403					clocks = <&bpmp TEGRA264_CLK_I2S8>,
404					       <&bpmp TEGRA264_CLK_I2S8_SCLK_IN>;
405					clock-names = "i2s", "sync_input";
406					assigned-clocks = <&bpmp TEGRA264_CLK_I2S8>;
407					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
408					assigned-clock-rates = <1536000>;
409					sound-name-prefix = "I2S8";
410					status = "disabled";
411
412					ports {
413						#address-cells = <1>;
414						#size-cells = <0>;
415
416						port@0 {
417							reg = <0>;
418
419							i2s8_cif: endpoint {
420								remote-endpoint = <&xbar_i2s8>;
421							};
422						};
423
424						i2s8_port: port@1 {
425							reg = <1>;
426
427							i2s8_dap: endpoint {
428								dai-format = "i2s";
429								/* placeholder for external codec */
430							};
431						};
432					};
433				};
434
435				tegra_dmic1: dmic@9300000 {
436					compatible = "nvidia,tegra264-dmic",
437							"nvidia,tegra210-dmic";
438					reg = <0x0 0x9300000 0x0 0x10000>;
439					clocks = <&bpmp TEGRA264_CLK_DMIC1>;
440					clock-names = "dmic";
441					assigned-clocks = <&bpmp TEGRA264_CLK_DMIC1>;
442					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
443					assigned-clock-rates = <3072000>;
444					sound-name-prefix = "DMIC1";
445					status = "disabled";
446
447					ports {
448						#address-cells = <1>;
449						#size-cells = <0>;
450
451						port@0 {
452							reg = <0>;
453
454							dmic1_cif: endpoint {
455								remote-endpoint = <&xbar_dmic1>;
456							};
457						};
458
459						dmic1_port: port@1 {
460							reg = <1>;
461
462							dmic1_dap: endpoint {
463								/* placeholder for external codec */
464							};
465						};
466					};
467				};
468
469				tegra_dmic2: dmic@9310000 {
470					compatible = "nvidia,tegra264-dmic",
471						   "nvidia,tegra210-dmic";
472					reg = <0x0 0x9310000 0x0 0x10000>;
473					clocks = <&bpmp TEGRA264_CLK_DMIC1>;
474					clock-names = "dmic";
475					assigned-clocks = <&bpmp TEGRA264_CLK_DMIC1>;
476					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
477					assigned-clock-rates = <3072000>;
478					sound-name-prefix = "DMIC2";
479					status = "disabled";
480
481					ports {
482						#address-cells = <1>;
483						#size-cells = <0>;
484
485						port@0 {
486							reg = <0>;
487
488							dmic2_cif: endpoint {
489								remote-endpoint = <&xbar_dmic2>;
490							};
491						};
492
493						dmic2_port: port@1 {
494							reg = <1>;
495
496							dmic2_dap: endpoint {
497								/* placeholder for external codec */
498							};
499						};
500					};
501				};
502
503				tegra_dspk1: dspk@9380000 {
504					compatible = "nvidia,tegra264-dspk",
505							"nvidia,tegra186-dspk";
506					reg = <0x0 0x9380000 0x0 0x10000>;
507					clocks = <&bpmp TEGRA264_CLK_DSPK1>;
508					clock-names = "dspk";
509					assigned-clocks = <&bpmp TEGRA264_CLK_DSPK1>;
510					assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
511					assigned-clock-rates = <12288000>;
512					sound-name-prefix = "DSPK1";
513					status = "disabled";
514
515					ports {
516						#address-cells = <1>;
517						#size-cells = <0>;
518
519						port@0 {
520							reg = <0>;
521
522							dspk1_cif: endpoint {
523								remote-endpoint = <&xbar_dspk1>;
524							};
525						};
526
527						dspk1_port: port@1 {
528							reg = <1>;
529
530							dspk1_dap: endpoint {
531								/* placeholder for external codec */
532							};
533						};
534					};
535				};
536
537				tegra_amx1: amx@9510000 {
538					compatible = "nvidia,tegra264-amx";
539					reg = <0x0 0x9510000 0x0 0x10000>;
540					sound-name-prefix = "AMX1";
541
542					ports {
543						#address-cells = <1>;
544						#size-cells = <0>;
545
546						port@0 {
547							reg = <0>;
548
549							amx1_in1: endpoint {
550								remote-endpoint = <&xbar_amx1_in1>;
551							};
552						};
553
554						port@1 {
555							reg = <1>;
556
557							amx1_in2: endpoint {
558								remote-endpoint = <&xbar_amx1_in2>;
559							};
560						};
561
562						port@2 {
563							reg = <2>;
564
565							amx1_in3: endpoint {
566								remote-endpoint = <&xbar_amx1_in3>;
567							};
568						};
569
570						port@3 {
571							reg = <3>;
572
573							amx1_in4: endpoint {
574								remote-endpoint = <&xbar_amx1_in4>;
575							};
576						};
577
578						amx1_out_port: port@4 {
579							reg = <4>;
580
581							amx1_out: endpoint {
582								remote-endpoint = <&xbar_amx1_out>;
583							};
584						};
585					};
586				};
587
588				tegra_amx2: amx@9520000 {
589					compatible = "nvidia,tegra264-amx";
590					reg = <0x0 0x9520000 0x0 0x10000>;
591					sound-name-prefix = "AMX2";
592
593					ports {
594						#address-cells = <1>;
595						#size-cells = <0>;
596
597						port@0 {
598							reg = <0>;
599
600							amx2_in1: endpoint {
601								remote-endpoint = <&xbar_amx2_in1>;
602							};
603						};
604
605						port@1 {
606							reg = <1>;
607
608							amx2_in2: endpoint {
609								remote-endpoint = <&xbar_amx2_in2>;
610							};
611						};
612
613						port@2 {
614							reg = <2>;
615
616							amx2_in3: endpoint {
617								remote-endpoint = <&xbar_amx2_in3>;
618							};
619						};
620
621						port@3 {
622							reg = <3>;
623
624							amx2_in4: endpoint {
625								remote-endpoint = <&xbar_amx2_in4>;
626							};
627						};
628
629						amx2_out_port: port@4 {
630							reg = <4>;
631
632							amx2_out: endpoint {
633								remote-endpoint = <&xbar_amx2_out>;
634							};
635						};
636					};
637				};
638
639				tegra_amx3: amx@9530000 {
640					compatible = "nvidia,tegra264-amx";
641					reg = <0x0 0x9530000 0x0 0x10000>;
642					sound-name-prefix = "AMX3";
643
644					ports {
645						#address-cells = <1>;
646						#size-cells = <0>;
647
648						port@0 {
649							reg = <0>;
650
651							amx3_in1: endpoint {
652								remote-endpoint = <&xbar_amx3_in1>;
653							};
654						};
655
656						port@1 {
657							reg = <1>;
658
659							amx3_in2: endpoint {
660								remote-endpoint = <&xbar_amx3_in2>;
661							};
662						};
663
664						port@2 {
665							reg = <2>;
666
667							amx3_in3: endpoint {
668								remote-endpoint = <&xbar_amx3_in3>;
669							};
670						};
671
672						port@3 {
673							reg = <3>;
674
675							amx3_in4: endpoint {
676								remote-endpoint = <&xbar_amx3_in4>;
677							};
678						};
679
680						amx3_out_port: port@4 {
681							reg = <4>;
682
683							amx3_out: endpoint {
684								remote-endpoint = <&xbar_amx3_out>;
685							};
686						};
687					};
688				};
689
690				tegra_amx4: amx@9540000 {
691					compatible = "nvidia,tegra264-amx";
692					reg = <0x0 0x9540000 0x0 0x10000>;
693					sound-name-prefix = "AMX4";
694
695					ports {
696						#address-cells = <1>;
697						#size-cells = <0>;
698
699						port@0 {
700							reg = <0>;
701
702							amx4_in1: endpoint {
703								remote-endpoint = <&xbar_amx4_in1>;
704							};
705						};
706
707						port@1 {
708							reg = <1>;
709
710							amx4_in2: endpoint {
711								remote-endpoint = <&xbar_amx4_in2>;
712							};
713						};
714
715						port@2 {
716							reg = <2>;
717
718							amx4_in3: endpoint {
719								remote-endpoint = <&xbar_amx4_in3>;
720							};
721						};
722
723						port@3 {
724							reg = <3>;
725
726							amx4_in4: endpoint {
727								remote-endpoint = <&xbar_amx4_in4>;
728							};
729						};
730
731						amx4_out_port: port@4 {
732							reg = <4>;
733
734							amx4_out: endpoint {
735								remote-endpoint = <&xbar_amx4_out>;
736							};
737						};
738					};
739				};
740
741				tegra_amx5: amx@9550000 {
742					compatible = "nvidia,tegra264-amx";
743					reg = <0x0 0x9550000 0x0 0x10000>;
744					sound-name-prefix = "AMX5";
745
746					ports {
747						#address-cells = <1>;
748						#size-cells = <0>;
749
750						port@0 {
751							reg = <0>;
752
753							amx5_in1: endpoint {
754								remote-endpoint = <&xbar_amx5_in1>;
755							};
756						};
757
758						port@1 {
759							reg = <1>;
760
761							amx5_in2: endpoint {
762								remote-endpoint = <&xbar_amx5_in2>;
763							};
764						};
765
766						port@2 {
767							reg = <2>;
768
769							amx5_in3: endpoint {
770								remote-endpoint = <&xbar_amx5_in3>;
771							};
772						};
773
774						port@3 {
775							reg = <3>;
776
777							amx5_in4: endpoint {
778								remote-endpoint = <&xbar_amx5_in4>;
779							};
780						};
781
782						amx5_out_port: port@4 {
783							reg = <4>;
784
785							amx5_out: endpoint {
786								remote-endpoint = <&xbar_amx5_out>;
787							};
788						};
789					};
790				};
791
792				tegra_amx6: amx@9560000 {
793					compatible = "nvidia,tegra264-amx";
794					reg = <0x0 0x9560000 0x0 0x10000>;
795					sound-name-prefix = "AMX6";
796
797					ports {
798						#address-cells = <1>;
799						#size-cells = <0>;
800
801						port@0 {
802							reg = <0>;
803
804							amx6_in1: endpoint {
805								remote-endpoint = <&xbar_amx6_in1>;
806							};
807						};
808
809						port@1 {
810							reg = <1>;
811
812							amx6_in2: endpoint {
813								remote-endpoint = <&xbar_amx6_in2>;
814							};
815						};
816
817						port@2 {
818							reg = <2>;
819
820							amx6_in3: endpoint {
821								remote-endpoint = <&xbar_amx6_in3>;
822							};
823						};
824
825						port@3 {
826							reg = <3>;
827
828							amx6_in4: endpoint {
829								remote-endpoint = <&xbar_amx6_in4>;
830							};
831						};
832
833						amx6_out_port: port@4 {
834							reg = <4>;
835
836							amx6_out: endpoint {
837								remote-endpoint = <&xbar_amx6_out>;
838							};
839						};
840					};
841				};
842
843				tegra_adx1: adx@9590000 {
844					compatible = "nvidia,tegra264-adx";
845					reg = <0x0 0x9590000 0x0 0x10000>;
846					sound-name-prefix = "ADX1";
847
848					ports {
849						#address-cells = <1>;
850						#size-cells = <0>;
851
852						port@0 {
853							reg = <0>;
854
855							adx1_in: endpoint {
856								remote-endpoint = <&xbar_adx1_in>;
857							};
858						};
859
860						adx1_out1_port: port@1 {
861							reg = <1>;
862
863							adx1_out1: endpoint {
864								remote-endpoint = <&xbar_adx1_out1>;
865							};
866						};
867
868						adx1_out2_port: port@2 {
869							reg = <2>;
870
871							adx1_out2: endpoint {
872								remote-endpoint = <&xbar_adx1_out2>;
873							};
874						};
875
876						adx1_out3_port: port@3 {
877							reg = <3>;
878
879							adx1_out3: endpoint {
880								remote-endpoint = <&xbar_adx1_out3>;
881							};
882						};
883
884						adx1_out4_port: port@4 {
885							reg = <4>;
886
887							adx1_out4: endpoint {
888								remote-endpoint = <&xbar_adx1_out4>;
889							};
890						};
891					};
892				};
893
894				tegra_adx2: adx@95a0000 {
895					compatible = "nvidia,tegra264-adx";
896					reg = <0x0 0x95a0000 0x0 0x10000>;
897					sound-name-prefix = "ADX2";
898
899					ports {
900						#address-cells = <1>;
901						#size-cells = <0>;
902
903						port@0 {
904							reg = <0>;
905
906							adx2_in: endpoint {
907								remote-endpoint = <&xbar_adx2_in>;
908							};
909						};
910
911						adx2_out1_port: port@1 {
912							reg = <1>;
913
914							adx2_out1: endpoint {
915								remote-endpoint = <&xbar_adx2_out1>;
916							};
917						};
918
919						adx2_out2_port: port@2 {
920							reg = <2>;
921
922							adx2_out2: endpoint {
923								remote-endpoint = <&xbar_adx2_out2>;
924							};
925						};
926
927						adx2_out3_port: port@3 {
928							reg = <3>;
929
930							adx2_out3: endpoint {
931								remote-endpoint = <&xbar_adx2_out3>;
932							};
933						};
934
935						adx2_out4_port: port@4 {
936							reg = <4>;
937
938							adx2_out4: endpoint {
939								remote-endpoint = <&xbar_adx2_out4>;
940							};
941						};
942					};
943				};
944
945				tegra_adx3: adx@95b0000 {
946					compatible = "nvidia,tegra264-adx";
947					reg = <0x0 0x95b0000 0x0 0x10000>;
948					sound-name-prefix = "ADX3";
949
950					ports {
951						#address-cells = <1>;
952						#size-cells = <0>;
953
954						port@0 {
955							reg = <0>;
956
957							adx3_in: endpoint {
958								remote-endpoint = <&xbar_adx3_in>;
959							};
960						};
961
962						adx3_out1_port: port@1 {
963							reg = <1>;
964
965							adx3_out1: endpoint {
966								remote-endpoint = <&xbar_adx3_out1>;
967							};
968						};
969
970						adx3_out2_port: port@2 {
971							reg = <2>;
972
973							adx3_out2: endpoint {
974								remote-endpoint = <&xbar_adx3_out2>;
975							};
976						};
977
978						adx3_out3_port: port@3 {
979							reg = <3>;
980
981							adx3_out3: endpoint {
982								remote-endpoint = <&xbar_adx3_out3>;
983							};
984						};
985
986						adx3_out4_port: port@4 {
987							reg = <4>;
988
989							adx3_out4: endpoint {
990								remote-endpoint = <&xbar_adx3_out4>;
991							};
992						};
993					};
994				};
995
996				tegra_adx4: adx@95c0000 {
997					compatible = "nvidia,tegra264-adx";
998					reg = <0x0 0x95c0000 0x0 0x10000>;
999					sound-name-prefix = "ADX4";
1000
1001					ports {
1002						#address-cells = <1>;
1003						#size-cells = <0>;
1004
1005						port@0 {
1006							reg = <0>;
1007
1008							adx4_in: endpoint {
1009								remote-endpoint = <&xbar_adx4_in>;
1010							};
1011						};
1012
1013						adx4_out1_port: port@1 {
1014							reg = <1>;
1015
1016							adx4_out1: endpoint {
1017								remote-endpoint = <&xbar_adx4_out1>;
1018							};
1019						};
1020
1021						adx4_out2_port: port@2 {
1022							reg = <2>;
1023
1024							adx4_out2: endpoint {
1025								remote-endpoint = <&xbar_adx4_out2>;
1026							};
1027						};
1028
1029						adx4_out3_port: port@3 {
1030							reg = <3>;
1031
1032							adx4_out3: endpoint {
1033								remote-endpoint = <&xbar_adx4_out3>;
1034							};
1035						};
1036
1037						adx4_out4_port: port@4 {
1038							reg = <4>;
1039
1040							adx4_out4: endpoint {
1041								remote-endpoint = <&xbar_adx4_out4>;
1042							};
1043						};
1044					};
1045				};
1046
1047				tegra_adx5: adx@95d0000 {
1048					compatible = "nvidia,tegra264-adx";
1049					reg = <0x0 0x95d0000 0x0 0x10000>;
1050					sound-name-prefix = "ADX5";
1051
1052					ports {
1053						#address-cells = <1>;
1054						#size-cells = <0>;
1055
1056						port@0 {
1057							reg = <0>;
1058
1059							adx5_in: endpoint {
1060								remote-endpoint = <&xbar_adx5_in>;
1061							};
1062						};
1063
1064						adx5_out1_port: port@1 {
1065							reg = <1>;
1066
1067							adx5_out1: endpoint {
1068								remote-endpoint = <&xbar_adx5_out1>;
1069							};
1070						};
1071
1072						adx5_out2_port: port@2 {
1073							reg = <2>;
1074
1075							adx5_out2: endpoint {
1076								remote-endpoint = <&xbar_adx5_out2>;
1077							};
1078						};
1079
1080						adx5_out3_port: port@3 {
1081							reg = <3>;
1082
1083							adx5_out3: endpoint {
1084								remote-endpoint = <&xbar_adx5_out3>;
1085							};
1086						};
1087
1088						adx5_out4_port: port@4 {
1089							reg = <4>;
1090
1091							adx5_out4: endpoint {
1092								remote-endpoint = <&xbar_adx5_out4>;
1093							};
1094						};
1095					};
1096				};
1097
1098				tegra_adx6: adx@95e0000 {
1099					compatible = "nvidia,tegra264-adx";
1100					reg = <0x0 0x95e0000 0x0 0x10000>;
1101					sound-name-prefix = "ADX6";
1102
1103					ports {
1104						#address-cells = <1>;
1105						#size-cells = <0>;
1106
1107						port@0 {
1108							reg = <0>;
1109
1110							adx6_in: endpoint {
1111								remote-endpoint = <&xbar_adx6_in>;
1112							};
1113						};
1114
1115						adx6_out1_port: port@1 {
1116							reg = <1>;
1117
1118							adx6_out1: endpoint {
1119								remote-endpoint = <&xbar_adx6_out1>;
1120							};
1121						};
1122
1123						adx6_out2_port: port@2 {
1124							reg = <2>;
1125
1126							adx6_out2: endpoint {
1127								remote-endpoint = <&xbar_adx6_out2>;
1128							};
1129						};
1130
1131						adx6_out3_port: port@3 {
1132							reg = <3>;
1133
1134							adx6_out3: endpoint {
1135								remote-endpoint = <&xbar_adx6_out3>;
1136							};
1137						};
1138
1139						adx6_out4_port: port@4 {
1140							reg = <4>;
1141
1142							adx6_out4: endpoint {
1143								remote-endpoint = <&xbar_adx6_out4>;
1144							};
1145						};
1146					};
1147				};
1148
1149				tegra_admaif: admaif@9610000 {
1150					compatible = "nvidia,tegra264-admaif";
1151					reg = <0x0 0x9610000 0x0 0x10000>;
1152					dmas = <&adma 1>, <&adma 1>,
1153					     <&adma 2>, <&adma 2>,
1154					     <&adma 3>, <&adma 3>,
1155					     <&adma 4>, <&adma 4>,
1156					     <&adma 5>, <&adma 5>,
1157					     <&adma 6>, <&adma 6>,
1158					     <&adma 7>, <&adma 7>,
1159					     <&adma 8>, <&adma 8>,
1160					     <&adma 9>, <&adma 9>,
1161					     <&adma 10>, <&adma 10>,
1162					     <&adma 11>, <&adma 11>,
1163					     <&adma 12>, <&adma 12>,
1164					     <&adma 13>, <&adma 13>,
1165					     <&adma 14>, <&adma 14>,
1166					     <&adma 15>, <&adma 15>,
1167					     <&adma 16>, <&adma 16>,
1168					     <&adma 17>, <&adma 17>,
1169					     <&adma 18>, <&adma 18>,
1170					     <&adma 19>, <&adma 19>,
1171					     <&adma 20>, <&adma 20>,
1172					     <&adma 21>, <&adma 21>,
1173					     <&adma 22>, <&adma 22>,
1174					     <&adma 23>, <&adma 23>,
1175					     <&adma 24>, <&adma 24>,
1176					     <&adma 25>, <&adma 25>,
1177					     <&adma 26>, <&adma 26>,
1178					     <&adma 27>, <&adma 27>,
1179					     <&adma 28>, <&adma 28>,
1180					     <&adma 29>, <&adma 29>,
1181					     <&adma 30>, <&adma 30>,
1182					     <&adma 31>, <&adma 31>,
1183					     <&adma 32>, <&adma 32>;
1184					dma-names = "rx1", "tx1",
1185						"rx2", "tx2",
1186						"rx3", "tx3",
1187						"rx4", "tx4",
1188						"rx5", "tx5",
1189						"rx6", "tx6",
1190						"rx7", "tx7",
1191						"rx8", "tx8",
1192						"rx9", "tx9",
1193						"rx10", "tx10",
1194						"rx11", "tx11",
1195						"rx12", "tx12",
1196						"rx13", "tx13",
1197						"rx14", "tx14",
1198						"rx15", "tx15",
1199						"rx16", "tx16",
1200						"rx17", "tx17",
1201						"rx18", "tx18",
1202						"rx19", "tx19",
1203						"rx20", "tx20",
1204						"rx21", "tx21",
1205						"rx22", "tx22",
1206						"rx23", "tx23",
1207						"rx24", "tx24",
1208						"rx25", "tx25",
1209						"rx26", "tx26",
1210						"rx27", "tx27",
1211						"rx28", "tx28",
1212						"rx29", "tx29",
1213						"rx30", "tx30",
1214						"rx31", "tx31",
1215						"rx32", "tx32";
1216
1217					 interconnects =
1218						<&mc TEGRA264_MEMORY_CLIENT_APEDMAR &emc>,
1219						<&mc TEGRA264_MEMORY_CLIENT_APEDMAW &emc>;
1220						interconnect-names = "dma-mem", "write";
1221
1222					iommus = <&smmu1 TEGRA264_SID_APE>;
1223
1224					ports {
1225						#address-cells = <1>;
1226						#size-cells = <0>;
1227
1228						admaif0_port: port@0 {
1229							reg = <0x0>;
1230
1231							admaif0: endpoint {
1232								remote-endpoint = <&xbar_admaif0>;
1233							};
1234						};
1235
1236						admaif1_port: port@1 {
1237							reg = <0x1>;
1238
1239							admaif1: endpoint {
1240								remote-endpoint = <&xbar_admaif1>;
1241							};
1242						};
1243
1244						admaif2_port: port@2 {
1245							reg = <0x2>;
1246
1247							admaif2: endpoint {
1248								remote-endpoint = <&xbar_admaif2>;
1249							};
1250						};
1251
1252						admaif3_port: port@3 {
1253							reg = <0x3>;
1254
1255							admaif3: endpoint {
1256								remote-endpoint = <&xbar_admaif3>;
1257							};
1258						};
1259
1260						admaif4_port: port@4 {
1261							reg = <0x4>;
1262
1263							admaif4: endpoint {
1264								remote-endpoint = <&xbar_admaif4>;
1265							};
1266						};
1267
1268						admaif5_port: port@5 {
1269							reg = <0x5>;
1270
1271							admaif5: endpoint {
1272								remote-endpoint = <&xbar_admaif5>;
1273							};
1274						};
1275
1276						admaif6_port: port@6 {
1277							reg = <0x6>;
1278
1279							admaif6: endpoint {
1280								remote-endpoint = <&xbar_admaif6>;
1281							};
1282						};
1283
1284						admaif7_port: port@7 {
1285							reg = <0x7>;
1286
1287							admaif7: endpoint {
1288								remote-endpoint = <&xbar_admaif7>;
1289							};
1290						};
1291
1292						admaif8_port: port@8 {
1293							reg = <0x8>;
1294
1295							admaif8: endpoint {
1296								remote-endpoint = <&xbar_admaif8>;
1297							};
1298						};
1299
1300						admaif9_port: port@9 {
1301							reg = <0x9>;
1302
1303							admaif9: endpoint {
1304								remote-endpoint = <&xbar_admaif9>;
1305							};
1306						};
1307
1308						admaif10_port: port@a {
1309							reg = <0xa>;
1310
1311							admaif10: endpoint {
1312								remote-endpoint = <&xbar_admaif10>;
1313							};
1314						};
1315
1316						admaif11_port: port@b {
1317							reg = <0xb>;
1318
1319							admaif11: endpoint {
1320								remote-endpoint = <&xbar_admaif11>;
1321							};
1322						};
1323
1324						admaif12_port: port@c {
1325							reg = <0xc>;
1326
1327							admaif12: endpoint {
1328								remote-endpoint = <&xbar_admaif12>;
1329							};
1330						};
1331
1332						admaif13_port: port@d {
1333							reg = <0xd>;
1334
1335							admaif13: endpoint {
1336								remote-endpoint = <&xbar_admaif13>;
1337							};
1338						};
1339
1340						admaif14_port: port@e {
1341							reg = <0xe>;
1342
1343							admaif14: endpoint {
1344								remote-endpoint = <&xbar_admaif14>;
1345							};
1346						};
1347
1348						admaif15_port: port@f {
1349							reg = <0xf>;
1350
1351							admaif15: endpoint {
1352								remote-endpoint = <&xbar_admaif15>;
1353							};
1354						};
1355
1356						admaif16_port: port@10 {
1357							reg = <0x10>;
1358
1359							admaif16: endpoint {
1360								remote-endpoint = <&xbar_admaif16>;
1361							};
1362						};
1363
1364						admaif17_port: port@11 {
1365							reg = <0x11>;
1366
1367							admaif17: endpoint {
1368								remote-endpoint = <&xbar_admaif17>;
1369							};
1370						};
1371
1372						admaif18_port: port@12 {
1373							reg = <0x12>;
1374
1375							admaif18: endpoint {
1376								remote-endpoint = <&xbar_admaif18>;
1377							};
1378						};
1379
1380						admaif19_port: port@13 {
1381							reg = <0x13>;
1382
1383							admaif19: endpoint {
1384								remote-endpoint = <&xbar_admaif19>;
1385							};
1386						};
1387
1388						admaif20_port: port@14 {
1389							reg = <0x14>;
1390
1391							admaif20: endpoint {
1392								remote-endpoint = <&xbar_admaif20>;
1393							};
1394						};
1395
1396						admaif21_port: port@15 {
1397							reg = <0x15>;
1398
1399							admaif21: endpoint {
1400								remote-endpoint = <&xbar_admaif21>;
1401							};
1402						};
1403
1404						admaif22_port: port@16 {
1405							reg = <0x16>;
1406
1407							admaif22: endpoint {
1408								remote-endpoint = <&xbar_admaif22>;
1409							};
1410						};
1411
1412						admaif23_port: port@17 {
1413							reg = <0x17>;
1414
1415							admaif23: endpoint {
1416								remote-endpoint = <&xbar_admaif23>;
1417							};
1418						};
1419
1420						admaif24_port: port@18 {
1421							reg = <0x18>;
1422
1423							admaif24: endpoint {
1424								remote-endpoint = <&xbar_admaif24>;
1425							};
1426						};
1427
1428						admaif25_port: port@19 {
1429							reg = <0x19>;
1430
1431							admaif25: endpoint {
1432								remote-endpoint = <&xbar_admaif25>;
1433							};
1434						};
1435
1436						admaif26_port: port@1a {
1437							reg = <0x1a>;
1438
1439							admaif26: endpoint {
1440								remote-endpoint = <&xbar_admaif26>;
1441							};
1442						};
1443
1444						admaif27_port: port@1b {
1445							reg = <0x1b>;
1446
1447							admaif27: endpoint {
1448								remote-endpoint = <&xbar_admaif27>;
1449							};
1450						};
1451
1452						admaif28_port: port@1c {
1453							reg = <0x1c>;
1454
1455							admaif28: endpoint {
1456								remote-endpoint = <&xbar_admaif28>;
1457							};
1458						};
1459
1460						admaif29_port: port@1d {
1461							reg = <0x1d>;
1462
1463							admaif29: endpoint {
1464								remote-endpoint = <&xbar_admaif29>;
1465							};
1466						};
1467
1468						admaif30_port: port@1e {
1469							reg = <0x1e>;
1470
1471							admaif30: endpoint {
1472								remote-endpoint = <&xbar_admaif30>;
1473							};
1474						};
1475
1476						admaif31_port: port@1f {
1477							reg = <0x1f>;
1478
1479							admaif31: endpoint {
1480								remote-endpoint = <&xbar_admaif31>;
1481							};
1482						};
1483					};
1484				};
1485
1486				tegra_sfc1: sfc@9700000 {
1487					compatible = "nvidia,tegra264-sfc",
1488							"nvidia,tegra210-sfc";
1489					reg = <0x0 0x9700000 0x0 0x10000>;
1490					sound-name-prefix = "SFC1";
1491
1492					ports {
1493						#address-cells = <1>;
1494						#size-cells = <0>;
1495
1496						port@0 {
1497							reg = <0>;
1498
1499							sfc1_cif_in: endpoint {
1500								remote-endpoint = <&xbar_sfc1_in>;
1501							};
1502						};
1503
1504						sfc1_out_port: port@1 {
1505							reg = <1>;
1506
1507							sfc1_cif_out: endpoint {
1508								remote-endpoint = <&xbar_sfc1_out>;
1509							};
1510						};
1511					};
1512				};
1513
1514				tegra_sfc2: sfc@9710000 {
1515					compatible = "nvidia,tegra264-sfc",
1516							"nvidia,tegra210-sfc";
1517					reg = <0x0 0x9710000 0x0 0x10000>;
1518					sound-name-prefix = "SFC2";
1519
1520					ports {
1521						#address-cells = <1>;
1522						#size-cells = <0>;
1523
1524						port@0 {
1525							reg = <0>;
1526
1527							sfc2_cif_in: endpoint {
1528								remote-endpoint = <&xbar_sfc2_in>;
1529							};
1530						};
1531
1532						sfc2_out_port: port@1 {
1533							reg = <1>;
1534
1535							sfc2_cif_out: endpoint {
1536								remote-endpoint = <&xbar_sfc2_out>;
1537							};
1538						};
1539					};
1540				};
1541
1542				tegra_sfc3: sfc@9720000 {
1543					compatible = "nvidia,tegra264-sfc",
1544							"nvidia,tegra210-sfc";
1545					reg = <0x0 0x9720000 0x0 0x10000>;
1546					sound-name-prefix = "SFC3";
1547
1548					ports {
1549						#address-cells = <1>;
1550						#size-cells = <0>;
1551
1552						port@0 {
1553							reg = <0>;
1554
1555							sfc3_cif_in: endpoint {
1556								remote-endpoint = <&xbar_sfc3_in>;
1557							};
1558						};
1559
1560						sfc3_out_port: port@1 {
1561							reg = <1>;
1562
1563							sfc3_cif_out: endpoint {
1564								remote-endpoint = <&xbar_sfc3_out>;
1565							};
1566						};
1567					};
1568				};
1569
1570				tegra_sfc4: sfc@9730000 {
1571					compatible = "nvidia,tegra264-sfc",
1572							"nvidia,tegra210-sfc";
1573					reg = <0x0 0x9730000 0x0 0x10000>;
1574					sound-name-prefix = "SFC4";
1575
1576					ports {
1577						#address-cells = <1>;
1578						#size-cells = <0>;
1579
1580						port@0 {
1581							reg = <0>;
1582
1583							sfc4_cif_in: endpoint {
1584								remote-endpoint = <&xbar_sfc4_in>;
1585							};
1586						};
1587
1588						sfc4_out_port: port@1 {
1589							reg = <1>;
1590
1591							sfc4_cif_out: endpoint {
1592								remote-endpoint = <&xbar_sfc4_out>;
1593							};
1594						};
1595					};
1596				};
1597
1598				tegra_ope1: processing-engine@9780000 {
1599					compatible = "nvidia,tegra264-ope",
1600							"nvidia,tegra210-ope";
1601					reg = <0x0 0x9780000 0x0 0x10000>;
1602					#address-cells = <2>;
1603					#size-cells = <2>;
1604					ranges = <0x0 0x9780000 0x0 0x9780000 0x0 0x30000>;
1605					sound-name-prefix = "OPE1";
1606
1607					equalizer@9790000 {
1608						compatible = "nvidia,tegra264-peq",
1609								"nvidia,tegra210-peq";
1610						reg = <0x0 0x9790000 0x0 0x10000>;
1611					};
1612
1613					dynamic-range-compressor@97a0000 {
1614						compatible = "nvidia,tegra264-mbdrc",
1615								"nvidia,tegra210-mbdrc";
1616						reg = <0x0 0x97a0000 0x0 0x10000>;
1617					};
1618
1619					ports {
1620						#address-cells = <1>;
1621						#size-cells = <0>;
1622
1623						port@0 {
1624							reg = <0x0>;
1625
1626							ope1_cif_in_ep: endpoint {
1627								remote-endpoint =
1628									<&xbar_ope1_in_ep>;
1629							};
1630						};
1631
1632						ope1_out_port: port@1 {
1633							reg = <0x1>;
1634
1635							ope1_cif_out_ep: endpoint {
1636								remote-endpoint =
1637									<&xbar_ope1_out_ep>;
1638							};
1639						};
1640					};
1641				};
1642
1643				tegra_mvc1: mvc@9800000 {
1644					compatible = "nvidia,tegra264-mvc",
1645							"nvidia,tegra210-mvc";
1646					reg = <0x0 0x9800000 0x0 0x10000>;
1647					sound-name-prefix = "MVC1";
1648
1649					ports {
1650						#address-cells = <1>;
1651						#size-cells = <0>;
1652
1653						port@0 {
1654							reg = <0>;
1655
1656							mvc1_cif_in: endpoint {
1657								remote-endpoint = <&xbar_mvc1_in>;
1658							};
1659						};
1660
1661						mvc1_out_port: port@1 {
1662							reg = <1>;
1663
1664							mvc1_cif_out: endpoint {
1665								remote-endpoint = <&xbar_mvc1_out>;
1666							};
1667						};
1668					};
1669				};
1670
1671				tegra_mvc2: mvc@9810000 {
1672					compatible = "nvidia,tegra264-mvc",
1673							"nvidia,tegra210-mvc";
1674					reg = <0x0 0x9810000 0x0 0x10000>;
1675					sound-name-prefix = "MVC2";
1676
1677					ports {
1678						#address-cells = <1>;
1679						#size-cells = <0>;
1680
1681						port@0 {
1682							reg = <0>;
1683
1684							mvc2_cif_in: endpoint {
1685								remote-endpoint = <&xbar_mvc2_in>;
1686							};
1687						};
1688
1689						mvc2_out_port: port@1 {
1690							reg = <1>;
1691
1692							mvc2_cif_out: endpoint {
1693								remote-endpoint = <&xbar_mvc2_out>;
1694							};
1695						};
1696					};
1697				};
1698
1699				tegra_amixer: amixer@9820000 {
1700					compatible = "nvidia,tegra264-amixer",
1701							"nvidia,tegra210-amixer";
1702					reg = <0x0 0x9820000 0x0 0x10000>;
1703					sound-name-prefix = "MIXER1";
1704
1705					ports {
1706						#address-cells = <1>;
1707						#size-cells = <0>;
1708
1709						port@0 {
1710							reg = <0x0>;
1711
1712							mix_in1: endpoint {
1713								remote-endpoint = <&xbar_mix_in1>;
1714							};
1715						};
1716
1717						port@1 {
1718							reg = <0x1>;
1719
1720							mix_in2: endpoint {
1721								remote-endpoint = <&xbar_mix_in2>;
1722							};
1723						};
1724
1725						port@2 {
1726							reg = <0x2>;
1727
1728							mix_in3: endpoint {
1729								remote-endpoint = <&xbar_mix_in3>;
1730							};
1731						};
1732
1733						port@3 {
1734							reg = <0x3>;
1735
1736							mix_in4: endpoint {
1737								remote-endpoint = <&xbar_mix_in4>;
1738							};
1739						};
1740
1741						port@4 {
1742							reg = <0x4>;
1743
1744							mix_in5: endpoint {
1745								remote-endpoint = <&xbar_mix_in5>;
1746							};
1747						};
1748
1749						port@5 {
1750							reg = <0x5>;
1751
1752							mix_in6: endpoint {
1753								remote-endpoint = <&xbar_mix_in6>;
1754							};
1755						};
1756
1757						port@6 {
1758							reg = <0x6>;
1759
1760							mix_in7: endpoint {
1761								remote-endpoint = <&xbar_mix_in7>;
1762							};
1763						};
1764
1765						port@7 {
1766							reg = <0x7>;
1767
1768							mix_in8: endpoint {
1769								remote-endpoint = <&xbar_mix_in8>;
1770							};
1771						};
1772
1773						port@8 {
1774							reg = <0x8>;
1775
1776							mix_in9: endpoint {
1777								remote-endpoint = <&xbar_mix_in9>;
1778							};
1779						};
1780
1781						port@9 {
1782							reg = <0x9>;
1783
1784							mix_in10: endpoint {
1785								remote-endpoint = <&xbar_mix_in10>;
1786							};
1787						};
1788
1789						mix_out1_port: port@a {
1790							reg = <0xa>;
1791
1792							mix_out1: endpoint {
1793								remote-endpoint = <&xbar_mix_out1>;
1794							};
1795						};
1796
1797						mix_out2_port: port@b {
1798							reg = <0xb>;
1799
1800							mix_out2: endpoint {
1801								remote-endpoint = <&xbar_mix_out2>;
1802							};
1803						};
1804
1805						mix_out3_port: port@c {
1806							reg = <0xc>;
1807
1808							mix_out3: endpoint {
1809								remote-endpoint = <&xbar_mix_out3>;
1810							};
1811						};
1812
1813						mix_out4_port: port@d {
1814							reg = <0xd>;
1815
1816							mix_out4: endpoint {
1817								remote-endpoint = <&xbar_mix_out4>;
1818							};
1819						};
1820
1821						mix_out5_port: port@e {
1822							reg = <0xe>;
1823
1824							mix_out5: endpoint {
1825								remote-endpoint = <&xbar_mix_out5>;
1826							};
1827						};
1828					};
1829				};
1830
1831				tegra_asrc: asrc@9850000 {
1832					compatible = "nvidia,tegra264-asrc";
1833					reg = <0x0 0x9850000 0x0 0x10000>;
1834					sound-name-prefix = "ASRC1";
1835
1836					ports {
1837						#address-cells = <1>;
1838						#size-cells = <0>;
1839
1840						port@0 {
1841							reg = <0x0>;
1842
1843							asrc_in1_ep: endpoint {
1844								remote-endpoint =
1845									<&xbar_asrc_in1_ep>;
1846							};
1847						};
1848
1849						port@1 {
1850							reg = <0x1>;
1851
1852							asrc_in2_ep: endpoint {
1853								remote-endpoint =
1854									<&xbar_asrc_in2_ep>;
1855							};
1856						};
1857
1858						port@2 {
1859							reg = <0x2>;
1860
1861							asrc_in3_ep: endpoint {
1862								remote-endpoint =
1863									<&xbar_asrc_in3_ep>;
1864							};
1865						};
1866
1867						port@3 {
1868							reg = <0x3>;
1869
1870							asrc_in4_ep: endpoint {
1871								remote-endpoint =
1872									<&xbar_asrc_in4_ep>;
1873							};
1874						};
1875
1876						port@4 {
1877							reg = <0x4>;
1878
1879							asrc_in5_ep: endpoint {
1880								remote-endpoint =
1881									<&xbar_asrc_in5_ep>;
1882							};
1883						};
1884
1885						port@5 {
1886							reg = <0x5>;
1887
1888							asrc_in6_ep: endpoint {
1889								remote-endpoint =
1890									<&xbar_asrc_in6_ep>;
1891							};
1892						};
1893
1894						port@6 {
1895							reg = <0x6>;
1896
1897							asrc_in7_ep: endpoint {
1898								remote-endpoint =
1899									<&xbar_asrc_in7_ep>;
1900							};
1901						};
1902
1903						asrc_out1_port: port@7 {
1904							reg = <0x7>;
1905
1906							asrc_out1_ep: endpoint {
1907								remote-endpoint =
1908									<&xbar_asrc_out1_ep>;
1909							};
1910						};
1911
1912						asrc_out2_port: port@8 {
1913							reg = <0x8>;
1914
1915							asrc_out2_ep: endpoint {
1916								remote-endpoint =
1917									<&xbar_asrc_out2_ep>;
1918							};
1919						};
1920
1921						asrc_out3_port: port@9 {
1922							reg = <0x9>;
1923
1924							asrc_out3_ep: endpoint {
1925								remote-endpoint =
1926									<&xbar_asrc_out3_ep>;
1927							};
1928						};
1929
1930						asrc_out4_port: port@a {
1931							reg = <0xa>;
1932
1933							asrc_out4_ep: endpoint {
1934								remote-endpoint =
1935									<&xbar_asrc_out4_ep>;
1936							};
1937						};
1938
1939						asrc_out5_port: port@b {
1940							reg = <0xb>;
1941
1942							asrc_out5_ep: endpoint {
1943								remote-endpoint =
1944									<&xbar_asrc_out5_ep>;
1945							};
1946						};
1947
1948						asrc_out6_port:	port@c {
1949							reg = <0xc>;
1950
1951							asrc_out6_ep: endpoint {
1952								remote-endpoint =
1953									<&xbar_asrc_out6_ep>;
1954							};
1955						};
1956					};
1957				};
1958
1959				ports {
1960					#address-cells = <1>;
1961					#size-cells = <0>;
1962
1963					port@0 {
1964						reg = <0x0>;
1965
1966						xbar_admaif0: endpoint {
1967							remote-endpoint = <&admaif0>;
1968						};
1969					};
1970
1971					port@1 {
1972						reg = <0x1>;
1973
1974						xbar_admaif1: endpoint {
1975							remote-endpoint = <&admaif1>;
1976						};
1977					};
1978
1979					port@2 {
1980						reg = <0x2>;
1981
1982						xbar_admaif2: endpoint {
1983							remote-endpoint = <&admaif2>;
1984						};
1985					};
1986
1987					port@3 {
1988						reg = <0x3>;
1989
1990						xbar_admaif3: endpoint {
1991							remote-endpoint = <&admaif3>;
1992						};
1993					};
1994
1995					port@4 {
1996						reg = <0x4>;
1997
1998						xbar_admaif4: endpoint {
1999							remote-endpoint = <&admaif4>;
2000						};
2001					};
2002
2003					port@5 {
2004						reg = <0x5>;
2005
2006						xbar_admaif5: endpoint {
2007							remote-endpoint = <&admaif5>;
2008						};
2009					};
2010
2011					port@6 {
2012						reg = <0x6>;
2013
2014						xbar_admaif6: endpoint {
2015							remote-endpoint = <&admaif6>;
2016						};
2017					};
2018
2019					port@7 {
2020						reg = <0x7>;
2021
2022						xbar_admaif7: endpoint {
2023							remote-endpoint = <&admaif7>;
2024						};
2025					};
2026
2027					port@8 {
2028						reg = <0x8>;
2029
2030						xbar_admaif8: endpoint {
2031							remote-endpoint = <&admaif8>;
2032						};
2033					};
2034
2035					port@9 {
2036						reg = <0x9>;
2037
2038						xbar_admaif9: endpoint {
2039							remote-endpoint = <&admaif9>;
2040						};
2041					};
2042
2043					port@a {
2044						reg = <0xa>;
2045
2046						xbar_admaif10: endpoint {
2047							remote-endpoint = <&admaif10>;
2048						};
2049					};
2050
2051					port@b {
2052						reg = <0xb>;
2053
2054						xbar_admaif11: endpoint {
2055							remote-endpoint = <&admaif11>;
2056						};
2057					};
2058
2059					port@c {
2060						reg = <0xc>;
2061
2062						xbar_admaif12: endpoint {
2063							remote-endpoint = <&admaif12>;
2064						};
2065					};
2066
2067					port@d {
2068						reg = <0xd>;
2069
2070						xbar_admaif13: endpoint {
2071							remote-endpoint = <&admaif13>;
2072						};
2073					};
2074
2075					port@e {
2076						reg = <0xe>;
2077
2078						xbar_admaif14: endpoint {
2079							remote-endpoint = <&admaif14>;
2080						};
2081					};
2082
2083					port@f {
2084						reg = <0xf>;
2085
2086						xbar_admaif15: endpoint {
2087							remote-endpoint = <&admaif15>;
2088						};
2089					};
2090
2091					port@10 {
2092						reg = <0x10>;
2093
2094						xbar_admaif16: endpoint {
2095							remote-endpoint = <&admaif16>;
2096						};
2097					};
2098
2099					port@11 {
2100						reg = <0x11>;
2101
2102						xbar_admaif17: endpoint {
2103							remote-endpoint = <&admaif17>;
2104						};
2105					};
2106
2107					port@12 {
2108						reg = <0x12>;
2109
2110						xbar_admaif18: endpoint {
2111							remote-endpoint = <&admaif18>;
2112						};
2113					};
2114
2115					port@13 {
2116						reg = <0x13>;
2117
2118						xbar_admaif19: endpoint {
2119							remote-endpoint = <&admaif19>;
2120						};
2121					};
2122
2123					port@14 {
2124						reg = <0x14>;
2125
2126						xbar_admaif20: endpoint {
2127							remote-endpoint = <&admaif20>;
2128						};
2129					};
2130
2131					port@15 {
2132						reg = <0x15>;
2133
2134						xbar_admaif21: endpoint {
2135							remote-endpoint = <&admaif21>;
2136						};
2137					};
2138
2139					port@16 {
2140						reg = <0x16>;
2141
2142						xbar_admaif22: endpoint {
2143							remote-endpoint = <&admaif22>;
2144						};
2145					};
2146
2147					port@17 {
2148						reg = <0x17>;
2149
2150						xbar_admaif23: endpoint {
2151							remote-endpoint = <&admaif23>;
2152						};
2153					};
2154
2155					port@18 {
2156						reg = <0x18>;
2157
2158						xbar_admaif24: endpoint {
2159							remote-endpoint = <&admaif24>;
2160						};
2161					};
2162
2163					port@19 {
2164						reg = <0x19>;
2165
2166						xbar_admaif25: endpoint {
2167							remote-endpoint = <&admaif25>;
2168						};
2169					};
2170
2171					port@1a {
2172						reg = <0x1a>;
2173
2174						xbar_admaif26: endpoint {
2175							remote-endpoint = <&admaif26>;
2176						};
2177					};
2178
2179					port@1b {
2180						reg = <0x1b>;
2181
2182						xbar_admaif27: endpoint {
2183							remote-endpoint = <&admaif27>;
2184						};
2185					};
2186
2187					port@1c {
2188						reg = <0x1c>;
2189
2190						xbar_admaif28: endpoint {
2191							remote-endpoint = <&admaif28>;
2192						};
2193					};
2194
2195					port@1d {
2196						reg = <0x1d>;
2197
2198						xbar_admaif29: endpoint {
2199							remote-endpoint = <&admaif29>;
2200						};
2201					};
2202
2203					port@1e {
2204						reg = <0x1e>;
2205
2206						xbar_admaif30: endpoint {
2207							remote-endpoint = <&admaif30>;
2208						};
2209					};
2210
2211					port@1f {
2212						reg = <0x1f>;
2213
2214						xbar_admaif31: endpoint {
2215							remote-endpoint = <&admaif31>;
2216						};
2217					};
2218
2219					xbar_i2s1_port: port@20 {
2220						reg = <0x20>;
2221
2222						xbar_i2s1: endpoint {
2223							remote-endpoint = <&i2s1_cif>;
2224						};
2225					};
2226
2227					xbar_i2s2_port: port@21 {
2228						reg = <0x21>;
2229
2230						xbar_i2s2: endpoint {
2231							remote-endpoint = <&i2s2_cif>;
2232						};
2233					};
2234
2235					xbar_i2s3_port: port@22 {
2236						reg = <0x22>;
2237
2238						xbar_i2s3: endpoint {
2239							remote-endpoint = <&i2s3_cif>;
2240						};
2241					};
2242
2243					xbar_i2s4_port: port@23 {
2244						reg = <0x23>;
2245
2246						xbar_i2s4: endpoint {
2247							remote-endpoint = <&i2s4_cif>;
2248						};
2249					};
2250
2251					xbar_i2s5_port: port@24 {
2252						reg = <0x24>;
2253
2254						xbar_i2s5: endpoint {
2255							remote-endpoint = <&i2s5_cif>;
2256						};
2257					};
2258
2259					xbar_i2s6_port: port@25 {
2260						reg = <0x25>;
2261
2262						xbar_i2s6: endpoint {
2263							remote-endpoint = <&i2s6_cif>;
2264						};
2265					};
2266
2267					xbar_i2s7_port: port@26 {
2268						reg = <0x26>;
2269
2270						xbar_i2s7: endpoint {
2271							remote-endpoint = <&i2s7_cif>;
2272						};
2273					};
2274
2275					xbar_i2s8_port: port@27 {
2276						reg = <0x27>;
2277
2278						xbar_i2s8: endpoint {
2279							remote-endpoint = <&i2s8_cif>;
2280						};
2281					};
2282
2283					xbar_dmic1_port: port@28 {
2284						reg = <0x28>;
2285
2286						xbar_dmic1: endpoint {
2287							remote-endpoint = <&dmic1_cif>;
2288						};
2289					};
2290
2291					xbar_dmic2_port: port@29 {
2292						reg = <0x29>;
2293
2294						xbar_dmic2: endpoint {
2295							remote-endpoint = <&dmic2_cif>;
2296						};
2297					};
2298
2299					xbar_dspk1_port: port@2a {
2300						reg = <0x2a>;
2301
2302						xbar_dspk1: endpoint {
2303							remote-endpoint = <&dspk1_cif>;
2304						};
2305					};
2306
2307					xbar_sfc1_in_port: port@2b {
2308						reg = <0x2b>;
2309
2310						xbar_sfc1_in: endpoint {
2311							remote-endpoint = <&sfc1_cif_in>;
2312						};
2313					};
2314
2315					port@2c {
2316						reg = <0x2c>;
2317
2318						xbar_sfc1_out: endpoint {
2319							remote-endpoint = <&sfc1_cif_out>;
2320						};
2321					};
2322
2323					xbar_sfc2_in_port: port@2d {
2324						reg = <0x2d>;
2325
2326						xbar_sfc2_in: endpoint {
2327							remote-endpoint = <&sfc2_cif_in>;
2328						};
2329					};
2330
2331					port@2e {
2332						reg = <0x2e>;
2333
2334						xbar_sfc2_out: endpoint {
2335							remote-endpoint = <&sfc2_cif_out>;
2336						};
2337					};
2338
2339					xbar_sfc3_in_port: port@2f {
2340						reg = <0x2f>;
2341
2342						xbar_sfc3_in: endpoint {
2343							remote-endpoint = <&sfc3_cif_in>;
2344						};
2345					};
2346
2347					port@30 {
2348						reg = <0x30>;
2349
2350						xbar_sfc3_out: endpoint {
2351							remote-endpoint = <&sfc3_cif_out>;
2352						};
2353					};
2354
2355					xbar_sfc4_in_port: port@31 {
2356						reg = <0x31>;
2357
2358						xbar_sfc4_in: endpoint {
2359							remote-endpoint = <&sfc4_cif_in>;
2360						};
2361					};
2362
2363					port@32 {
2364						reg = <0x32>;
2365
2366						xbar_sfc4_out: endpoint {
2367							remote-endpoint = <&sfc4_cif_out>;
2368						};
2369					};
2370
2371					xbar_mvc1_in_port: port@33 {
2372						reg = <0x33>;
2373
2374						xbar_mvc1_in: endpoint {
2375							remote-endpoint = <&mvc1_cif_in>;
2376						};
2377					};
2378
2379					port@34 {
2380						reg = <0x34>;
2381
2382						xbar_mvc1_out: endpoint {
2383							remote-endpoint = <&mvc1_cif_out>;
2384						};
2385					};
2386
2387					xbar_mvc2_in_port: port@35 {
2388						reg = <0x35>;
2389
2390						xbar_mvc2_in: endpoint {
2391							remote-endpoint = <&mvc2_cif_in>;
2392						};
2393					};
2394
2395					port@36 {
2396						reg = <0x36>;
2397
2398						xbar_mvc2_out: endpoint {
2399							remote-endpoint = <&mvc2_cif_out>;
2400						};
2401					};
2402
2403					xbar_amx1_in1_port: port@37 {
2404						reg = <0x37>;
2405
2406						xbar_amx1_in1: endpoint {
2407							remote-endpoint = <&amx1_in1>;
2408						};
2409					};
2410
2411					xbar_amx1_in2_port: port@38 {
2412						reg = <0x38>;
2413
2414						xbar_amx1_in2: endpoint {
2415							remote-endpoint = <&amx1_in2>;
2416						};
2417					};
2418
2419					xbar_amx1_in3_port: port@39 {
2420						reg = <0x39>;
2421
2422						xbar_amx1_in3: endpoint {
2423							remote-endpoint = <&amx1_in3>;
2424						};
2425					};
2426
2427					xbar_amx1_in4_port: port@3a {
2428						reg = <0x3a>;
2429
2430						xbar_amx1_in4: endpoint {
2431							remote-endpoint = <&amx1_in4>;
2432						};
2433					};
2434
2435					port@3b {
2436						reg = <0x3b>;
2437
2438						xbar_amx1_out: endpoint {
2439							remote-endpoint = <&amx1_out>;
2440						};
2441					};
2442
2443					xbar_amx2_in1_port: port@3c {
2444						reg = <0x3c>;
2445
2446						xbar_amx2_in1: endpoint {
2447							remote-endpoint = <&amx2_in1>;
2448						};
2449					};
2450
2451					xbar_amx2_in2_port: port@3d {
2452						reg = <0x3d>;
2453
2454						xbar_amx2_in2: endpoint {
2455							remote-endpoint = <&amx2_in2>;
2456						};
2457					};
2458
2459					xbar_amx2_in3_port: port@3e {
2460						reg = <0x3e>;
2461
2462						xbar_amx2_in3: endpoint {
2463							remote-endpoint = <&amx2_in3>;
2464						};
2465					};
2466
2467					xbar_amx2_in4_port: port@3f {
2468						reg = <0x3f>;
2469
2470						xbar_amx2_in4: endpoint {
2471							remote-endpoint = <&amx2_in4>;
2472						};
2473					};
2474
2475					port@40 {
2476						reg = <0x40>;
2477
2478						xbar_amx2_out: endpoint {
2479							remote-endpoint = <&amx2_out>;
2480						};
2481					};
2482
2483					xbar_amx3_in1_port: port@41 {
2484						reg = <0x41>;
2485
2486						xbar_amx3_in1: endpoint {
2487							remote-endpoint = <&amx3_in1>;
2488						};
2489					};
2490
2491					xbar_amx3_in2_port: port@42 {
2492						reg = <0x42>;
2493
2494						xbar_amx3_in2: endpoint {
2495							remote-endpoint = <&amx3_in2>;
2496						};
2497					};
2498
2499					xbar_amx3_in3_port: port@43 {
2500						reg = <0x43>;
2501
2502						xbar_amx3_in3: endpoint {
2503							remote-endpoint = <&amx3_in3>;
2504						};
2505					};
2506
2507					xbar_amx3_in4_port: port@44 {
2508						reg = <0x44>;
2509
2510						xbar_amx3_in4: endpoint {
2511							remote-endpoint = <&amx3_in4>;
2512						};
2513					};
2514
2515					port@45 {
2516						reg = <0x45>;
2517
2518						xbar_amx3_out: endpoint {
2519							remote-endpoint = <&amx3_out>;
2520						};
2521					};
2522
2523					xbar_amx4_in1_port: port@46 {
2524						reg = <0x46>;
2525
2526						xbar_amx4_in1: endpoint {
2527							remote-endpoint = <&amx4_in1>;
2528						};
2529					};
2530
2531					xbar_amx4_in2_port: port@47 {
2532						reg = <0x47>;
2533
2534						xbar_amx4_in2: endpoint {
2535							remote-endpoint = <&amx4_in2>;
2536						};
2537					};
2538
2539					xbar_amx4_in3_port: port@48 {
2540						reg = <0x48>;
2541
2542						xbar_amx4_in3: endpoint {
2543							remote-endpoint = <&amx4_in3>;
2544						};
2545					};
2546
2547					xbar_amx4_in4_port: port@49 {
2548						reg = <0x49>;
2549
2550						xbar_amx4_in4: endpoint {
2551							remote-endpoint = <&amx4_in4>;
2552						};
2553					};
2554
2555					port@4a {
2556						reg = <0x4a>;
2557
2558						xbar_amx4_out: endpoint {
2559							remote-endpoint = <&amx4_out>;
2560						};
2561					};
2562
2563					xbar_amx5_in1_port: port@4b {
2564						reg = <0x4b>;
2565
2566						xbar_amx5_in1: endpoint {
2567							remote-endpoint = <&amx5_in1>;
2568						};
2569					};
2570
2571					xbar_amx5_in2_port: port@4c {
2572						reg = <0x4c>;
2573
2574						xbar_amx5_in2: endpoint {
2575							remote-endpoint = <&amx5_in2>;
2576						};
2577					};
2578
2579					xbar_amx5_in3_port: port@4d {
2580						reg = <0x4d>;
2581
2582						xbar_amx5_in3: endpoint {
2583							remote-endpoint = <&amx5_in3>;
2584						};
2585					};
2586
2587					xbar_amx5_in4_port: port@4e {
2588						reg = <0x4e>;
2589
2590						xbar_amx5_in4: endpoint {
2591							remote-endpoint = <&amx5_in4>;
2592						};
2593					};
2594
2595					port@4f {
2596						reg = <0x4f>;
2597
2598						xbar_amx5_out: endpoint {
2599							remote-endpoint = <&amx5_out>;
2600						};
2601					};
2602
2603					xbar_amx6_in1_port: port@50 {
2604						reg = <0x50>;
2605
2606						xbar_amx6_in1: endpoint {
2607							remote-endpoint = <&amx6_in1>;
2608						};
2609					};
2610
2611					xbar_amx6_in2_port: port@51 {
2612						reg = <0x51>;
2613
2614						xbar_amx6_in2: endpoint {
2615							remote-endpoint = <&amx6_in2>;
2616						};
2617					};
2618
2619					xbar_amx6_in3_port: port@52 {
2620						reg = <0x52>;
2621
2622						xbar_amx6_in3: endpoint {
2623							remote-endpoint = <&amx6_in3>;
2624						};
2625					};
2626
2627					xbar_amx6_in4_port: port@53 {
2628						reg = <0x53>;
2629
2630						xbar_amx6_in4: endpoint {
2631							remote-endpoint = <&amx6_in4>;
2632						};
2633					};
2634
2635					port@54 {
2636						reg = <0x54>;
2637
2638						xbar_amx6_out: endpoint {
2639							remote-endpoint = <&amx6_out>;
2640						};
2641					};
2642
2643					xbar_adx1_in_port: port@55 {
2644						reg = <0x55>;
2645
2646						xbar_adx1_in: endpoint {
2647							remote-endpoint = <&adx1_in>;
2648						};
2649					};
2650
2651					port@56 {
2652						reg = <0x56>;
2653
2654						xbar_adx1_out1: endpoint {
2655							remote-endpoint = <&adx1_out1>;
2656						};
2657					};
2658
2659					port@57 {
2660						reg = <0x57>;
2661
2662						xbar_adx1_out2: endpoint {
2663							remote-endpoint = <&adx1_out2>;
2664						};
2665					};
2666
2667					port@58 {
2668						reg = <0x58>;
2669
2670						xbar_adx1_out3: endpoint {
2671							remote-endpoint = <&adx1_out3>;
2672						};
2673					};
2674
2675					port@59 {
2676						reg = <0x59>;
2677
2678						xbar_adx1_out4: endpoint {
2679							remote-endpoint = <&adx1_out4>;
2680						};
2681					};
2682
2683					xbar_adx2_in_port: port@5a {
2684						reg = <0x5a>;
2685
2686						xbar_adx2_in: endpoint {
2687							remote-endpoint = <&adx2_in>;
2688						};
2689					};
2690
2691					port@5b {
2692						reg = <0x5b>;
2693
2694						xbar_adx2_out1: endpoint {
2695							remote-endpoint = <&adx2_out1>;
2696						};
2697					};
2698
2699					port@5c {
2700						reg = <0x5c>;
2701
2702						xbar_adx2_out2: endpoint {
2703							remote-endpoint = <&adx2_out2>;
2704						};
2705					};
2706
2707					port@5d {
2708						reg = <0x5d>;
2709
2710						xbar_adx2_out3: endpoint {
2711							remote-endpoint = <&adx2_out3>;
2712						};
2713					};
2714
2715					port@5e {
2716						reg = <0x5e>;
2717
2718						xbar_adx2_out4: endpoint {
2719							remote-endpoint = <&adx2_out4>;
2720						};
2721					};
2722
2723					xbar_adx3_in_port: port@5f {
2724						reg = <0x5f>;
2725
2726						xbar_adx3_in: endpoint {
2727							remote-endpoint = <&adx3_in>;
2728						};
2729					};
2730
2731					port@60 {
2732						reg = <0x60>;
2733
2734						xbar_adx3_out1: endpoint {
2735							remote-endpoint = <&adx3_out1>;
2736						};
2737					};
2738
2739					port@61 {
2740						reg = <0x61>;
2741
2742						xbar_adx3_out2: endpoint {
2743							remote-endpoint = <&adx3_out2>;
2744						};
2745					};
2746
2747					port@62 {
2748						reg = <0x62>;
2749
2750						xbar_adx3_out3: endpoint {
2751							remote-endpoint = <&adx3_out3>;
2752						};
2753					};
2754
2755					port@63 {
2756						reg = <0x63>;
2757
2758						xbar_adx3_out4: endpoint {
2759							remote-endpoint = <&adx3_out4>;
2760						};
2761					};
2762
2763					xbar_adx4_in_port: port@64 {
2764						reg = <0x64>;
2765
2766						xbar_adx4_in: endpoint {
2767							remote-endpoint = <&adx4_in>;
2768						};
2769					};
2770
2771					port@65 {
2772						reg = <0x65>;
2773
2774						xbar_adx4_out1: endpoint {
2775							remote-endpoint = <&adx4_out1>;
2776						};
2777					};
2778
2779					port@66 {
2780						reg = <0x66>;
2781
2782						xbar_adx4_out2: endpoint {
2783							remote-endpoint = <&adx4_out2>;
2784						};
2785					};
2786
2787					port@67 {
2788						reg = <0x67>;
2789
2790						xbar_adx4_out3: endpoint {
2791							remote-endpoint = <&adx4_out3>;
2792						};
2793					};
2794
2795					port@68 {
2796						reg = <0x68>;
2797
2798						xbar_adx4_out4: endpoint {
2799							remote-endpoint = <&adx4_out4>;
2800						};
2801					};
2802
2803					xbar_adx5_in_port: port@69 {
2804						reg = <0x69>;
2805
2806						xbar_adx5_in: endpoint {
2807							remote-endpoint = <&adx5_in>;
2808						};
2809					};
2810
2811					port@6a {
2812						reg = <0x6a>;
2813
2814						xbar_adx5_out1: endpoint {
2815							remote-endpoint = <&adx5_out1>;
2816						};
2817					};
2818
2819					port@6b {
2820						reg = <0x6b>;
2821
2822						xbar_adx5_out2: endpoint {
2823							remote-endpoint = <&adx5_out2>;
2824						};
2825					};
2826
2827					port@6c {
2828						reg = <0x6c>;
2829
2830						xbar_adx5_out3: endpoint {
2831							remote-endpoint = <&adx5_out3>;
2832						};
2833					};
2834
2835					port@6d {
2836						reg = <0x6d>;
2837
2838						xbar_adx5_out4: endpoint {
2839							remote-endpoint = <&adx5_out4>;
2840						};
2841					};
2842
2843					xbar_adx6_in_port: port@6e {
2844						reg = <0x6e>;
2845
2846						xbar_adx6_in: endpoint {
2847							remote-endpoint = <&adx6_in>;
2848						};
2849					};
2850
2851					port@6f {
2852						reg = <0x6f>;
2853
2854						xbar_adx6_out1: endpoint {
2855							remote-endpoint = <&adx6_out1>;
2856						};
2857					};
2858
2859					port@70 {
2860						reg = <0x70>;
2861
2862						xbar_adx6_out2: endpoint {
2863							remote-endpoint = <&adx6_out2>;
2864						};
2865					};
2866
2867					port@71 {
2868						reg = <0x71>;
2869
2870						xbar_adx6_out3: endpoint {
2871							remote-endpoint = <&adx6_out3>;
2872						};
2873					};
2874
2875					port@72 {
2876						reg = <0x72>;
2877
2878						xbar_adx6_out4: endpoint {
2879							remote-endpoint = <&adx6_out4>;
2880						};
2881					};
2882
2883					xbar_mix_in1_port: port@73 {
2884						reg = <0x73>;
2885
2886						xbar_mix_in1: endpoint {
2887							remote-endpoint = <&mix_in1>;
2888						};
2889					};
2890
2891					xbar_mix_in2_port: port@74 {
2892						reg = <0x74>;
2893
2894						xbar_mix_in2: endpoint {
2895							remote-endpoint = <&mix_in2>;
2896						};
2897					};
2898
2899					xbar_mix_in3_port: port@75 {
2900						reg = <0x75>;
2901
2902						xbar_mix_in3: endpoint {
2903							remote-endpoint = <&mix_in3>;
2904						};
2905					};
2906
2907					xbar_mix_in4_port: port@76 {
2908						reg = <0x76>;
2909
2910						xbar_mix_in4: endpoint {
2911							remote-endpoint = <&mix_in4>;
2912						};
2913					};
2914
2915					xbar_mix_in5_port: port@77 {
2916						reg = <0x77>;
2917
2918						xbar_mix_in5: endpoint {
2919							remote-endpoint = <&mix_in5>;
2920						};
2921					};
2922
2923					xbar_mix_in6_port: port@78 {
2924						reg = <0x78>;
2925
2926						xbar_mix_in6: endpoint {
2927							remote-endpoint = <&mix_in6>;
2928						};
2929					};
2930
2931					xbar_mix_in7_port: port@79 {
2932						reg = <0x79>;
2933
2934						xbar_mix_in7: endpoint {
2935							remote-endpoint = <&mix_in7>;
2936						};
2937					};
2938
2939					xbar_mix_in8_port: port@7a {
2940						reg = <0x7a>;
2941
2942						xbar_mix_in8: endpoint {
2943							remote-endpoint = <&mix_in8>;
2944						};
2945					};
2946
2947					xbar_mix_in9_port: port@7b {
2948						reg = <0x7b>;
2949
2950						xbar_mix_in9: endpoint {
2951							remote-endpoint = <&mix_in9>;
2952						};
2953					};
2954
2955					xbar_mix_in10_port: port@7c {
2956						reg = <0x7c>;
2957
2958						xbar_mix_in10: endpoint {
2959							remote-endpoint = <&mix_in10>;
2960						};
2961					};
2962
2963					port@7d {
2964						reg = <0x7d>;
2965
2966						xbar_mix_out1: endpoint {
2967							remote-endpoint = <&mix_out1>;
2968						};
2969					};
2970
2971					port@7e {
2972						reg = <0x7e>;
2973
2974						xbar_mix_out2: endpoint {
2975							remote-endpoint = <&mix_out2>;
2976						};
2977					};
2978
2979					port@7f {
2980						reg = <0x7f>;
2981
2982						xbar_mix_out3: endpoint {
2983							remote-endpoint = <&mix_out3>;
2984						};
2985					};
2986
2987					port@80 {
2988						reg = <0x80>;
2989
2990						xbar_mix_out4: endpoint {
2991							remote-endpoint = <&mix_out4>;
2992						};
2993					};
2994
2995					port@81 {
2996						reg = <0x81>;
2997
2998						xbar_mix_out5: endpoint {
2999							remote-endpoint = <&mix_out5>;
3000						};
3001					};
3002
3003					xbar_asrc_in1_port: port@82 {
3004						reg = <0x82>;
3005
3006						xbar_asrc_in1_ep: endpoint {
3007							remote-endpoint = <&asrc_in1_ep>;
3008						};
3009					};
3010
3011					port@83 {
3012						reg = <0x83>;
3013
3014						xbar_asrc_out1_ep: endpoint {
3015							remote-endpoint = <&asrc_out1_ep>;
3016						};
3017					};
3018
3019					xbar_asrc_in2_port: port@84 {
3020						reg = <0x84>;
3021
3022						xbar_asrc_in2_ep: endpoint {
3023							remote-endpoint = <&asrc_in2_ep>;
3024						};
3025					};
3026
3027					port@85 {
3028						reg = <0x85>;
3029
3030						xbar_asrc_out2_ep: endpoint {
3031							remote-endpoint = <&asrc_out2_ep>;
3032						};
3033					};
3034
3035					xbar_asrc_in3_port: port@86 {
3036						reg = <0x86>;
3037
3038						xbar_asrc_in3_ep: endpoint {
3039							remote-endpoint = <&asrc_in3_ep>;
3040						};
3041					};
3042
3043					port@87 {
3044						reg = <0x87>;
3045
3046						xbar_asrc_out3_ep: endpoint {
3047							remote-endpoint = <&asrc_out3_ep>;
3048						};
3049					};
3050
3051					xbar_asrc_in4_port: port@88 {
3052						reg = <0x88>;
3053
3054						xbar_asrc_in4_ep: endpoint {
3055							remote-endpoint = <&asrc_in4_ep>;
3056						};
3057					};
3058
3059					port@89 {
3060						reg = <0x89>;
3061
3062						xbar_asrc_out4_ep: endpoint {
3063							remote-endpoint = <&asrc_out4_ep>;
3064						};
3065					};
3066
3067					xbar_asrc_in5_port: port@8a {
3068						reg = <0x8a>;
3069
3070						xbar_asrc_in5_ep: endpoint {
3071							remote-endpoint = <&asrc_in5_ep>;
3072						};
3073					};
3074
3075					port@8b {
3076						reg = <0x8b>;
3077
3078						xbar_asrc_out5_ep: endpoint {
3079							remote-endpoint = <&asrc_out5_ep>;
3080						};
3081					};
3082
3083					xbar_asrc_in6_port: port@8c {
3084						reg = <0x8c>;
3085
3086						xbar_asrc_in6_ep: endpoint {
3087							remote-endpoint = <&asrc_in6_ep>;
3088						};
3089					};
3090
3091					port@8d {
3092						reg = <0x8d>;
3093
3094						xbar_asrc_out6_ep: endpoint {
3095							remote-endpoint = <&asrc_out6_ep>;
3096						};
3097					};
3098
3099					xbar_asrc_in7_port: port@8e {
3100						reg = <0x8e>;
3101
3102						xbar_asrc_in7_ep: endpoint {
3103							remote-endpoint = <&asrc_in7_ep>;
3104						};
3105					};
3106
3107					xbar_ope1_in_port: port@8f {
3108						reg = <0x8f>;
3109
3110						xbar_ope1_in_ep: endpoint {
3111							remote-endpoint = <&ope1_cif_in_ep>;
3112						};
3113					};
3114
3115					port@90 {
3116						reg = <0x90>;
3117
3118						xbar_ope1_out_ep: endpoint {
3119							remote-endpoint = <&ope1_cif_out_ep>;
3120						};
3121					};
3122				};
3123			};
3124
3125			agic_page0: interrupt-controller@9960000 {
3126				compatible = "nvidia,tegra264-agic",
3127						"nvidia,tegra210-agic";
3128				#interrupt-cells = <3>;
3129				interrupt-controller;
3130				reg = <0x0 0x9961000 0x0 0x1000>,
3131					<0x0 0x9962000 0x0 0x1000>;
3132				interrupts = <GIC_SPI 0x230
3133					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
3134				clocks = <&bpmp TEGRA264_CLK_ADSP>;
3135				clock-names = "clk";
3136				status = "disabled";
3137			};
3138
3139			agic_page1: interrupt-controller@9970000 {
3140				compatible = "nvidia,tegra264-agic",
3141					   "nvidia,tegra210-agic";
3142				#interrupt-cells = <3>;
3143				interrupt-controller;
3144				reg = <0x0 0x9971000 0x0 0x1000>,
3145					<0x0 0x9972000 0x0 0x1000>;
3146				interrupts = <GIC_SPI 0x231
3147					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
3148				clocks = <&bpmp TEGRA264_CLK_ADSP>;
3149				clock-names = "clk";
3150				status = "disabled";
3151			};
3152
3153			agic_page2: interrupt-controller@9980000 {
3154				compatible = "nvidia,tegra264-agic",
3155						"nvidia,tegra210-agic";
3156				#interrupt-cells = <3>;
3157				interrupt-controller;
3158				reg = <0x0 0x9981000 0x0 0x1000>,
3159					<0x0 0x9982000 0x0 0x1000>;
3160				interrupts = <GIC_SPI 0x232
3161					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
3162				clocks = <&bpmp TEGRA264_CLK_ADSP>;
3163				clock-names = "clk";
3164				status = "disabled";
3165			};
3166
3167			agic_page3: interrupt-controller@9990000 {
3168				compatible = "nvidia,tegra264-agic",
3169						"nvidia,tegra210-agic";
3170				#interrupt-cells = <3>;
3171				interrupt-controller;
3172				reg = <0x0 0x9991000 0x0 0x1000>,
3173					<0x0 0x9992000 0x0 0x1000>;
3174				interrupts = <GIC_SPI 0x233
3175					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
3176				clocks = <&bpmp TEGRA264_CLK_ADSP>;
3177				clock-names = "clk";
3178				status = "disabled";
3179			};
3180
3181			agic_page4: interrupt-controller@99a0000 {
3182				compatible = "nvidia,tegra264-agic",
3183						"nvidia,tegra210-agic";
3184				#interrupt-cells = <3>;
3185				interrupt-controller;
3186				reg = <0x0 0x99a1000 0x0 0x1000>,
3187					<0x0 0x99a2000 0x0 0x1000>;
3188				interrupts = <GIC_SPI 0x234
3189					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
3190				clocks = <&bpmp TEGRA264_CLK_ADSP>;
3191				clock-names = "clk";
3192				status = "disabled";
3193			};
3194
3195			agic_page5: interrupt-controller@99b0000 {
3196				compatible = "nvidia,tegra264-agic",
3197						"nvidia,tegra210-agic";
3198				#interrupt-cells = <3>;
3199				interrupt-controller;
3200				reg = <0x0 0x99b1000 0x0 0x1000>,
3201					<0x0 0x99b2000 0x0 0x1000>;
3202				interrupts = <GIC_SPI 0x235
3203					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
3204				clocks = <&bpmp TEGRA264_CLK_ADSP>;
3205				clock-names = "clk";
3206				status = "disabled";
3207			};
3208		};
3209
3210		gpcdma: dma-controller@8400000 {
3211			compatible = "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma";
3212			reg = <0x0 0x08400000 0x0 0x210000>;
3213			interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>,
3214				     <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
3215				     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>,
3216				     <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
3217				     <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
3218				     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
3219				     <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
3220				     <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
3221				     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
3222				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
3223				     <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
3224				     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
3225				     <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
3226				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
3227				     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
3228				     <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
3229				     <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>,
3230				     <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>,
3231				     <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
3232				     <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
3233				     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
3234				     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>,
3235				     <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
3236				     <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>,
3237				     <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
3238				     <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>,
3239				     <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>,
3240				     <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>,
3241				     <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>,
3242				     <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>,
3243				     <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>,
3244				     <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>;
3245			#dma-cells = <1>;
3246			iommus = <&smmu1 0x00000800>;
3247			dma-coherent;
3248			dma-channel-mask = <0xfffffffe>;
3249			status = "disabled";
3250		};
3251
3252		hsp_top: hsp@8800000 {
3253			compatible = "nvidia,tegra264-hsp";
3254			reg = <0x0 0x08800000 0x0 0xd0000>;
3255			interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>,
3256				     <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>,
3257				     <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>,
3258				     <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>,
3259				     <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>,
3260				     <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>,
3261				     <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>,
3262				     <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH>,
3263				     <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
3264			interrupt-names = "doorbell", "shared0", "shared1", "shared2",
3265					  "shared3", "shared4", "shared5", "shared6",
3266					  "shared7";
3267			#mbox-cells = <2>;
3268		};
3269
3270		rtc: rtc@c2c0000 {
3271			compatible = "nvidia,tegra264-rtc", "nvidia,tegra20-rtc";
3272			reg = <0x0 0x0c2c0000 0x0 0x10000>;
3273			interrupt-parent = <&pmc>;
3274			interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
3275			clocks = <&bpmp TEGRA264_CLK_CLK_S>;
3276			clock-names = "rtc";
3277			status = "disabled";
3278		};
3279
3280		serial@c4e0000 {
3281			compatible = "nvidia,tegra264-utc";
3282			reg = <0x0 0x0c4e0000 0x0 0x8000>,
3283			      <0x0 0x0c4e8000 0x0 0x8000>;
3284			reg-names = "tx", "rx";
3285			interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
3286			rx-threshold = <4>;
3287			tx-threshold = <4>;
3288			status = "disabled";
3289		};
3290
3291		serial@c5a0000 {
3292			compatible = "nvidia,tegra264-utc";
3293			reg = <0x0 0x0c5a0000 0x0 0x8000>,
3294			      <0x0 0x0c5a8000 0x0 0x8000>;
3295			reg-names = "tx", "rx";
3296			interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>;
3297			rx-threshold = <4>;
3298			tx-threshold = <4>;
3299			status = "disabled";
3300		};
3301
3302		uart0: serial@c5f0000 {
3303			compatible = "arm,sbsa-uart";
3304			reg = <0x0 0x0c5f0000 0x0 0x10000>;
3305			interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>;
3306			status = "disabled";
3307		};
3308
3309		i2c2: i2c@c600000 {
3310			compatible = "nvidia,tegra264-i2c";
3311			reg = <0x0 0x0c600000 0x0 0x10000>;
3312			interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>;
3313			clock-frequency = <400000>;
3314			clocks = <&bpmp TEGRA264_CLK_AON_I2C>,
3315				 <&bpmp TEGRA264_CLK_PLLAON>;
3316			clock-names = "div-clk", "parent";
3317			assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>;
3318			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>;
3319			resets = <&bpmp TEGRA264_RESET_I2C2>;
3320			reset-names = "i2c";
3321			status = "disabled";
3322		};
3323
3324		i2c3: i2c@c610000 {
3325			compatible = "nvidia,tegra264-i2c";
3326			reg = <0x0 0x0c610000 0x0 0x10000>;
3327			interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
3328			clock-frequency = <400000>;
3329			clocks = <&bpmp TEGRA264_CLK_AON_I2C>,
3330				 <&bpmp TEGRA264_CLK_PLLAON>;
3331			clock-names = "div-clk", "parent";
3332			assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>;
3333			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>;
3334			resets = <&bpmp TEGRA264_RESET_I2C3>;
3335			reset-names = "i2c";
3336			status = "disabled";
3337		};
3338
3339		pmc: pmc@c800000 {
3340			compatible = "nvidia,tegra264-pmc";
3341			reg = <0x0 0x0c800000 0x0 0x100000>,
3342			      <0x0 0x0c990000 0x0 0x10000>,
3343			      <0x0 0x0ca00000 0x0 0x10000>,
3344			      <0x0 0x0c980000 0x0 0x10000>,
3345			      <0x0 0x0c9c0000 0x0 0x40000>;
3346			reg-names = "pmc", "wake", "aotag", "scratch", "misc";
3347			#interrupt-cells = <2>;
3348			interrupt-controller;
3349		};
3350	};
3351
3352	/* TOP_MMIO */
3353	bus@8100000000 {
3354		compatible = "simple-bus";
3355
3356		#address-cells = <2>;
3357		#size-cells = <2>;
3358
3359		ranges = <0x00 0x00000000 0x81 0x00000000 0x01 0x00000000>, /* MMIO */
3360			 <0x01 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */
3361			 <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */
3362
3363		smmu1: iommu@5000000 {
3364			compatible = "arm,smmu-v3";
3365			reg = <0x00 0x5000000 0x0 0x200000>;
3366			interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
3367				     <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>;
3368			interrupt-names = "eventq", "gerror";
3369			status = "disabled";
3370
3371			#iommu-cells = <1>;
3372			dma-coherent;
3373		};
3374
3375		smmu2: iommu@6000000 {
3376			compatible = "arm,smmu-v3";
3377			reg = <0x00 0x6000000 0x0 0x200000>;
3378			interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
3379				     <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
3380			interrupt-names = "eventq", "gerror";
3381			status = "disabled";
3382
3383			#iommu-cells = <1>;
3384			dma-coherent;
3385		};
3386
3387		mc: memory-controller@8020000 {
3388			compatible = "nvidia,tegra264-mc";
3389			reg = <0x00 0x8020000 0x0 0x20000>, /* MC broadcast */
3390			      <0x00 0x8040000 0x0 0x20000>, /* MC  0 */
3391			      <0x00 0x8060000 0x0 0x20000>, /* MC  1 */
3392			      <0x00 0x8080000 0x0 0x20000>, /* MC  2 */
3393			      <0x00 0x80a0000 0x0 0x20000>, /* MC  3 */
3394			      <0x00 0x80c0000 0x0 0x20000>, /* MC  4 */
3395			      <0x00 0x80e0000 0x0 0x20000>, /* MC  5 */
3396			      <0x00 0x8100000 0x0 0x20000>, /* MC  6 */
3397			      <0x00 0x8120000 0x0 0x20000>, /* MC  7 */
3398			      <0x00 0x8140000 0x0 0x20000>, /* MC  8 */
3399			      <0x00 0x8160000 0x0 0x20000>, /* MC  9 */
3400			      <0x00 0x8180000 0x0 0x20000>, /* MC 10 */
3401			      <0x00 0x81a0000 0x0 0x20000>, /* MC 11 */
3402			      <0x00 0x81c0000 0x0 0x20000>, /* MC 12 */
3403			      <0x00 0x81e0000 0x0 0x20000>, /* MC 13 */
3404			      <0x00 0x8200000 0x0 0x20000>, /* MC 14 */
3405			      <0x00 0x8220000 0x0 0x20000>; /* MC 15 */
3406			reg-names = "broadcast", "ch0", "ch1", "ch2", "ch3",
3407				    "ch4", "ch5", "ch6", "ch7", "ch8", "ch9",
3408				    "ch10", "ch11", "ch12", "ch13", "ch14",
3409				    "ch15";
3410			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
3411				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3412				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3413				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3414				     <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
3415				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
3416				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3417				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
3418			#interconnect-cells = <1>;
3419
3420			#address-cells = <2>;
3421			#size-cells = <2>;
3422
3423			/* limit the DMA range for memory clients to [39:0] */
3424			dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
3425
3426			emc: external-memory-controller@8800000 {
3427				compatible = "nvidia,tegra264-emc";
3428				reg = <0x00 0x8800000 0x0 0x20000>,
3429				      <0x00 0x8890000 0x0 0x20000>;
3430				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
3431				clocks = <&bpmp TEGRA264_CLK_EMC>;
3432				clock-names = "emc";
3433
3434				#interconnect-cells = <0>;
3435				nvidia,bpmp = <&bpmp>;
3436			};
3437		};
3438
3439		smmu0: iommu@a000000 {
3440			compatible = "arm,smmu-v3";
3441			reg = <0x00 0xa000000 0x0 0x200000>;
3442			interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
3443				     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
3444			interrupt-names = "eventq", "gerror";
3445			status = "disabled";
3446
3447			#iommu-cells = <1>;
3448			dma-coherent;
3449		};
3450
3451		smmu4: iommu@b000000 {
3452			compatible = "arm,smmu-v3";
3453			reg = <0x00 0xb000000 0x0 0x200000>;
3454			interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
3455				     <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
3456			interrupt-names = "eventq", "gerror";
3457			status = "disabled";
3458
3459			#iommu-cells = <1>;
3460			dma-coherent;
3461		};
3462
3463		i2c14: i2c@c410000 {
3464			compatible = "nvidia,tegra264-i2c";
3465			reg = <0x00 0x0c410000 0x0 0x10000>;
3466			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
3467			clock-frequency = <400000>;
3468			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
3469				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3470			clock-names = "div-clk", "parent";
3471			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
3472			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3473			resets = <&bpmp TEGRA264_RESET_I2C14>;
3474			reset-names = "i2c";
3475			status = "disabled";
3476		};
3477
3478		i2c15: i2c@c420000 {
3479			compatible = "nvidia,tegra264-i2c";
3480			reg = <0x00 0x0c420000 0x0 0x10000>;
3481			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
3482			clock-frequency = <400000>;
3483			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
3484				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3485			clock-names = "div-clk", "parent";
3486			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
3487			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3488			resets = <&bpmp TEGRA264_RESET_I2C15>;
3489			reset-names = "i2c";
3490			status = "disabled";
3491		};
3492
3493		i2c16: i2c@c430000 {
3494			compatible = "nvidia,tegra264-i2c";
3495			reg = <0x00 0x0c430000 0x0 0x10000>;
3496			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
3497			clock-frequency = <400000>;
3498			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
3499				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3500			clock-names = "div-clk", "parent";
3501			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
3502			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3503			resets = <&bpmp TEGRA264_RESET_I2C16>;
3504			reset-names = "i2c";
3505			status = "disabled";
3506		};
3507
3508		i2c0: i2c@c630000 {
3509			compatible = "nvidia,tegra264-i2c";
3510			reg = <0x00 0x0c630000 0x0 0x10000>;
3511			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
3512			clock-frequency = <400000>;
3513			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
3514				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3515			clock-names = "div-clk", "parent";
3516			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
3517			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3518			resets = <&bpmp TEGRA264_RESET_I2C0>;
3519			reset-names = "i2c";
3520			status = "disabled";
3521		};
3522
3523		i2c1: i2c@c640000 {
3524			compatible = "nvidia,tegra264-i2c";
3525			reg = <0x00 0x0c640000 0x0 0x10000>;
3526			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
3527			clock-frequency = <400000>;
3528			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
3529				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3530			clock-names = "div-clk", "parent";
3531			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
3532			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3533			resets = <&bpmp TEGRA264_RESET_I2C1>;
3534			reset-names = "i2c";
3535			status = "disabled";
3536		};
3537
3538		i2c4: i2c@c650000 {
3539			compatible = "nvidia,tegra264-i2c";
3540			reg = <0x00 0x0c650000 0x0 0x10000>;
3541			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
3542			clock-frequency = <400000>;
3543			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
3544				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3545			clock-names = "div-clk", "parent";
3546			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
3547			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3548			resets = <&bpmp TEGRA264_RESET_I2C4>;
3549			reset-names = "i2c";
3550			status = "disabled";
3551		};
3552
3553		i2c6: i2c@c670000 {
3554			compatible = "nvidia,tegra264-i2c";
3555			reg = <0x00 0x0c670000 0x0 0x10000>;
3556			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
3557			clock-frequency = <400000>;
3558			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
3559				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3560			clock-names = "div-clk", "parent";
3561			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
3562			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3563			resets = <&bpmp TEGRA264_RESET_I2C6>;
3564			reset-names = "i2c";
3565			status = "disabled";
3566		};
3567
3568		i2c7: i2c@c680000 {
3569			compatible = "nvidia,tegra264-i2c";
3570			reg = <0x00 0x0c680000 0x0 0x10000>;
3571			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
3572			clock-frequency = <400000>;
3573			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
3574				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3575			clock-names = "div-clk", "parent";
3576			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
3577			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3578			resets = <&bpmp TEGRA264_RESET_I2C7>;
3579			reset-names = "i2c";
3580			status = "disabled";
3581		};
3582
3583		i2c8: i2c@c690000 {
3584			compatible = "nvidia,tegra264-i2c";
3585			reg = <0x00 0x0c690000 0x0 0x10000>;
3586			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
3587			clock-frequency = <400000>;
3588			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
3589				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3590			clock-names = "div-clk", "parent";
3591			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
3592			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3593			resets = <&bpmp TEGRA264_RESET_I2C8>;
3594			reset-names = "i2c";
3595			status = "disabled";
3596		};
3597
3598		i2c9: i2c@c6a0000 {
3599			compatible = "nvidia,tegra264-i2c";
3600			reg = <0x00 0x0c6a0000 0x0 0x10000>;
3601			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
3602			clock-frequency = <400000>;
3603			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
3604				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3605			clock-names = "div-clk", "parent";
3606			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
3607			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3608			resets = <&bpmp TEGRA264_RESET_I2C9>;
3609			reset-names = "i2c";
3610			status = "disabled";
3611		};
3612
3613		i2c10: i2c@c6b0000 {
3614			compatible = "nvidia,tegra264-i2c";
3615			reg = <0x00 0x0c6b0000 0x0 0x10000>;
3616			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3617			clock-frequency = <400000>;
3618			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
3619				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3620			clock-names = "div-clk", "parent";
3621			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
3622			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3623			resets = <&bpmp TEGRA264_RESET_I2C10>;
3624			reset-names = "i2c";
3625			status = "disabled";
3626		};
3627
3628		i2c11: i2c@c6c0000 {
3629			compatible = "nvidia,tegra264-i2c";
3630			reg = <0x00 0x0c6c0000 0x0 0x10000>;
3631			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3632			clock-frequency = <400000>;
3633			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
3634				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3635			clock-names = "div-clk", "parent";
3636			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
3637			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3638			resets = <&bpmp TEGRA264_RESET_I2C11>;
3639			reset-names = "i2c";
3640			status = "disabled";
3641		};
3642
3643		i2c12: i2c@c6d0000 {
3644			compatible = "nvidia,tegra264-i2c";
3645			reg = <0x00 0x0c6d0000 0x0 0x10000>;
3646			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
3647			clock-frequency = <400000>;
3648			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
3649				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3650			clock-names = "div-clk", "parent";
3651			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
3652			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
3653			resets = <&bpmp TEGRA264_RESET_I2C12>;
3654			reset-names = "i2c";
3655			status = "disabled";
3656		};
3657
3658		gic: interrupt-controller@46000000 {
3659			compatible = "arm,gic-v3";
3660			reg = <0x00 0x46000000 0x0 0x010000>, /* GICD */
3661			      <0x00 0x46080000 0x0 0x400000>; /* GICR */
3662			interrupt-parent = <&gic>;
3663			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
3664
3665			redistributor-stride = <0x0 0x40000>;
3666			#redistributor-regions = <1>;
3667			#interrupt-cells = <3>;
3668			interrupt-controller;
3669
3670			#address-cells = <2>;
3671			#size-cells = <2>;
3672
3673			ranges = <0x0 0x0 0x00 0x46000000 0x0 0x1000000>;
3674
3675			its: msi-controller@40000 {
3676				compatible = "arm,gic-v3-its";
3677				reg = <0x0 0x40000 0x0 0x40000>;
3678				#msi-cells = <1>;
3679				msi-controller;
3680			};
3681		};
3682	};
3683
3684	/* DISP_USB MMIO */
3685	bus@8800000000 {
3686		compatible = "simple-bus";
3687		#address-cells = <2>;
3688		#size-cells = <2>;
3689
3690		ranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>;
3691
3692		smmu3: iommu@6000000 {
3693			compatible = "arm,smmu-v3";
3694			reg = <0x00 0x6000000 0x0 0x200000>;
3695			interrupts = <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
3696				     <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>;
3697			interrupt-names = "eventq", "gerror";
3698			status = "disabled";
3699
3700			#iommu-cells = <1>;
3701			dma-coherent;
3702		};
3703
3704		hda@90b0000 {
3705			compatible = "nvidia,tegra264-hda";
3706			reg = <0x0 0x90b0000 0x0 0x10000>;
3707			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
3708			clocks = <&bpmp TEGRA264_CLK_AZA_2XBIT>;
3709			clock-names = "hda";
3710			resets = <&bpmp TEGRA264_RESET_HDA>,
3711				 <&bpmp TEGRA264_RESET_HDACODEC>;
3712			reset-names = "hda", "hda2codec_2x";
3713			interconnects = <&mc TEGRA264_MEMORY_CLIENT_HDAR &emc>,
3714					<&mc TEGRA264_MEMORY_CLIENT_HDAW &emc>;
3715			interconnect-names = "dma-mem", "write";
3716			iommus = <&smmu3 TEGRA264_SID_HDA>;
3717			status = "disabled";
3718		};
3719	};
3720
3721	/* UPHY MMIO */
3722	bus@a800000000 {
3723		compatible = "simple-bus";
3724		#address-cells = <2>;
3725		#size-cells = <2>;
3726
3727		ranges = <0x00 0x00000000 0xa8 0x00000000 0x40 0x00000000>, /* MMIO, ECAM, prefetchable memory, I/O */
3728			 <0x80 0x00000000 0x00 0x20000000 0x00 0x40000000>; /* non-prefetchable memory (32-bit) */
3729	};
3730
3731	cpus {
3732		#address-cells = <1>;
3733		#size-cells = <0>;
3734
3735		cpu0: cpu@0 {
3736			compatible = "arm,armv8";
3737			device_type = "cpu";
3738			reg = <0x00000>;
3739			status = "okay";
3740
3741			enable-method = "psci";
3742
3743			i-cache-size = <65536>;
3744			i-cache-line-size = <64>;
3745			i-cache-sets = <256>;
3746			d-cache-size = <65536>;
3747			d-cache-line-size = <64>;
3748			d-cache-sets = <256>;
3749		};
3750
3751		cpu1: cpu@1 {
3752			compatible = "arm,armv8";
3753			device_type = "cpu";
3754			reg = <0x10000>;
3755			status = "okay";
3756
3757			enable-method = "psci";
3758
3759			i-cache-size = <65536>;
3760			i-cache-line-size = <64>;
3761			i-cache-sets = <256>;
3762			d-cache-size = <65536>;
3763			d-cache-line-size = <64>;
3764			d-cache-sets = <256>;
3765		};
3766	};
3767
3768	bpmp: bpmp {
3769		compatible = "nvidia,tegra264-bpmp", "nvidia,tegra186-bpmp";
3770		mboxes = <&hsp_top TEGRA_HSP_MBOX_TYPE_DB
3771				   TEGRA_HSP_DB_MASTER_BPMP>;
3772		memory-region = <&shmem_bpmp>;
3773		#clock-cells = <1>;
3774		#reset-cells = <1>;
3775		#power-domain-cells = <1>;
3776
3777		i2c {
3778			compatible = "nvidia,tegra186-bpmp-i2c";
3779			nvidia,bpmp-bus-id = <5>;
3780			#address-cells = <1>;
3781			#size-cells = <0>;
3782		};
3783
3784		thermal {
3785			compatible = "nvidia,tegra186-bpmp-thermal";
3786			#thermal-sensor-cells = <1>;
3787		};
3788	};
3789
3790	pmu {
3791		compatible = "arm,armv8-pmuv3";
3792		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
3793		status = "okay";
3794	};
3795
3796	psci {
3797		compatible = "arm,psci-1.0";
3798		status = "okay";
3799		method = "smc";
3800	};
3801
3802	sound {
3803		compatible = "nvidia,tegra264-audio-graph-card";
3804
3805		clocks = <&bpmp TEGRA264_CLK_PLLA1>,
3806				<&bpmp TEGRA264_CLK_PLLA1_OUT1>;
3807		clock-names = "pll_a", "plla_out0";
3808		assigned-clocks = <&bpmp TEGRA264_CLK_PLLA1>,
3809			<&bpmp TEGRA264_CLK_PLLA1_OUT1>,
3810			<&bpmp TEGRA264_CLK_AUD_MCLK>;
3811		assigned-clock-parents = <0>,
3812			<&bpmp TEGRA264_CLK_PLLA1>,
3813			<&bpmp TEGRA264_CLK_PLLA1_OUT1>;
3814
3815		status = "disabled";
3816	};
3817
3818	timer {
3819		compatible = "arm,armv8-timer";
3820		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3821			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3822			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3823			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
3824			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
3825		status = "okay";
3826	};
3827};
3828