1// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 3#include <dt-bindings/clock/nvidia,tegra264.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/nvidia,tegra264.h> 7#include <dt-bindings/reset/nvidia,tegra264.h> 8 9/ { 10 compatible = "nvidia,tegra264"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 reserved-memory { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 ranges; 19 20 shmem_bpmp: shmem@86070000 { 21 compatible = "nvidia,tegra264-bpmp-shmem"; 22 reg = <0x0 0x86070000 0x0 0x2000>; 23 no-map; 24 }; 25 }; 26 27 /* SYSTEM MMIO */ 28 bus@0 { 29 compatible = "simple-bus"; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 ranges = <0x00 0x00000000 0x00 0x00000000 0x01 0x00000000>; 35 36 misc@100000 { 37 compatible = "nvidia,tegra234-misc"; 38 reg = <0x0 0x00100000 0x0 0x0f000>, 39 <0x0 0x0c140000 0x0 0x10000>; 40 }; 41 42 timer@8000000 { 43 compatible = "nvidia,tegra234-timer"; 44 reg = <0x0 0x08000000 0x0 0x140000>; 45 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>; 49 status = "disabled"; 50 }; 51 52 gpcdma: dma-controller@8400000 { 53 compatible = "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma"; 54 reg = <0x0 0x08400000 0x0 0x210000>; 55 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>; 87 #dma-cells = <1>; 88 iommus = <&smmu1 0x00000800>; 89 dma-coherent; 90 dma-channel-mask = <0xfffffffe>; 91 status = "disabled"; 92 }; 93 94 hsp_top: hsp@8800000 { 95 compatible = "nvidia,tegra264-hsp"; 96 reg = <0x0 0x08800000 0x0 0xd0000>; 97 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>; 106 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 107 "shared3", "shared4", "shared5", "shared6", 108 "shared7"; 109 #mbox-cells = <2>; 110 }; 111 112 rtc: rtc@c2c0000 { 113 compatible = "nvidia,tegra264-rtc", "nvidia,tegra20-rtc"; 114 reg = <0x0 0x0c2c0000 0x0 0x10000>; 115 interrupt-parent = <&pmc>; 116 interrupts = <65 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&bpmp TEGRA264_CLK_CLK_S>; 118 clock-names = "rtc"; 119 status = "disabled"; 120 }; 121 122 serial@c4e0000 { 123 compatible = "nvidia,tegra264-utc"; 124 reg = <0x0 0x0c4e0000 0x0 0x8000>, 125 <0x0 0x0c4e8000 0x0 0x8000>; 126 reg-names = "tx", "rx"; 127 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; 128 rx-threshold = <4>; 129 tx-threshold = <4>; 130 status = "disabled"; 131 }; 132 133 serial@c5a0000 { 134 compatible = "nvidia,tegra264-utc"; 135 reg = <0x0 0x0c5a0000 0x0 0x8000>, 136 <0x0 0x0c5a8000 0x0 0x8000>; 137 reg-names = "tx", "rx"; 138 interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>; 139 rx-threshold = <4>; 140 tx-threshold = <4>; 141 status = "disabled"; 142 }; 143 144 uart0: serial@c5f0000 { 145 compatible = "arm,sbsa-uart"; 146 reg = <0x0 0x0c5f0000 0x0 0x10000>; 147 interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>; 148 status = "disabled"; 149 }; 150 151 i2c2: i2c@c600000 { 152 compatible = "nvidia,tegra264-i2c"; 153 reg = <0x0 0x0c600000 0x0 0x10000>; 154 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>; 155 clock-frequency = <400000>; 156 clocks = <&bpmp TEGRA264_CLK_AON_I2C>, 157 <&bpmp TEGRA264_CLK_PLLAON>; 158 clock-names = "div-clk", "parent"; 159 assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>; 160 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>; 161 resets = <&bpmp TEGRA264_RESET_I2C2>; 162 reset-names = "i2c"; 163 status = "disabled"; 164 }; 165 166 i2c3: i2c@c610000 { 167 compatible = "nvidia,tegra264-i2c"; 168 reg = <0x0 0x0c610000 0x0 0x10000>; 169 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 170 clock-frequency = <400000>; 171 clocks = <&bpmp TEGRA264_CLK_AON_I2C>, 172 <&bpmp TEGRA264_CLK_PLLAON>; 173 clock-names = "div-clk", "parent"; 174 assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>; 175 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>; 176 resets = <&bpmp TEGRA264_RESET_I2C3>; 177 reset-names = "i2c"; 178 status = "disabled"; 179 }; 180 181 pmc: pmc@c800000 { 182 compatible = "nvidia,tegra264-pmc"; 183 reg = <0x0 0x0c800000 0x0 0x100000>, 184 <0x0 0x0c990000 0x0 0x10000>, 185 <0x0 0x0ca00000 0x0 0x10000>, 186 <0x0 0x0c980000 0x0 0x10000>, 187 <0x0 0x0c9c0000 0x0 0x40000>; 188 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 189 #interrupt-cells = <2>; 190 interrupt-controller; 191 }; 192 }; 193 194 /* TOP_MMIO */ 195 bus@8100000000 { 196 compatible = "simple-bus"; 197 198 #address-cells = <2>; 199 #size-cells = <2>; 200 201 ranges = <0x00 0x00000000 0x81 0x00000000 0x01 0x00000000>, /* MMIO */ 202 <0x01 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */ 203 <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */ 204 205 smmu1: iommu@5000000 { 206 compatible = "arm,smmu-v3"; 207 reg = <0x00 0x5000000 0x0 0x200000>; 208 interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>, 209 <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>; 210 interrupt-names = "eventq", "gerror"; 211 status = "disabled"; 212 213 #iommu-cells = <1>; 214 dma-coherent; 215 }; 216 217 smmu2: iommu@6000000 { 218 compatible = "arm,smmu-v3"; 219 reg = <0x00 0x6000000 0x0 0x200000>; 220 interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>, 221 <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; 222 interrupt-names = "eventq", "gerror"; 223 status = "disabled"; 224 225 #iommu-cells = <1>; 226 dma-coherent; 227 }; 228 229 mc: memory-controller@8020000 { 230 compatible = "nvidia,tegra264-mc"; 231 reg = <0x00 0x8020000 0x0 0x20000>, /* MC broadcast */ 232 <0x00 0x8040000 0x0 0x20000>, /* MC 0 */ 233 <0x00 0x8060000 0x0 0x20000>, /* MC 1 */ 234 <0x00 0x8080000 0x0 0x20000>, /* MC 2 */ 235 <0x00 0x80a0000 0x0 0x20000>, /* MC 3 */ 236 <0x00 0x80c0000 0x0 0x20000>, /* MC 4 */ 237 <0x00 0x80e0000 0x0 0x20000>, /* MC 5 */ 238 <0x00 0x8100000 0x0 0x20000>, /* MC 6 */ 239 <0x00 0x8120000 0x0 0x20000>, /* MC 7 */ 240 <0x00 0x8140000 0x0 0x20000>, /* MC 8 */ 241 <0x00 0x8160000 0x0 0x20000>, /* MC 9 */ 242 <0x00 0x8180000 0x0 0x20000>, /* MC 10 */ 243 <0x00 0x81a0000 0x0 0x20000>, /* MC 11 */ 244 <0x00 0x81c0000 0x0 0x20000>, /* MC 12 */ 245 <0x00 0x81e0000 0x0 0x20000>, /* MC 13 */ 246 <0x00 0x8200000 0x0 0x20000>, /* MC 14 */ 247 <0x00 0x8220000 0x0 0x20000>; /* MC 15 */ 248 reg-names = "broadcast", "ch0", "ch1", "ch2", "ch3", 249 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", 250 "ch10", "ch11", "ch12", "ch13", "ch14", 251 "ch15"; 252 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 260 #interconnect-cells = <1>; 261 262 #address-cells = <2>; 263 #size-cells = <2>; 264 265 /* limit the DMA range for memory clients to [39:0] */ 266 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 267 268 emc: external-memory-controller@8800000 { 269 compatible = "nvidia,tegra264-emc"; 270 reg = <0x00 0x8800000 0x0 0x20000>, 271 <0x00 0x8890000 0x0 0x20000>; 272 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&bpmp TEGRA264_CLK_EMC>; 274 clock-names = "emc"; 275 276 #interconnect-cells = <0>; 277 nvidia,bpmp = <&bpmp>; 278 }; 279 }; 280 281 smmu0: iommu@a000000 { 282 compatible = "arm,smmu-v3"; 283 reg = <0x00 0xa000000 0x0 0x200000>; 284 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 285 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 286 interrupt-names = "eventq", "gerror"; 287 status = "disabled"; 288 289 #iommu-cells = <1>; 290 dma-coherent; 291 }; 292 293 smmu4: iommu@b000000 { 294 compatible = "arm,smmu-v3"; 295 reg = <0x00 0xb000000 0x0 0x200000>; 296 interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 297 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; 298 interrupt-names = "eventq", "gerror"; 299 status = "disabled"; 300 301 #iommu-cells = <1>; 302 dma-coherent; 303 }; 304 305 i2c14: i2c@c410000 { 306 compatible = "nvidia,tegra264-i2c"; 307 reg = <0x00 0x0c410000 0x0 0x10000>; 308 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 309 clock-frequency = <400000>; 310 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 311 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 312 clock-names = "div-clk", "parent"; 313 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 314 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 315 resets = <&bpmp TEGRA264_RESET_I2C14>; 316 reset-names = "i2c"; 317 status = "disabled"; 318 }; 319 320 i2c15: i2c@c420000 { 321 compatible = "nvidia,tegra264-i2c"; 322 reg = <0x00 0x0c420000 0x0 0x10000>; 323 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 324 clock-frequency = <400000>; 325 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 326 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 327 clock-names = "div-clk", "parent"; 328 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 329 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 330 resets = <&bpmp TEGRA264_RESET_I2C15>; 331 reset-names = "i2c"; 332 status = "disabled"; 333 }; 334 335 i2c16: i2c@c430000 { 336 compatible = "nvidia,tegra264-i2c"; 337 reg = <0x00 0x0c430000 0x0 0x10000>; 338 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 339 clock-frequency = <400000>; 340 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 341 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 342 clock-names = "div-clk", "parent"; 343 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 344 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 345 resets = <&bpmp TEGRA264_RESET_I2C16>; 346 reset-names = "i2c"; 347 status = "disabled"; 348 }; 349 350 i2c0: i2c@c630000 { 351 compatible = "nvidia,tegra264-i2c"; 352 reg = <0x00 0x0c630000 0x0 0x10000>; 353 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 354 clock-frequency = <400000>; 355 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 356 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 357 clock-names = "div-clk", "parent"; 358 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 359 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 360 resets = <&bpmp TEGRA264_RESET_I2C0>; 361 reset-names = "i2c"; 362 status = "disabled"; 363 }; 364 365 i2c1: i2c@c640000 { 366 compatible = "nvidia,tegra264-i2c"; 367 reg = <0x00 0x0c640000 0x0 0x10000>; 368 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 369 clock-frequency = <400000>; 370 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 371 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 372 clock-names = "div-clk", "parent"; 373 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 374 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 375 resets = <&bpmp TEGRA264_RESET_I2C1>; 376 reset-names = "i2c"; 377 status = "disabled"; 378 }; 379 380 i2c4: i2c@c650000 { 381 compatible = "nvidia,tegra264-i2c"; 382 reg = <0x00 0x0c650000 0x0 0x10000>; 383 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 384 clock-frequency = <400000>; 385 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 386 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 387 clock-names = "div-clk", "parent"; 388 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 389 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 390 resets = <&bpmp TEGRA264_RESET_I2C4>; 391 reset-names = "i2c"; 392 status = "disabled"; 393 }; 394 395 i2c6: i2c@c670000 { 396 compatible = "nvidia,tegra264-i2c"; 397 reg = <0x00 0x0c670000 0x0 0x10000>; 398 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 399 clock-frequency = <400000>; 400 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 401 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 402 clock-names = "div-clk", "parent"; 403 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 404 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 405 resets = <&bpmp TEGRA264_RESET_I2C6>; 406 reset-names = "i2c"; 407 status = "disabled"; 408 }; 409 410 i2c7: i2c@c680000 { 411 compatible = "nvidia,tegra264-i2c"; 412 reg = <0x00 0x0c680000 0x0 0x10000>; 413 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 414 clock-frequency = <400000>; 415 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 416 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 417 clock-names = "div-clk", "parent"; 418 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 419 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 420 resets = <&bpmp TEGRA264_RESET_I2C7>; 421 reset-names = "i2c"; 422 status = "disabled"; 423 }; 424 425 i2c8: i2c@c690000 { 426 compatible = "nvidia,tegra264-i2c"; 427 reg = <0x00 0x0c690000 0x0 0x10000>; 428 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 429 clock-frequency = <400000>; 430 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 431 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 432 clock-names = "div-clk", "parent"; 433 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 434 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 435 resets = <&bpmp TEGRA264_RESET_I2C8>; 436 reset-names = "i2c"; 437 status = "disabled"; 438 }; 439 440 i2c9: i2c@c6a0000 { 441 compatible = "nvidia,tegra264-i2c"; 442 reg = <0x00 0x0c6a0000 0x0 0x10000>; 443 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 444 clock-frequency = <400000>; 445 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 446 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 447 clock-names = "div-clk", "parent"; 448 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 449 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 450 resets = <&bpmp TEGRA264_RESET_I2C9>; 451 reset-names = "i2c"; 452 status = "disabled"; 453 }; 454 455 i2c10: i2c@c6b0000 { 456 compatible = "nvidia,tegra264-i2c"; 457 reg = <0x00 0x0c6b0000 0x0 0x10000>; 458 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 459 clock-frequency = <400000>; 460 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 461 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 462 clock-names = "div-clk", "parent"; 463 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 464 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 465 resets = <&bpmp TEGRA264_RESET_I2C10>; 466 reset-names = "i2c"; 467 status = "disabled"; 468 }; 469 470 i2c11: i2c@c6c0000 { 471 compatible = "nvidia,tegra264-i2c"; 472 reg = <0x00 0x0c6c0000 0x0 0x10000>; 473 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 474 clock-frequency = <400000>; 475 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 476 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 477 clock-names = "div-clk", "parent"; 478 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 479 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 480 resets = <&bpmp TEGRA264_RESET_I2C11>; 481 reset-names = "i2c"; 482 status = "disabled"; 483 }; 484 485 i2c12: i2c@c6d0000 { 486 compatible = "nvidia,tegra264-i2c"; 487 reg = <0x00 0x0c6d0000 0x0 0x10000>; 488 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 489 clock-frequency = <400000>; 490 clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, 491 <&bpmp TEGRA264_CLK_PLLP_OUT0>; 492 clock-names = "div-clk", "parent"; 493 assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; 494 assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; 495 resets = <&bpmp TEGRA264_RESET_I2C12>; 496 reset-names = "i2c"; 497 status = "disabled"; 498 }; 499 500 gic: interrupt-controller@46000000 { 501 compatible = "arm,gic-v3"; 502 reg = <0x00 0x46000000 0x0 0x010000>, /* GICD */ 503 <0x00 0x46080000 0x0 0x400000>; /* GICR */ 504 interrupt-parent = <&gic>; 505 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 506 507 redistributor-stride = <0x0 0x40000>; 508 #redistributor-regions = <1>; 509 #interrupt-cells = <3>; 510 interrupt-controller; 511 512 #address-cells = <2>; 513 #size-cells = <2>; 514 515 ranges = <0x0 0x0 0x00 0x46000000 0x0 0x1000000>; 516 517 its: msi-controller@40000 { 518 compatible = "arm,gic-v3-its"; 519 reg = <0x0 0x40000 0x0 0x40000>; 520 #msi-cells = <1>; 521 msi-controller; 522 }; 523 }; 524 }; 525 526 /* DISP_USB MMIO */ 527 bus@8800000000 { 528 compatible = "simple-bus"; 529 #address-cells = <2>; 530 #size-cells = <2>; 531 532 ranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>; 533 534 smmu3: iommu@6000000 { 535 compatible = "arm,smmu-v3"; 536 reg = <0x00 0x6000000 0x0 0x200000>; 537 interrupts = <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>, 538 <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>; 539 interrupt-names = "eventq", "gerror"; 540 status = "disabled"; 541 542 #iommu-cells = <1>; 543 dma-coherent; 544 }; 545 }; 546 547 /* UPHY MMIO */ 548 bus@a800000000 { 549 compatible = "simple-bus"; 550 #address-cells = <2>; 551 #size-cells = <2>; 552 553 ranges = <0x00 0x00000000 0xa8 0x00000000 0x40 0x00000000>, /* MMIO, ECAM, prefetchable memory, I/O */ 554 <0x80 0x00000000 0x00 0x20000000 0x00 0x40000000>; /* non-prefetchable memory (32-bit) */ 555 }; 556 557 cpus { 558 #address-cells = <1>; 559 #size-cells = <0>; 560 561 cpu0: cpu@0 { 562 compatible = "arm,armv8"; 563 device_type = "cpu"; 564 reg = <0x00000>; 565 status = "okay"; 566 567 enable-method = "psci"; 568 569 i-cache-size = <65536>; 570 i-cache-line-size = <64>; 571 i-cache-sets = <256>; 572 d-cache-size = <65536>; 573 d-cache-line-size = <64>; 574 d-cache-sets = <256>; 575 }; 576 577 cpu1: cpu@1 { 578 compatible = "arm,armv8"; 579 device_type = "cpu"; 580 reg = <0x10000>; 581 status = "okay"; 582 583 enable-method = "psci"; 584 585 i-cache-size = <65536>; 586 i-cache-line-size = <64>; 587 i-cache-sets = <256>; 588 d-cache-size = <65536>; 589 d-cache-line-size = <64>; 590 d-cache-sets = <256>; 591 }; 592 }; 593 594 bpmp: bpmp { 595 compatible = "nvidia,tegra264-bpmp", "nvidia,tegra186-bpmp"; 596 mboxes = <&hsp_top TEGRA_HSP_MBOX_TYPE_DB 597 TEGRA_HSP_DB_MASTER_BPMP>; 598 memory-region = <&shmem_bpmp>; 599 #clock-cells = <1>; 600 #reset-cells = <1>; 601 #power-domain-cells = <1>; 602 603 i2c { 604 compatible = "nvidia,tegra186-bpmp-i2c"; 605 nvidia,bpmp-bus-id = <5>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 }; 609 610 thermal { 611 compatible = "nvidia,tegra186-bpmp-thermal"; 612 #thermal-sensor-cells = <1>; 613 }; 614 }; 615 616 pmu { 617 compatible = "arm,armv8-pmuv3"; 618 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 619 status = "okay"; 620 }; 621 622 psci { 623 compatible = "arm,psci-1.0"; 624 status = "okay"; 625 method = "smc"; 626 }; 627 628 timer { 629 compatible = "arm,armv8-timer"; 630 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 631 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 632 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 633 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 634 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 635 status = "okay"; 636 }; 637}; 638