1// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 3#include <dt-bindings/clock/nvidia,tegra264.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/nvidia,tegra264.h> 7#include <dt-bindings/reset/nvidia,tegra264.h> 8 9/ { 10 compatible = "nvidia,tegra264"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 numa-node-id = <0>; 15 16 reserved-memory { 17 #address-cells = <2>; 18 #size-cells = <2>; 19 ranges; 20 21 shmem_bpmp: shmem@86070000 { 22 compatible = "nvidia,tegra264-bpmp-shmem"; 23 reg = <0x0 0x86070000 0x0 0x2000>; 24 no-map; 25 }; 26 }; 27 28 /* SYSTEM MMIO */ 29 bus@0 { 30 compatible = "simple-bus"; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 ranges = <0x00 0x00000000 0x00 0x00000000 0x01 0x00000000>; 36 37 misc@100000 { 38 compatible = "nvidia,tegra234-misc"; 39 reg = <0x0 0x00100000 0x0 0x0f000>, 40 <0x0 0x0c140000 0x0 0x10000>; 41 }; 42 43 timer@8000000 { 44 compatible = "nvidia,tegra234-timer"; 45 reg = <0x0 0x08000000 0x0 0x140000>; 46 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>; 50 status = "disabled"; 51 }; 52 53 gpcdma: dma-controller@8400000 { 54 compatible = "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma"; 55 reg = <0x0 0x08400000 0x0 0x210000>; 56 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>; 88 #dma-cells = <1>; 89 iommus = <&smmu1 0x00000800>; 90 dma-coherent; 91 dma-channel-mask = <0xfffffffe>; 92 status = "disabled"; 93 }; 94 95 hsp_top: hsp@8800000 { 96 compatible = "nvidia,tegra264-hsp"; 97 reg = <0x0 0x08800000 0x0 0xd0000>; 98 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>; 107 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 108 "shared3", "shared4", "shared5", "shared6", 109 "shared7"; 110 #mbox-cells = <2>; 111 }; 112 113 rtc: rtc@c2c0000 { 114 compatible = "nvidia,tegra264-rtc", "nvidia,tegra20-rtc"; 115 reg = <0x0 0x0c2c0000 0x0 0x10000>; 116 interrupt-parent = <&pmc>; 117 interrupts = <65 IRQ_TYPE_LEVEL_HIGH>; 118 clocks = <&bpmp TEGRA264_CLK_CLK_S>; 119 clock-names = "rtc"; 120 status = "disabled"; 121 }; 122 123 serial@c4e0000 { 124 compatible = "nvidia,tegra264-utc"; 125 reg = <0x0 0x0c4e0000 0x0 0x8000>, 126 <0x0 0x0c4e8000 0x0 0x8000>; 127 reg-names = "tx", "rx"; 128 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; 129 rx-threshold = <4>; 130 tx-threshold = <4>; 131 status = "disabled"; 132 }; 133 134 serial@c5a0000 { 135 compatible = "nvidia,tegra264-utc"; 136 reg = <0x0 0x0c5a0000 0x0 0x8000>, 137 <0x0 0x0c5a8000 0x0 0x8000>; 138 reg-names = "tx", "rx"; 139 interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>; 140 rx-threshold = <4>; 141 tx-threshold = <4>; 142 status = "disabled"; 143 }; 144 145 uart0: serial@c5f0000 { 146 compatible = "arm,sbsa-uart"; 147 reg = <0x0 0x0c5f0000 0x0 0x10000>; 148 interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>; 149 status = "disabled"; 150 }; 151 152 pmc: pmc@c800000 { 153 compatible = "nvidia,tegra264-pmc"; 154 reg = <0x0 0x0c800000 0x0 0x100000>, 155 <0x0 0x0c990000 0x0 0x10000>, 156 <0x0 0x0ca00000 0x0 0x10000>, 157 <0x0 0x0c980000 0x0 0x10000>, 158 <0x0 0x0c9c0000 0x0 0x40000>; 159 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 160 #interrupt-cells = <2>; 161 interrupt-controller; 162 }; 163 }; 164 165 /* TOP_MMIO */ 166 bus@8100000000 { 167 compatible = "simple-bus"; 168 169 #address-cells = <2>; 170 #size-cells = <2>; 171 172 ranges = <0x00 0x00000000 0x81 0x00000000 0x01 0x00000000>, /* MMIO */ 173 <0x01 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */ 174 <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */ 175 176 smmu1: iommu@5000000 { 177 compatible = "arm,smmu-v3"; 178 reg = <0x00 0x5000000 0x0 0x200000>; 179 interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>, 180 <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>; 181 interrupt-names = "eventq", "gerror"; 182 status = "disabled"; 183 184 #iommu-cells = <1>; 185 dma-coherent; 186 }; 187 188 smmu2: iommu@6000000 { 189 compatible = "arm,smmu-v3"; 190 reg = <0x00 0x6000000 0x0 0x200000>; 191 interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>, 192 <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; 193 interrupt-names = "eventq", "gerror"; 194 status = "disabled"; 195 196 #iommu-cells = <1>; 197 dma-coherent; 198 }; 199 200 mc: memory-controller@8020000 { 201 compatible = "nvidia,tegra264-mc"; 202 reg = <0x00 0x8020000 0x0 0x20000>, /* MC broadcast */ 203 <0x00 0x8040000 0x0 0x20000>, /* MC 0 */ 204 <0x00 0x8060000 0x0 0x20000>, /* MC 1 */ 205 <0x00 0x8080000 0x0 0x20000>, /* MC 2 */ 206 <0x00 0x80a0000 0x0 0x20000>, /* MC 3 */ 207 <0x00 0x80c0000 0x0 0x20000>, /* MC 4 */ 208 <0x00 0x80e0000 0x0 0x20000>, /* MC 5 */ 209 <0x00 0x8100000 0x0 0x20000>, /* MC 6 */ 210 <0x00 0x8120000 0x0 0x20000>, /* MC 7 */ 211 <0x00 0x8140000 0x0 0x20000>, /* MC 8 */ 212 <0x00 0x8160000 0x0 0x20000>, /* MC 9 */ 213 <0x00 0x8180000 0x0 0x20000>, /* MC 10 */ 214 <0x00 0x81a0000 0x0 0x20000>, /* MC 11 */ 215 <0x00 0x81c0000 0x0 0x20000>, /* MC 12 */ 216 <0x00 0x81e0000 0x0 0x20000>, /* MC 13 */ 217 <0x00 0x8200000 0x0 0x20000>, /* MC 14 */ 218 <0x00 0x8220000 0x0 0x20000>; /* MC 15 */ 219 reg-names = "broadcast", "ch0", "ch1", "ch2", "ch3", 220 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", 221 "ch10", "ch11", "ch12", "ch13", "ch14", 222 "ch15"; 223 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 231 #interconnect-cells = <1>; 232 233 #address-cells = <2>; 234 #size-cells = <2>; 235 236 /* limit the DMA range for memory clients to [39:0] */ 237 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 238 239 emc: external-memory-controller@8800000 { 240 compatible = "nvidia,tegra264-emc"; 241 reg = <0x00 0x8800000 0x0 0x20000>, 242 <0x00 0x8890000 0x0 0x20000>; 243 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&bpmp TEGRA264_CLK_EMC>; 245 clock-names = "emc"; 246 247 #interconnect-cells = <0>; 248 nvidia,bpmp = <&bpmp>; 249 }; 250 }; 251 252 smmu0: iommu@a000000 { 253 compatible = "arm,smmu-v3"; 254 reg = <0x00 0xa000000 0x0 0x200000>; 255 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 256 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 257 interrupt-names = "eventq", "gerror"; 258 status = "disabled"; 259 260 #iommu-cells = <1>; 261 dma-coherent; 262 }; 263 264 smmu4: iommu@b000000 { 265 compatible = "arm,smmu-v3"; 266 reg = <0x00 0xb000000 0x0 0x200000>; 267 interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 268 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; 269 interrupt-names = "eventq", "gerror"; 270 status = "disabled"; 271 272 #iommu-cells = <1>; 273 dma-coherent; 274 }; 275 276 gic: interrupt-controller@46000000 { 277 compatible = "arm,gic-v3"; 278 reg = <0x00 0x46000000 0x0 0x010000>, /* GICD */ 279 <0x00 0x46080000 0x0 0x400000>; /* GICR */ 280 interrupt-parent = <&gic>; 281 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 282 283 redistributor-stride = <0x0 0x40000>; 284 #redistributor-regions = <1>; 285 #interrupt-cells = <3>; 286 interrupt-controller; 287 288 #address-cells = <2>; 289 #size-cells = <2>; 290 291 ranges = <0x0 0x0 0x00 0x46000000 0x0 0x1000000>; 292 293 its: msi-controller@40000 { 294 compatible = "arm,gic-v3-its"; 295 reg = <0x0 0x40000 0x0 0x40000>; 296 #msi-cells = <1>; 297 msi-controller; 298 }; 299 }; 300 }; 301 302 /* DISP_USB MMIO */ 303 bus@8800000000 { 304 compatible = "simple-bus"; 305 #address-cells = <2>; 306 #size-cells = <2>; 307 308 ranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>; 309 310 smmu3: iommu@6000000 { 311 compatible = "arm,smmu-v3"; 312 reg = <0x00 0x6000000 0x0 0x200000>; 313 interrupts = <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>, 314 <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>; 315 interrupt-names = "eventq", "gerror"; 316 status = "disabled"; 317 318 #iommu-cells = <1>; 319 dma-coherent; 320 }; 321 }; 322 323 /* UPHY MMIO */ 324 bus@a800000000 { 325 compatible = "simple-bus"; 326 #address-cells = <2>; 327 #size-cells = <2>; 328 329 ranges = <0x00 0x00000000 0xa8 0x00000000 0x40 0x00000000>, /* MMIO, ECAM, prefetchable memory, I/O */ 330 <0x80 0x00000000 0x00 0x20000000 0x00 0x40000000>; /* non-prefetchable memory (32-bit) */ 331 }; 332 333 cpus { 334 #address-cells = <1>; 335 #size-cells = <0>; 336 337 cpu0: cpu@0 { 338 compatible = "arm,armv8"; 339 device_type = "cpu"; 340 reg = <0x00000>; 341 status = "okay"; 342 343 enable-method = "psci"; 344 numa-node-id = <0>; 345 346 i-cache-size = <65536>; 347 i-cache-line-size = <64>; 348 i-cache-sets = <256>; 349 d-cache-size = <65536>; 350 d-cache-line-size = <64>; 351 d-cache-sets = <256>; 352 }; 353 354 cpu1: cpu@1 { 355 compatible = "arm,armv8"; 356 device_type = "cpu"; 357 reg = <0x10000>; 358 status = "okay"; 359 360 enable-method = "psci"; 361 numa-node-id = <0>; 362 363 i-cache-size = <65536>; 364 i-cache-line-size = <64>; 365 i-cache-sets = <256>; 366 d-cache-size = <65536>; 367 d-cache-line-size = <64>; 368 d-cache-sets = <256>; 369 }; 370 }; 371 372 bpmp: bpmp { 373 compatible = "nvidia,tegra264-bpmp", "nvidia,tegra186-bpmp"; 374 mboxes = <&hsp_top TEGRA_HSP_MBOX_TYPE_DB 375 TEGRA_HSP_DB_MASTER_BPMP>; 376 memory-region = <&shmem_bpmp>; 377 #clock-cells = <1>; 378 #reset-cells = <1>; 379 #power-domain-cells = <1>; 380 381 i2c { 382 compatible = "nvidia,tegra186-bpmp-i2c"; 383 nvidia,bpmp-bus-id = <5>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 }; 387 388 thermal { 389 compatible = "nvidia,tegra186-bpmp-thermal"; 390 #thermal-sensor-cells = <1>; 391 }; 392 }; 393 394 pmu { 395 compatible = "arm,armv8-pmuv3"; 396 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 397 status = "okay"; 398 }; 399 400 psci { 401 compatible = "arm,psci-1.0"; 402 status = "okay"; 403 method = "smc"; 404 }; 405 406 timer { 407 compatible = "arm,armv8-timer"; 408 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 409 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 410 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 411 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 412 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 413 status = "okay"; 414 }; 415}; 416