1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra234-mc.h> 7#include <dt-bindings/reset/tegra234-reset.h> 8 9/ { 10 compatible = "nvidia,tegra234"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 bus@0 { 16 compatible = "simple-bus"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 ranges = <0x0 0x0 0x0 0x40000000>; 21 22 misc@100000 { 23 compatible = "nvidia,tegra234-misc"; 24 reg = <0x00100000 0xf000>, 25 <0x0010f000 0x1000>; 26 status = "okay"; 27 }; 28 29 gpio: gpio@2200000 { 30 compatible = "nvidia,tegra234-gpio"; 31 reg-names = "security", "gpio"; 32 reg = <0x02200000 0x10000>, 33 <0x02210000 0x10000>; 34 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 82 #interrupt-cells = <2>; 83 interrupt-controller; 84 #gpio-cells = <2>; 85 gpio-controller; 86 }; 87 88 mc: memory-controller@2c00000 { 89 compatible = "nvidia,tegra234-mc"; 90 reg = <0x02c00000 0x100000>, 91 <0x02b80000 0x040000>, 92 <0x01700000 0x100000>; 93 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 94 #interconnect-cells = <1>; 95 status = "okay"; 96 97 #address-cells = <2>; 98 #size-cells = <2>; 99 100 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 101 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 102 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 103 104 /* 105 * Bit 39 of addresses passing through the memory 106 * controller selects the XBAR format used when memory 107 * is accessed. This is used to transparently access 108 * memory in the XBAR format used by the discrete GPU 109 * (bit 39 set) or Tegra (bit 39 clear). 110 * 111 * As a consequence, the operating system must ensure 112 * that bit 39 is never used implicitly, for example 113 * via an I/O virtual address mapping of an IOMMU. If 114 * devices require access to the XBAR switch, their 115 * drivers must set this bit explicitly. 116 * 117 * Limit the DMA range for memory clients to [38:0]. 118 */ 119 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 120 121 emc: external-memory-controller@2c60000 { 122 compatible = "nvidia,tegra234-emc"; 123 reg = <0x0 0x02c60000 0x0 0x90000>, 124 <0x0 0x01780000 0x0 0x80000>; 125 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 126 clocks = <&bpmp TEGRA234_CLK_EMC>; 127 clock-names = "emc"; 128 status = "okay"; 129 130 #interconnect-cells = <0>; 131 132 nvidia,bpmp = <&bpmp>; 133 }; 134 }; 135 136 uarta: serial@3100000 { 137 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 138 reg = <0x03100000 0x10000>; 139 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&bpmp TEGRA234_CLK_UARTA>; 141 clock-names = "serial"; 142 resets = <&bpmp TEGRA234_RESET_UARTA>; 143 reset-names = "serial"; 144 status = "disabled"; 145 }; 146 147 mmc@3460000 { 148 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 149 reg = <0x03460000 0x20000>; 150 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 151 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 152 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 153 clock-names = "sdhci", "tmclk"; 154 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 155 <&bpmp TEGRA234_CLK_PLLC4>; 156 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 157 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 158 reset-names = "sdhci"; 159 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 160 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 161 interconnect-names = "dma-mem", "write"; 162 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 163 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 164 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 165 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 166 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 167 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 168 nvidia,default-tap = <0x8>; 169 nvidia,default-trim = <0x14>; 170 nvidia,dqs-trim = <40>; 171 supports-cqe; 172 status = "disabled"; 173 }; 174 175 fuse@3810000 { 176 compatible = "nvidia,tegra234-efuse"; 177 reg = <0x03810000 0x10000>; 178 clocks = <&bpmp TEGRA234_CLK_FUSE>; 179 clock-names = "fuse"; 180 }; 181 182 hsp_top0: hsp@3c00000 { 183 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 184 reg = <0x03c00000 0xa0000>; 185 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 194 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 195 "shared3", "shared4", "shared5", "shared6", 196 "shared7"; 197 #mbox-cells = <2>; 198 }; 199 200 hsp_aon: hsp@c150000 { 201 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 202 reg = <0x0c150000 0x90000>; 203 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 207 /* 208 * Shared interrupt 0 is routed only to AON/SPE, so 209 * we only have 4 shared interrupts for the CCPLEX. 210 */ 211 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 212 #mbox-cells = <2>; 213 }; 214 215 rtc@c2a0000 { 216 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 217 reg = <0x0c2a0000 0x10000>; 218 interrupt-parent = <&pmc>; 219 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 221 clock-names = "rtc"; 222 status = "disabled"; 223 }; 224 225 gpio_aon: gpio@c2f0000 { 226 compatible = "nvidia,tegra234-gpio-aon"; 227 reg-names = "security", "gpio"; 228 reg = <0x0c2f0000 0x1000>, 229 <0x0c2f1000 0x1000>; 230 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 234 #interrupt-cells = <2>; 235 interrupt-controller; 236 #gpio-cells = <2>; 237 gpio-controller; 238 }; 239 240 pmc: pmc@c360000 { 241 compatible = "nvidia,tegra234-pmc"; 242 reg = <0x0c360000 0x10000>, 243 <0x0c370000 0x10000>, 244 <0x0c380000 0x10000>, 245 <0x0c390000 0x10000>, 246 <0x0c3a0000 0x10000>; 247 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 248 249 #interrupt-cells = <2>; 250 interrupt-controller; 251 }; 252 253 gic: interrupt-controller@f400000 { 254 compatible = "arm,gic-v3"; 255 reg = <0x0f400000 0x010000>, /* GICD */ 256 <0x0f440000 0x200000>; /* GICR */ 257 interrupt-parent = <&gic>; 258 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 259 260 #redistributor-regions = <1>; 261 #interrupt-cells = <3>; 262 interrupt-controller; 263 }; 264 }; 265 266 sram@40000000 { 267 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 268 reg = <0x0 0x40000000 0x0 0x80000>; 269 #address-cells = <1>; 270 #size-cells = <1>; 271 ranges = <0x0 0x0 0x40000000 0x80000>; 272 273 cpu_bpmp_tx: sram@70000 { 274 reg = <0x70000 0x1000>; 275 label = "cpu-bpmp-tx"; 276 pool; 277 }; 278 279 cpu_bpmp_rx: sram@71000 { 280 reg = <0x71000 0x1000>; 281 label = "cpu-bpmp-rx"; 282 pool; 283 }; 284 }; 285 286 bpmp: bpmp { 287 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 288 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 289 TEGRA_HSP_DB_MASTER_BPMP>; 290 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 291 #clock-cells = <1>; 292 #reset-cells = <1>; 293 #power-domain-cells = <1>; 294 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 295 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 296 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 297 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 298 interconnect-names = "read", "write", "dma-mem", "dma-write"; 299 300 bpmp_i2c: i2c { 301 compatible = "nvidia,tegra186-bpmp-i2c"; 302 nvidia,bpmp-bus-id = <5>; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 }; 306 }; 307 308 cpus { 309 #address-cells = <1>; 310 #size-cells = <0>; 311 312 cpu0_0: cpu@0 { 313 compatible = "arm,cortex-a78"; 314 device_type = "cpu"; 315 reg = <0x00000>; 316 317 enable-method = "psci"; 318 319 i-cache-size = <65536>; 320 i-cache-line-size = <64>; 321 i-cache-sets = <256>; 322 d-cache-size = <65536>; 323 d-cache-line-size = <64>; 324 d-cache-sets = <256>; 325 next-level-cache = <&l2c0_0>; 326 }; 327 328 cpu0_1: cpu@100 { 329 compatible = "arm,cortex-a78"; 330 device_type = "cpu"; 331 reg = <0x00100>; 332 333 enable-method = "psci"; 334 335 i-cache-size = <65536>; 336 i-cache-line-size = <64>; 337 i-cache-sets = <256>; 338 d-cache-size = <65536>; 339 d-cache-line-size = <64>; 340 d-cache-sets = <256>; 341 next-level-cache = <&l2c0_1>; 342 }; 343 344 cpu0_2: cpu@200 { 345 compatible = "arm,cortex-a78"; 346 device_type = "cpu"; 347 reg = <0x00200>; 348 349 enable-method = "psci"; 350 351 i-cache-size = <65536>; 352 i-cache-line-size = <64>; 353 i-cache-sets = <256>; 354 d-cache-size = <65536>; 355 d-cache-line-size = <64>; 356 d-cache-sets = <256>; 357 next-level-cache = <&l2c0_2>; 358 }; 359 360 cpu0_3: cpu@300 { 361 compatible = "arm,cortex-a78"; 362 device_type = "cpu"; 363 reg = <0x00300>; 364 365 enable-method = "psci"; 366 367 i-cache-size = <65536>; 368 i-cache-line-size = <64>; 369 i-cache-sets = <256>; 370 d-cache-size = <65536>; 371 d-cache-line-size = <64>; 372 d-cache-sets = <256>; 373 next-level-cache = <&l2c0_3>; 374 }; 375 376 cpu1_0: cpu@10000 { 377 compatible = "arm,cortex-a78"; 378 device_type = "cpu"; 379 reg = <0x10000>; 380 381 enable-method = "psci"; 382 383 i-cache-size = <65536>; 384 i-cache-line-size = <64>; 385 i-cache-sets = <256>; 386 d-cache-size = <65536>; 387 d-cache-line-size = <64>; 388 d-cache-sets = <256>; 389 next-level-cache = <&l2c1_0>; 390 }; 391 392 cpu1_1: cpu@10100 { 393 compatible = "arm,cortex-a78"; 394 device_type = "cpu"; 395 reg = <0x10100>; 396 397 enable-method = "psci"; 398 399 i-cache-size = <65536>; 400 i-cache-line-size = <64>; 401 i-cache-sets = <256>; 402 d-cache-size = <65536>; 403 d-cache-line-size = <64>; 404 d-cache-sets = <256>; 405 next-level-cache = <&l2c1_1>; 406 }; 407 408 cpu1_2: cpu@10200 { 409 compatible = "arm,cortex-a78"; 410 device_type = "cpu"; 411 reg = <0x10200>; 412 413 enable-method = "psci"; 414 415 i-cache-size = <65536>; 416 i-cache-line-size = <64>; 417 i-cache-sets = <256>; 418 d-cache-size = <65536>; 419 d-cache-line-size = <64>; 420 d-cache-sets = <256>; 421 next-level-cache = <&l2c1_2>; 422 }; 423 424 cpu1_3: cpu@10300 { 425 compatible = "arm,cortex-a78"; 426 device_type = "cpu"; 427 reg = <0x10300>; 428 429 enable-method = "psci"; 430 431 i-cache-size = <65536>; 432 i-cache-line-size = <64>; 433 i-cache-sets = <256>; 434 d-cache-size = <65536>; 435 d-cache-line-size = <64>; 436 d-cache-sets = <256>; 437 next-level-cache = <&l2c1_3>; 438 }; 439 440 cpu2_0: cpu@20000 { 441 compatible = "arm,cortex-a78"; 442 device_type = "cpu"; 443 reg = <0x20000>; 444 445 enable-method = "psci"; 446 447 i-cache-size = <65536>; 448 i-cache-line-size = <64>; 449 i-cache-sets = <256>; 450 d-cache-size = <65536>; 451 d-cache-line-size = <64>; 452 d-cache-sets = <256>; 453 next-level-cache = <&l2c2_0>; 454 }; 455 456 cpu2_1: cpu@20100 { 457 compatible = "arm,cortex-a78"; 458 device_type = "cpu"; 459 reg = <0x20100>; 460 461 enable-method = "psci"; 462 463 i-cache-size = <65536>; 464 i-cache-line-size = <64>; 465 i-cache-sets = <256>; 466 d-cache-size = <65536>; 467 d-cache-line-size = <64>; 468 d-cache-sets = <256>; 469 next-level-cache = <&l2c2_1>; 470 }; 471 472 cpu2_2: cpu@20200 { 473 compatible = "arm,cortex-a78"; 474 device_type = "cpu"; 475 reg = <0x20200>; 476 477 enable-method = "psci"; 478 479 i-cache-size = <65536>; 480 i-cache-line-size = <64>; 481 i-cache-sets = <256>; 482 d-cache-size = <65536>; 483 d-cache-line-size = <64>; 484 d-cache-sets = <256>; 485 next-level-cache = <&l2c2_2>; 486 }; 487 488 cpu2_3: cpu@20300 { 489 compatible = "arm,cortex-a78"; 490 device_type = "cpu"; 491 reg = <0x20300>; 492 493 enable-method = "psci"; 494 495 i-cache-size = <65536>; 496 i-cache-line-size = <64>; 497 i-cache-sets = <256>; 498 d-cache-size = <65536>; 499 d-cache-line-size = <64>; 500 d-cache-sets = <256>; 501 next-level-cache = <&l2c2_3>; 502 }; 503 504 cpu-map { 505 cluster0 { 506 core0 { 507 cpu = <&cpu0_0>; 508 }; 509 510 core1 { 511 cpu = <&cpu0_1>; 512 }; 513 514 core2 { 515 cpu = <&cpu0_2>; 516 }; 517 518 core3 { 519 cpu = <&cpu0_3>; 520 }; 521 }; 522 523 cluster1 { 524 core0 { 525 cpu = <&cpu1_0>; 526 }; 527 528 core1 { 529 cpu = <&cpu1_1>; 530 }; 531 532 core2 { 533 cpu = <&cpu1_2>; 534 }; 535 536 core3 { 537 cpu = <&cpu1_3>; 538 }; 539 }; 540 541 cluster2 { 542 core0 { 543 cpu = <&cpu2_0>; 544 }; 545 546 core1 { 547 cpu = <&cpu2_1>; 548 }; 549 550 core2 { 551 cpu = <&cpu2_2>; 552 }; 553 554 core3 { 555 cpu = <&cpu2_3>; 556 }; 557 }; 558 }; 559 560 l2c0_0: l2-cache00 { 561 cache-size = <262144>; 562 cache-line-size = <64>; 563 cache-sets = <512>; 564 cache-unified; 565 next-level-cache = <&l3c0>; 566 }; 567 568 l2c0_1: l2-cache01 { 569 cache-size = <262144>; 570 cache-line-size = <64>; 571 cache-sets = <512>; 572 cache-unified; 573 next-level-cache = <&l3c0>; 574 }; 575 576 l2c0_2: l2-cache02 { 577 cache-size = <262144>; 578 cache-line-size = <64>; 579 cache-sets = <512>; 580 cache-unified; 581 next-level-cache = <&l3c0>; 582 }; 583 584 l2c0_3: l2-cache03 { 585 cache-size = <262144>; 586 cache-line-size = <64>; 587 cache-sets = <512>; 588 cache-unified; 589 next-level-cache = <&l3c0>; 590 }; 591 592 l2c1_0: l2-cache10 { 593 cache-size = <262144>; 594 cache-line-size = <64>; 595 cache-sets = <512>; 596 cache-unified; 597 next-level-cache = <&l3c1>; 598 }; 599 600 l2c1_1: l2-cache11 { 601 cache-size = <262144>; 602 cache-line-size = <64>; 603 cache-sets = <512>; 604 cache-unified; 605 next-level-cache = <&l3c1>; 606 }; 607 608 l2c1_2: l2-cache12 { 609 cache-size = <262144>; 610 cache-line-size = <64>; 611 cache-sets = <512>; 612 cache-unified; 613 next-level-cache = <&l3c1>; 614 }; 615 616 l2c1_3: l2-cache13 { 617 cache-size = <262144>; 618 cache-line-size = <64>; 619 cache-sets = <512>; 620 cache-unified; 621 next-level-cache = <&l3c1>; 622 }; 623 624 l2c2_0: l2-cache20 { 625 cache-size = <262144>; 626 cache-line-size = <64>; 627 cache-sets = <512>; 628 cache-unified; 629 next-level-cache = <&l3c2>; 630 }; 631 632 l2c2_1: l2-cache21 { 633 cache-size = <262144>; 634 cache-line-size = <64>; 635 cache-sets = <512>; 636 cache-unified; 637 next-level-cache = <&l3c2>; 638 }; 639 640 l2c2_2: l2-cache22 { 641 cache-size = <262144>; 642 cache-line-size = <64>; 643 cache-sets = <512>; 644 cache-unified; 645 next-level-cache = <&l3c2>; 646 }; 647 648 l2c2_3: l2-cache23 { 649 cache-size = <262144>; 650 cache-line-size = <64>; 651 cache-sets = <512>; 652 cache-unified; 653 next-level-cache = <&l3c2>; 654 }; 655 656 l3c0: l3-cache0 { 657 cache-size = <2097152>; 658 cache-line-size = <64>; 659 cache-sets = <2048>; 660 }; 661 662 l3c1: l3-cache1 { 663 cache-size = <2097152>; 664 cache-line-size = <64>; 665 cache-sets = <2048>; 666 }; 667 668 l3c2: l3-cache2 { 669 cache-size = <2097152>; 670 cache-line-size = <64>; 671 cache-sets = <2048>; 672 }; 673 }; 674 675 pmu { 676 compatible = "arm,cortex-a78-pmu"; 677 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 678 status = "okay"; 679 }; 680 681 psci { 682 compatible = "arm,psci-1.0"; 683 status = "okay"; 684 method = "smc"; 685 }; 686 687 tcu: serial { 688 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 689 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 690 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 691 mbox-names = "rx", "tx"; 692 status = "disabled"; 693 }; 694 695 timer { 696 compatible = "arm,armv8-timer"; 697 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 698 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 699 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 700 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 701 interrupt-parent = <&gic>; 702 always-on; 703 }; 704}; 705