1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/gpio/tegra234-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/tegra234-mc.h> 8#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9#include <dt-bindings/power/tegra234-powergate.h> 10#include <dt-bindings/reset/tegra234-reset.h> 11 12/ { 13 compatible = "nvidia,tegra234"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 bus@0 { 19 compatible = "simple-bus"; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra234-misc"; 27 reg = <0x0 0x00100000 0x0 0xf000>, 28 <0x0 0x0010f000 0x0 0x1000>; 29 status = "okay"; 30 }; 31 32 timer@2080000 { 33 compatible = "nvidia,tegra234-timer"; 34 reg = <0x0 0x02080000 0x0 0x00121000>; 35 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 51 status = "okay"; 52 }; 53 54 gpio: gpio@2200000 { 55 compatible = "nvidia,tegra234-gpio"; 56 reg-names = "security", "gpio"; 57 reg = <0x0 0x02200000 0x0 0x10000>, 58 <0x0 0x02210000 0x0 0x10000>; 59 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 107 #interrupt-cells = <2>; 108 interrupt-controller; 109 #gpio-cells = <2>; 110 gpio-controller; 111 }; 112 113 gpcdma: dma-controller@2600000 { 114 compatible = "nvidia,tegra234-gpcdma", 115 "nvidia,tegra186-gpcdma"; 116 reg = <0x0 0x2600000 0x0 0x210000>; 117 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 118 reset-names = "gpcdma"; 119 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 151 #dma-cells = <1>; 152 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 153 dma-channel-mask = <0xfffffffe>; 154 dma-coherent; 155 }; 156 157 aconnect@2900000 { 158 compatible = "nvidia,tegra234-aconnect", 159 "nvidia,tegra210-aconnect"; 160 clocks = <&bpmp TEGRA234_CLK_APE>, 161 <&bpmp TEGRA234_CLK_APB2APE>; 162 clock-names = "ape", "apb2ape"; 163 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 164 status = "disabled"; 165 166 #address-cells = <2>; 167 #size-cells = <2>; 168 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 169 170 tegra_ahub: ahub@2900800 { 171 compatible = "nvidia,tegra234-ahub"; 172 reg = <0x0 0x02900800 0x0 0x800>; 173 clocks = <&bpmp TEGRA234_CLK_AHUB>; 174 clock-names = "ahub"; 175 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 176 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 177 status = "disabled"; 178 179 #address-cells = <2>; 180 #size-cells = <2>; 181 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 182 183 tegra_i2s1: i2s@2901000 { 184 compatible = "nvidia,tegra234-i2s", 185 "nvidia,tegra210-i2s"; 186 reg = <0x0 0x2901000 0x0 0x100>; 187 clocks = <&bpmp TEGRA234_CLK_I2S1>, 188 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 189 clock-names = "i2s", "sync_input"; 190 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 191 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 192 assigned-clock-rates = <1536000>; 193 sound-name-prefix = "I2S1"; 194 status = "disabled"; 195 }; 196 197 tegra_i2s2: i2s@2901100 { 198 compatible = "nvidia,tegra234-i2s", 199 "nvidia,tegra210-i2s"; 200 reg = <0x0 0x2901100 0x0 0x100>; 201 clocks = <&bpmp TEGRA234_CLK_I2S2>, 202 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 203 clock-names = "i2s", "sync_input"; 204 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 205 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 206 assigned-clock-rates = <1536000>; 207 sound-name-prefix = "I2S2"; 208 status = "disabled"; 209 }; 210 211 tegra_i2s3: i2s@2901200 { 212 compatible = "nvidia,tegra234-i2s", 213 "nvidia,tegra210-i2s"; 214 reg = <0x0 0x2901200 0x0 0x100>; 215 clocks = <&bpmp TEGRA234_CLK_I2S3>, 216 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 217 clock-names = "i2s", "sync_input"; 218 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 219 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 220 assigned-clock-rates = <1536000>; 221 sound-name-prefix = "I2S3"; 222 status = "disabled"; 223 }; 224 225 tegra_i2s4: i2s@2901300 { 226 compatible = "nvidia,tegra234-i2s", 227 "nvidia,tegra210-i2s"; 228 reg = <0x0 0x2901300 0x0 0x100>; 229 clocks = <&bpmp TEGRA234_CLK_I2S4>, 230 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 231 clock-names = "i2s", "sync_input"; 232 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 233 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 234 assigned-clock-rates = <1536000>; 235 sound-name-prefix = "I2S4"; 236 status = "disabled"; 237 }; 238 239 tegra_i2s5: i2s@2901400 { 240 compatible = "nvidia,tegra234-i2s", 241 "nvidia,tegra210-i2s"; 242 reg = <0x0 0x2901400 0x0 0x100>; 243 clocks = <&bpmp TEGRA234_CLK_I2S5>, 244 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 245 clock-names = "i2s", "sync_input"; 246 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 247 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 248 assigned-clock-rates = <1536000>; 249 sound-name-prefix = "I2S5"; 250 status = "disabled"; 251 }; 252 253 tegra_i2s6: i2s@2901500 { 254 compatible = "nvidia,tegra234-i2s", 255 "nvidia,tegra210-i2s"; 256 reg = <0x0 0x2901500 0x0 0x100>; 257 clocks = <&bpmp TEGRA234_CLK_I2S6>, 258 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 259 clock-names = "i2s", "sync_input"; 260 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 261 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 262 assigned-clock-rates = <1536000>; 263 sound-name-prefix = "I2S6"; 264 status = "disabled"; 265 }; 266 267 tegra_sfc1: sfc@2902000 { 268 compatible = "nvidia,tegra234-sfc", 269 "nvidia,tegra210-sfc"; 270 reg = <0x0 0x2902000 0x0 0x200>; 271 sound-name-prefix = "SFC1"; 272 status = "disabled"; 273 }; 274 275 tegra_sfc2: sfc@2902200 { 276 compatible = "nvidia,tegra234-sfc", 277 "nvidia,tegra210-sfc"; 278 reg = <0x0 0x2902200 0x0 0x200>; 279 sound-name-prefix = "SFC2"; 280 status = "disabled"; 281 }; 282 283 tegra_sfc3: sfc@2902400 { 284 compatible = "nvidia,tegra234-sfc", 285 "nvidia,tegra210-sfc"; 286 reg = <0x0 0x2902400 0x0 0x200>; 287 sound-name-prefix = "SFC3"; 288 status = "disabled"; 289 }; 290 291 tegra_sfc4: sfc@2902600 { 292 compatible = "nvidia,tegra234-sfc", 293 "nvidia,tegra210-sfc"; 294 reg = <0x0 0x2902600 0x0 0x200>; 295 sound-name-prefix = "SFC4"; 296 status = "disabled"; 297 }; 298 299 tegra_amx1: amx@2903000 { 300 compatible = "nvidia,tegra234-amx", 301 "nvidia,tegra194-amx"; 302 reg = <0x0 0x2903000 0x0 0x100>; 303 sound-name-prefix = "AMX1"; 304 status = "disabled"; 305 }; 306 307 tegra_amx2: amx@2903100 { 308 compatible = "nvidia,tegra234-amx", 309 "nvidia,tegra194-amx"; 310 reg = <0x0 0x2903100 0x0 0x100>; 311 sound-name-prefix = "AMX2"; 312 status = "disabled"; 313 }; 314 315 tegra_amx3: amx@2903200 { 316 compatible = "nvidia,tegra234-amx", 317 "nvidia,tegra194-amx"; 318 reg = <0x0 0x2903200 0x0 0x100>; 319 sound-name-prefix = "AMX3"; 320 status = "disabled"; 321 }; 322 323 tegra_amx4: amx@2903300 { 324 compatible = "nvidia,tegra234-amx", 325 "nvidia,tegra194-amx"; 326 reg = <0x0 0x2903300 0x0 0x100>; 327 sound-name-prefix = "AMX4"; 328 status = "disabled"; 329 }; 330 331 tegra_adx1: adx@2903800 { 332 compatible = "nvidia,tegra234-adx", 333 "nvidia,tegra210-adx"; 334 reg = <0x0 0x2903800 0x0 0x100>; 335 sound-name-prefix = "ADX1"; 336 status = "disabled"; 337 }; 338 339 tegra_adx2: adx@2903900 { 340 compatible = "nvidia,tegra234-adx", 341 "nvidia,tegra210-adx"; 342 reg = <0x0 0x2903900 0x0 0x100>; 343 sound-name-prefix = "ADX2"; 344 status = "disabled"; 345 }; 346 347 tegra_adx3: adx@2903a00 { 348 compatible = "nvidia,tegra234-adx", 349 "nvidia,tegra210-adx"; 350 reg = <0x0 0x2903a00 0x0 0x100>; 351 sound-name-prefix = "ADX3"; 352 status = "disabled"; 353 }; 354 355 tegra_adx4: adx@2903b00 { 356 compatible = "nvidia,tegra234-adx", 357 "nvidia,tegra210-adx"; 358 reg = <0x0 0x2903b00 0x0 0x100>; 359 sound-name-prefix = "ADX4"; 360 status = "disabled"; 361 }; 362 363 364 tegra_dmic1: dmic@2904000 { 365 compatible = "nvidia,tegra234-dmic", 366 "nvidia,tegra210-dmic"; 367 reg = <0x0 0x2904000 0x0 0x100>; 368 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 369 clock-names = "dmic"; 370 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 371 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 372 assigned-clock-rates = <3072000>; 373 sound-name-prefix = "DMIC1"; 374 status = "disabled"; 375 }; 376 377 tegra_dmic2: dmic@2904100 { 378 compatible = "nvidia,tegra234-dmic", 379 "nvidia,tegra210-dmic"; 380 reg = <0x0 0x2904100 0x0 0x100>; 381 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 382 clock-names = "dmic"; 383 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 384 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 385 assigned-clock-rates = <3072000>; 386 sound-name-prefix = "DMIC2"; 387 status = "disabled"; 388 }; 389 390 tegra_dmic3: dmic@2904200 { 391 compatible = "nvidia,tegra234-dmic", 392 "nvidia,tegra210-dmic"; 393 reg = <0x0 0x2904200 0x0 0x100>; 394 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 395 clock-names = "dmic"; 396 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 397 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 398 assigned-clock-rates = <3072000>; 399 sound-name-prefix = "DMIC3"; 400 status = "disabled"; 401 }; 402 403 tegra_dmic4: dmic@2904300 { 404 compatible = "nvidia,tegra234-dmic", 405 "nvidia,tegra210-dmic"; 406 reg = <0x0 0x2904300 0x0 0x100>; 407 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 408 clock-names = "dmic"; 409 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 410 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 411 assigned-clock-rates = <3072000>; 412 sound-name-prefix = "DMIC4"; 413 status = "disabled"; 414 }; 415 416 tegra_dspk1: dspk@2905000 { 417 compatible = "nvidia,tegra234-dspk", 418 "nvidia,tegra186-dspk"; 419 reg = <0x0 0x2905000 0x0 0x100>; 420 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 421 clock-names = "dspk"; 422 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 423 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 424 assigned-clock-rates = <12288000>; 425 sound-name-prefix = "DSPK1"; 426 status = "disabled"; 427 }; 428 429 tegra_dspk2: dspk@2905100 { 430 compatible = "nvidia,tegra234-dspk", 431 "nvidia,tegra186-dspk"; 432 reg = <0x0 0x2905100 0x0 0x100>; 433 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 434 clock-names = "dspk"; 435 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 436 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 437 assigned-clock-rates = <12288000>; 438 sound-name-prefix = "DSPK2"; 439 status = "disabled"; 440 }; 441 442 tegra_ope1: processing-engine@2908000 { 443 compatible = "nvidia,tegra234-ope", 444 "nvidia,tegra210-ope"; 445 reg = <0x0 0x2908000 0x0 0x100>; 446 sound-name-prefix = "OPE1"; 447 status = "disabled"; 448 449 #address-cells = <2>; 450 #size-cells = <2>; 451 ranges; 452 453 equalizer@2908100 { 454 compatible = "nvidia,tegra234-peq", 455 "nvidia,tegra210-peq"; 456 reg = <0x0 0x2908100 0x0 0x100>; 457 }; 458 459 dynamic-range-compressor@2908200 { 460 compatible = "nvidia,tegra234-mbdrc", 461 "nvidia,tegra210-mbdrc"; 462 reg = <0x0 0x2908200 0x0 0x200>; 463 }; 464 }; 465 466 tegra_mvc1: mvc@290a000 { 467 compatible = "nvidia,tegra234-mvc", 468 "nvidia,tegra210-mvc"; 469 reg = <0x0 0x290a000 0x0 0x200>; 470 sound-name-prefix = "MVC1"; 471 status = "disabled"; 472 }; 473 474 tegra_mvc2: mvc@290a200 { 475 compatible = "nvidia,tegra234-mvc", 476 "nvidia,tegra210-mvc"; 477 reg = <0x0 0x290a200 0x0 0x200>; 478 sound-name-prefix = "MVC2"; 479 status = "disabled"; 480 }; 481 482 tegra_amixer: amixer@290bb00 { 483 compatible = "nvidia,tegra234-amixer", 484 "nvidia,tegra210-amixer"; 485 reg = <0x0 0x290bb00 0x0 0x800>; 486 sound-name-prefix = "MIXER1"; 487 status = "disabled"; 488 }; 489 490 tegra_admaif: admaif@290f000 { 491 compatible = "nvidia,tegra234-admaif", 492 "nvidia,tegra186-admaif"; 493 reg = <0x0 0x0290f000 0x0 0x1000>; 494 dmas = <&adma 1>, <&adma 1>, 495 <&adma 2>, <&adma 2>, 496 <&adma 3>, <&adma 3>, 497 <&adma 4>, <&adma 4>, 498 <&adma 5>, <&adma 5>, 499 <&adma 6>, <&adma 6>, 500 <&adma 7>, <&adma 7>, 501 <&adma 8>, <&adma 8>, 502 <&adma 9>, <&adma 9>, 503 <&adma 10>, <&adma 10>, 504 <&adma 11>, <&adma 11>, 505 <&adma 12>, <&adma 12>, 506 <&adma 13>, <&adma 13>, 507 <&adma 14>, <&adma 14>, 508 <&adma 15>, <&adma 15>, 509 <&adma 16>, <&adma 16>, 510 <&adma 17>, <&adma 17>, 511 <&adma 18>, <&adma 18>, 512 <&adma 19>, <&adma 19>, 513 <&adma 20>, <&adma 20>; 514 dma-names = "rx1", "tx1", 515 "rx2", "tx2", 516 "rx3", "tx3", 517 "rx4", "tx4", 518 "rx5", "tx5", 519 "rx6", "tx6", 520 "rx7", "tx7", 521 "rx8", "tx8", 522 "rx9", "tx9", 523 "rx10", "tx10", 524 "rx11", "tx11", 525 "rx12", "tx12", 526 "rx13", "tx13", 527 "rx14", "tx14", 528 "rx15", "tx15", 529 "rx16", "tx16", 530 "rx17", "tx17", 531 "rx18", "tx18", 532 "rx19", "tx19", 533 "rx20", "tx20"; 534 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 535 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 536 interconnect-names = "dma-mem", "write"; 537 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 538 status = "disabled"; 539 }; 540 541 tegra_asrc: asrc@2910000 { 542 compatible = "nvidia,tegra234-asrc", 543 "nvidia,tegra186-asrc"; 544 reg = <0x0 0x2910000 0x0 0x2000>; 545 sound-name-prefix = "ASRC1"; 546 status = "disabled"; 547 }; 548 }; 549 550 adma: dma-controller@2930000 { 551 compatible = "nvidia,tegra234-adma", 552 "nvidia,tegra186-adma"; 553 reg = <0x0 0x02930000 0x0 0x20000>; 554 interrupt-parent = <&agic>; 555 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 587 #dma-cells = <1>; 588 clocks = <&bpmp TEGRA234_CLK_AHUB>; 589 clock-names = "d_audio"; 590 status = "disabled"; 591 }; 592 593 agic: interrupt-controller@2a40000 { 594 compatible = "nvidia,tegra234-agic", 595 "nvidia,tegra210-agic"; 596 #interrupt-cells = <3>; 597 interrupt-controller; 598 reg = <0x0 0x02a41000 0x0 0x1000>, 599 <0x0 0x02a42000 0x0 0x2000>; 600 interrupts = <GIC_SPI 145 601 (GIC_CPU_MASK_SIMPLE(4) | 602 IRQ_TYPE_LEVEL_HIGH)>; 603 clocks = <&bpmp TEGRA234_CLK_APE>; 604 clock-names = "clk"; 605 status = "disabled"; 606 }; 607 }; 608 609 mc: memory-controller@2c00000 { 610 compatible = "nvidia,tegra234-mc"; 611 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 612 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 613 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 614 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 615 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 616 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 617 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 618 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 619 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 620 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 621 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 622 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 623 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 624 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 625 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 626 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 627 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 628 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 629 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 630 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 631 "ch11", "ch12", "ch13", "ch14", "ch15"; 632 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 633 #interconnect-cells = <1>; 634 status = "okay"; 635 636 #address-cells = <2>; 637 #size-cells = <2>; 638 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 639 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 640 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 641 642 /* 643 * Bit 39 of addresses passing through the memory 644 * controller selects the XBAR format used when memory 645 * is accessed. This is used to transparently access 646 * memory in the XBAR format used by the discrete GPU 647 * (bit 39 set) or Tegra (bit 39 clear). 648 * 649 * As a consequence, the operating system must ensure 650 * that bit 39 is never used implicitly, for example 651 * via an I/O virtual address mapping of an IOMMU. If 652 * devices require access to the XBAR switch, their 653 * drivers must set this bit explicitly. 654 * 655 * Limit the DMA range for memory clients to [38:0]. 656 */ 657 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 658 659 emc: external-memory-controller@2c60000 { 660 compatible = "nvidia,tegra234-emc"; 661 reg = <0x0 0x02c60000 0x0 0x90000>, 662 <0x0 0x01780000 0x0 0x80000>; 663 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&bpmp TEGRA234_CLK_EMC>; 665 clock-names = "emc"; 666 status = "okay"; 667 668 #interconnect-cells = <0>; 669 670 nvidia,bpmp = <&bpmp>; 671 }; 672 }; 673 674 uarta: serial@3100000 { 675 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 676 reg = <0x0 0x03100000 0x0 0x10000>; 677 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&bpmp TEGRA234_CLK_UARTA>; 679 resets = <&bpmp TEGRA234_RESET_UARTA>; 680 status = "disabled"; 681 }; 682 683 gen1_i2c: i2c@3160000 { 684 compatible = "nvidia,tegra194-i2c"; 685 reg = <0x0 0x3160000 0x0 0x100>; 686 status = "disabled"; 687 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 clock-frequency = <400000>; 691 clocks = <&bpmp TEGRA234_CLK_I2C1 692 &bpmp TEGRA234_CLK_PLLP_OUT0>; 693 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 694 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 695 clock-names = "div-clk", "parent"; 696 resets = <&bpmp TEGRA234_RESET_I2C1>; 697 reset-names = "i2c"; 698 dmas = <&gpcdma 21>, <&gpcdma 21>; 699 dma-names = "rx", "tx"; 700 }; 701 702 cam_i2c: i2c@3180000 { 703 compatible = "nvidia,tegra194-i2c"; 704 reg = <0x0 0x3180000 0x0 0x100>; 705 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 status = "disabled"; 709 clock-frequency = <400000>; 710 clocks = <&bpmp TEGRA234_CLK_I2C3 711 &bpmp TEGRA234_CLK_PLLP_OUT0>; 712 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 713 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 714 clock-names = "div-clk", "parent"; 715 resets = <&bpmp TEGRA234_RESET_I2C3>; 716 reset-names = "i2c"; 717 dmas = <&gpcdma 23>, <&gpcdma 23>; 718 dma-names = "rx", "tx"; 719 }; 720 721 dp_aux_ch1_i2c: i2c@3190000 { 722 compatible = "nvidia,tegra194-i2c"; 723 reg = <0x0 0x3190000 0x0 0x100>; 724 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 725 #address-cells = <1>; 726 #size-cells = <0>; 727 status = "disabled"; 728 clock-frequency = <100000>; 729 clocks = <&bpmp TEGRA234_CLK_I2C4 730 &bpmp TEGRA234_CLK_PLLP_OUT0>; 731 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 732 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 733 clock-names = "div-clk", "parent"; 734 resets = <&bpmp TEGRA234_RESET_I2C4>; 735 reset-names = "i2c"; 736 dmas = <&gpcdma 26>, <&gpcdma 26>; 737 dma-names = "rx", "tx"; 738 }; 739 740 dp_aux_ch0_i2c: i2c@31b0000 { 741 compatible = "nvidia,tegra194-i2c"; 742 reg = <0x0 0x31b0000 0x0 0x100>; 743 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 744 #address-cells = <1>; 745 #size-cells = <0>; 746 status = "disabled"; 747 clock-frequency = <100000>; 748 clocks = <&bpmp TEGRA234_CLK_I2C6 749 &bpmp TEGRA234_CLK_PLLP_OUT0>; 750 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 751 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 752 clock-names = "div-clk", "parent"; 753 resets = <&bpmp TEGRA234_RESET_I2C6>; 754 reset-names = "i2c"; 755 dmas = <&gpcdma 30>, <&gpcdma 30>; 756 dma-names = "rx", "tx"; 757 }; 758 759 dp_aux_ch2_i2c: i2c@31c0000 { 760 compatible = "nvidia,tegra194-i2c"; 761 reg = <0x0 0x31c0000 0x0 0x100>; 762 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 status = "disabled"; 766 clock-frequency = <100000>; 767 clocks = <&bpmp TEGRA234_CLK_I2C7 768 &bpmp TEGRA234_CLK_PLLP_OUT0>; 769 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 770 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 771 clock-names = "div-clk", "parent"; 772 resets = <&bpmp TEGRA234_RESET_I2C7>; 773 reset-names = "i2c"; 774 dmas = <&gpcdma 27>, <&gpcdma 27>; 775 dma-names = "rx", "tx"; 776 }; 777 778 uarti: serial@31d0000 { 779 compatible = "arm,sbsa-uart"; 780 reg = <0x0 0x31d0000 0x0 0x10000>; 781 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 782 status = "disabled"; 783 }; 784 785 dp_aux_ch3_i2c: i2c@31e0000 { 786 compatible = "nvidia,tegra194-i2c"; 787 reg = <0x0 0x31e0000 0x0 0x100>; 788 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 status = "disabled"; 792 clock-frequency = <100000>; 793 clocks = <&bpmp TEGRA234_CLK_I2C9 794 &bpmp TEGRA234_CLK_PLLP_OUT0>; 795 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 796 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 797 clock-names = "div-clk", "parent"; 798 resets = <&bpmp TEGRA234_RESET_I2C9>; 799 reset-names = "i2c"; 800 dmas = <&gpcdma 31>, <&gpcdma 31>; 801 dma-names = "rx", "tx"; 802 }; 803 804 spi@3270000 { 805 compatible = "nvidia,tegra234-qspi"; 806 reg = <0x0 0x3270000 0x0 0x1000>; 807 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 811 <&bpmp TEGRA234_CLK_QSPI0_PM>; 812 clock-names = "qspi", "qspi_out"; 813 resets = <&bpmp TEGRA234_RESET_QSPI0>; 814 status = "disabled"; 815 }; 816 817 pwm1: pwm@3280000 { 818 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 819 reg = <0x0 0x3280000 0x0 0x10000>; 820 clocks = <&bpmp TEGRA234_CLK_PWM1>; 821 resets = <&bpmp TEGRA234_RESET_PWM1>; 822 reset-names = "pwm"; 823 status = "disabled"; 824 #pwm-cells = <2>; 825 }; 826 827 pwm2: pwm@3290000 { 828 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 829 reg = <0x0 0x3290000 0x0 0x10000>; 830 clocks = <&bpmp TEGRA234_CLK_PWM2>; 831 resets = <&bpmp TEGRA234_RESET_PWM2>; 832 reset-names = "pwm"; 833 status = "disabled"; 834 #pwm-cells = <2>; 835 }; 836 837 pwm3: pwm@32a0000 { 838 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 839 reg = <0x0 0x32a0000 0x0 0x10000>; 840 clocks = <&bpmp TEGRA234_CLK_PWM3>; 841 resets = <&bpmp TEGRA234_RESET_PWM3>; 842 reset-names = "pwm"; 843 status = "disabled"; 844 #pwm-cells = <2>; 845 }; 846 847 pwm5: pwm@32c0000 { 848 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 849 reg = <0x0 0x32c0000 0x0 0x10000>; 850 clocks = <&bpmp TEGRA234_CLK_PWM5>; 851 resets = <&bpmp TEGRA234_RESET_PWM5>; 852 reset-names = "pwm"; 853 status = "disabled"; 854 #pwm-cells = <2>; 855 }; 856 857 pwm6: pwm@32d0000 { 858 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 859 reg = <0x0 0x32d0000 0x0 0x10000>; 860 clocks = <&bpmp TEGRA234_CLK_PWM6>; 861 resets = <&bpmp TEGRA234_RESET_PWM6>; 862 reset-names = "pwm"; 863 status = "disabled"; 864 #pwm-cells = <2>; 865 }; 866 867 pwm7: pwm@32e0000 { 868 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 869 reg = <0x0 0x32e0000 0x0 0x10000>; 870 clocks = <&bpmp TEGRA234_CLK_PWM7>; 871 resets = <&bpmp TEGRA234_RESET_PWM7>; 872 reset-names = "pwm"; 873 status = "disabled"; 874 #pwm-cells = <2>; 875 }; 876 877 pwm8: pwm@32f0000 { 878 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 879 reg = <0x0 0x32f0000 0x0 0x10000>; 880 clocks = <&bpmp TEGRA234_CLK_PWM8>; 881 resets = <&bpmp TEGRA234_RESET_PWM8>; 882 reset-names = "pwm"; 883 status = "disabled"; 884 #pwm-cells = <2>; 885 }; 886 887 spi@3300000 { 888 compatible = "nvidia,tegra234-qspi"; 889 reg = <0x0 0x3300000 0x0 0x1000>; 890 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 894 <&bpmp TEGRA234_CLK_QSPI1_PM>; 895 clock-names = "qspi", "qspi_out"; 896 resets = <&bpmp TEGRA234_RESET_QSPI1>; 897 status = "disabled"; 898 }; 899 900 mmc@3400000 { 901 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 902 reg = <0x0 0x03400000 0x0 0x20000>; 903 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 905 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 906 clock-names = "sdhci", "tmclk"; 907 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 908 <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 909 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 910 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 911 resets = <&bpmp TEGRA234_RESET_SDMMC1>; 912 reset-names = "sdhci"; 913 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 914 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 915 interconnect-names = "dma-mem", "write"; 916 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 917 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 918 pinctrl-0 = <&sdmmc1_3v3>; 919 pinctrl-1 = <&sdmmc1_1v8>; 920 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 921 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 922 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 923 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 924 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 925 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 926 nvidia,default-tap = <14>; 927 nvidia,default-trim = <0x8>; 928 sd-uhs-sdr25; 929 sd-uhs-sdr50; 930 sd-uhs-ddr50; 931 sd-uhs-sdr104; 932 status = "disabled"; 933 }; 934 935 mmc@3460000 { 936 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 937 reg = <0x0 0x03460000 0x0 0x20000>; 938 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 939 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 940 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 941 clock-names = "sdhci", "tmclk"; 942 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 943 <&bpmp TEGRA234_CLK_PLLC4>; 944 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 945 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 946 reset-names = "sdhci"; 947 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 948 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 949 interconnect-names = "dma-mem", "write"; 950 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 951 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 952 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 953 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 954 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 955 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 956 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 957 nvidia,default-tap = <0x8>; 958 nvidia,default-trim = <0x14>; 959 nvidia,dqs-trim = <40>; 960 supports-cqe; 961 status = "disabled"; 962 }; 963 964 hda@3510000 { 965 compatible = "nvidia,tegra234-hda"; 966 reg = <0x0 0x3510000 0x0 0x10000>; 967 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 969 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 970 clock-names = "hda", "hda2codec_2x"; 971 resets = <&bpmp TEGRA234_RESET_HDA>, 972 <&bpmp TEGRA234_RESET_HDACODEC>; 973 reset-names = "hda", "hda2codec_2x"; 974 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 975 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 976 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 977 interconnect-names = "dma-mem", "write"; 978 iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 979 status = "disabled"; 980 }; 981 982 xusb_padctl: padctl@3520000 { 983 compatible = "nvidia,tegra234-xusb-padctl"; 984 reg = <0x0 0x03520000 0x0 0x20000>, 985 <0x0 0x03540000 0x0 0x10000>; 986 reg-names = "padctl", "ao"; 987 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 988 989 resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; 990 reset-names = "padctl"; 991 992 status = "disabled"; 993 994 pads { 995 usb2 { 996 clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; 997 clock-names = "trk"; 998 999 lanes { 1000 usb2-0 { 1001 nvidia,function = "xusb"; 1002 status = "disabled"; 1003 #phy-cells = <0>; 1004 }; 1005 1006 usb2-1 { 1007 nvidia,function = "xusb"; 1008 status = "disabled"; 1009 #phy-cells = <0>; 1010 }; 1011 1012 usb2-2 { 1013 nvidia,function = "xusb"; 1014 status = "disabled"; 1015 #phy-cells = <0>; 1016 }; 1017 1018 usb2-3 { 1019 nvidia,function = "xusb"; 1020 status = "disabled"; 1021 #phy-cells = <0>; 1022 }; 1023 }; 1024 }; 1025 1026 usb3 { 1027 lanes { 1028 usb3-0 { 1029 nvidia,function = "xusb"; 1030 status = "disabled"; 1031 #phy-cells = <0>; 1032 }; 1033 1034 usb3-1 { 1035 nvidia,function = "xusb"; 1036 status = "disabled"; 1037 #phy-cells = <0>; 1038 }; 1039 1040 usb3-2 { 1041 nvidia,function = "xusb"; 1042 status = "disabled"; 1043 #phy-cells = <0>; 1044 }; 1045 1046 usb3-3 { 1047 nvidia,function = "xusb"; 1048 status = "disabled"; 1049 #phy-cells = <0>; 1050 }; 1051 }; 1052 }; 1053 }; 1054 1055 ports { 1056 usb2-0 { 1057 status = "disabled"; 1058 }; 1059 1060 usb2-1 { 1061 status = "disabled"; 1062 }; 1063 1064 usb2-2 { 1065 status = "disabled"; 1066 }; 1067 1068 usb2-3 { 1069 status = "disabled"; 1070 }; 1071 1072 usb3-0 { 1073 status = "disabled"; 1074 }; 1075 1076 usb3-1 { 1077 status = "disabled"; 1078 }; 1079 1080 usb3-2 { 1081 status = "disabled"; 1082 }; 1083 1084 usb3-3 { 1085 status = "disabled"; 1086 }; 1087 }; 1088 }; 1089 1090 usb@3550000 { 1091 compatible = "nvidia,tegra234-xudc"; 1092 reg = <0x0 0x03550000 0x0 0x8000>, 1093 <0x0 0x03558000 0x0 0x8000>; 1094 reg-names = "base", "fpci"; 1095 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, 1097 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1098 <&bpmp TEGRA234_CLK_XUSB_SS>, 1099 <&bpmp TEGRA234_CLK_XUSB_FS>; 1100 clock-names = "dev", "ss", "ss_src", "fs_src"; 1101 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, 1102 <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; 1103 interconnect-names = "dma-mem", "write"; 1104 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; 1105 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, 1106 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1107 power-domain-names = "dev", "ss"; 1108 nvidia,xusb-padctl = <&xusb_padctl>; 1109 dma-coherent; 1110 status = "disabled"; 1111 }; 1112 1113 usb@3610000 { 1114 compatible = "nvidia,tegra234-xusb"; 1115 reg = <0x0 0x03610000 0x0 0x40000>, 1116 <0x0 0x03600000 0x0 0x10000>, 1117 <0x0 0x03650000 0x0 0x10000>; 1118 reg-names = "hcd", "fpci", "bar2"; 1119 1120 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1122 1123 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, 1124 <&bpmp TEGRA234_CLK_XUSB_FALCON>, 1125 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 1126 <&bpmp TEGRA234_CLK_XUSB_SS>, 1127 <&bpmp TEGRA234_CLK_CLK_M>, 1128 <&bpmp TEGRA234_CLK_XUSB_FS>, 1129 <&bpmp TEGRA234_CLK_UTMIP_PLL>, 1130 <&bpmp TEGRA234_CLK_CLK_M>, 1131 <&bpmp TEGRA234_CLK_PLLE>; 1132 clock-names = "xusb_host", "xusb_falcon_src", 1133 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1134 "xusb_fs_src", "pll_u_480m", "clk_m", 1135 "pll_e"; 1136 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1137 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1138 interconnect-names = "dma-mem", "write"; 1139 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; 1140 1141 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, 1142 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 1143 power-domain-names = "xusb_host", "xusb_ss"; 1144 1145 nvidia,xusb-padctl = <&xusb_padctl>; 1146 dma-coherent; 1147 status = "disabled"; 1148 }; 1149 1150 fuse@3810000 { 1151 compatible = "nvidia,tegra234-efuse"; 1152 reg = <0x0 0x03810000 0x0 0x10000>; 1153 clocks = <&bpmp TEGRA234_CLK_FUSE>; 1154 clock-names = "fuse"; 1155 }; 1156 1157 hte_lic: hardware-timestamp@3aa0000 { 1158 compatible = "nvidia,tegra234-gte-lic"; 1159 reg = <0x0 0x3aa0000 0x0 0x10000>; 1160 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1161 nvidia,int-threshold = <1>; 1162 #timestamp-cells = <1>; 1163 }; 1164 1165 hsp_top0: hsp@3c00000 { 1166 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1167 reg = <0x0 0x03c00000 0x0 0xa0000>; 1168 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1177 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1178 "shared3", "shared4", "shared5", "shared6", 1179 "shared7"; 1180 #mbox-cells = <2>; 1181 }; 1182 1183 p2u_hsio_0: phy@3e00000 { 1184 compatible = "nvidia,tegra234-p2u"; 1185 reg = <0x0 0x03e00000 0x0 0x10000>; 1186 reg-names = "ctl"; 1187 1188 #phy-cells = <0>; 1189 }; 1190 1191 p2u_hsio_1: phy@3e10000 { 1192 compatible = "nvidia,tegra234-p2u"; 1193 reg = <0x0 0x03e10000 0x0 0x10000>; 1194 reg-names = "ctl"; 1195 1196 #phy-cells = <0>; 1197 }; 1198 1199 p2u_hsio_2: phy@3e20000 { 1200 compatible = "nvidia,tegra234-p2u"; 1201 reg = <0x0 0x03e20000 0x0 0x10000>; 1202 reg-names = "ctl"; 1203 1204 #phy-cells = <0>; 1205 }; 1206 1207 p2u_hsio_3: phy@3e30000 { 1208 compatible = "nvidia,tegra234-p2u"; 1209 reg = <0x0 0x03e30000 0x0 0x10000>; 1210 reg-names = "ctl"; 1211 1212 #phy-cells = <0>; 1213 }; 1214 1215 p2u_hsio_4: phy@3e40000 { 1216 compatible = "nvidia,tegra234-p2u"; 1217 reg = <0x0 0x03e40000 0x0 0x10000>; 1218 reg-names = "ctl"; 1219 1220 #phy-cells = <0>; 1221 }; 1222 1223 p2u_hsio_5: phy@3e50000 { 1224 compatible = "nvidia,tegra234-p2u"; 1225 reg = <0x0 0x03e50000 0x0 0x10000>; 1226 reg-names = "ctl"; 1227 1228 #phy-cells = <0>; 1229 }; 1230 1231 p2u_hsio_6: phy@3e60000 { 1232 compatible = "nvidia,tegra234-p2u"; 1233 reg = <0x0 0x03e60000 0x0 0x10000>; 1234 reg-names = "ctl"; 1235 1236 #phy-cells = <0>; 1237 }; 1238 1239 p2u_hsio_7: phy@3e70000 { 1240 compatible = "nvidia,tegra234-p2u"; 1241 reg = <0x0 0x03e70000 0x0 0x10000>; 1242 reg-names = "ctl"; 1243 1244 #phy-cells = <0>; 1245 }; 1246 1247 p2u_nvhs_0: phy@3e90000 { 1248 compatible = "nvidia,tegra234-p2u"; 1249 reg = <0x0 0x03e90000 0x0 0x10000>; 1250 reg-names = "ctl"; 1251 1252 #phy-cells = <0>; 1253 }; 1254 1255 p2u_nvhs_1: phy@3ea0000 { 1256 compatible = "nvidia,tegra234-p2u"; 1257 reg = <0x0 0x03ea0000 0x0 0x10000>; 1258 reg-names = "ctl"; 1259 1260 #phy-cells = <0>; 1261 }; 1262 1263 p2u_nvhs_2: phy@3eb0000 { 1264 compatible = "nvidia,tegra234-p2u"; 1265 reg = <0x0 0x03eb0000 0x0 0x10000>; 1266 reg-names = "ctl"; 1267 1268 #phy-cells = <0>; 1269 }; 1270 1271 p2u_nvhs_3: phy@3ec0000 { 1272 compatible = "nvidia,tegra234-p2u"; 1273 reg = <0x0 0x03ec0000 0x0 0x10000>; 1274 reg-names = "ctl"; 1275 1276 #phy-cells = <0>; 1277 }; 1278 1279 p2u_nvhs_4: phy@3ed0000 { 1280 compatible = "nvidia,tegra234-p2u"; 1281 reg = <0x0 0x03ed0000 0x0 0x10000>; 1282 reg-names = "ctl"; 1283 1284 #phy-cells = <0>; 1285 }; 1286 1287 p2u_nvhs_5: phy@3ee0000 { 1288 compatible = "nvidia,tegra234-p2u"; 1289 reg = <0x0 0x03ee0000 0x0 0x10000>; 1290 reg-names = "ctl"; 1291 1292 #phy-cells = <0>; 1293 }; 1294 1295 p2u_nvhs_6: phy@3ef0000 { 1296 compatible = "nvidia,tegra234-p2u"; 1297 reg = <0x0 0x03ef0000 0x0 0x10000>; 1298 reg-names = "ctl"; 1299 1300 #phy-cells = <0>; 1301 }; 1302 1303 p2u_nvhs_7: phy@3f00000 { 1304 compatible = "nvidia,tegra234-p2u"; 1305 reg = <0x0 0x03f00000 0x0 0x10000>; 1306 reg-names = "ctl"; 1307 1308 #phy-cells = <0>; 1309 }; 1310 1311 p2u_gbe_0: phy@3f20000 { 1312 compatible = "nvidia,tegra234-p2u"; 1313 reg = <0x0 0x03f20000 0x0 0x10000>; 1314 reg-names = "ctl"; 1315 1316 #phy-cells = <0>; 1317 }; 1318 1319 p2u_gbe_1: phy@3f30000 { 1320 compatible = "nvidia,tegra234-p2u"; 1321 reg = <0x0 0x03f30000 0x0 0x10000>; 1322 reg-names = "ctl"; 1323 1324 #phy-cells = <0>; 1325 }; 1326 1327 p2u_gbe_2: phy@3f40000 { 1328 compatible = "nvidia,tegra234-p2u"; 1329 reg = <0x0 0x03f40000 0x0 0x10000>; 1330 reg-names = "ctl"; 1331 1332 #phy-cells = <0>; 1333 }; 1334 1335 p2u_gbe_3: phy@3f50000 { 1336 compatible = "nvidia,tegra234-p2u"; 1337 reg = <0x0 0x03f50000 0x0 0x10000>; 1338 reg-names = "ctl"; 1339 1340 #phy-cells = <0>; 1341 }; 1342 1343 p2u_gbe_4: phy@3f60000 { 1344 compatible = "nvidia,tegra234-p2u"; 1345 reg = <0x0 0x03f60000 0x0 0x10000>; 1346 reg-names = "ctl"; 1347 1348 #phy-cells = <0>; 1349 }; 1350 1351 p2u_gbe_5: phy@3f70000 { 1352 compatible = "nvidia,tegra234-p2u"; 1353 reg = <0x0 0x03f70000 0x0 0x10000>; 1354 reg-names = "ctl"; 1355 1356 #phy-cells = <0>; 1357 }; 1358 1359 p2u_gbe_6: phy@3f80000 { 1360 compatible = "nvidia,tegra234-p2u"; 1361 reg = <0x0 0x03f80000 0x0 0x10000>; 1362 reg-names = "ctl"; 1363 1364 #phy-cells = <0>; 1365 }; 1366 1367 p2u_gbe_7: phy@3f90000 { 1368 compatible = "nvidia,tegra234-p2u"; 1369 reg = <0x0 0x03f90000 0x0 0x10000>; 1370 reg-names = "ctl"; 1371 1372 #phy-cells = <0>; 1373 }; 1374 1375 ethernet@6800000 { 1376 compatible = "nvidia,tegra234-mgbe"; 1377 reg = <0x0 0x06800000 0x0 0x10000>, 1378 <0x0 0x06810000 0x0 0x10000>, 1379 <0x0 0x068a0000 0x0 0x10000>; 1380 reg-names = "hypervisor", "mac", "xpcs"; 1381 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 1382 interrupt-names = "common"; 1383 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 1384 <&bpmp TEGRA234_CLK_MGBE0_MAC>, 1385 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 1386 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 1387 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 1388 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 1389 <&bpmp TEGRA234_CLK_MGBE0_TX>, 1390 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 1391 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 1392 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 1393 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 1394 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 1395 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1396 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1397 "rx-pcs", "tx-pcs"; 1398 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 1399 <&bpmp TEGRA234_RESET_MGBE0_PCS>; 1400 reset-names = "mac", "pcs"; 1401 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 1402 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 1403 interconnect-names = "dma-mem", "write"; 1404 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 1405 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; 1406 status = "disabled"; 1407 }; 1408 1409 ethernet@6900000 { 1410 compatible = "nvidia,tegra234-mgbe"; 1411 reg = <0x0 0x06900000 0x0 0x10000>, 1412 <0x0 0x06910000 0x0 0x10000>, 1413 <0x0 0x069a0000 0x0 0x10000>; 1414 reg-names = "hypervisor", "mac", "xpcs"; 1415 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 1416 interrupt-names = "common"; 1417 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 1418 <&bpmp TEGRA234_CLK_MGBE1_MAC>, 1419 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 1420 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 1421 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 1422 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 1423 <&bpmp TEGRA234_CLK_MGBE1_TX>, 1424 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 1425 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 1426 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 1427 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 1428 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 1429 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1430 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1431 "rx-pcs", "tx-pcs"; 1432 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 1433 <&bpmp TEGRA234_RESET_MGBE1_PCS>; 1434 reset-names = "mac", "pcs"; 1435 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 1436 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 1437 interconnect-names = "dma-mem", "write"; 1438 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 1439 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 1440 status = "disabled"; 1441 }; 1442 1443 ethernet@6a00000 { 1444 compatible = "nvidia,tegra234-mgbe"; 1445 reg = <0x0 0x06a00000 0x0 0x10000>, 1446 <0x0 0x06a10000 0x0 0x10000>, 1447 <0x0 0x06aa0000 0x0 0x10000>; 1448 reg-names = "hypervisor", "mac", "xpcs"; 1449 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 1450 interrupt-names = "common"; 1451 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 1452 <&bpmp TEGRA234_CLK_MGBE2_MAC>, 1453 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 1454 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 1455 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 1456 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 1457 <&bpmp TEGRA234_CLK_MGBE2_TX>, 1458 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 1459 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 1460 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 1461 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 1462 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 1463 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1464 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1465 "rx-pcs", "tx-pcs"; 1466 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 1467 <&bpmp TEGRA234_RESET_MGBE2_PCS>; 1468 reset-names = "mac", "pcs"; 1469 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 1470 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 1471 interconnect-names = "dma-mem", "write"; 1472 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 1473 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 1474 status = "disabled"; 1475 }; 1476 1477 ethernet@6b00000 { 1478 compatible = "nvidia,tegra234-mgbe"; 1479 reg = <0x0 0x06b00000 0x0 0x10000>, 1480 <0x0 0x06b10000 0x0 0x10000>, 1481 <0x0 0x06ba0000 0x0 0x10000>; 1482 reg-names = "hypervisor", "mac", "xpcs"; 1483 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1484 interrupt-names = "common"; 1485 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 1486 <&bpmp TEGRA234_CLK_MGBE3_MAC>, 1487 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 1488 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 1489 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 1490 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 1491 <&bpmp TEGRA234_CLK_MGBE3_TX>, 1492 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 1493 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 1494 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 1495 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 1496 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 1497 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 1498 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 1499 "rx-pcs", "tx-pcs"; 1500 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 1501 <&bpmp TEGRA234_RESET_MGBE3_PCS>; 1502 reset-names = "mac", "pcs"; 1503 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 1504 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 1505 interconnect-names = "dma-mem", "write"; 1506 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 1507 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 1508 status = "disabled"; 1509 }; 1510 1511 smmu_niso1: iommu@8000000 { 1512 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1513 reg = <0x0 0x8000000 0x0 0x1000000>, 1514 <0x0 0x7000000 0x0 0x1000000>; 1515 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1547 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1548 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1549 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1550 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1551 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1645 stream-match-mask = <0x7f80>; 1646 #global-interrupts = <2>; 1647 #iommu-cells = <1>; 1648 1649 nvidia,memory-controller = <&mc>; 1650 status = "okay"; 1651 }; 1652 1653 sce-fabric@b600000 { 1654 compatible = "nvidia,tegra234-sce-fabric"; 1655 reg = <0x0 0xb600000 0x0 0x40000>; 1656 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1657 status = "okay"; 1658 }; 1659 1660 rce-fabric@be00000 { 1661 compatible = "nvidia,tegra234-rce-fabric"; 1662 reg = <0x0 0xbe00000 0x0 0x40000>; 1663 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1664 status = "okay"; 1665 }; 1666 1667 hsp_aon: hsp@c150000 { 1668 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1669 reg = <0x0 0x0c150000 0x0 0x90000>; 1670 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1674 /* 1675 * Shared interrupt 0 is routed only to AON/SPE, so 1676 * we only have 4 shared interrupts for the CCPLEX. 1677 */ 1678 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1679 #mbox-cells = <2>; 1680 }; 1681 1682 hte_aon: hardware-timestamp@c1e0000 { 1683 compatible = "nvidia,tegra234-gte-aon"; 1684 reg = <0x0 0xc1e0000 0x0 0x10000>; 1685 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1686 nvidia,int-threshold = <1>; 1687 nvidia,gpio-controller = <&gpio_aon>; 1688 #timestamp-cells = <1>; 1689 }; 1690 1691 gen2_i2c: i2c@c240000 { 1692 compatible = "nvidia,tegra194-i2c"; 1693 reg = <0x0 0xc240000 0x0 0x100>; 1694 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1695 #address-cells = <1>; 1696 #size-cells = <0>; 1697 status = "disabled"; 1698 clock-frequency = <100000>; 1699 clocks = <&bpmp TEGRA234_CLK_I2C2 1700 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1701 clock-names = "div-clk", "parent"; 1702 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1703 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1704 resets = <&bpmp TEGRA234_RESET_I2C2>; 1705 reset-names = "i2c"; 1706 dmas = <&gpcdma 22>, <&gpcdma 22>; 1707 dma-names = "rx", "tx"; 1708 }; 1709 1710 gen8_i2c: i2c@c250000 { 1711 compatible = "nvidia,tegra194-i2c"; 1712 reg = <0x0 0xc250000 0x0 0x100>; 1713 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1714 #address-cells = <1>; 1715 #size-cells = <0>; 1716 status = "disabled"; 1717 clock-frequency = <400000>; 1718 clocks = <&bpmp TEGRA234_CLK_I2C8 1719 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1720 clock-names = "div-clk", "parent"; 1721 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1722 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1723 resets = <&bpmp TEGRA234_RESET_I2C8>; 1724 reset-names = "i2c"; 1725 dmas = <&gpcdma 0>, <&gpcdma 0>; 1726 dma-names = "rx", "tx"; 1727 }; 1728 1729 rtc@c2a0000 { 1730 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 1731 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1732 interrupt-parent = <&pmc>; 1733 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1734 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1735 clock-names = "rtc"; 1736 status = "disabled"; 1737 }; 1738 1739 gpio_aon: gpio@c2f0000 { 1740 compatible = "nvidia,tegra234-gpio-aon"; 1741 reg-names = "security", "gpio"; 1742 reg = <0x0 0x0c2f0000 0x0 0x1000>, 1743 <0x0 0x0c2f1000 0x0 0x1000>; 1744 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1748 #interrupt-cells = <2>; 1749 interrupt-controller; 1750 #gpio-cells = <2>; 1751 gpio-controller; 1752 }; 1753 1754 pwm4: pwm@c340000 { 1755 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 1756 reg = <0x0 0xc340000 0x0 0x10000>; 1757 clocks = <&bpmp TEGRA234_CLK_PWM4>; 1758 resets = <&bpmp TEGRA234_RESET_PWM4>; 1759 reset-names = "pwm"; 1760 status = "disabled"; 1761 #pwm-cells = <2>; 1762 }; 1763 1764 pmc: pmc@c360000 { 1765 compatible = "nvidia,tegra234-pmc"; 1766 reg = <0x0 0x0c360000 0x0 0x10000>, 1767 <0x0 0x0c370000 0x0 0x10000>, 1768 <0x0 0x0c380000 0x0 0x10000>, 1769 <0x0 0x0c390000 0x0 0x10000>, 1770 <0x0 0x0c3a0000 0x0 0x10000>; 1771 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1772 1773 #interrupt-cells = <2>; 1774 interrupt-controller; 1775 1776 sdmmc1_1v8: sdmmc1-1v8 { 1777 pins = "sdmmc1-hv"; 1778 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1779 }; 1780 1781 sdmmc1_3v3: sdmmc1-3v3 { 1782 pins = "sdmmc1-hv"; 1783 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1784 }; 1785 1786 sdmmc3_1v8: sdmmc3-1v8 { 1787 pins = "sdmmc3-hv"; 1788 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1789 }; 1790 1791 sdmmc3_3v3: sdmmc3-3v3 { 1792 pins = "sdmmc3-hv"; 1793 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1794 }; 1795 }; 1796 1797 aon-fabric@c600000 { 1798 compatible = "nvidia,tegra234-aon-fabric"; 1799 reg = <0x0 0xc600000 0x0 0x40000>; 1800 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1801 status = "okay"; 1802 }; 1803 1804 bpmp-fabric@d600000 { 1805 compatible = "nvidia,tegra234-bpmp-fabric"; 1806 reg = <0x0 0xd600000 0x0 0x40000>; 1807 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1808 status = "okay"; 1809 }; 1810 1811 dce-fabric@de00000 { 1812 compatible = "nvidia,tegra234-sce-fabric"; 1813 reg = <0x0 0xde00000 0x0 0x40000>; 1814 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1815 status = "okay"; 1816 }; 1817 1818 ccplex@e000000 { 1819 compatible = "nvidia,tegra234-ccplex-cluster"; 1820 reg = <0x0 0x0e000000 0x0 0x5ffff>; 1821 nvidia,bpmp = <&bpmp>; 1822 status = "okay"; 1823 }; 1824 1825 gic: interrupt-controller@f400000 { 1826 compatible = "arm,gic-v3"; 1827 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 1828 <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 1829 interrupt-parent = <&gic>; 1830 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1831 1832 #redistributor-regions = <1>; 1833 #interrupt-cells = <3>; 1834 interrupt-controller; 1835 }; 1836 1837 smmu_iso: iommu@10000000 { 1838 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1839 reg = <0x0 0x10000000 0x0 0x1000000>; 1840 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1913 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1914 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1928 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1935 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1957 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1958 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1959 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1960 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1962 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1963 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1969 stream-match-mask = <0x7f80>; 1970 #global-interrupts = <1>; 1971 #iommu-cells = <1>; 1972 1973 nvidia,memory-controller = <&mc>; 1974 status = "okay"; 1975 }; 1976 1977 smmu_niso0: iommu@12000000 { 1978 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1979 reg = <0x0 0x12000000 0x0 0x1000000>, 1980 <0x0 0x11000000 0x0 0x1000000>; 1981 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1994 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1995 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1996 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1999 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2007 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2008 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2015 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2016 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2023 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2027 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2028 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2029 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2031 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2045 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2046 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2047 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2048 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 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170 IRQ_TYPE_LEVEL_HIGH>, 2081 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2083 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2085 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2087 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2111 stream-match-mask = <0x7f80>; 2112 #global-interrupts = <2>; 2113 #iommu-cells = <1>; 2114 2115 nvidia,memory-controller = <&mc>; 2116 status = "okay"; 2117 }; 2118 2119 cbb-fabric@13a00000 { 2120 compatible = "nvidia,tegra234-cbb-fabric"; 2121 reg = <0x0 0x13a00000 0x0 0x400000>; 2122 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 2123 status = "okay"; 2124 }; 2125 2126 host1x@13e00000 { 2127 compatible = "nvidia,tegra234-host1x"; 2128 reg = <0x0 0x13e00000 0x0 0x10000>, 2129 <0x0 0x13e10000 0x0 0x10000>, 2130 <0x0 0x13e40000 0x0 0x10000>; 2131 reg-names = "common", "hypervisor", "vm"; 2132 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2141 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 2142 "syncpt5", "syncpt6", "syncpt7", "host1x"; 2143 clocks = <&bpmp TEGRA234_CLK_HOST1X>; 2144 clock-names = "host1x"; 2145 2146 #address-cells = <2>; 2147 #size-cells = <2>; 2148 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 2149 2150 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 2151 interconnect-names = "dma-mem"; 2152 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 2153 dma-coherent; 2154 2155 /* Context isolation domains */ 2156 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 2157 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 2158 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 2159 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 2160 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 2161 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 2162 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 2163 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 2164 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 2165 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 2166 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 2167 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 2168 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 2169 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 2170 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 2171 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 2172 2173 vic@15340000 { 2174 compatible = "nvidia,tegra234-vic"; 2175 reg = <0x0 0x15340000 0x0 0x00040000>; 2176 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2177 clocks = <&bpmp TEGRA234_CLK_VIC>; 2178 clock-names = "vic"; 2179 resets = <&bpmp TEGRA234_RESET_VIC>; 2180 reset-names = "vic"; 2181 2182 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 2183 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 2184 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 2185 interconnect-names = "dma-mem", "write"; 2186 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 2187 dma-coherent; 2188 }; 2189 2190 nvdec@15480000 { 2191 compatible = "nvidia,tegra234-nvdec"; 2192 reg = <0x0 0x15480000 0x0 0x00040000>; 2193 clocks = <&bpmp TEGRA234_CLK_NVDEC>, 2194 <&bpmp TEGRA234_CLK_FUSE>, 2195 <&bpmp TEGRA234_CLK_TSEC_PKA>; 2196 clock-names = "nvdec", "fuse", "tsec_pka"; 2197 resets = <&bpmp TEGRA234_RESET_NVDEC>; 2198 reset-names = "nvdec"; 2199 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 2200 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 2201 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 2202 interconnect-names = "dma-mem", "write"; 2203 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 2204 dma-coherent; 2205 2206 nvidia,memory-controller = <&mc>; 2207 2208 /* 2209 * Placeholder values that firmware needs to update with the real 2210 * offsets parsed from the microcode headers. 2211 */ 2212 nvidia,bl-manifest-offset = <0>; 2213 nvidia,bl-data-offset = <0>; 2214 nvidia,bl-code-offset = <0>; 2215 nvidia,os-manifest-offset = <0>; 2216 nvidia,os-data-offset = <0>; 2217 nvidia,os-code-offset = <0>; 2218 2219 /* 2220 * Firmware needs to set this to "okay" once the above values have 2221 * been updated. 2222 */ 2223 status = "disabled"; 2224 }; 2225 }; 2226 2227 pcie@140a0000 { 2228 compatible = "nvidia,tegra234-pcie"; 2229 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 2230 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 2231 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 2232 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2233 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2234 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2235 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2236 2237 #address-cells = <3>; 2238 #size-cells = <2>; 2239 device_type = "pci"; 2240 num-lanes = <4>; 2241 num-viewport = <8>; 2242 linux,pci-domain = <8>; 2243 2244 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 2245 clock-names = "core"; 2246 2247 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 2248 <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 2249 reset-names = "apb", "core"; 2250 2251 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2252 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2253 interrupt-names = "intr", "msi"; 2254 2255 #interrupt-cells = <1>; 2256 interrupt-map-mask = <0 0 0 0>; 2257 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2258 2259 nvidia,bpmp = <&bpmp 8>; 2260 2261 nvidia,aspm-cmrt-us = <60>; 2262 nvidia,aspm-pwr-on-t-us = <20>; 2263 nvidia,aspm-l0s-entrance-latency-us = <3>; 2264 2265 bus-range = <0x0 0xff>; 2266 2267 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2268 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2269 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2270 2271 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 2272 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 2273 interconnect-names = "dma-mem", "write"; 2274 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 2275 iommu-map-mask = <0x0>; 2276 dma-coherent; 2277 2278 status = "disabled"; 2279 }; 2280 2281 pcie@140c0000 { 2282 compatible = "nvidia,tegra234-pcie"; 2283 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 2284 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 2285 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 2286 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2287 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2288 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2289 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2290 2291 #address-cells = <3>; 2292 #size-cells = <2>; 2293 device_type = "pci"; 2294 num-lanes = <4>; 2295 num-viewport = <8>; 2296 linux,pci-domain = <9>; 2297 2298 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 2299 clock-names = "core"; 2300 2301 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 2302 <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 2303 reset-names = "apb", "core"; 2304 2305 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2306 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2307 interrupt-names = "intr", "msi"; 2308 2309 #interrupt-cells = <1>; 2310 interrupt-map-mask = <0 0 0 0>; 2311 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2312 2313 nvidia,bpmp = <&bpmp 9>; 2314 2315 nvidia,aspm-cmrt-us = <60>; 2316 nvidia,aspm-pwr-on-t-us = <20>; 2317 nvidia,aspm-l0s-entrance-latency-us = <3>; 2318 2319 bus-range = <0x0 0xff>; 2320 2321 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 2322 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2323 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2324 2325 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 2326 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 2327 interconnect-names = "dma-mem", "write"; 2328 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 2329 iommu-map-mask = <0x0>; 2330 dma-coherent; 2331 2332 status = "disabled"; 2333 }; 2334 2335 pcie@140e0000 { 2336 compatible = "nvidia,tegra234-pcie"; 2337 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2338 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2339 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 2340 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2341 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2342 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2343 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2344 2345 #address-cells = <3>; 2346 #size-cells = <2>; 2347 device_type = "pci"; 2348 num-lanes = <4>; 2349 num-viewport = <8>; 2350 linux,pci-domain = <10>; 2351 2352 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2353 clock-names = "core"; 2354 2355 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2356 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2357 reset-names = "apb", "core"; 2358 2359 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2360 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2361 interrupt-names = "intr", "msi"; 2362 2363 #interrupt-cells = <1>; 2364 interrupt-map-mask = <0 0 0 0>; 2365 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2366 2367 nvidia,bpmp = <&bpmp 10>; 2368 2369 nvidia,aspm-cmrt-us = <60>; 2370 nvidia,aspm-pwr-on-t-us = <20>; 2371 nvidia,aspm-l0s-entrance-latency-us = <3>; 2372 2373 bus-range = <0x0 0xff>; 2374 2375 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2376 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2377 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2378 2379 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2380 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2381 interconnect-names = "dma-mem", "write"; 2382 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2383 iommu-map-mask = <0x0>; 2384 dma-coherent; 2385 2386 status = "disabled"; 2387 }; 2388 2389 pcie-ep@140e0000 { 2390 compatible = "nvidia,tegra234-pcie-ep"; 2391 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 2392 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 2393 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2394 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 2395 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2396 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2397 2398 num-lanes = <4>; 2399 2400 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 2401 clock-names = "core"; 2402 2403 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 2404 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 2405 reset-names = "apb", "core"; 2406 2407 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2408 interrupt-names = "intr"; 2409 2410 nvidia,bpmp = <&bpmp 10>; 2411 2412 nvidia,enable-ext-refclk; 2413 nvidia,aspm-cmrt-us = <60>; 2414 nvidia,aspm-pwr-on-t-us = <20>; 2415 nvidia,aspm-l0s-entrance-latency-us = <3>; 2416 2417 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 2418 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 2419 interconnect-names = "dma-mem", "write"; 2420 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 2421 iommu-map-mask = <0x0>; 2422 dma-coherent; 2423 2424 status = "disabled"; 2425 }; 2426 2427 pcie@14100000 { 2428 compatible = "nvidia,tegra234-pcie"; 2429 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2430 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2431 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2432 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2433 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2434 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2435 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2436 2437 #address-cells = <3>; 2438 #size-cells = <2>; 2439 device_type = "pci"; 2440 num-lanes = <1>; 2441 num-viewport = <8>; 2442 linux,pci-domain = <1>; 2443 2444 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 2445 clock-names = "core"; 2446 2447 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 2448 <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 2449 reset-names = "apb", "core"; 2450 2451 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2452 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2453 interrupt-names = "intr", "msi"; 2454 2455 #interrupt-cells = <1>; 2456 interrupt-map-mask = <0 0 0 0>; 2457 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2458 2459 nvidia,bpmp = <&bpmp 1>; 2460 2461 nvidia,aspm-cmrt-us = <60>; 2462 nvidia,aspm-pwr-on-t-us = <20>; 2463 nvidia,aspm-l0s-entrance-latency-us = <3>; 2464 2465 bus-range = <0x0 0xff>; 2466 2467 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2468 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2469 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2470 2471 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 2472 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 2473 interconnect-names = "dma-mem", "write"; 2474 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 2475 iommu-map-mask = <0x0>; 2476 dma-coherent; 2477 2478 status = "disabled"; 2479 }; 2480 2481 pcie@14120000 { 2482 compatible = "nvidia,tegra234-pcie"; 2483 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2484 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2485 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2486 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2487 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2488 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 2489 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2490 2491 #address-cells = <3>; 2492 #size-cells = <2>; 2493 device_type = "pci"; 2494 num-lanes = <1>; 2495 num-viewport = <8>; 2496 linux,pci-domain = <2>; 2497 2498 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 2499 clock-names = "core"; 2500 2501 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 2502 <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 2503 reset-names = "apb", "core"; 2504 2505 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2506 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2507 interrupt-names = "intr", "msi"; 2508 2509 #interrupt-cells = <1>; 2510 interrupt-map-mask = <0 0 0 0>; 2511 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2512 2513 nvidia,bpmp = <&bpmp 2>; 2514 2515 nvidia,aspm-cmrt-us = <60>; 2516 nvidia,aspm-pwr-on-t-us = <20>; 2517 nvidia,aspm-l0s-entrance-latency-us = <3>; 2518 2519 bus-range = <0x0 0xff>; 2520 2521 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2522 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2523 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2524 2525 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 2526 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 2527 interconnect-names = "dma-mem", "write"; 2528 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 2529 iommu-map-mask = <0x0>; 2530 dma-coherent; 2531 2532 status = "disabled"; 2533 }; 2534 2535 pcie@14140000 { 2536 compatible = "nvidia,tegra234-pcie"; 2537 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 2538 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2539 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2540 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2541 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2542 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2543 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2544 2545 #address-cells = <3>; 2546 #size-cells = <2>; 2547 device_type = "pci"; 2548 num-lanes = <1>; 2549 num-viewport = <8>; 2550 linux,pci-domain = <3>; 2551 2552 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 2553 clock-names = "core"; 2554 2555 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 2556 <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 2557 reset-names = "apb", "core"; 2558 2559 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2560 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2561 interrupt-names = "intr", "msi"; 2562 2563 #interrupt-cells = <1>; 2564 interrupt-map-mask = <0 0 0 0>; 2565 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2566 2567 nvidia,bpmp = <&bpmp 3>; 2568 2569 nvidia,aspm-cmrt-us = <60>; 2570 nvidia,aspm-pwr-on-t-us = <20>; 2571 nvidia,aspm-l0s-entrance-latency-us = <3>; 2572 2573 bus-range = <0x0 0xff>; 2574 2575 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 2576 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2577 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2578 2579 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 2580 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 2581 interconnect-names = "dma-mem", "write"; 2582 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 2583 iommu-map-mask = <0x0>; 2584 dma-coherent; 2585 2586 status = "disabled"; 2587 }; 2588 2589 pcie@14160000 { 2590 compatible = "nvidia,tegra234-pcie"; 2591 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 2592 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2593 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2594 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2595 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2596 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2597 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2598 2599 #address-cells = <3>; 2600 #size-cells = <2>; 2601 device_type = "pci"; 2602 num-lanes = <4>; 2603 num-viewport = <8>; 2604 linux,pci-domain = <4>; 2605 2606 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 2607 clock-names = "core"; 2608 2609 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 2610 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 2611 reset-names = "apb", "core"; 2612 2613 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2614 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2615 interrupt-names = "intr", "msi"; 2616 2617 #interrupt-cells = <1>; 2618 interrupt-map-mask = <0 0 0 0>; 2619 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2620 2621 nvidia,bpmp = <&bpmp 4>; 2622 2623 nvidia,aspm-cmrt-us = <60>; 2624 nvidia,aspm-pwr-on-t-us = <20>; 2625 nvidia,aspm-l0s-entrance-latency-us = <3>; 2626 2627 bus-range = <0x0 0xff>; 2628 2629 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2630 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2631 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2632 2633 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 2634 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 2635 interconnect-names = "dma-mem", "write"; 2636 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 2637 iommu-map-mask = <0x0>; 2638 dma-coherent; 2639 2640 status = "disabled"; 2641 }; 2642 2643 pcie@14180000 { 2644 compatible = "nvidia,tegra234-pcie"; 2645 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 2646 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2647 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2648 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2649 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2650 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2651 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2652 2653 #address-cells = <3>; 2654 #size-cells = <2>; 2655 device_type = "pci"; 2656 num-lanes = <4>; 2657 num-viewport = <8>; 2658 linux,pci-domain = <0>; 2659 2660 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 2661 clock-names = "core"; 2662 2663 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 2664 <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 2665 reset-names = "apb", "core"; 2666 2667 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2668 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2669 interrupt-names = "intr", "msi"; 2670 2671 #interrupt-cells = <1>; 2672 interrupt-map-mask = <0 0 0 0>; 2673 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2674 2675 nvidia,bpmp = <&bpmp 0>; 2676 2677 nvidia,aspm-cmrt-us = <60>; 2678 nvidia,aspm-pwr-on-t-us = <20>; 2679 nvidia,aspm-l0s-entrance-latency-us = <3>; 2680 2681 bus-range = <0x0 0xff>; 2682 2683 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2684 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2685 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2686 2687 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 2688 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 2689 interconnect-names = "dma-mem", "write"; 2690 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 2691 iommu-map-mask = <0x0>; 2692 dma-coherent; 2693 2694 status = "disabled"; 2695 }; 2696 2697 pcie@141a0000 { 2698 compatible = "nvidia,tegra234-pcie"; 2699 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2700 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2701 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2702 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2703 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2704 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2705 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2706 2707 #address-cells = <3>; 2708 #size-cells = <2>; 2709 device_type = "pci"; 2710 num-lanes = <8>; 2711 num-viewport = <8>; 2712 linux,pci-domain = <5>; 2713 2714 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2715 clock-names = "core"; 2716 2717 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2718 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2719 reset-names = "apb", "core"; 2720 2721 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2722 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2723 interrupt-names = "intr", "msi"; 2724 2725 #interrupt-cells = <1>; 2726 interrupt-map-mask = <0 0 0 0>; 2727 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2728 2729 nvidia,bpmp = <&bpmp 5>; 2730 2731 nvidia,aspm-cmrt-us = <60>; 2732 nvidia,aspm-pwr-on-t-us = <20>; 2733 nvidia,aspm-l0s-entrance-latency-us = <3>; 2734 2735 bus-range = <0x0 0xff>; 2736 2737 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 2738 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2739 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2740 2741 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2742 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2743 interconnect-names = "dma-mem", "write"; 2744 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2745 iommu-map-mask = <0x0>; 2746 dma-coherent; 2747 2748 status = "disabled"; 2749 }; 2750 2751 pcie-ep@141a0000 { 2752 compatible = "nvidia,tegra234-pcie-ep"; 2753 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 2754 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2755 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2756 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2757 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2758 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2759 2760 num-lanes = <8>; 2761 2762 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 2763 clock-names = "core"; 2764 2765 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 2766 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 2767 reset-names = "apb", "core"; 2768 2769 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2770 interrupt-names = "intr"; 2771 2772 nvidia,bpmp = <&bpmp 5>; 2773 2774 nvidia,enable-ext-refclk; 2775 nvidia,aspm-cmrt-us = <60>; 2776 nvidia,aspm-pwr-on-t-us = <20>; 2777 nvidia,aspm-l0s-entrance-latency-us = <3>; 2778 2779 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 2780 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 2781 interconnect-names = "dma-mem", "write"; 2782 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 2783 iommu-map-mask = <0x0>; 2784 dma-coherent; 2785 2786 status = "disabled"; 2787 }; 2788 2789 pcie@141c0000 { 2790 compatible = "nvidia,tegra234-pcie"; 2791 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2792 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2793 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 2794 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2795 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2796 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2797 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2798 2799 #address-cells = <3>; 2800 #size-cells = <2>; 2801 device_type = "pci"; 2802 num-lanes = <4>; 2803 num-viewport = <8>; 2804 linux,pci-domain = <6>; 2805 2806 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2807 clock-names = "core"; 2808 2809 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2810 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2811 reset-names = "apb", "core"; 2812 2813 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2814 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2815 interrupt-names = "intr", "msi"; 2816 2817 #interrupt-cells = <1>; 2818 interrupt-map-mask = <0 0 0 0>; 2819 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2820 2821 nvidia,bpmp = <&bpmp 6>; 2822 2823 nvidia,aspm-cmrt-us = <60>; 2824 nvidia,aspm-pwr-on-t-us = <20>; 2825 nvidia,aspm-l0s-entrance-latency-us = <3>; 2826 2827 bus-range = <0x0 0xff>; 2828 2829 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 2830 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2831 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2832 2833 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2834 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2835 interconnect-names = "dma-mem", "write"; 2836 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2837 iommu-map-mask = <0x0>; 2838 dma-coherent; 2839 2840 status = "disabled"; 2841 }; 2842 2843 pcie-ep@141c0000 { 2844 compatible = "nvidia,tegra234-pcie-ep"; 2845 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 2846 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 2847 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2848 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 2849 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 2850 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2851 2852 num-lanes = <4>; 2853 2854 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 2855 clock-names = "core"; 2856 2857 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 2858 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 2859 reset-names = "apb", "core"; 2860 2861 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2862 interrupt-names = "intr"; 2863 2864 nvidia,bpmp = <&bpmp 6>; 2865 2866 nvidia,enable-ext-refclk; 2867 nvidia,aspm-cmrt-us = <60>; 2868 nvidia,aspm-pwr-on-t-us = <20>; 2869 nvidia,aspm-l0s-entrance-latency-us = <3>; 2870 2871 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 2872 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 2873 interconnect-names = "dma-mem", "write"; 2874 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 2875 iommu-map-mask = <0x0>; 2876 dma-coherent; 2877 2878 status = "disabled"; 2879 }; 2880 2881 pcie@141e0000 { 2882 compatible = "nvidia,tegra234-pcie"; 2883 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2884 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2885 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 2886 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2887 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2888 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 2889 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 2890 2891 #address-cells = <3>; 2892 #size-cells = <2>; 2893 device_type = "pci"; 2894 num-lanes = <8>; 2895 num-viewport = <8>; 2896 linux,pci-domain = <7>; 2897 2898 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2899 clock-names = "core"; 2900 2901 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2902 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2903 reset-names = "apb", "core"; 2904 2905 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2906 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2907 interrupt-names = "intr", "msi"; 2908 2909 #interrupt-cells = <1>; 2910 interrupt-map-mask = <0 0 0 0>; 2911 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2912 2913 nvidia,bpmp = <&bpmp 7>; 2914 2915 nvidia,aspm-cmrt-us = <60>; 2916 nvidia,aspm-pwr-on-t-us = <20>; 2917 nvidia,aspm-l0s-entrance-latency-us = <3>; 2918 2919 bus-range = <0x0 0xff>; 2920 2921 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 2922 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 2923 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 2924 2925 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2926 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2927 interconnect-names = "dma-mem", "write"; 2928 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2929 iommu-map-mask = <0x0>; 2930 dma-coherent; 2931 2932 status = "disabled"; 2933 }; 2934 2935 pcie-ep@141e0000 { 2936 compatible = "nvidia,tegra234-pcie-ep"; 2937 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 2938 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 2939 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2940 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 2941 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 2942 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2943 2944 num-lanes = <8>; 2945 2946 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 2947 clock-names = "core"; 2948 2949 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 2950 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 2951 reset-names = "apb", "core"; 2952 2953 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2954 interrupt-names = "intr"; 2955 2956 nvidia,bpmp = <&bpmp 7>; 2957 2958 nvidia,enable-ext-refclk; 2959 nvidia,aspm-cmrt-us = <60>; 2960 nvidia,aspm-pwr-on-t-us = <20>; 2961 nvidia,aspm-l0s-entrance-latency-us = <3>; 2962 2963 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 2964 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 2965 interconnect-names = "dma-mem", "write"; 2966 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 2967 iommu-map-mask = <0x0>; 2968 dma-coherent; 2969 2970 status = "disabled"; 2971 }; 2972 }; 2973 2974 sram@40000000 { 2975 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 2976 reg = <0x0 0x40000000 0x0 0x80000>; 2977 2978 #address-cells = <1>; 2979 #size-cells = <1>; 2980 ranges = <0x0 0x0 0x40000000 0x80000>; 2981 2982 no-memory-wc; 2983 2984 cpu_bpmp_tx: sram@70000 { 2985 reg = <0x70000 0x1000>; 2986 label = "cpu-bpmp-tx"; 2987 pool; 2988 }; 2989 2990 cpu_bpmp_rx: sram@71000 { 2991 reg = <0x71000 0x1000>; 2992 label = "cpu-bpmp-rx"; 2993 pool; 2994 }; 2995 }; 2996 2997 bpmp: bpmp { 2998 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 2999 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 3000 TEGRA_HSP_DB_MASTER_BPMP>; 3001 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 3002 #clock-cells = <1>; 3003 #reset-cells = <1>; 3004 #power-domain-cells = <1>; 3005 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 3006 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 3007 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 3008 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 3009 interconnect-names = "read", "write", "dma-mem", "dma-write"; 3010 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 3011 3012 bpmp_i2c: i2c { 3013 compatible = "nvidia,tegra186-bpmp-i2c"; 3014 nvidia,bpmp-bus-id = <5>; 3015 #address-cells = <1>; 3016 #size-cells = <0>; 3017 }; 3018 }; 3019 3020 cpus { 3021 #address-cells = <1>; 3022 #size-cells = <0>; 3023 3024 cpu0_0: cpu@0 { 3025 compatible = "arm,cortex-a78"; 3026 device_type = "cpu"; 3027 reg = <0x00000>; 3028 3029 enable-method = "psci"; 3030 3031 i-cache-size = <65536>; 3032 i-cache-line-size = <64>; 3033 i-cache-sets = <256>; 3034 d-cache-size = <65536>; 3035 d-cache-line-size = <64>; 3036 d-cache-sets = <256>; 3037 next-level-cache = <&l2c0_0>; 3038 }; 3039 3040 cpu0_1: cpu@100 { 3041 compatible = "arm,cortex-a78"; 3042 device_type = "cpu"; 3043 reg = <0x00100>; 3044 3045 enable-method = "psci"; 3046 3047 i-cache-size = <65536>; 3048 i-cache-line-size = <64>; 3049 i-cache-sets = <256>; 3050 d-cache-size = <65536>; 3051 d-cache-line-size = <64>; 3052 d-cache-sets = <256>; 3053 next-level-cache = <&l2c0_1>; 3054 }; 3055 3056 cpu0_2: cpu@200 { 3057 compatible = "arm,cortex-a78"; 3058 device_type = "cpu"; 3059 reg = <0x00200>; 3060 3061 enable-method = "psci"; 3062 3063 i-cache-size = <65536>; 3064 i-cache-line-size = <64>; 3065 i-cache-sets = <256>; 3066 d-cache-size = <65536>; 3067 d-cache-line-size = <64>; 3068 d-cache-sets = <256>; 3069 next-level-cache = <&l2c0_2>; 3070 }; 3071 3072 cpu0_3: cpu@300 { 3073 compatible = "arm,cortex-a78"; 3074 device_type = "cpu"; 3075 reg = <0x00300>; 3076 3077 enable-method = "psci"; 3078 3079 i-cache-size = <65536>; 3080 i-cache-line-size = <64>; 3081 i-cache-sets = <256>; 3082 d-cache-size = <65536>; 3083 d-cache-line-size = <64>; 3084 d-cache-sets = <256>; 3085 next-level-cache = <&l2c0_3>; 3086 }; 3087 3088 cpu1_0: cpu@10000 { 3089 compatible = "arm,cortex-a78"; 3090 device_type = "cpu"; 3091 reg = <0x10000>; 3092 3093 enable-method = "psci"; 3094 3095 i-cache-size = <65536>; 3096 i-cache-line-size = <64>; 3097 i-cache-sets = <256>; 3098 d-cache-size = <65536>; 3099 d-cache-line-size = <64>; 3100 d-cache-sets = <256>; 3101 next-level-cache = <&l2c1_0>; 3102 }; 3103 3104 cpu1_1: cpu@10100 { 3105 compatible = "arm,cortex-a78"; 3106 device_type = "cpu"; 3107 reg = <0x10100>; 3108 3109 enable-method = "psci"; 3110 3111 i-cache-size = <65536>; 3112 i-cache-line-size = <64>; 3113 i-cache-sets = <256>; 3114 d-cache-size = <65536>; 3115 d-cache-line-size = <64>; 3116 d-cache-sets = <256>; 3117 next-level-cache = <&l2c1_1>; 3118 }; 3119 3120 cpu1_2: cpu@10200 { 3121 compatible = "arm,cortex-a78"; 3122 device_type = "cpu"; 3123 reg = <0x10200>; 3124 3125 enable-method = "psci"; 3126 3127 i-cache-size = <65536>; 3128 i-cache-line-size = <64>; 3129 i-cache-sets = <256>; 3130 d-cache-size = <65536>; 3131 d-cache-line-size = <64>; 3132 d-cache-sets = <256>; 3133 next-level-cache = <&l2c1_2>; 3134 }; 3135 3136 cpu1_3: cpu@10300 { 3137 compatible = "arm,cortex-a78"; 3138 device_type = "cpu"; 3139 reg = <0x10300>; 3140 3141 enable-method = "psci"; 3142 3143 i-cache-size = <65536>; 3144 i-cache-line-size = <64>; 3145 i-cache-sets = <256>; 3146 d-cache-size = <65536>; 3147 d-cache-line-size = <64>; 3148 d-cache-sets = <256>; 3149 next-level-cache = <&l2c1_3>; 3150 }; 3151 3152 cpu2_0: cpu@20000 { 3153 compatible = "arm,cortex-a78"; 3154 device_type = "cpu"; 3155 reg = <0x20000>; 3156 3157 enable-method = "psci"; 3158 3159 i-cache-size = <65536>; 3160 i-cache-line-size = <64>; 3161 i-cache-sets = <256>; 3162 d-cache-size = <65536>; 3163 d-cache-line-size = <64>; 3164 d-cache-sets = <256>; 3165 next-level-cache = <&l2c2_0>; 3166 }; 3167 3168 cpu2_1: cpu@20100 { 3169 compatible = "arm,cortex-a78"; 3170 device_type = "cpu"; 3171 reg = <0x20100>; 3172 3173 enable-method = "psci"; 3174 3175 i-cache-size = <65536>; 3176 i-cache-line-size = <64>; 3177 i-cache-sets = <256>; 3178 d-cache-size = <65536>; 3179 d-cache-line-size = <64>; 3180 d-cache-sets = <256>; 3181 next-level-cache = <&l2c2_1>; 3182 }; 3183 3184 cpu2_2: cpu@20200 { 3185 compatible = "arm,cortex-a78"; 3186 device_type = "cpu"; 3187 reg = <0x20200>; 3188 3189 enable-method = "psci"; 3190 3191 i-cache-size = <65536>; 3192 i-cache-line-size = <64>; 3193 i-cache-sets = <256>; 3194 d-cache-size = <65536>; 3195 d-cache-line-size = <64>; 3196 d-cache-sets = <256>; 3197 next-level-cache = <&l2c2_2>; 3198 }; 3199 3200 cpu2_3: cpu@20300 { 3201 compatible = "arm,cortex-a78"; 3202 device_type = "cpu"; 3203 reg = <0x20300>; 3204 3205 enable-method = "psci"; 3206 3207 i-cache-size = <65536>; 3208 i-cache-line-size = <64>; 3209 i-cache-sets = <256>; 3210 d-cache-size = <65536>; 3211 d-cache-line-size = <64>; 3212 d-cache-sets = <256>; 3213 next-level-cache = <&l2c2_3>; 3214 }; 3215 3216 cpu-map { 3217 cluster0 { 3218 core0 { 3219 cpu = <&cpu0_0>; 3220 }; 3221 3222 core1 { 3223 cpu = <&cpu0_1>; 3224 }; 3225 3226 core2 { 3227 cpu = <&cpu0_2>; 3228 }; 3229 3230 core3 { 3231 cpu = <&cpu0_3>; 3232 }; 3233 }; 3234 3235 cluster1 { 3236 core0 { 3237 cpu = <&cpu1_0>; 3238 }; 3239 3240 core1 { 3241 cpu = <&cpu1_1>; 3242 }; 3243 3244 core2 { 3245 cpu = <&cpu1_2>; 3246 }; 3247 3248 core3 { 3249 cpu = <&cpu1_3>; 3250 }; 3251 }; 3252 3253 cluster2 { 3254 core0 { 3255 cpu = <&cpu2_0>; 3256 }; 3257 3258 core1 { 3259 cpu = <&cpu2_1>; 3260 }; 3261 3262 core2 { 3263 cpu = <&cpu2_2>; 3264 }; 3265 3266 core3 { 3267 cpu = <&cpu2_3>; 3268 }; 3269 }; 3270 }; 3271 3272 l2c0_0: l2-cache00 { 3273 compatible = "cache"; 3274 cache-size = <262144>; 3275 cache-line-size = <64>; 3276 cache-sets = <512>; 3277 cache-unified; 3278 cache-level = <2>; 3279 next-level-cache = <&l3c0>; 3280 }; 3281 3282 l2c0_1: l2-cache01 { 3283 compatible = "cache"; 3284 cache-size = <262144>; 3285 cache-line-size = <64>; 3286 cache-sets = <512>; 3287 cache-unified; 3288 cache-level = <2>; 3289 next-level-cache = <&l3c0>; 3290 }; 3291 3292 l2c0_2: l2-cache02 { 3293 compatible = "cache"; 3294 cache-size = <262144>; 3295 cache-line-size = <64>; 3296 cache-sets = <512>; 3297 cache-unified; 3298 cache-level = <2>; 3299 next-level-cache = <&l3c0>; 3300 }; 3301 3302 l2c0_3: l2-cache03 { 3303 compatible = "cache"; 3304 cache-size = <262144>; 3305 cache-line-size = <64>; 3306 cache-sets = <512>; 3307 cache-unified; 3308 cache-level = <2>; 3309 next-level-cache = <&l3c0>; 3310 }; 3311 3312 l2c1_0: l2-cache10 { 3313 compatible = "cache"; 3314 cache-size = <262144>; 3315 cache-line-size = <64>; 3316 cache-sets = <512>; 3317 cache-unified; 3318 cache-level = <2>; 3319 next-level-cache = <&l3c1>; 3320 }; 3321 3322 l2c1_1: l2-cache11 { 3323 compatible = "cache"; 3324 cache-size = <262144>; 3325 cache-line-size = <64>; 3326 cache-sets = <512>; 3327 cache-unified; 3328 cache-level = <2>; 3329 next-level-cache = <&l3c1>; 3330 }; 3331 3332 l2c1_2: l2-cache12 { 3333 compatible = "cache"; 3334 cache-size = <262144>; 3335 cache-line-size = <64>; 3336 cache-sets = <512>; 3337 cache-unified; 3338 cache-level = <2>; 3339 next-level-cache = <&l3c1>; 3340 }; 3341 3342 l2c1_3: l2-cache13 { 3343 compatible = "cache"; 3344 cache-size = <262144>; 3345 cache-line-size = <64>; 3346 cache-sets = <512>; 3347 cache-unified; 3348 cache-level = <2>; 3349 next-level-cache = <&l3c1>; 3350 }; 3351 3352 l2c2_0: l2-cache20 { 3353 compatible = "cache"; 3354 cache-size = <262144>; 3355 cache-line-size = <64>; 3356 cache-sets = <512>; 3357 cache-unified; 3358 cache-level = <2>; 3359 next-level-cache = <&l3c2>; 3360 }; 3361 3362 l2c2_1: l2-cache21 { 3363 compatible = "cache"; 3364 cache-size = <262144>; 3365 cache-line-size = <64>; 3366 cache-sets = <512>; 3367 cache-unified; 3368 cache-level = <2>; 3369 next-level-cache = <&l3c2>; 3370 }; 3371 3372 l2c2_2: l2-cache22 { 3373 compatible = "cache"; 3374 cache-size = <262144>; 3375 cache-line-size = <64>; 3376 cache-sets = <512>; 3377 cache-unified; 3378 cache-level = <2>; 3379 next-level-cache = <&l3c2>; 3380 }; 3381 3382 l2c2_3: l2-cache23 { 3383 compatible = "cache"; 3384 cache-size = <262144>; 3385 cache-line-size = <64>; 3386 cache-sets = <512>; 3387 cache-unified; 3388 cache-level = <2>; 3389 next-level-cache = <&l3c2>; 3390 }; 3391 3392 l3c0: l3-cache0 { 3393 compatible = "cache"; 3394 cache-unified; 3395 cache-size = <2097152>; 3396 cache-line-size = <64>; 3397 cache-sets = <2048>; 3398 cache-level = <3>; 3399 }; 3400 3401 l3c1: l3-cache1 { 3402 compatible = "cache"; 3403 cache-unified; 3404 cache-size = <2097152>; 3405 cache-line-size = <64>; 3406 cache-sets = <2048>; 3407 cache-level = <3>; 3408 }; 3409 3410 l3c2: l3-cache2 { 3411 compatible = "cache"; 3412 cache-unified; 3413 cache-size = <2097152>; 3414 cache-line-size = <64>; 3415 cache-sets = <2048>; 3416 cache-level = <3>; 3417 }; 3418 }; 3419 3420 dsu-pmu0 { 3421 compatible = "arm,dsu-pmu"; 3422 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 3423 cpus = <&cpu0_0>, <&cpu0_1>, <&cpu0_2>, <&cpu0_3>; 3424 }; 3425 3426 dsu-pmu1 { 3427 compatible = "arm,dsu-pmu"; 3428 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>; 3429 cpus = <&cpu1_0>, <&cpu1_1>, <&cpu1_2>, <&cpu1_3>; 3430 }; 3431 3432 dsu-pmu2 { 3433 compatible = "arm,dsu-pmu"; 3434 interrupts = <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 3435 cpus = <&cpu2_0>, <&cpu2_1>, <&cpu2_2>, <&cpu2_3>; 3436 }; 3437 3438 pmu { 3439 compatible = "arm,cortex-a78-pmu"; 3440 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 3441 status = "okay"; 3442 }; 3443 3444 psci { 3445 compatible = "arm,psci-1.0"; 3446 status = "okay"; 3447 method = "smc"; 3448 }; 3449 3450 tcu: serial { 3451 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 3452 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3453 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3454 mbox-names = "rx", "tx"; 3455 status = "disabled"; 3456 }; 3457 3458 sound { 3459 status = "disabled"; 3460 3461 clocks = <&bpmp TEGRA234_CLK_PLLA>, 3462 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3463 clock-names = "pll_a", "plla_out0"; 3464 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 3465 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 3466 <&bpmp TEGRA234_CLK_AUD_MCLK>; 3467 assigned-clock-parents = <0>, 3468 <&bpmp TEGRA234_CLK_PLLA>, 3469 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 3470 }; 3471 3472 timer { 3473 compatible = "arm,armv8-timer"; 3474 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3475 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3476 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3477 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3478 interrupt-parent = <&gic>; 3479 always-on; 3480 }; 3481}; 3482