1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/thermal/tegra124-soctherm.h> 8 9/ { 10 compatible = "nvidia,tegra210"; 11 interrupt-parent = <&lic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 pcie@1003000 { 16 compatible = "nvidia,tegra210-pcie"; 17 device_type = "pci"; 18 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 19 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 20 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 21 reg-names = "pads", "afi", "cs"; 22 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 23 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24 interrupt-names = "intr", "msi"; 25 26 #interrupt-cells = <1>; 27 interrupt-map-mask = <0 0 0 0>; 28 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 29 30 bus-range = <0x00 0xff>; 31 #address-cells = <3>; 32 #size-cells = <2>; 33 34 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 35 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 36 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 37 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 38 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 39 40 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 41 <&tegra_car TEGRA210_CLK_AFI>, 42 <&tegra_car TEGRA210_CLK_PLL_E>, 43 <&tegra_car TEGRA210_CLK_CML0>; 44 clock-names = "pex", "afi", "pll_e", "cml"; 45 resets = <&tegra_car 70>, 46 <&tegra_car 72>, 47 <&tegra_car 74>; 48 reset-names = "pex", "afi", "pcie_x"; 49 status = "disabled"; 50 51 pci@1,0 { 52 device_type = "pci"; 53 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 54 reg = <0x000800 0 0 0 0>; 55 bus-range = <0x00 0xff>; 56 status = "disabled"; 57 58 #address-cells = <3>; 59 #size-cells = <2>; 60 ranges; 61 62 nvidia,num-lanes = <4>; 63 }; 64 65 pci@2,0 { 66 device_type = "pci"; 67 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 68 reg = <0x001000 0 0 0 0>; 69 bus-range = <0x00 0xff>; 70 status = "disabled"; 71 72 #address-cells = <3>; 73 #size-cells = <2>; 74 ranges; 75 76 nvidia,num-lanes = <1>; 77 }; 78 }; 79 80 host1x@50000000 { 81 compatible = "nvidia,tegra210-host1x", "simple-bus"; 82 reg = <0x0 0x50000000 0x0 0x00034000>; 83 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 84 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 85 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 86 clock-names = "host1x"; 87 resets = <&tegra_car 28>; 88 reset-names = "host1x"; 89 90 #address-cells = <2>; 91 #size-cells = <2>; 92 93 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 94 95 iommus = <&mc TEGRA_SWGROUP_HC>; 96 97 dpaux1: dpaux@54040000 { 98 compatible = "nvidia,tegra210-dpaux"; 99 reg = <0x0 0x54040000 0x0 0x00040000>; 100 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 101 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 102 <&tegra_car TEGRA210_CLK_PLL_DP>; 103 clock-names = "dpaux", "parent"; 104 resets = <&tegra_car 207>; 105 reset-names = "dpaux"; 106 power-domains = <&pd_sor>; 107 status = "disabled"; 108 109 state_dpaux1_aux: pinmux-aux { 110 groups = "dpaux-io"; 111 function = "aux"; 112 }; 113 114 state_dpaux1_i2c: pinmux-i2c { 115 groups = "dpaux-io"; 116 function = "i2c"; 117 }; 118 119 state_dpaux1_off: pinmux-off { 120 groups = "dpaux-io"; 121 function = "off"; 122 }; 123 124 i2c-bus { 125 #address-cells = <1>; 126 #size-cells = <0>; 127 }; 128 }; 129 130 vi@54080000 { 131 compatible = "nvidia,tegra210-vi"; 132 reg = <0x0 0x54080000 0x0 0x00040000>; 133 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 134 status = "disabled"; 135 }; 136 137 tsec@54100000 { 138 compatible = "nvidia,tegra210-tsec"; 139 reg = <0x0 0x54100000 0x0 0x00040000>; 140 }; 141 142 dc@54200000 { 143 compatible = "nvidia,tegra210-dc"; 144 reg = <0x0 0x54200000 0x0 0x00040000>; 145 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 147 <&tegra_car TEGRA210_CLK_PLL_P>; 148 clock-names = "dc", "parent"; 149 resets = <&tegra_car 27>; 150 reset-names = "dc"; 151 152 iommus = <&mc TEGRA_SWGROUP_DC>; 153 154 nvidia,head = <0>; 155 }; 156 157 dc@54240000 { 158 compatible = "nvidia,tegra210-dc"; 159 reg = <0x0 0x54240000 0x0 0x00040000>; 160 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 161 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 162 <&tegra_car TEGRA210_CLK_PLL_P>; 163 clock-names = "dc", "parent"; 164 resets = <&tegra_car 26>; 165 reset-names = "dc"; 166 167 iommus = <&mc TEGRA_SWGROUP_DCB>; 168 169 nvidia,head = <1>; 170 }; 171 172 dsi@54300000 { 173 compatible = "nvidia,tegra210-dsi"; 174 reg = <0x0 0x54300000 0x0 0x00040000>; 175 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 176 <&tegra_car TEGRA210_CLK_DSIALP>, 177 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 178 clock-names = "dsi", "lp", "parent"; 179 resets = <&tegra_car 48>; 180 reset-names = "dsi"; 181 power-domains = <&pd_sor>; 182 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 183 184 status = "disabled"; 185 186 #address-cells = <1>; 187 #size-cells = <0>; 188 }; 189 190 vic@54340000 { 191 compatible = "nvidia,tegra210-vic"; 192 reg = <0x0 0x54340000 0x0 0x00040000>; 193 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 194 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 195 clock-names = "vic"; 196 resets = <&tegra_car 178>; 197 reset-names = "vic"; 198 199 iommus = <&mc TEGRA_SWGROUP_VIC>; 200 power-domains = <&pd_vic>; 201 }; 202 203 nvjpg@54380000 { 204 compatible = "nvidia,tegra210-nvjpg"; 205 reg = <0x0 0x54380000 0x0 0x00040000>; 206 status = "disabled"; 207 }; 208 209 dsi@54400000 { 210 compatible = "nvidia,tegra210-dsi"; 211 reg = <0x0 0x54400000 0x0 0x00040000>; 212 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 213 <&tegra_car TEGRA210_CLK_DSIBLP>, 214 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 215 clock-names = "dsi", "lp", "parent"; 216 resets = <&tegra_car 82>; 217 reset-names = "dsi"; 218 power-domains = <&pd_sor>; 219 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 220 221 status = "disabled"; 222 223 #address-cells = <1>; 224 #size-cells = <0>; 225 }; 226 227 nvdec@54480000 { 228 compatible = "nvidia,tegra210-nvdec"; 229 reg = <0x0 0x54480000 0x0 0x00040000>; 230 status = "disabled"; 231 }; 232 233 nvenc@544c0000 { 234 compatible = "nvidia,tegra210-nvenc"; 235 reg = <0x0 0x544c0000 0x0 0x00040000>; 236 status = "disabled"; 237 }; 238 239 tsec@54500000 { 240 compatible = "nvidia,tegra210-tsec"; 241 reg = <0x0 0x54500000 0x0 0x00040000>; 242 status = "disabled"; 243 }; 244 245 sor@54540000 { 246 compatible = "nvidia,tegra210-sor"; 247 reg = <0x0 0x54540000 0x0 0x00040000>; 248 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 250 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 251 <&tegra_car TEGRA210_CLK_PLL_DP>, 252 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 253 clock-names = "sor", "parent", "dp", "safe"; 254 resets = <&tegra_car 182>; 255 reset-names = "sor"; 256 pinctrl-0 = <&state_dpaux_aux>; 257 pinctrl-1 = <&state_dpaux_i2c>; 258 pinctrl-2 = <&state_dpaux_off>; 259 pinctrl-names = "aux", "i2c", "off"; 260 power-domains = <&pd_sor>; 261 status = "disabled"; 262 }; 263 264 sor@54580000 { 265 compatible = "nvidia,tegra210-sor1"; 266 reg = <0x0 0x54580000 0x0 0x00040000>; 267 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 269 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 270 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 271 <&tegra_car TEGRA210_CLK_PLL_DP>, 272 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 273 clock-names = "sor", "out", "parent", "dp", "safe"; 274 resets = <&tegra_car 183>; 275 reset-names = "sor"; 276 pinctrl-0 = <&state_dpaux1_aux>; 277 pinctrl-1 = <&state_dpaux1_i2c>; 278 pinctrl-2 = <&state_dpaux1_off>; 279 pinctrl-names = "aux", "i2c", "off"; 280 power-domains = <&pd_sor>; 281 status = "disabled"; 282 }; 283 284 dpaux: dpaux@545c0000 { 285 compatible = "nvidia,tegra124-dpaux"; 286 reg = <0x0 0x545c0000 0x0 0x00040000>; 287 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 289 <&tegra_car TEGRA210_CLK_PLL_DP>; 290 clock-names = "dpaux", "parent"; 291 resets = <&tegra_car 181>; 292 reset-names = "dpaux"; 293 power-domains = <&pd_sor>; 294 status = "disabled"; 295 296 state_dpaux_aux: pinmux-aux { 297 groups = "dpaux-io"; 298 function = "aux"; 299 }; 300 301 state_dpaux_i2c: pinmux-i2c { 302 groups = "dpaux-io"; 303 function = "i2c"; 304 }; 305 306 state_dpaux_off: pinmux-off { 307 groups = "dpaux-io"; 308 function = "off"; 309 }; 310 311 i2c-bus { 312 #address-cells = <1>; 313 #size-cells = <0>; 314 }; 315 }; 316 317 isp@54600000 { 318 compatible = "nvidia,tegra210-isp"; 319 reg = <0x0 0x54600000 0x0 0x00040000>; 320 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 321 status = "disabled"; 322 }; 323 324 isp@54680000 { 325 compatible = "nvidia,tegra210-isp"; 326 reg = <0x0 0x54680000 0x0 0x00040000>; 327 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 328 status = "disabled"; 329 }; 330 331 i2c@546c0000 { 332 compatible = "nvidia,tegra210-i2c-vi"; 333 reg = <0x0 0x546c0000 0x0 0x00040000>; 334 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 335 status = "disabled"; 336 }; 337 }; 338 339 gic: interrupt-controller@50041000 { 340 compatible = "arm,gic-400"; 341 #interrupt-cells = <3>; 342 interrupt-controller; 343 reg = <0x0 0x50041000 0x0 0x1000>, 344 <0x0 0x50042000 0x0 0x2000>, 345 <0x0 0x50044000 0x0 0x2000>, 346 <0x0 0x50046000 0x0 0x2000>; 347 interrupts = <GIC_PPI 9 348 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 349 interrupt-parent = <&gic>; 350 }; 351 352 gpu@57000000 { 353 compatible = "nvidia,gm20b"; 354 reg = <0x0 0x57000000 0x0 0x01000000>, 355 <0x0 0x58000000 0x0 0x01000000>; 356 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 358 interrupt-names = "stall", "nonstall"; 359 clocks = <&tegra_car TEGRA210_CLK_GPU>, 360 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 361 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 362 clock-names = "gpu", "pwr", "ref"; 363 resets = <&tegra_car 184>; 364 reset-names = "gpu"; 365 366 iommus = <&mc TEGRA_SWGROUP_GPU>; 367 368 status = "disabled"; 369 }; 370 371 lic: interrupt-controller@60004000 { 372 compatible = "nvidia,tegra210-ictlr"; 373 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 374 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 375 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 376 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 377 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 378 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 379 interrupt-controller; 380 #interrupt-cells = <3>; 381 interrupt-parent = <&gic>; 382 }; 383 384 timer@60005000 { 385 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 386 reg = <0x0 0x60005000 0x0 0x400>; 387 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 394 clock-names = "timer"; 395 }; 396 397 tegra_car: clock@60006000 { 398 compatible = "nvidia,tegra210-car"; 399 reg = <0x0 0x60006000 0x0 0x1000>; 400 #clock-cells = <1>; 401 #reset-cells = <1>; 402 }; 403 404 flow-controller@60007000 { 405 compatible = "nvidia,tegra210-flowctrl"; 406 reg = <0x0 0x60007000 0x0 0x1000>; 407 }; 408 409 gpio: gpio@6000d000 { 410 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 411 reg = <0x0 0x6000d000 0x0 0x1000>; 412 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 420 #gpio-cells = <2>; 421 gpio-controller; 422 #interrupt-cells = <2>; 423 interrupt-controller; 424 }; 425 426 apbdma: dma@60020000 { 427 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 428 reg = <0x0 0x60020000 0x0 0x1400>; 429 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 462 clock-names = "dma"; 463 resets = <&tegra_car 34>; 464 reset-names = "dma"; 465 #dma-cells = <1>; 466 }; 467 468 apbmisc@70000800 { 469 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 470 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 471 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 472 }; 473 474 pinmux: pinmux@700008d4 { 475 compatible = "nvidia,tegra210-pinmux"; 476 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 477 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 478 }; 479 480 /* 481 * There are two serial driver i.e. 8250 based simple serial 482 * driver and APB DMA based serial driver for higher baudrate 483 * and performance. To enable the 8250 based driver, the compatible 484 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 485 * the APB DMA based serial driver, the compatible is 486 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 487 */ 488 uarta: serial@70006000 { 489 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 490 reg = <0x0 0x70006000 0x0 0x40>; 491 reg-shift = <2>; 492 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 494 clock-names = "serial"; 495 resets = <&tegra_car 6>; 496 reset-names = "serial"; 497 dmas = <&apbdma 8>, <&apbdma 8>; 498 dma-names = "rx", "tx"; 499 status = "disabled"; 500 }; 501 502 uartb: serial@70006040 { 503 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 504 reg = <0x0 0x70006040 0x0 0x40>; 505 reg-shift = <2>; 506 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 508 clock-names = "serial"; 509 resets = <&tegra_car 7>; 510 reset-names = "serial"; 511 dmas = <&apbdma 9>, <&apbdma 9>; 512 dma-names = "rx", "tx"; 513 status = "disabled"; 514 }; 515 516 uartc: serial@70006200 { 517 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 518 reg = <0x0 0x70006200 0x0 0x40>; 519 reg-shift = <2>; 520 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 522 clock-names = "serial"; 523 resets = <&tegra_car 55>; 524 reset-names = "serial"; 525 dmas = <&apbdma 10>, <&apbdma 10>; 526 dma-names = "rx", "tx"; 527 status = "disabled"; 528 }; 529 530 uartd: serial@70006300 { 531 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 532 reg = <0x0 0x70006300 0x0 0x40>; 533 reg-shift = <2>; 534 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 536 clock-names = "serial"; 537 resets = <&tegra_car 65>; 538 reset-names = "serial"; 539 dmas = <&apbdma 19>, <&apbdma 19>; 540 dma-names = "rx", "tx"; 541 status = "disabled"; 542 }; 543 544 pwm: pwm@7000a000 { 545 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 546 reg = <0x0 0x7000a000 0x0 0x100>; 547 #pwm-cells = <2>; 548 clocks = <&tegra_car TEGRA210_CLK_PWM>; 549 clock-names = "pwm"; 550 resets = <&tegra_car 17>; 551 reset-names = "pwm"; 552 status = "disabled"; 553 }; 554 555 i2c@7000c000 { 556 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 557 reg = <0x0 0x7000c000 0x0 0x100>; 558 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 562 clock-names = "div-clk"; 563 resets = <&tegra_car 12>; 564 reset-names = "i2c"; 565 dmas = <&apbdma 21>, <&apbdma 21>; 566 dma-names = "rx", "tx"; 567 status = "disabled"; 568 }; 569 570 i2c@7000c400 { 571 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 572 reg = <0x0 0x7000c400 0x0 0x100>; 573 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 577 clock-names = "div-clk"; 578 resets = <&tegra_car 54>; 579 reset-names = "i2c"; 580 dmas = <&apbdma 22>, <&apbdma 22>; 581 dma-names = "rx", "tx"; 582 status = "disabled"; 583 }; 584 585 i2c@7000c500 { 586 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 587 reg = <0x0 0x7000c500 0x0 0x100>; 588 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 592 clock-names = "div-clk"; 593 resets = <&tegra_car 67>; 594 reset-names = "i2c"; 595 dmas = <&apbdma 23>, <&apbdma 23>; 596 dma-names = "rx", "tx"; 597 status = "disabled"; 598 }; 599 600 i2c@7000c700 { 601 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 602 reg = <0x0 0x7000c700 0x0 0x100>; 603 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 607 clock-names = "div-clk"; 608 resets = <&tegra_car 103>; 609 reset-names = "i2c"; 610 dmas = <&apbdma 26>, <&apbdma 26>; 611 dma-names = "rx", "tx"; 612 pinctrl-0 = <&state_dpaux1_i2c>; 613 pinctrl-1 = <&state_dpaux1_off>; 614 pinctrl-names = "default", "idle"; 615 status = "disabled"; 616 }; 617 618 i2c@7000d000 { 619 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 620 reg = <0x0 0x7000d000 0x0 0x100>; 621 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 625 clock-names = "div-clk"; 626 resets = <&tegra_car 47>; 627 reset-names = "i2c"; 628 dmas = <&apbdma 24>, <&apbdma 24>; 629 dma-names = "rx", "tx"; 630 status = "disabled"; 631 }; 632 633 i2c@7000d100 { 634 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 635 reg = <0x0 0x7000d100 0x0 0x100>; 636 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 637 #address-cells = <1>; 638 #size-cells = <0>; 639 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 640 clock-names = "div-clk"; 641 resets = <&tegra_car 166>; 642 reset-names = "i2c"; 643 dmas = <&apbdma 30>, <&apbdma 30>; 644 dma-names = "rx", "tx"; 645 pinctrl-0 = <&state_dpaux_i2c>; 646 pinctrl-1 = <&state_dpaux_off>; 647 pinctrl-names = "default", "idle"; 648 status = "disabled"; 649 }; 650 651 spi@7000d400 { 652 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 653 reg = <0x0 0x7000d400 0x0 0x200>; 654 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 655 #address-cells = <1>; 656 #size-cells = <0>; 657 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 658 clock-names = "spi"; 659 resets = <&tegra_car 41>; 660 reset-names = "spi"; 661 dmas = <&apbdma 15>, <&apbdma 15>; 662 dma-names = "rx", "tx"; 663 status = "disabled"; 664 }; 665 666 spi@7000d600 { 667 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 668 reg = <0x0 0x7000d600 0x0 0x200>; 669 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 673 clock-names = "spi"; 674 resets = <&tegra_car 44>; 675 reset-names = "spi"; 676 dmas = <&apbdma 16>, <&apbdma 16>; 677 dma-names = "rx", "tx"; 678 status = "disabled"; 679 }; 680 681 spi@7000d800 { 682 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 683 reg = <0x0 0x7000d800 0x0 0x200>; 684 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 688 clock-names = "spi"; 689 resets = <&tegra_car 46>; 690 reset-names = "spi"; 691 dmas = <&apbdma 17>, <&apbdma 17>; 692 dma-names = "rx", "tx"; 693 status = "disabled"; 694 }; 695 696 spi@7000da00 { 697 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 698 reg = <0x0 0x7000da00 0x0 0x200>; 699 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 703 clock-names = "spi"; 704 resets = <&tegra_car 68>; 705 reset-names = "spi"; 706 dmas = <&apbdma 18>, <&apbdma 18>; 707 dma-names = "rx", "tx"; 708 status = "disabled"; 709 }; 710 711 rtc@7000e000 { 712 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 713 reg = <0x0 0x7000e000 0x0 0x100>; 714 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&tegra_car TEGRA210_CLK_RTC>; 716 clock-names = "rtc"; 717 }; 718 719 pmc: pmc@7000e400 { 720 compatible = "nvidia,tegra210-pmc"; 721 reg = <0x0 0x7000e400 0x0 0x400>; 722 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 723 clock-names = "pclk", "clk32k_in"; 724 725 powergates { 726 pd_audio: aud { 727 clocks = <&tegra_car TEGRA210_CLK_APE>, 728 <&tegra_car TEGRA210_CLK_APB2APE>; 729 resets = <&tegra_car 198>; 730 #power-domain-cells = <0>; 731 }; 732 733 pd_sor: sor { 734 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 735 <&tegra_car TEGRA210_CLK_SOR1>, 736 <&tegra_car TEGRA210_CLK_CSI>, 737 <&tegra_car TEGRA210_CLK_DSIA>, 738 <&tegra_car TEGRA210_CLK_DSIB>, 739 <&tegra_car TEGRA210_CLK_DPAUX>, 740 <&tegra_car TEGRA210_CLK_DPAUX1>, 741 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 742 resets = <&tegra_car TEGRA210_CLK_SOR0>, 743 <&tegra_car TEGRA210_CLK_SOR1>, 744 <&tegra_car TEGRA210_CLK_CSI>, 745 <&tegra_car TEGRA210_CLK_DSIA>, 746 <&tegra_car TEGRA210_CLK_DSIB>, 747 <&tegra_car TEGRA210_CLK_DPAUX>, 748 <&tegra_car TEGRA210_CLK_DPAUX1>, 749 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 750 #power-domain-cells = <0>; 751 }; 752 753 pd_xusbss: xusba { 754 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 755 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 756 #power-domain-cells = <0>; 757 }; 758 759 pd_xusbdev: xusbb { 760 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 761 resets = <&tegra_car 95>; 762 #power-domain-cells = <0>; 763 }; 764 765 pd_xusbhost: xusbc { 766 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 767 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 768 #power-domain-cells = <0>; 769 }; 770 771 pd_vic: vic { 772 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 773 clock-names = "vic"; 774 resets = <&tegra_car 178>; 775 reset-names = "vic"; 776 #power-domain-cells = <0>; 777 }; 778 }; 779 }; 780 781 fuse@7000f800 { 782 compatible = "nvidia,tegra210-efuse"; 783 reg = <0x0 0x7000f800 0x0 0x400>; 784 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 785 clock-names = "fuse"; 786 resets = <&tegra_car 39>; 787 reset-names = "fuse"; 788 }; 789 790 mc: memory-controller@70019000 { 791 compatible = "nvidia,tegra210-mc"; 792 reg = <0x0 0x70019000 0x0 0x1000>; 793 clocks = <&tegra_car TEGRA210_CLK_MC>; 794 clock-names = "mc"; 795 796 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 797 798 #iommu-cells = <1>; 799 }; 800 801 sata@70020000 { 802 compatible = "nvidia,tegra210-ahci"; 803 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 804 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 805 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 806 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&tegra_car TEGRA210_CLK_SATA>, 808 <&tegra_car TEGRA210_CLK_SATA_OOB>; 809 clock-names = "sata", "sata-oob"; 810 resets = <&tegra_car 124>, 811 <&tegra_car 123>, 812 <&tegra_car 129>; 813 reset-names = "sata", "sata-oob", "sata-cold"; 814 status = "disabled"; 815 }; 816 817 hda@70030000 { 818 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 819 reg = <0x0 0x70030000 0x0 0x10000>; 820 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 821 clocks = <&tegra_car TEGRA210_CLK_HDA>, 822 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 823 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 824 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 825 resets = <&tegra_car 125>, /* hda */ 826 <&tegra_car 128>, /* hda2hdmi */ 827 <&tegra_car 111>; /* hda2codec_2x */ 828 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 829 status = "disabled"; 830 }; 831 832 usb@70090000 { 833 compatible = "nvidia,tegra210-xusb"; 834 reg = <0x0 0x70090000 0x0 0x8000>, 835 <0x0 0x70098000 0x0 0x1000>, 836 <0x0 0x70099000 0x0 0x1000>; 837 reg-names = "hcd", "fpci", "ipfs"; 838 839 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 841 842 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 843 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 844 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 845 <&tegra_car TEGRA210_CLK_XUSB_SS>, 846 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 847 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 848 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 849 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 850 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 851 <&tegra_car TEGRA210_CLK_CLK_M>, 852 <&tegra_car TEGRA210_CLK_PLL_E>; 853 clock-names = "xusb_host", "xusb_host_src", 854 "xusb_falcon_src", "xusb_ss", 855 "xusb_ss_div2", "xusb_ss_src", 856 "xusb_hs_src", "xusb_fs_src", 857 "pll_u_480m", "clk_m", "pll_e"; 858 resets = <&tegra_car 89>, <&tegra_car 156>, 859 <&tegra_car 143>; 860 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 861 862 nvidia,xusb-padctl = <&padctl>; 863 864 status = "disabled"; 865 }; 866 867 padctl: padctl@7009f000 { 868 compatible = "nvidia,tegra210-xusb-padctl"; 869 reg = <0x0 0x7009f000 0x0 0x1000>; 870 resets = <&tegra_car 142>; 871 reset-names = "padctl"; 872 873 status = "disabled"; 874 875 pads { 876 usb2 { 877 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 878 clock-names = "trk"; 879 status = "disabled"; 880 881 lanes { 882 usb2-0 { 883 status = "disabled"; 884 #phy-cells = <0>; 885 }; 886 887 usb2-1 { 888 status = "disabled"; 889 #phy-cells = <0>; 890 }; 891 892 usb2-2 { 893 status = "disabled"; 894 #phy-cells = <0>; 895 }; 896 897 usb2-3 { 898 status = "disabled"; 899 #phy-cells = <0>; 900 }; 901 }; 902 }; 903 904 hsic { 905 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 906 clock-names = "trk"; 907 status = "disabled"; 908 909 lanes { 910 hsic-0 { 911 status = "disabled"; 912 #phy-cells = <0>; 913 }; 914 915 hsic-1 { 916 status = "disabled"; 917 #phy-cells = <0>; 918 }; 919 }; 920 }; 921 922 pcie { 923 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 924 clock-names = "pll"; 925 resets = <&tegra_car 205>; 926 reset-names = "phy"; 927 status = "disabled"; 928 929 lanes { 930 pcie-0 { 931 status = "disabled"; 932 #phy-cells = <0>; 933 }; 934 935 pcie-1 { 936 status = "disabled"; 937 #phy-cells = <0>; 938 }; 939 940 pcie-2 { 941 status = "disabled"; 942 #phy-cells = <0>; 943 }; 944 945 pcie-3 { 946 status = "disabled"; 947 #phy-cells = <0>; 948 }; 949 950 pcie-4 { 951 status = "disabled"; 952 #phy-cells = <0>; 953 }; 954 955 pcie-5 { 956 status = "disabled"; 957 #phy-cells = <0>; 958 }; 959 960 pcie-6 { 961 status = "disabled"; 962 #phy-cells = <0>; 963 }; 964 }; 965 }; 966 967 sata { 968 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 969 clock-names = "pll"; 970 resets = <&tegra_car 204>; 971 reset-names = "phy"; 972 status = "disabled"; 973 974 lanes { 975 sata-0 { 976 status = "disabled"; 977 #phy-cells = <0>; 978 }; 979 }; 980 }; 981 }; 982 983 ports { 984 usb2-0 { 985 status = "disabled"; 986 }; 987 988 usb2-1 { 989 status = "disabled"; 990 }; 991 992 usb2-2 { 993 status = "disabled"; 994 }; 995 996 usb2-3 { 997 status = "disabled"; 998 }; 999 1000 hsic-0 { 1001 status = "disabled"; 1002 }; 1003 1004 usb3-0 { 1005 status = "disabled"; 1006 }; 1007 1008 usb3-1 { 1009 status = "disabled"; 1010 }; 1011 1012 usb3-2 { 1013 status = "disabled"; 1014 }; 1015 1016 usb3-3 { 1017 status = "disabled"; 1018 }; 1019 }; 1020 }; 1021 1022 sdhci@700b0000 { 1023 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1024 reg = <0x0 0x700b0000 0x0 0x200>; 1025 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1027 clock-names = "sdhci"; 1028 resets = <&tegra_car 14>; 1029 reset-names = "sdhci"; 1030 status = "disabled"; 1031 }; 1032 1033 sdhci@700b0200 { 1034 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1035 reg = <0x0 0x700b0200 0x0 0x200>; 1036 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1038 clock-names = "sdhci"; 1039 resets = <&tegra_car 9>; 1040 reset-names = "sdhci"; 1041 status = "disabled"; 1042 }; 1043 1044 sdhci@700b0400 { 1045 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1046 reg = <0x0 0x700b0400 0x0 0x200>; 1047 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1049 clock-names = "sdhci"; 1050 resets = <&tegra_car 69>; 1051 reset-names = "sdhci"; 1052 status = "disabled"; 1053 }; 1054 1055 sdhci@700b0600 { 1056 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1057 reg = <0x0 0x700b0600 0x0 0x200>; 1058 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1060 clock-names = "sdhci"; 1061 resets = <&tegra_car 15>; 1062 reset-names = "sdhci"; 1063 status = "disabled"; 1064 }; 1065 1066 mipi: mipi@700e3000 { 1067 compatible = "nvidia,tegra210-mipi"; 1068 reg = <0x0 0x700e3000 0x0 0x100>; 1069 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1070 clock-names = "mipi-cal"; 1071 power-domains = <&pd_sor>; 1072 #nvidia,mipi-calibrate-cells = <1>; 1073 }; 1074 1075 aconnect@702c0000 { 1076 compatible = "nvidia,tegra210-aconnect"; 1077 clocks = <&tegra_car TEGRA210_CLK_APE>, 1078 <&tegra_car TEGRA210_CLK_APB2APE>; 1079 clock-names = "ape", "apb2ape"; 1080 power-domains = <&pd_audio>; 1081 #address-cells = <1>; 1082 #size-cells = <1>; 1083 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1084 status = "disabled"; 1085 1086 adma: dma@702e2000 { 1087 compatible = "nvidia,tegra210-adma"; 1088 reg = <0x702e2000 0x2000>; 1089 interrupt-parent = <&agic>; 1090 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1112 #dma-cells = <1>; 1113 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1114 clock-names = "d_audio"; 1115 status = "disabled"; 1116 }; 1117 1118 agic: agic@702f9000 { 1119 compatible = "nvidia,tegra210-agic"; 1120 #interrupt-cells = <3>; 1121 interrupt-controller; 1122 reg = <0x702f9000 0x2000>, 1123 <0x702fa000 0x2000>; 1124 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1125 clocks = <&tegra_car TEGRA210_CLK_APE>; 1126 clock-names = "clk"; 1127 status = "disabled"; 1128 }; 1129 }; 1130 1131 spi@70410000 { 1132 compatible = "nvidia,tegra210-qspi"; 1133 reg = <0x0 0x70410000 0x0 0x1000>; 1134 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1138 clock-names = "qspi"; 1139 resets = <&tegra_car 211>; 1140 reset-names = "qspi"; 1141 dmas = <&apbdma 5>, <&apbdma 5>; 1142 dma-names = "rx", "tx"; 1143 status = "disabled"; 1144 }; 1145 1146 usb@7d000000 { 1147 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1148 reg = <0x0 0x7d000000 0x0 0x4000>; 1149 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1150 phy_type = "utmi"; 1151 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1152 clock-names = "usb"; 1153 resets = <&tegra_car 22>; 1154 reset-names = "usb"; 1155 nvidia,phy = <&phy1>; 1156 status = "disabled"; 1157 }; 1158 1159 phy1: usb-phy@7d000000 { 1160 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1161 reg = <0x0 0x7d000000 0x0 0x4000>, 1162 <0x0 0x7d000000 0x0 0x4000>; 1163 phy_type = "utmi"; 1164 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1165 <&tegra_car TEGRA210_CLK_PLL_U>, 1166 <&tegra_car TEGRA210_CLK_USBD>; 1167 clock-names = "reg", "pll_u", "utmi-pads"; 1168 resets = <&tegra_car 22>, <&tegra_car 22>; 1169 reset-names = "usb", "utmi-pads"; 1170 nvidia,hssync-start-delay = <0>; 1171 nvidia,idle-wait-delay = <17>; 1172 nvidia,elastic-limit = <16>; 1173 nvidia,term-range-adj = <6>; 1174 nvidia,xcvr-setup = <9>; 1175 nvidia,xcvr-lsfslew = <0>; 1176 nvidia,xcvr-lsrslew = <3>; 1177 nvidia,hssquelch-level = <2>; 1178 nvidia,hsdiscon-level = <5>; 1179 nvidia,xcvr-hsslew = <12>; 1180 nvidia,has-utmi-pad-registers; 1181 status = "disabled"; 1182 }; 1183 1184 usb@7d004000 { 1185 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1186 reg = <0x0 0x7d004000 0x0 0x4000>; 1187 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1188 phy_type = "utmi"; 1189 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1190 clock-names = "usb"; 1191 resets = <&tegra_car 58>; 1192 reset-names = "usb"; 1193 nvidia,phy = <&phy2>; 1194 status = "disabled"; 1195 }; 1196 1197 phy2: usb-phy@7d004000 { 1198 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1199 reg = <0x0 0x7d004000 0x0 0x4000>, 1200 <0x0 0x7d000000 0x0 0x4000>; 1201 phy_type = "utmi"; 1202 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1203 <&tegra_car TEGRA210_CLK_PLL_U>, 1204 <&tegra_car TEGRA210_CLK_USBD>; 1205 clock-names = "reg", "pll_u", "utmi-pads"; 1206 resets = <&tegra_car 58>, <&tegra_car 22>; 1207 reset-names = "usb", "utmi-pads"; 1208 nvidia,hssync-start-delay = <0>; 1209 nvidia,idle-wait-delay = <17>; 1210 nvidia,elastic-limit = <16>; 1211 nvidia,term-range-adj = <6>; 1212 nvidia,xcvr-setup = <9>; 1213 nvidia,xcvr-lsfslew = <0>; 1214 nvidia,xcvr-lsrslew = <3>; 1215 nvidia,hssquelch-level = <2>; 1216 nvidia,hsdiscon-level = <5>; 1217 nvidia,xcvr-hsslew = <12>; 1218 status = "disabled"; 1219 }; 1220 1221 cpus { 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 1225 cpu@0 { 1226 device_type = "cpu"; 1227 compatible = "arm,cortex-a57"; 1228 reg = <0>; 1229 }; 1230 1231 cpu@1 { 1232 device_type = "cpu"; 1233 compatible = "arm,cortex-a57"; 1234 reg = <1>; 1235 }; 1236 1237 cpu@2 { 1238 device_type = "cpu"; 1239 compatible = "arm,cortex-a57"; 1240 reg = <2>; 1241 }; 1242 1243 cpu@3 { 1244 device_type = "cpu"; 1245 compatible = "arm,cortex-a57"; 1246 reg = <3>; 1247 }; 1248 }; 1249 1250 timer { 1251 compatible = "arm,armv8-timer"; 1252 interrupts = <GIC_PPI 13 1253 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1254 <GIC_PPI 14 1255 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1256 <GIC_PPI 11 1257 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1258 <GIC_PPI 10 1259 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1260 interrupt-parent = <&gic>; 1261 }; 1262 1263 soctherm: thermal-sensor@700e2000 { 1264 compatible = "nvidia,tegra210-soctherm"; 1265 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 1266 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1267 reg-names = "soctherm-reg", "car-reg"; 1268 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1269 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1270 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1271 clock-names = "tsensor", "soctherm"; 1272 resets = <&tegra_car 78>; 1273 reset-names = "soctherm"; 1274 #thermal-sensor-cells = <1>; 1275 1276 throttle-cfgs { 1277 throttle_heavy: heavy { 1278 nvidia,priority = <100>; 1279 nvidia,cpu-throt-percent = <85>; 1280 1281 #cooling-cells = <2>; 1282 }; 1283 }; 1284 }; 1285 1286 thermal-zones { 1287 cpu { 1288 polling-delay-passive = <1000>; 1289 polling-delay = <0>; 1290 1291 thermal-sensors = 1292 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1293 1294 trips { 1295 cpu-shutdown-trip { 1296 temperature = <102500>; 1297 hysteresis = <0>; 1298 type = "critical"; 1299 }; 1300 1301 cpu_throttle_trip: throttle-trip { 1302 temperature = <98500>; 1303 hysteresis = <1000>; 1304 type = "hot"; 1305 }; 1306 }; 1307 1308 cooling-maps { 1309 map0 { 1310 trip = <&cpu_throttle_trip>; 1311 cooling-device = <&throttle_heavy 1 1>; 1312 }; 1313 }; 1314 }; 1315 mem { 1316 polling-delay-passive = <0>; 1317 polling-delay = <0>; 1318 1319 thermal-sensors = 1320 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1321 1322 trips { 1323 mem-shutdown-trip { 1324 temperature = <103000>; 1325 hysteresis = <0>; 1326 type = "critical"; 1327 }; 1328 }; 1329 1330 cooling-maps { 1331 /* 1332 * There are currently no cooling maps, 1333 * because there are no cooling devices. 1334 */ 1335 }; 1336 }; 1337 gpu { 1338 polling-delay-passive = <1000>; 1339 polling-delay = <0>; 1340 1341 thermal-sensors = 1342 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1343 1344 trips { 1345 gpu-shutdown-trip { 1346 temperature = <103000>; 1347 hysteresis = <0>; 1348 type = "critical"; 1349 }; 1350 1351 gpu_throttle_trip: throttle-trip { 1352 temperature = <100000>; 1353 hysteresis = <1000>; 1354 type = "hot"; 1355 }; 1356 }; 1357 1358 cooling-maps { 1359 map0 { 1360 trip = <&gpu_throttle_trip>; 1361 cooling-device = <&throttle_heavy 1 1>; 1362 }; 1363 }; 1364 }; 1365 pllx { 1366 polling-delay-passive = <0>; 1367 polling-delay = <0>; 1368 1369 thermal-sensors = 1370 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1371 1372 trips { 1373 pllx-shutdown-trip { 1374 temperature = <103000>; 1375 hysteresis = <0>; 1376 type = "critical"; 1377 }; 1378 }; 1379 1380 cooling-maps { 1381 /* 1382 * There are currently no cooling maps, 1383 * because there are no cooling devices. 1384 */ 1385 }; 1386 }; 1387 }; 1388}; 1389