1#include <dt-bindings/clock/tegra210-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra210-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/thermal/tegra124-soctherm.h> 7 8/ { 9 compatible = "nvidia,tegra210"; 10 interrupt-parent = <&lic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 pcie-controller@01003000 { 15 compatible = "nvidia,tegra210-pcie"; 16 device_type = "pci"; 17 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 18 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 19 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 20 reg-names = "pads", "afi", "cs"; 21 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 22 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 23 interrupt-names = "intr", "msi"; 24 25 #interrupt-cells = <1>; 26 interrupt-map-mask = <0 0 0 0>; 27 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 28 29 bus-range = <0x00 0xff>; 30 #address-cells = <3>; 31 #size-cells = <2>; 32 33 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 34 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 35 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 36 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 37 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 38 39 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 40 <&tegra_car TEGRA210_CLK_AFI>, 41 <&tegra_car TEGRA210_CLK_PLL_E>, 42 <&tegra_car TEGRA210_CLK_CML0>; 43 clock-names = "pex", "afi", "pll_e", "cml"; 44 resets = <&tegra_car 70>, 45 <&tegra_car 72>, 46 <&tegra_car 74>; 47 reset-names = "pex", "afi", "pcie_x"; 48 status = "disabled"; 49 50 pci@1,0 { 51 device_type = "pci"; 52 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 53 reg = <0x000800 0 0 0 0>; 54 status = "disabled"; 55 56 #address-cells = <3>; 57 #size-cells = <2>; 58 ranges; 59 60 nvidia,num-lanes = <4>; 61 }; 62 63 pci@2,0 { 64 device_type = "pci"; 65 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 66 reg = <0x001000 0 0 0 0>; 67 status = "disabled"; 68 69 #address-cells = <3>; 70 #size-cells = <2>; 71 ranges; 72 73 nvidia,num-lanes = <1>; 74 }; 75 }; 76 77 host1x@50000000 { 78 compatible = "nvidia,tegra210-host1x", "simple-bus"; 79 reg = <0x0 0x50000000 0x0 0x00034000>; 80 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 81 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 82 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 83 clock-names = "host1x"; 84 resets = <&tegra_car 28>; 85 reset-names = "host1x"; 86 87 #address-cells = <2>; 88 #size-cells = <2>; 89 90 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 91 92 iommus = <&mc TEGRA_SWGROUP_HC>; 93 94 dpaux1: dpaux@54040000 { 95 compatible = "nvidia,tegra210-dpaux"; 96 reg = <0x0 0x54040000 0x0 0x00040000>; 97 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 98 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 99 <&tegra_car TEGRA210_CLK_PLL_DP>; 100 clock-names = "dpaux", "parent"; 101 resets = <&tegra_car 207>; 102 reset-names = "dpaux"; 103 power-domains = <&pd_sor>; 104 status = "disabled"; 105 106 state_dpaux1_aux: pinmux-aux { 107 groups = "dpaux-io"; 108 function = "aux"; 109 }; 110 111 state_dpaux1_i2c: pinmux-i2c { 112 groups = "dpaux-io"; 113 function = "i2c"; 114 }; 115 116 state_dpaux1_off: pinmux-off { 117 groups = "dpaux-io"; 118 function = "off"; 119 }; 120 121 i2c-bus { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 }; 125 }; 126 127 vi@54080000 { 128 compatible = "nvidia,tegra210-vi"; 129 reg = <0x0 0x54080000 0x0 0x00040000>; 130 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 131 status = "disabled"; 132 }; 133 134 tsec@54100000 { 135 compatible = "nvidia,tegra210-tsec"; 136 reg = <0x0 0x54100000 0x0 0x00040000>; 137 }; 138 139 dc@54200000 { 140 compatible = "nvidia,tegra210-dc"; 141 reg = <0x0 0x54200000 0x0 0x00040000>; 142 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 143 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 144 <&tegra_car TEGRA210_CLK_PLL_P>; 145 clock-names = "dc", "parent"; 146 resets = <&tegra_car 27>; 147 reset-names = "dc"; 148 149 iommus = <&mc TEGRA_SWGROUP_DC>; 150 151 nvidia,head = <0>; 152 }; 153 154 dc@54240000 { 155 compatible = "nvidia,tegra210-dc"; 156 reg = <0x0 0x54240000 0x0 0x00040000>; 157 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 158 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 159 <&tegra_car TEGRA210_CLK_PLL_P>; 160 clock-names = "dc", "parent"; 161 resets = <&tegra_car 26>; 162 reset-names = "dc"; 163 164 iommus = <&mc TEGRA_SWGROUP_DCB>; 165 166 nvidia,head = <1>; 167 }; 168 169 dsi@54300000 { 170 compatible = "nvidia,tegra210-dsi"; 171 reg = <0x0 0x54300000 0x0 0x00040000>; 172 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 173 <&tegra_car TEGRA210_CLK_DSIALP>, 174 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 175 clock-names = "dsi", "lp", "parent"; 176 resets = <&tegra_car 48>; 177 reset-names = "dsi"; 178 power-domains = <&pd_sor>; 179 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 180 181 status = "disabled"; 182 183 #address-cells = <1>; 184 #size-cells = <0>; 185 }; 186 187 vic@54340000 { 188 compatible = "nvidia,tegra210-vic"; 189 reg = <0x0 0x54340000 0x0 0x00040000>; 190 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 192 clock-names = "vic"; 193 resets = <&tegra_car 178>; 194 reset-names = "vic"; 195 196 iommus = <&mc TEGRA_SWGROUP_VIC>; 197 power-domains = <&pd_vic>; 198 }; 199 200 nvjpg@54380000 { 201 compatible = "nvidia,tegra210-nvjpg"; 202 reg = <0x0 0x54380000 0x0 0x00040000>; 203 status = "disabled"; 204 }; 205 206 dsi@54400000 { 207 compatible = "nvidia,tegra210-dsi"; 208 reg = <0x0 0x54400000 0x0 0x00040000>; 209 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 210 <&tegra_car TEGRA210_CLK_DSIBLP>, 211 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 212 clock-names = "dsi", "lp", "parent"; 213 resets = <&tegra_car 82>; 214 reset-names = "dsi"; 215 power-domains = <&pd_sor>; 216 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 217 218 status = "disabled"; 219 220 #address-cells = <1>; 221 #size-cells = <0>; 222 }; 223 224 nvdec@54480000 { 225 compatible = "nvidia,tegra210-nvdec"; 226 reg = <0x0 0x54480000 0x0 0x00040000>; 227 status = "disabled"; 228 }; 229 230 nvenc@544c0000 { 231 compatible = "nvidia,tegra210-nvenc"; 232 reg = <0x0 0x544c0000 0x0 0x00040000>; 233 status = "disabled"; 234 }; 235 236 tsec@54500000 { 237 compatible = "nvidia,tegra210-tsec"; 238 reg = <0x0 0x54500000 0x0 0x00040000>; 239 status = "disabled"; 240 }; 241 242 sor@54540000 { 243 compatible = "nvidia,tegra210-sor"; 244 reg = <0x0 0x54540000 0x0 0x00040000>; 245 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 247 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 248 <&tegra_car TEGRA210_CLK_PLL_DP>, 249 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 250 clock-names = "sor", "parent", "dp", "safe"; 251 resets = <&tegra_car 182>; 252 reset-names = "sor"; 253 pinctrl-0 = <&state_dpaux_aux>; 254 pinctrl-1 = <&state_dpaux_i2c>; 255 pinctrl-2 = <&state_dpaux_off>; 256 pinctrl-names = "aux", "i2c", "off"; 257 power-domains = <&pd_sor>; 258 status = "disabled"; 259 }; 260 261 sor@54580000 { 262 compatible = "nvidia,tegra210-sor1"; 263 reg = <0x0 0x54580000 0x0 0x00040000>; 264 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 266 <&tegra_car TEGRA210_CLK_SOR1_SRC>, 267 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 268 <&tegra_car TEGRA210_CLK_PLL_DP>, 269 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 270 clock-names = "sor", "source", "parent", "dp", "safe"; 271 resets = <&tegra_car 183>; 272 reset-names = "sor"; 273 pinctrl-0 = <&state_dpaux1_aux>; 274 pinctrl-1 = <&state_dpaux1_i2c>; 275 pinctrl-2 = <&state_dpaux1_off>; 276 pinctrl-names = "aux", "i2c", "off"; 277 power-domains = <&pd_sor>; 278 status = "disabled"; 279 }; 280 281 dpaux: dpaux@545c0000 { 282 compatible = "nvidia,tegra124-dpaux"; 283 reg = <0x0 0x545c0000 0x0 0x00040000>; 284 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 286 <&tegra_car TEGRA210_CLK_PLL_DP>; 287 clock-names = "dpaux", "parent"; 288 resets = <&tegra_car 181>; 289 reset-names = "dpaux"; 290 power-domains = <&pd_sor>; 291 status = "disabled"; 292 293 state_dpaux_aux: pinmux-aux { 294 groups = "dpaux-io"; 295 function = "aux"; 296 }; 297 298 state_dpaux_i2c: pinmux-i2c { 299 groups = "dpaux-io"; 300 function = "i2c"; 301 }; 302 303 state_dpaux_off: pinmux-off { 304 groups = "dpaux-io"; 305 function = "off"; 306 }; 307 308 i2c-bus { 309 #address-cells = <1>; 310 #size-cells = <0>; 311 }; 312 }; 313 314 isp@54600000 { 315 compatible = "nvidia,tegra210-isp"; 316 reg = <0x0 0x54600000 0x0 0x00040000>; 317 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 318 status = "disabled"; 319 }; 320 321 isp@54680000 { 322 compatible = "nvidia,tegra210-isp"; 323 reg = <0x0 0x54680000 0x0 0x00040000>; 324 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 325 status = "disabled"; 326 }; 327 328 i2c@546c0000 { 329 compatible = "nvidia,tegra210-i2c-vi"; 330 reg = <0x0 0x546c0000 0x0 0x00040000>; 331 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 332 status = "disabled"; 333 }; 334 }; 335 336 gic: interrupt-controller@50041000 { 337 compatible = "arm,gic-400"; 338 #interrupt-cells = <3>; 339 interrupt-controller; 340 reg = <0x0 0x50041000 0x0 0x1000>, 341 <0x0 0x50042000 0x0 0x2000>, 342 <0x0 0x50044000 0x0 0x2000>, 343 <0x0 0x50046000 0x0 0x2000>; 344 interrupts = <GIC_PPI 9 345 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 346 interrupt-parent = <&gic>; 347 }; 348 349 gpu@57000000 { 350 compatible = "nvidia,gm20b"; 351 reg = <0x0 0x57000000 0x0 0x01000000>, 352 <0x0 0x58000000 0x0 0x01000000>; 353 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 355 interrupt-names = "stall", "nonstall"; 356 clocks = <&tegra_car TEGRA210_CLK_GPU>, 357 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 358 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 359 clock-names = "gpu", "pwr", "ref"; 360 resets = <&tegra_car 184>; 361 reset-names = "gpu"; 362 363 iommus = <&mc TEGRA_SWGROUP_GPU>; 364 365 status = "disabled"; 366 }; 367 368 lic: interrupt-controller@60004000 { 369 compatible = "nvidia,tegra210-ictlr"; 370 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 371 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 372 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 373 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 374 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 375 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 376 interrupt-controller; 377 #interrupt-cells = <3>; 378 interrupt-parent = <&gic>; 379 }; 380 381 timer@60005000 { 382 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; 383 reg = <0x0 0x60005000 0x0 0x400>; 384 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 391 clock-names = "timer"; 392 }; 393 394 tegra_car: clock@60006000 { 395 compatible = "nvidia,tegra210-car"; 396 reg = <0x0 0x60006000 0x0 0x1000>; 397 #clock-cells = <1>; 398 #reset-cells = <1>; 399 }; 400 401 flow-controller@60007000 { 402 compatible = "nvidia,tegra210-flowctrl"; 403 reg = <0x0 0x60007000 0x0 0x1000>; 404 }; 405 406 gpio: gpio@6000d000 { 407 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 408 reg = <0x0 0x6000d000 0x0 0x1000>; 409 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 417 #gpio-cells = <2>; 418 gpio-controller; 419 #interrupt-cells = <2>; 420 interrupt-controller; 421 }; 422 423 apbdma: dma@60020000 { 424 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 425 reg = <0x0 0x60020000 0x0 0x1400>; 426 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 459 clock-names = "dma"; 460 resets = <&tegra_car 34>; 461 reset-names = "dma"; 462 #dma-cells = <1>; 463 }; 464 465 apbmisc@70000800 { 466 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 467 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 468 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 469 }; 470 471 pinmux: pinmux@700008d4 { 472 compatible = "nvidia,tegra210-pinmux"; 473 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 474 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 475 }; 476 477 /* 478 * There are two serial driver i.e. 8250 based simple serial 479 * driver and APB DMA based serial driver for higher baudrate 480 * and performance. To enable the 8250 based driver, the compatible 481 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 482 * the APB DMA based serial driver, the compatible is 483 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 484 */ 485 uarta: serial@70006000 { 486 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 487 reg = <0x0 0x70006000 0x0 0x40>; 488 reg-shift = <2>; 489 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 491 clock-names = "serial"; 492 resets = <&tegra_car 6>; 493 reset-names = "serial"; 494 dmas = <&apbdma 8>, <&apbdma 8>; 495 dma-names = "rx", "tx"; 496 status = "disabled"; 497 }; 498 499 uartb: serial@70006040 { 500 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 501 reg = <0x0 0x70006040 0x0 0x40>; 502 reg-shift = <2>; 503 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 505 clock-names = "serial"; 506 resets = <&tegra_car 7>; 507 reset-names = "serial"; 508 dmas = <&apbdma 9>, <&apbdma 9>; 509 dma-names = "rx", "tx"; 510 status = "disabled"; 511 }; 512 513 uartc: serial@70006200 { 514 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 515 reg = <0x0 0x70006200 0x0 0x40>; 516 reg-shift = <2>; 517 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 519 clock-names = "serial"; 520 resets = <&tegra_car 55>; 521 reset-names = "serial"; 522 dmas = <&apbdma 10>, <&apbdma 10>; 523 dma-names = "rx", "tx"; 524 status = "disabled"; 525 }; 526 527 uartd: serial@70006300 { 528 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 529 reg = <0x0 0x70006300 0x0 0x40>; 530 reg-shift = <2>; 531 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 533 clock-names = "serial"; 534 resets = <&tegra_car 65>; 535 reset-names = "serial"; 536 dmas = <&apbdma 19>, <&apbdma 19>; 537 dma-names = "rx", "tx"; 538 status = "disabled"; 539 }; 540 541 pwm: pwm@7000a000 { 542 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 543 reg = <0x0 0x7000a000 0x0 0x100>; 544 #pwm-cells = <2>; 545 clocks = <&tegra_car TEGRA210_CLK_PWM>; 546 clock-names = "pwm"; 547 resets = <&tegra_car 17>; 548 reset-names = "pwm"; 549 status = "disabled"; 550 }; 551 552 i2c@7000c000 { 553 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 554 reg = <0x0 0x7000c000 0x0 0x100>; 555 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 559 clock-names = "div-clk"; 560 resets = <&tegra_car 12>; 561 reset-names = "i2c"; 562 dmas = <&apbdma 21>, <&apbdma 21>; 563 dma-names = "rx", "tx"; 564 status = "disabled"; 565 }; 566 567 i2c@7000c400 { 568 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 569 reg = <0x0 0x7000c400 0x0 0x100>; 570 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 574 clock-names = "div-clk"; 575 resets = <&tegra_car 54>; 576 reset-names = "i2c"; 577 dmas = <&apbdma 22>, <&apbdma 22>; 578 dma-names = "rx", "tx"; 579 status = "disabled"; 580 }; 581 582 i2c@7000c500 { 583 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 584 reg = <0x0 0x7000c500 0x0 0x100>; 585 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 589 clock-names = "div-clk"; 590 resets = <&tegra_car 67>; 591 reset-names = "i2c"; 592 dmas = <&apbdma 23>, <&apbdma 23>; 593 dma-names = "rx", "tx"; 594 status = "disabled"; 595 }; 596 597 i2c@7000c700 { 598 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 599 reg = <0x0 0x7000c700 0x0 0x100>; 600 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 604 clock-names = "div-clk"; 605 resets = <&tegra_car 103>; 606 reset-names = "i2c"; 607 dmas = <&apbdma 26>, <&apbdma 26>; 608 dma-names = "rx", "tx"; 609 pinctrl-0 = <&state_dpaux1_i2c>; 610 pinctrl-1 = <&state_dpaux1_off>; 611 pinctrl-names = "default", "idle"; 612 status = "disabled"; 613 }; 614 615 i2c@7000d000 { 616 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 617 reg = <0x0 0x7000d000 0x0 0x100>; 618 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 622 clock-names = "div-clk"; 623 resets = <&tegra_car 47>; 624 reset-names = "i2c"; 625 dmas = <&apbdma 24>, <&apbdma 24>; 626 dma-names = "rx", "tx"; 627 status = "disabled"; 628 }; 629 630 i2c@7000d100 { 631 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c"; 632 reg = <0x0 0x7000d100 0x0 0x100>; 633 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 634 #address-cells = <1>; 635 #size-cells = <0>; 636 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 637 clock-names = "div-clk"; 638 resets = <&tegra_car 166>; 639 reset-names = "i2c"; 640 dmas = <&apbdma 30>, <&apbdma 30>; 641 dma-names = "rx", "tx"; 642 pinctrl-0 = <&state_dpaux_i2c>; 643 pinctrl-1 = <&state_dpaux_off>; 644 pinctrl-names = "default", "idle"; 645 status = "disabled"; 646 }; 647 648 spi@7000d400 { 649 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 650 reg = <0x0 0x7000d400 0x0 0x200>; 651 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 655 clock-names = "spi"; 656 resets = <&tegra_car 41>; 657 reset-names = "spi"; 658 dmas = <&apbdma 15>, <&apbdma 15>; 659 dma-names = "rx", "tx"; 660 status = "disabled"; 661 }; 662 663 spi@7000d600 { 664 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 665 reg = <0x0 0x7000d600 0x0 0x200>; 666 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 670 clock-names = "spi"; 671 resets = <&tegra_car 44>; 672 reset-names = "spi"; 673 dmas = <&apbdma 16>, <&apbdma 16>; 674 dma-names = "rx", "tx"; 675 status = "disabled"; 676 }; 677 678 spi@7000d800 { 679 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 680 reg = <0x0 0x7000d800 0x0 0x200>; 681 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 685 clock-names = "spi"; 686 resets = <&tegra_car 46>; 687 reset-names = "spi"; 688 dmas = <&apbdma 17>, <&apbdma 17>; 689 dma-names = "rx", "tx"; 690 status = "disabled"; 691 }; 692 693 spi@7000da00 { 694 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 695 reg = <0x0 0x7000da00 0x0 0x200>; 696 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 700 clock-names = "spi"; 701 resets = <&tegra_car 68>; 702 reset-names = "spi"; 703 dmas = <&apbdma 18>, <&apbdma 18>; 704 dma-names = "rx", "tx"; 705 status = "disabled"; 706 }; 707 708 rtc@7000e000 { 709 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 710 reg = <0x0 0x7000e000 0x0 0x100>; 711 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&tegra_car TEGRA210_CLK_RTC>; 713 clock-names = "rtc"; 714 }; 715 716 pmc: pmc@7000e400 { 717 compatible = "nvidia,tegra210-pmc"; 718 reg = <0x0 0x7000e400 0x0 0x400>; 719 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 720 clock-names = "pclk", "clk32k_in"; 721 722 powergates { 723 pd_audio: aud { 724 clocks = <&tegra_car TEGRA210_CLK_APE>, 725 <&tegra_car TEGRA210_CLK_APB2APE>; 726 resets = <&tegra_car 198>; 727 #power-domain-cells = <0>; 728 }; 729 730 pd_sor: sor { 731 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 732 <&tegra_car TEGRA210_CLK_SOR1>, 733 <&tegra_car TEGRA210_CLK_CSI>, 734 <&tegra_car TEGRA210_CLK_DSIA>, 735 <&tegra_car TEGRA210_CLK_DSIB>, 736 <&tegra_car TEGRA210_CLK_DPAUX>, 737 <&tegra_car TEGRA210_CLK_DPAUX1>, 738 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 739 resets = <&tegra_car TEGRA210_CLK_SOR0>, 740 <&tegra_car TEGRA210_CLK_SOR1>, 741 <&tegra_car TEGRA210_CLK_CSI>, 742 <&tegra_car TEGRA210_CLK_DSIA>, 743 <&tegra_car TEGRA210_CLK_DSIB>, 744 <&tegra_car TEGRA210_CLK_DPAUX>, 745 <&tegra_car TEGRA210_CLK_DPAUX1>, 746 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 747 #power-domain-cells = <0>; 748 }; 749 750 pd_xusbss: xusba { 751 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 752 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 753 #power-domain-cells = <0>; 754 }; 755 756 pd_xusbdev: xusbb { 757 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 758 resets = <&tegra_car 95>; 759 #power-domain-cells = <0>; 760 }; 761 762 pd_xusbhost: xusbc { 763 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 764 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 765 #power-domain-cells = <0>; 766 }; 767 768 pd_vic: vic { 769 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 770 clock-names = "vic"; 771 resets = <&tegra_car 178>; 772 reset-names = "vic"; 773 #power-domain-cells = <0>; 774 }; 775 }; 776 }; 777 778 fuse@7000f800 { 779 compatible = "nvidia,tegra210-efuse"; 780 reg = <0x0 0x7000f800 0x0 0x400>; 781 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 782 clock-names = "fuse"; 783 resets = <&tegra_car 39>; 784 reset-names = "fuse"; 785 }; 786 787 mc: memory-controller@70019000 { 788 compatible = "nvidia,tegra210-mc"; 789 reg = <0x0 0x70019000 0x0 0x1000>; 790 clocks = <&tegra_car TEGRA210_CLK_MC>; 791 clock-names = "mc"; 792 793 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 794 795 #iommu-cells = <1>; 796 }; 797 798 hda@70030000 { 799 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 800 reg = <0x0 0x70030000 0x0 0x10000>; 801 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&tegra_car TEGRA210_CLK_HDA>, 803 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 804 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 805 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 806 resets = <&tegra_car 125>, /* hda */ 807 <&tegra_car 128>, /* hda2hdmi */ 808 <&tegra_car 111>; /* hda2codec_2x */ 809 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 810 status = "disabled"; 811 }; 812 813 usb@70090000 { 814 compatible = "nvidia,tegra210-xusb"; 815 reg = <0x0 0x70090000 0x0 0x8000>, 816 <0x0 0x70098000 0x0 0x1000>, 817 <0x0 0x70099000 0x0 0x1000>; 818 reg-names = "hcd", "fpci", "ipfs"; 819 820 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 822 823 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 824 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 825 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 826 <&tegra_car TEGRA210_CLK_XUSB_SS>, 827 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 828 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 829 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 830 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 831 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 832 <&tegra_car TEGRA210_CLK_CLK_M>, 833 <&tegra_car TEGRA210_CLK_PLL_E>; 834 clock-names = "xusb_host", "xusb_host_src", 835 "xusb_falcon_src", "xusb_ss", 836 "xusb_ss_div2", "xusb_ss_src", 837 "xusb_hs_src", "xusb_fs_src", 838 "pll_u_480m", "clk_m", "pll_e"; 839 resets = <&tegra_car 89>, <&tegra_car 156>, 840 <&tegra_car 143>; 841 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 842 843 nvidia,xusb-padctl = <&padctl>; 844 845 status = "disabled"; 846 }; 847 848 padctl: padctl@7009f000 { 849 compatible = "nvidia,tegra210-xusb-padctl"; 850 reg = <0x0 0x7009f000 0x0 0x1000>; 851 resets = <&tegra_car 142>; 852 reset-names = "padctl"; 853 854 status = "disabled"; 855 856 pads { 857 usb2 { 858 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 859 clock-names = "trk"; 860 status = "disabled"; 861 862 lanes { 863 usb2-0 { 864 status = "disabled"; 865 #phy-cells = <0>; 866 }; 867 868 usb2-1 { 869 status = "disabled"; 870 #phy-cells = <0>; 871 }; 872 873 usb2-2 { 874 status = "disabled"; 875 #phy-cells = <0>; 876 }; 877 878 usb2-3 { 879 status = "disabled"; 880 #phy-cells = <0>; 881 }; 882 }; 883 }; 884 885 hsic { 886 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 887 clock-names = "trk"; 888 status = "disabled"; 889 890 lanes { 891 hsic-0 { 892 status = "disabled"; 893 #phy-cells = <0>; 894 }; 895 896 hsic-1 { 897 status = "disabled"; 898 #phy-cells = <0>; 899 }; 900 }; 901 }; 902 903 pcie { 904 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 905 clock-names = "pll"; 906 resets = <&tegra_car 205>; 907 reset-names = "phy"; 908 status = "disabled"; 909 910 lanes { 911 pcie-0 { 912 status = "disabled"; 913 #phy-cells = <0>; 914 }; 915 916 pcie-1 { 917 status = "disabled"; 918 #phy-cells = <0>; 919 }; 920 921 pcie-2 { 922 status = "disabled"; 923 #phy-cells = <0>; 924 }; 925 926 pcie-3 { 927 status = "disabled"; 928 #phy-cells = <0>; 929 }; 930 931 pcie-4 { 932 status = "disabled"; 933 #phy-cells = <0>; 934 }; 935 936 pcie-5 { 937 status = "disabled"; 938 #phy-cells = <0>; 939 }; 940 941 pcie-6 { 942 status = "disabled"; 943 #phy-cells = <0>; 944 }; 945 }; 946 }; 947 948 sata { 949 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 950 clock-names = "pll"; 951 resets = <&tegra_car 204>; 952 reset-names = "phy"; 953 status = "disabled"; 954 955 lanes { 956 sata-0 { 957 status = "disabled"; 958 #phy-cells = <0>; 959 }; 960 }; 961 }; 962 }; 963 964 ports { 965 usb2-0 { 966 status = "disabled"; 967 }; 968 969 usb2-1 { 970 status = "disabled"; 971 }; 972 973 usb2-2 { 974 status = "disabled"; 975 }; 976 977 usb2-3 { 978 status = "disabled"; 979 }; 980 981 hsic-0 { 982 status = "disabled"; 983 }; 984 985 usb3-0 { 986 status = "disabled"; 987 }; 988 989 usb3-1 { 990 status = "disabled"; 991 }; 992 993 usb3-2 { 994 status = "disabled"; 995 }; 996 997 usb3-3 { 998 status = "disabled"; 999 }; 1000 }; 1001 }; 1002 1003 sdhci@700b0000 { 1004 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1005 reg = <0x0 0x700b0000 0x0 0x200>; 1006 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1008 clock-names = "sdhci"; 1009 resets = <&tegra_car 14>; 1010 reset-names = "sdhci"; 1011 status = "disabled"; 1012 }; 1013 1014 sdhci@700b0200 { 1015 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1016 reg = <0x0 0x700b0200 0x0 0x200>; 1017 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1019 clock-names = "sdhci"; 1020 resets = <&tegra_car 9>; 1021 reset-names = "sdhci"; 1022 status = "disabled"; 1023 }; 1024 1025 sdhci@700b0400 { 1026 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1027 reg = <0x0 0x700b0400 0x0 0x200>; 1028 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1029 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1030 clock-names = "sdhci"; 1031 resets = <&tegra_car 69>; 1032 reset-names = "sdhci"; 1033 status = "disabled"; 1034 }; 1035 1036 sdhci@700b0600 { 1037 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1038 reg = <0x0 0x700b0600 0x0 0x200>; 1039 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1040 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1041 clock-names = "sdhci"; 1042 resets = <&tegra_car 15>; 1043 reset-names = "sdhci"; 1044 status = "disabled"; 1045 }; 1046 1047 mipi: mipi@700e3000 { 1048 compatible = "nvidia,tegra210-mipi"; 1049 reg = <0x0 0x700e3000 0x0 0x100>; 1050 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1051 clock-names = "mipi-cal"; 1052 power-domains = <&pd_sor>; 1053 #nvidia,mipi-calibrate-cells = <1>; 1054 }; 1055 1056 aconnect@702c0000 { 1057 compatible = "nvidia,tegra210-aconnect"; 1058 clocks = <&tegra_car TEGRA210_CLK_APE>, 1059 <&tegra_car TEGRA210_CLK_APB2APE>; 1060 clock-names = "ape", "apb2ape"; 1061 power-domains = <&pd_audio>; 1062 #address-cells = <1>; 1063 #size-cells = <1>; 1064 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1065 status = "disabled"; 1066 1067 adma: dma@702e2000 { 1068 compatible = "nvidia,tegra210-adma"; 1069 reg = <0x702e2000 0x2000>; 1070 interrupt-parent = <&agic>; 1071 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1093 #dma-cells = <1>; 1094 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1095 clock-names = "d_audio"; 1096 status = "disabled"; 1097 }; 1098 1099 agic: agic@702f9000 { 1100 compatible = "nvidia,tegra210-agic"; 1101 #interrupt-cells = <3>; 1102 interrupt-controller; 1103 reg = <0x702f9000 0x2000>, 1104 <0x702fa000 0x2000>; 1105 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1106 clocks = <&tegra_car TEGRA210_CLK_APE>; 1107 clock-names = "clk"; 1108 status = "disabled"; 1109 }; 1110 }; 1111 1112 spi@70410000 { 1113 compatible = "nvidia,tegra210-qspi"; 1114 reg = <0x0 0x70410000 0x0 0x1000>; 1115 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1119 clock-names = "qspi"; 1120 resets = <&tegra_car 211>; 1121 reset-names = "qspi"; 1122 dmas = <&apbdma 5>, <&apbdma 5>; 1123 dma-names = "rx", "tx"; 1124 status = "disabled"; 1125 }; 1126 1127 usb@7d000000 { 1128 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1129 reg = <0x0 0x7d000000 0x0 0x4000>; 1130 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1131 phy_type = "utmi"; 1132 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1133 clock-names = "usb"; 1134 resets = <&tegra_car 22>; 1135 reset-names = "usb"; 1136 nvidia,phy = <&phy1>; 1137 status = "disabled"; 1138 }; 1139 1140 phy1: usb-phy@7d000000 { 1141 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1142 reg = <0x0 0x7d000000 0x0 0x4000>, 1143 <0x0 0x7d000000 0x0 0x4000>; 1144 phy_type = "utmi"; 1145 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1146 <&tegra_car TEGRA210_CLK_PLL_U>, 1147 <&tegra_car TEGRA210_CLK_USBD>; 1148 clock-names = "reg", "pll_u", "utmi-pads"; 1149 resets = <&tegra_car 22>, <&tegra_car 22>; 1150 reset-names = "usb", "utmi-pads"; 1151 nvidia,hssync-start-delay = <0>; 1152 nvidia,idle-wait-delay = <17>; 1153 nvidia,elastic-limit = <16>; 1154 nvidia,term-range-adj = <6>; 1155 nvidia,xcvr-setup = <9>; 1156 nvidia,xcvr-lsfslew = <0>; 1157 nvidia,xcvr-lsrslew = <3>; 1158 nvidia,hssquelch-level = <2>; 1159 nvidia,hsdiscon-level = <5>; 1160 nvidia,xcvr-hsslew = <12>; 1161 nvidia,has-utmi-pad-registers; 1162 status = "disabled"; 1163 }; 1164 1165 usb@7d004000 { 1166 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1167 reg = <0x0 0x7d004000 0x0 0x4000>; 1168 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1169 phy_type = "utmi"; 1170 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1171 clock-names = "usb"; 1172 resets = <&tegra_car 58>; 1173 reset-names = "usb"; 1174 nvidia,phy = <&phy2>; 1175 status = "disabled"; 1176 }; 1177 1178 phy2: usb-phy@7d004000 { 1179 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1180 reg = <0x0 0x7d004000 0x0 0x4000>, 1181 <0x0 0x7d000000 0x0 0x4000>; 1182 phy_type = "utmi"; 1183 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1184 <&tegra_car TEGRA210_CLK_PLL_U>, 1185 <&tegra_car TEGRA210_CLK_USBD>; 1186 clock-names = "reg", "pll_u", "utmi-pads"; 1187 resets = <&tegra_car 58>, <&tegra_car 22>; 1188 reset-names = "usb", "utmi-pads"; 1189 nvidia,hssync-start-delay = <0>; 1190 nvidia,idle-wait-delay = <17>; 1191 nvidia,elastic-limit = <16>; 1192 nvidia,term-range-adj = <6>; 1193 nvidia,xcvr-setup = <9>; 1194 nvidia,xcvr-lsfslew = <0>; 1195 nvidia,xcvr-lsrslew = <3>; 1196 nvidia,hssquelch-level = <2>; 1197 nvidia,hsdiscon-level = <5>; 1198 nvidia,xcvr-hsslew = <12>; 1199 status = "disabled"; 1200 }; 1201 1202 cpus { 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 1206 cpu@0 { 1207 device_type = "cpu"; 1208 compatible = "arm,cortex-a57"; 1209 reg = <0>; 1210 }; 1211 1212 cpu@1 { 1213 device_type = "cpu"; 1214 compatible = "arm,cortex-a57"; 1215 reg = <1>; 1216 }; 1217 1218 cpu@2 { 1219 device_type = "cpu"; 1220 compatible = "arm,cortex-a57"; 1221 reg = <2>; 1222 }; 1223 1224 cpu@3 { 1225 device_type = "cpu"; 1226 compatible = "arm,cortex-a57"; 1227 reg = <3>; 1228 }; 1229 }; 1230 1231 timer { 1232 compatible = "arm,armv8-timer"; 1233 interrupts = <GIC_PPI 13 1234 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1235 <GIC_PPI 14 1236 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1237 <GIC_PPI 11 1238 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1239 <GIC_PPI 10 1240 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1241 interrupt-parent = <&gic>; 1242 }; 1243 1244 soctherm: thermal-sensor@700e2000 { 1245 compatible = "nvidia,tegra210-soctherm"; 1246 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 1247 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1248 reg-names = "soctherm-reg", "car-reg"; 1249 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1250 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1251 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1252 clock-names = "tsensor", "soctherm"; 1253 resets = <&tegra_car 78>; 1254 reset-names = "soctherm"; 1255 #thermal-sensor-cells = <1>; 1256 1257 throttle-cfgs { 1258 throttle_heavy: heavy { 1259 nvidia,priority = <100>; 1260 nvidia,cpu-throt-percent = <85>; 1261 1262 #cooling-cells = <2>; 1263 }; 1264 }; 1265 }; 1266 1267 thermal-zones { 1268 cpu { 1269 polling-delay-passive = <1000>; 1270 polling-delay = <0>; 1271 1272 thermal-sensors = 1273 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1274 1275 trips { 1276 cpu-shutdown-trip { 1277 temperature = <102500>; 1278 hysteresis = <0>; 1279 type = "critical"; 1280 }; 1281 1282 cpu_throttle_trip: throttle-trip { 1283 temperature = <98500>; 1284 hysteresis = <1000>; 1285 type = "hot"; 1286 }; 1287 }; 1288 1289 cooling-maps { 1290 map0 { 1291 trip = <&cpu_throttle_trip>; 1292 cooling-device = <&throttle_heavy 1 1>; 1293 }; 1294 }; 1295 }; 1296 mem { 1297 polling-delay-passive = <0>; 1298 polling-delay = <0>; 1299 1300 thermal-sensors = 1301 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1302 1303 trips { 1304 mem-shutdown-trip { 1305 temperature = <103000>; 1306 hysteresis = <0>; 1307 type = "critical"; 1308 }; 1309 }; 1310 1311 cooling-maps { 1312 /* 1313 * There are currently no cooling maps, 1314 * because there are no cooling devices. 1315 */ 1316 }; 1317 }; 1318 gpu { 1319 polling-delay-passive = <1000>; 1320 polling-delay = <0>; 1321 1322 thermal-sensors = 1323 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1324 1325 trips { 1326 gpu-shutdown-trip { 1327 temperature = <103000>; 1328 hysteresis = <0>; 1329 type = "critical"; 1330 }; 1331 1332 gpu_throttle_trip: throttle-trip { 1333 temperature = <100000>; 1334 hysteresis = <1000>; 1335 type = "hot"; 1336 }; 1337 }; 1338 1339 cooling-maps { 1340 map0 { 1341 trip = <&gpu_throttle_trip>; 1342 cooling-device = <&throttle_heavy 1 1>; 1343 }; 1344 }; 1345 }; 1346 pllx { 1347 polling-delay-passive = <0>; 1348 polling-delay = <0>; 1349 1350 thermal-sensors = 1351 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1352 1353 trips { 1354 pllx-shutdown-trip { 1355 temperature = <103000>; 1356 hysteresis = <0>; 1357 type = "critical"; 1358 }; 1359 }; 1360 1361 cooling-maps { 1362 /* 1363 * There are currently no cooling maps, 1364 * because there are no cooling devices. 1365 */ 1366 }; 1367 }; 1368 }; 1369}; 1370