1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12#include "tegra210-peripherals-opp.dtsi" 13 14/ { 15 compatible = "nvidia,tegra210"; 16 interrupt-parent = <&lic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 pcie@1003000 { 21 compatible = "nvidia,tegra210-pcie"; 22 device_type = "pci"; 23 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 24 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 25 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 26 reg-names = "pads", "afi", "cs"; 27 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 28 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 29 interrupt-names = "intr", "msi"; 30 31 #interrupt-cells = <1>; 32 interrupt-map-mask = <0 0 0 0>; 33 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 34 35 bus-range = <0x00 0xff>; 36 #address-cells = <3>; 37 #size-cells = <2>; 38 39 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 40 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 41 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 42 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 43 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 44 45 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 46 <&tegra_car TEGRA210_CLK_AFI>, 47 <&tegra_car TEGRA210_CLK_PLL_E>, 48 <&tegra_car TEGRA210_CLK_CML0>; 49 clock-names = "pex", "afi", "pll_e", "cml"; 50 resets = <&tegra_car 70>, 51 <&tegra_car 72>, 52 <&tegra_car 74>; 53 reset-names = "pex", "afi", "pcie_x"; 54 55 pinctrl-names = "default", "idle"; 56 pinctrl-0 = <&pex_dpd_disable>; 57 pinctrl-1 = <&pex_dpd_enable>; 58 59 status = "disabled"; 60 61 pci@1,0 { 62 device_type = "pci"; 63 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 64 reg = <0x000800 0 0 0 0>; 65 bus-range = <0x00 0xff>; 66 status = "disabled"; 67 68 #address-cells = <3>; 69 #size-cells = <2>; 70 ranges; 71 72 nvidia,num-lanes = <4>; 73 }; 74 75 pci@2,0 { 76 device_type = "pci"; 77 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 78 reg = <0x001000 0 0 0 0>; 79 bus-range = <0x00 0xff>; 80 status = "disabled"; 81 82 #address-cells = <3>; 83 #size-cells = <2>; 84 ranges; 85 86 nvidia,num-lanes = <1>; 87 }; 88 }; 89 90 host1x@50000000 { 91 compatible = "nvidia,tegra210-host1x"; 92 reg = <0x0 0x50000000 0x0 0x00034000>; 93 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 94 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 95 interrupt-names = "syncpt", "host1x"; 96 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 97 clock-names = "host1x"; 98 resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>; 99 reset-names = "host1x", "mc"; 100 101 #address-cells = <2>; 102 #size-cells = <2>; 103 104 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 105 106 iommus = <&mc TEGRA_SWGROUP_HC>; 107 108 dpaux1: dpaux@54040000 { 109 compatible = "nvidia,tegra210-dpaux"; 110 reg = <0x0 0x54040000 0x0 0x00040000>; 111 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 112 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 113 <&tegra_car TEGRA210_CLK_PLL_DP>; 114 clock-names = "dpaux", "parent"; 115 resets = <&tegra_car 207>; 116 reset-names = "dpaux"; 117 power-domains = <&pd_sor>; 118 status = "disabled"; 119 120 state_dpaux1_aux: pinmux-aux { 121 groups = "dpaux-io"; 122 function = "aux"; 123 }; 124 125 state_dpaux1_i2c: pinmux-i2c { 126 groups = "dpaux-io"; 127 function = "i2c"; 128 }; 129 130 state_dpaux1_off: pinmux-off { 131 groups = "dpaux-io"; 132 function = "off"; 133 }; 134 135 i2c-bus { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 }; 139 }; 140 141 vi@54080000 { 142 compatible = "nvidia,tegra210-vi"; 143 reg = <0x0 0x54080000 0x0 0x700>; 144 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 145 status = "disabled"; 146 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 147 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 148 149 clocks = <&tegra_car TEGRA210_CLK_VI>; 150 power-domains = <&pd_venc>; 151 152 #address-cells = <1>; 153 #size-cells = <1>; 154 155 ranges = <0x0 0x0 0x54080000 0x2000>; 156 157 csi@838 { 158 compatible = "nvidia,tegra210-csi"; 159 reg = <0x838 0x1300>; 160 status = "disabled"; 161 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 162 <&tegra_car TEGRA210_CLK_CILCD>, 163 <&tegra_car TEGRA210_CLK_CILE>, 164 <&tegra_car TEGRA210_CLK_CSI_TPG>; 165 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 166 <&tegra_car TEGRA210_CLK_PLL_P>, 167 <&tegra_car TEGRA210_CLK_PLL_P>; 168 assigned-clock-rates = <102000000>, 169 <102000000>, 170 <102000000>, 171 <972000000>; 172 173 clocks = <&tegra_car TEGRA210_CLK_CSI>, 174 <&tegra_car TEGRA210_CLK_CILAB>, 175 <&tegra_car TEGRA210_CLK_CILCD>, 176 <&tegra_car TEGRA210_CLK_CILE>, 177 <&tegra_car TEGRA210_CLK_CSI_TPG>; 178 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 179 power-domains = <&pd_sor>; 180 }; 181 }; 182 183 tsec@54100000 { 184 compatible = "nvidia,tegra210-tsec"; 185 reg = <0x0 0x54100000 0x0 0x00040000>; 186 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&tegra_car TEGRA210_CLK_TSEC>; 188 resets = <&tegra_car 83>; 189 status = "disabled"; 190 }; 191 192 dc@54200000 { 193 compatible = "nvidia,tegra210-dc"; 194 reg = <0x0 0x54200000 0x0 0x00040000>; 195 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&tegra_car TEGRA210_CLK_DISP1>; 197 clock-names = "dc"; 198 resets = <&tegra_car 27>; 199 reset-names = "dc"; 200 201 iommus = <&mc TEGRA_SWGROUP_DC>; 202 203 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 204 nvidia,head = <0>; 205 }; 206 207 dc@54240000 { 208 compatible = "nvidia,tegra210-dc"; 209 reg = <0x0 0x54240000 0x0 0x00040000>; 210 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&tegra_car TEGRA210_CLK_DISP2>; 212 clock-names = "dc"; 213 resets = <&tegra_car 26>; 214 reset-names = "dc"; 215 216 iommus = <&mc TEGRA_SWGROUP_DCB>; 217 218 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 219 nvidia,head = <1>; 220 }; 221 222 dsia: dsi@54300000 { 223 compatible = "nvidia,tegra210-dsi"; 224 reg = <0x0 0x54300000 0x0 0x00040000>; 225 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 226 <&tegra_car TEGRA210_CLK_DSIALP>, 227 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 228 clock-names = "dsi", "lp", "parent"; 229 resets = <&tegra_car 48>; 230 reset-names = "dsi"; 231 power-domains = <&pd_sor>; 232 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 233 234 status = "disabled"; 235 236 #address-cells = <1>; 237 #size-cells = <0>; 238 }; 239 240 vic@54340000 { 241 compatible = "nvidia,tegra210-vic"; 242 reg = <0x0 0x54340000 0x0 0x00040000>; 243 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 245 clock-names = "vic"; 246 resets = <&tegra_car 178>; 247 reset-names = "vic"; 248 249 iommus = <&mc TEGRA_SWGROUP_VIC>; 250 power-domains = <&pd_vic>; 251 }; 252 253 nvjpg@54380000 { 254 compatible = "nvidia,tegra210-nvjpg"; 255 reg = <0x0 0x54380000 0x0 0x00040000>; 256 clocks = <&tegra_car TEGRA210_CLK_NVJPG>; 257 clock-names = "nvjpg"; 258 resets = <&tegra_car 195>; 259 reset-names = "nvjpg"; 260 261 iommus = <&mc TEGRA_SWGROUP_NVJPG>; 262 power-domains = <&pd_nvjpg>; 263 }; 264 265 dsib: dsi@54400000 { 266 compatible = "nvidia,tegra210-dsi"; 267 reg = <0x0 0x54400000 0x0 0x00040000>; 268 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 269 <&tegra_car TEGRA210_CLK_DSIBLP>, 270 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 271 clock-names = "dsi", "lp", "parent"; 272 resets = <&tegra_car 82>; 273 reset-names = "dsi"; 274 power-domains = <&pd_sor>; 275 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 276 277 status = "disabled"; 278 279 #address-cells = <1>; 280 #size-cells = <0>; 281 }; 282 283 nvdec@54480000 { 284 compatible = "nvidia,tegra210-nvdec"; 285 reg = <0x0 0x54480000 0x0 0x00040000>; 286 clocks = <&tegra_car TEGRA210_CLK_NVDEC>; 287 clock-names = "nvdec"; 288 resets = <&tegra_car 194>; 289 reset-names = "nvdec"; 290 291 iommus = <&mc TEGRA_SWGROUP_NVDEC>; 292 power-domains = <&pd_nvdec>; 293 }; 294 295 nvenc@544c0000 { 296 compatible = "nvidia,tegra210-nvenc"; 297 reg = <0x0 0x544c0000 0x0 0x00040000>; 298 clocks = <&tegra_car TEGRA210_CLK_NVENC>; 299 clock-names = "nvenc"; 300 resets = <&tegra_car 219>; 301 reset-names = "nvenc"; 302 303 iommus = <&mc TEGRA_SWGROUP_NVENC>; 304 power-domains = <&pd_nvenc>; 305 }; 306 307 tsec@54500000 { 308 compatible = "nvidia,tegra210-tsec"; 309 reg = <0x0 0x54500000 0x0 0x00040000>; 310 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&tegra_car TEGRA210_CLK_TSECB>; 312 resets = <&tegra_car 206>; 313 status = "disabled"; 314 }; 315 316 sor0: sor@54540000 { 317 compatible = "nvidia,tegra210-sor"; 318 reg = <0x0 0x54540000 0x0 0x00040000>; 319 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 321 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 322 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 323 <&tegra_car TEGRA210_CLK_PLL_DP>, 324 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 325 clock-names = "sor", "out", "parent", "dp", "safe"; 326 resets = <&tegra_car 182>; 327 reset-names = "sor"; 328 pinctrl-0 = <&state_dpaux_aux>; 329 pinctrl-1 = <&state_dpaux_i2c>; 330 pinctrl-2 = <&state_dpaux_off>; 331 pinctrl-names = "aux", "i2c", "off"; 332 power-domains = <&pd_sor>; 333 status = "disabled"; 334 }; 335 336 sor1: sor@54580000 { 337 compatible = "nvidia,tegra210-sor1"; 338 reg = <0x0 0x54580000 0x0 0x00040000>; 339 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 341 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 342 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 343 <&tegra_car TEGRA210_CLK_PLL_DP>, 344 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 345 clock-names = "sor", "out", "parent", "dp", "safe"; 346 resets = <&tegra_car 183>; 347 reset-names = "sor"; 348 pinctrl-0 = <&state_dpaux1_aux>; 349 pinctrl-1 = <&state_dpaux1_i2c>; 350 pinctrl-2 = <&state_dpaux1_off>; 351 pinctrl-names = "aux", "i2c", "off"; 352 power-domains = <&pd_sor>; 353 status = "disabled"; 354 }; 355 356 dpaux: dpaux@545c0000 { 357 compatible = "nvidia,tegra210-dpaux"; 358 reg = <0x0 0x545c0000 0x0 0x00040000>; 359 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 361 <&tegra_car TEGRA210_CLK_PLL_DP>; 362 clock-names = "dpaux", "parent"; 363 resets = <&tegra_car 181>; 364 reset-names = "dpaux"; 365 power-domains = <&pd_sor>; 366 status = "disabled"; 367 368 state_dpaux_aux: pinmux-aux { 369 groups = "dpaux-io"; 370 function = "aux"; 371 }; 372 373 state_dpaux_i2c: pinmux-i2c { 374 groups = "dpaux-io"; 375 function = "i2c"; 376 }; 377 378 state_dpaux_off: pinmux-off { 379 groups = "dpaux-io"; 380 function = "off"; 381 }; 382 383 i2c-bus { 384 #address-cells = <1>; 385 #size-cells = <0>; 386 }; 387 }; 388 389 isp@54600000 { 390 compatible = "nvidia,tegra210-isp"; 391 reg = <0x0 0x54600000 0x0 0x00040000>; 392 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&tegra_car TEGRA210_CLK_ISPA>; 394 resets = <&tegra_car 23>; 395 reset-names = "isp"; 396 status = "disabled"; 397 }; 398 399 isp@54680000 { 400 compatible = "nvidia,tegra210-isp"; 401 reg = <0x0 0x54680000 0x0 0x00040000>; 402 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&tegra_car TEGRA210_CLK_ISPB>; 404 resets = <&tegra_car 3>; 405 reset-names = "isp"; 406 status = "disabled"; 407 }; 408 409 i2c@546c0000 { 410 compatible = "nvidia,tegra210-i2c-vi"; 411 reg = <0x0 0x546c0000 0x0 0x00040000>; 412 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 414 <&tegra_car TEGRA210_CLK_I2CSLOW>; 415 clock-names = "div-clk", "slow"; 416 resets = <&tegra_car 208>; 417 reset-names = "i2c"; 418 power-domains = <&pd_venc>; 419 status = "disabled"; 420 421 #address-cells = <1>; 422 #size-cells = <0>; 423 }; 424 }; 425 426 gic: interrupt-controller@50041000 { 427 compatible = "arm,gic-400"; 428 #address-cells = <0>; 429 #interrupt-cells = <3>; 430 interrupt-controller; 431 reg = <0x0 0x50041000 0x0 0x1000>, 432 <0x0 0x50042000 0x0 0x2000>, 433 <0x0 0x50044000 0x0 0x2000>, 434 <0x0 0x50046000 0x0 0x2000>; 435 interrupts = <GIC_PPI 9 436 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 437 interrupt-parent = <&gic>; 438 }; 439 440 gpu@57000000 { 441 compatible = "nvidia,gm20b"; 442 reg = <0x0 0x57000000 0x0 0x01000000>, 443 <0x0 0x58000000 0x0 0x01000000>; 444 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 446 interrupt-names = "stall", "nonstall"; 447 clocks = <&tegra_car TEGRA210_CLK_GPU>, 448 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 449 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 450 clock-names = "gpu", "pwr", "ref"; 451 resets = <&tegra_car 184>; 452 reset-names = "gpu"; 453 454 iommus = <&mc TEGRA_SWGROUP_GPU>; 455 456 status = "disabled"; 457 }; 458 459 lic: interrupt-controller@60004000 { 460 compatible = "nvidia,tegra210-ictlr"; 461 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 462 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 463 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 464 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 465 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 466 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 467 interrupt-controller; 468 #interrupt-cells = <3>; 469 interrupt-parent = <&gic>; 470 }; 471 472 timer@60005000 { 473 compatible = "nvidia,tegra210-timer"; 474 reg = <0x0 0x60005000 0x0 0x400>; 475 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 490 clock-names = "timer"; 491 }; 492 493 tegra_car: clock@60006000 { 494 compatible = "nvidia,tegra210-car"; 495 reg = <0x0 0x60006000 0x0 0x1000>; 496 #clock-cells = <1>; 497 #reset-cells = <1>; 498 }; 499 500 flow-controller@60007000 { 501 compatible = "nvidia,tegra210-flowctrl"; 502 reg = <0x0 0x60007000 0x0 0x1000>; 503 }; 504 505 actmon@6000c800 { 506 compatible = "nvidia,tegra210-actmon", "nvidia,tegra124-actmon"; 507 reg = <0x0 0x6000c800 0x0 0x400>; 508 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&tegra_car TEGRA210_CLK_ACTMON>, 510 <&tegra_car TEGRA210_CLK_EMC>; 511 clock-names = "actmon", "emc"; 512 resets = <&tegra_car 119>; 513 reset-names = "actmon"; 514 operating-points-v2 = <&emc_bw_dfs_opp_table>; 515 interconnects = <&mc TEGRA210_MC_MPCORER &emc>; 516 interconnect-names = "cpu-read"; 517 #cooling-cells = <2>; 518 }; 519 520 gpio: gpio@6000d000 { 521 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 522 reg = <0x0 0x6000d000 0x0 0x1000>; 523 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 531 #gpio-cells = <2>; 532 gpio-controller; 533 #interrupt-cells = <2>; 534 interrupt-controller; 535 }; 536 537 apbdma: dma-controller@60020000 { 538 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 539 reg = <0x0 0x60020000 0x0 0x1400>; 540 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 573 clock-names = "dma"; 574 resets = <&tegra_car 34>; 575 reset-names = "dma"; 576 #dma-cells = <1>; 577 }; 578 579 apbmisc@70000800 { 580 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 581 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 582 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 583 }; 584 585 pinmux: pinmux@700008d4 { 586 compatible = "nvidia,tegra210-pinmux"; 587 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 588 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 589 590 sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv { 591 sdmmc1 { 592 nvidia,pins = "drive_sdmmc1"; 593 nvidia,pull-down-strength = <0x4>; 594 nvidia,pull-up-strength = <0x3>; 595 }; 596 }; 597 598 sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv { 599 sdmmc1 { 600 nvidia,pins = "drive_sdmmc1"; 601 nvidia,pull-down-strength = <0x8>; 602 nvidia,pull-up-strength = <0x8>; 603 }; 604 }; 605 606 sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv { 607 sdmmc2 { 608 nvidia,pins = "drive_sdmmc2"; 609 nvidia,pull-down-strength = <0x10>; 610 nvidia,pull-up-strength = <0x10>; 611 }; 612 }; 613 614 sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv { 615 sdmmc3 { 616 nvidia,pins = "drive_sdmmc3"; 617 nvidia,pull-down-strength = <0x4>; 618 nvidia,pull-up-strength = <0x3>; 619 }; 620 }; 621 622 sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv { 623 sdmmc3 { 624 nvidia,pins = "drive_sdmmc3"; 625 nvidia,pull-down-strength = <0x8>; 626 nvidia,pull-up-strength = <0x8>; 627 }; 628 }; 629 630 sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv { 631 sdmmc4 { 632 nvidia,pins = "drive_sdmmc4"; 633 nvidia,pull-down-strength = <0x10>; 634 nvidia,pull-up-strength = <0x10>; 635 }; 636 }; 637 }; 638 639 /* 640 * There are two serial driver i.e. 8250 based simple serial 641 * driver and APB DMA based serial driver for higher baudrate 642 * and performance. To enable the 8250 based driver, the compatible 643 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 644 * the APB DMA based serial driver, the compatible is 645 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 646 */ 647 uarta: serial@70006000 { 648 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 649 reg = <0x0 0x70006000 0x0 0x40>; 650 reg-shift = <2>; 651 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 653 resets = <&tegra_car 6>; 654 dmas = <&apbdma 8>, <&apbdma 8>; 655 dma-names = "rx", "tx"; 656 status = "disabled"; 657 }; 658 659 uartb: serial@70006040 { 660 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 661 reg = <0x0 0x70006040 0x0 0x40>; 662 reg-shift = <2>; 663 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 665 resets = <&tegra_car 7>; 666 dmas = <&apbdma 9>, <&apbdma 9>; 667 dma-names = "rx", "tx"; 668 status = "disabled"; 669 }; 670 671 uartc: serial@70006200 { 672 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 673 reg = <0x0 0x70006200 0x0 0x40>; 674 reg-shift = <2>; 675 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 677 resets = <&tegra_car 55>; 678 dmas = <&apbdma 10>, <&apbdma 10>; 679 dma-names = "rx", "tx"; 680 status = "disabled"; 681 }; 682 683 uartd: serial@70006300 { 684 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 685 reg = <0x0 0x70006300 0x0 0x40>; 686 reg-shift = <2>; 687 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 689 resets = <&tegra_car 65>; 690 dmas = <&apbdma 19>, <&apbdma 19>; 691 dma-names = "rx", "tx"; 692 status = "disabled"; 693 }; 694 695 pwm: pwm@7000a000 { 696 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 697 reg = <0x0 0x7000a000 0x0 0x100>; 698 #pwm-cells = <2>; 699 clocks = <&tegra_car TEGRA210_CLK_PWM>; 700 resets = <&tegra_car 17>; 701 reset-names = "pwm"; 702 status = "disabled"; 703 }; 704 705 i2c@7000c000 { 706 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 707 reg = <0x0 0x7000c000 0x0 0x100>; 708 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 712 clock-names = "div-clk"; 713 resets = <&tegra_car 12>; 714 reset-names = "i2c"; 715 dmas = <&apbdma 21>, <&apbdma 21>; 716 dma-names = "rx", "tx"; 717 status = "disabled"; 718 }; 719 720 i2c@7000c400 { 721 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 722 reg = <0x0 0x7000c400 0x0 0x100>; 723 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 724 #address-cells = <1>; 725 #size-cells = <0>; 726 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 727 clock-names = "div-clk"; 728 resets = <&tegra_car 54>; 729 reset-names = "i2c"; 730 dmas = <&apbdma 22>, <&apbdma 22>; 731 dma-names = "rx", "tx"; 732 status = "disabled"; 733 }; 734 735 i2c@7000c500 { 736 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 737 reg = <0x0 0x7000c500 0x0 0x100>; 738 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 739 #address-cells = <1>; 740 #size-cells = <0>; 741 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 742 clock-names = "div-clk"; 743 resets = <&tegra_car 67>; 744 reset-names = "i2c"; 745 dmas = <&apbdma 23>, <&apbdma 23>; 746 dma-names = "rx", "tx"; 747 status = "disabled"; 748 }; 749 750 i2c@7000c700 { 751 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 752 reg = <0x0 0x7000c700 0x0 0x100>; 753 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 754 #address-cells = <1>; 755 #size-cells = <0>; 756 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 757 clock-names = "div-clk"; 758 resets = <&tegra_car 103>; 759 reset-names = "i2c"; 760 dmas = <&apbdma 26>, <&apbdma 26>; 761 dma-names = "rx", "tx"; 762 pinctrl-0 = <&state_dpaux1_i2c>; 763 pinctrl-1 = <&state_dpaux1_off>; 764 pinctrl-names = "default", "idle"; 765 status = "disabled"; 766 }; 767 768 i2c@7000d000 { 769 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 770 reg = <0x0 0x7000d000 0x0 0x100>; 771 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 775 clock-names = "div-clk"; 776 resets = <&tegra_car 47>; 777 reset-names = "i2c"; 778 dmas = <&apbdma 24>, <&apbdma 24>; 779 dma-names = "rx", "tx"; 780 status = "disabled"; 781 }; 782 783 i2c@7000d100 { 784 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 785 reg = <0x0 0x7000d100 0x0 0x100>; 786 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 790 clock-names = "div-clk"; 791 resets = <&tegra_car 166>; 792 reset-names = "i2c"; 793 dmas = <&apbdma 30>, <&apbdma 30>; 794 dma-names = "rx", "tx"; 795 pinctrl-0 = <&state_dpaux_i2c>; 796 pinctrl-1 = <&state_dpaux_off>; 797 pinctrl-names = "default", "idle"; 798 status = "disabled"; 799 }; 800 801 spi@7000d400 { 802 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 803 reg = <0x0 0x7000d400 0x0 0x200>; 804 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 808 clock-names = "spi"; 809 resets = <&tegra_car 41>; 810 reset-names = "spi"; 811 dmas = <&apbdma 15>, <&apbdma 15>; 812 dma-names = "rx", "tx"; 813 status = "disabled"; 814 }; 815 816 spi@7000d600 { 817 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 818 reg = <0x0 0x7000d600 0x0 0x200>; 819 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 823 clock-names = "spi"; 824 resets = <&tegra_car 44>; 825 reset-names = "spi"; 826 dmas = <&apbdma 16>, <&apbdma 16>; 827 dma-names = "rx", "tx"; 828 status = "disabled"; 829 }; 830 831 spi@7000d800 { 832 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 833 reg = <0x0 0x7000d800 0x0 0x200>; 834 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 838 clock-names = "spi"; 839 resets = <&tegra_car 46>; 840 reset-names = "spi"; 841 dmas = <&apbdma 17>, <&apbdma 17>; 842 dma-names = "rx", "tx"; 843 status = "disabled"; 844 }; 845 846 spi@7000da00 { 847 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 848 reg = <0x0 0x7000da00 0x0 0x200>; 849 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 853 clock-names = "spi"; 854 resets = <&tegra_car 68>; 855 reset-names = "spi"; 856 dmas = <&apbdma 18>, <&apbdma 18>; 857 dma-names = "rx", "tx"; 858 status = "disabled"; 859 }; 860 861 rtc@7000e000 { 862 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 863 reg = <0x0 0x7000e000 0x0 0x100>; 864 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 865 interrupt-parent = <&tegra_pmc>; 866 clocks = <&tegra_car TEGRA210_CLK_RTC>; 867 clock-names = "rtc"; 868 }; 869 870 tegra_pmc: pmc@7000e400 { 871 compatible = "nvidia,tegra210-pmc"; 872 reg = <0x0 0x7000e400 0x0 0x400>; 873 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 874 clock-names = "pclk", "clk32k_in"; 875 #clock-cells = <1>; 876 #interrupt-cells = <2>; 877 interrupt-controller; 878 879 pinmux { 880 pex_dpd_disable: pex-dpd-disable { 881 pins = "pex-bias", "pex-clk1", "pex-clk2"; 882 low-power-disable; 883 }; 884 885 pex_dpd_enable: pex-dpd-enable { 886 pins = "pex-bias", "pex-clk1", "pex-clk2"; 887 low-power-enable; 888 }; 889 890 sdmmc1_1v8: sdmmc1-1v8 { 891 pins = "sdmmc1"; 892 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 893 }; 894 895 sdmmc1_3v3: sdmmc1-3v3 { 896 pins = "sdmmc1"; 897 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 898 }; 899 900 sdmmc3_1v8: sdmmc3-1v8 { 901 pins = "sdmmc3"; 902 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 903 }; 904 905 sdmmc3_3v3: sdmmc3-3v3 { 906 pins = "sdmmc3"; 907 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 908 }; 909 910 gpio_1v8: gpio-1v8 { 911 pins = "gpio"; 912 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 913 }; 914 915 gpio_3v3: gpio-3v3 { 916 pins = "gpio"; 917 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 918 }; 919 }; 920 921 powergates { 922 pd_audio: aud { 923 clocks = <&tegra_car TEGRA210_CLK_APE>, 924 <&tegra_car TEGRA210_CLK_APB2APE>; 925 resets = <&tegra_car 198>; 926 #power-domain-cells = <0>; 927 }; 928 929 pd_nvenc: mpe { 930 clocks = <&tegra_car TEGRA210_CLK_NVENC>; 931 resets = <&tegra_car 219>; 932 #power-domain-cells = <0>; 933 }; 934 935 pd_nvdec: nvdec { 936 clocks = <&tegra_car TEGRA210_CLK_NVDEC>; 937 resets = <&tegra_car 194>; 938 #power-domain-cells = <0>; 939 }; 940 941 pd_sor: sor { 942 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 943 <&tegra_car TEGRA210_CLK_SOR1>, 944 <&tegra_car TEGRA210_CLK_CILAB>, 945 <&tegra_car TEGRA210_CLK_CILCD>, 946 <&tegra_car TEGRA210_CLK_CILE>, 947 <&tegra_car TEGRA210_CLK_DSIA>, 948 <&tegra_car TEGRA210_CLK_DSIB>, 949 <&tegra_car TEGRA210_CLK_DPAUX>, 950 <&tegra_car TEGRA210_CLK_DPAUX1>, 951 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 952 resets = <&tegra_car TEGRA210_CLK_SOR0>, 953 <&tegra_car TEGRA210_CLK_SOR1>, 954 <&tegra_car TEGRA210_CLK_DSIA>, 955 <&tegra_car TEGRA210_CLK_DSIB>, 956 <&tegra_car TEGRA210_CLK_DPAUX>, 957 <&tegra_car TEGRA210_CLK_DPAUX1>, 958 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 959 #power-domain-cells = <0>; 960 }; 961 962 pd_venc: venc { 963 clocks = <&tegra_car TEGRA210_CLK_VI>, 964 <&tegra_car TEGRA210_CLK_CSI>; 965 resets = <&mc TEGRA210_MC_RESET_VI>, 966 <&tegra_car 20>, 967 <&tegra_car 52>; 968 #power-domain-cells = <0>; 969 }; 970 971 pd_vic: vic { 972 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 973 resets = <&tegra_car 178>; 974 #power-domain-cells = <0>; 975 }; 976 977 pd_xusbss: xusba { 978 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 979 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 980 #power-domain-cells = <0>; 981 }; 982 983 pd_xusbdev: xusbb { 984 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 985 resets = <&tegra_car 95>; 986 #power-domain-cells = <0>; 987 }; 988 989 pd_xusbhost: xusbc { 990 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 991 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 992 #power-domain-cells = <0>; 993 }; 994 995 pd_nvjpg: nvjpg { 996 clocks = <&tegra_car TEGRA210_CLK_NVJPG>; 997 resets = <&tegra_car 195>; 998 #power-domain-cells = <0>; 999 }; 1000 }; 1001 }; 1002 1003 fuse@7000f800 { 1004 compatible = "nvidia,tegra210-efuse"; 1005 reg = <0x0 0x7000f800 0x0 0x400>; 1006 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 1007 clock-names = "fuse"; 1008 resets = <&tegra_car 39>; 1009 reset-names = "fuse"; 1010 }; 1011 1012 cec@70015000 { 1013 compatible = "nvidia,tegra210-cec"; 1014 reg = <0x0 0x070015000 0x0 0x1000>; 1015 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&tegra_car TEGRA210_CLK_CEC>; 1017 clock-names = "cec"; 1018 status = "disabled"; 1019 }; 1020 1021 mc: memory-controller@70019000 { 1022 compatible = "nvidia,tegra210-mc"; 1023 reg = <0x0 0x70019000 0x0 0x1000>; 1024 clocks = <&tegra_car TEGRA210_CLK_MC>; 1025 clock-names = "mc"; 1026 1027 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1028 1029 #iommu-cells = <1>; 1030 #reset-cells = <1>; 1031 }; 1032 1033 emc: external-memory-controller@7001b000 { 1034 compatible = "nvidia,tegra210-emc"; 1035 reg = <0x0 0x7001b000 0x0 0x1000>, 1036 <0x0 0x7001e000 0x0 0x1000>, 1037 <0x0 0x7001f000 0x0 0x1000>; 1038 clocks = <&tegra_car TEGRA210_CLK_EMC>; 1039 clock-names = "emc"; 1040 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1041 nvidia,memory-controller = <&mc>; 1042 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 1043 1044 #cooling-cells = <2>; 1045 }; 1046 1047 sata@70020000 { 1048 compatible = "nvidia,tegra210-ahci"; 1049 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 1050 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 1051 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 1052 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1053 clocks = <&tegra_car TEGRA210_CLK_SATA>, 1054 <&tegra_car TEGRA210_CLK_SATA_OOB>; 1055 clock-names = "sata", "sata-oob"; 1056 resets = <&tegra_car 124>, 1057 <&tegra_car 129>, 1058 <&tegra_car 123>; 1059 reset-names = "sata", "sata-cold", "sata-oob"; 1060 status = "disabled"; 1061 }; 1062 1063 hda@70030000 { 1064 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 1065 reg = <0x0 0x70030000 0x0 0x10000>; 1066 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1067 clocks = <&tegra_car TEGRA210_CLK_HDA>, 1068 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 1069 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 1070 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1071 resets = <&tegra_car 125>, /* hda */ 1072 <&tegra_car 128>, /* hda2hdmi */ 1073 <&tegra_car 111>; /* hda2codec_2x */ 1074 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1075 power-domains = <&pd_sor>; 1076 status = "disabled"; 1077 }; 1078 1079 usb@70090000 { 1080 compatible = "nvidia,tegra210-xusb"; 1081 reg = <0x0 0x70090000 0x0 0x8000>, 1082 <0x0 0x70098000 0x0 0x1000>, 1083 <0x0 0x70099000 0x0 0x1000>; 1084 reg-names = "hcd", "fpci", "ipfs"; 1085 1086 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1088 1089 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1090 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1091 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1092 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1093 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1094 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1095 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1096 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1097 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1098 <&tegra_car TEGRA210_CLK_CLK_M>, 1099 <&tegra_car TEGRA210_CLK_PLL_E>; 1100 clock-names = "xusb_host", "xusb_host_src", 1101 "xusb_falcon_src", "xusb_ss", 1102 "xusb_ss_div2", "xusb_ss_src", 1103 "xusb_hs_src", "xusb_fs_src", 1104 "pll_u_480m", "clk_m", "pll_e"; 1105 resets = <&tegra_car 89>, <&tegra_car 156>, 1106 <&tegra_car 143>; 1107 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1108 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1109 power-domain-names = "xusb_host", "xusb_ss"; 1110 1111 nvidia,xusb-padctl = <&padctl>; 1112 1113 status = "disabled"; 1114 }; 1115 1116 padctl: padctl@7009f000 { 1117 compatible = "nvidia,tegra210-xusb-padctl"; 1118 reg = <0x0 0x7009f000 0x0 0x1000>; 1119 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1120 resets = <&tegra_car 142>; 1121 reset-names = "padctl"; 1122 nvidia,pmc = <&tegra_pmc>; 1123 1124 status = "disabled"; 1125 1126 pads { 1127 usb2 { 1128 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1129 clock-names = "trk"; 1130 status = "disabled"; 1131 1132 lanes { 1133 usb2-0 { 1134 status = "disabled"; 1135 #phy-cells = <0>; 1136 }; 1137 1138 usb2-1 { 1139 status = "disabled"; 1140 #phy-cells = <0>; 1141 }; 1142 1143 usb2-2 { 1144 status = "disabled"; 1145 #phy-cells = <0>; 1146 }; 1147 1148 usb2-3 { 1149 status = "disabled"; 1150 #phy-cells = <0>; 1151 }; 1152 }; 1153 }; 1154 1155 hsic { 1156 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1157 clock-names = "trk"; 1158 status = "disabled"; 1159 1160 lanes { 1161 hsic-0 { 1162 status = "disabled"; 1163 #phy-cells = <0>; 1164 }; 1165 1166 hsic-1 { 1167 status = "disabled"; 1168 #phy-cells = <0>; 1169 }; 1170 }; 1171 }; 1172 1173 pcie { 1174 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1175 clock-names = "pll"; 1176 resets = <&tegra_car 205>; 1177 reset-names = "phy"; 1178 status = "disabled"; 1179 1180 lanes { 1181 pcie-0 { 1182 status = "disabled"; 1183 #phy-cells = <0>; 1184 }; 1185 1186 pcie-1 { 1187 status = "disabled"; 1188 #phy-cells = <0>; 1189 }; 1190 1191 pcie-2 { 1192 status = "disabled"; 1193 #phy-cells = <0>; 1194 }; 1195 1196 pcie-3 { 1197 status = "disabled"; 1198 #phy-cells = <0>; 1199 }; 1200 1201 pcie-4 { 1202 status = "disabled"; 1203 #phy-cells = <0>; 1204 }; 1205 1206 pcie-5 { 1207 status = "disabled"; 1208 #phy-cells = <0>; 1209 }; 1210 1211 pcie-6 { 1212 status = "disabled"; 1213 #phy-cells = <0>; 1214 }; 1215 }; 1216 }; 1217 1218 sata { 1219 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1220 clock-names = "pll"; 1221 resets = <&tegra_car 204>; 1222 reset-names = "phy"; 1223 status = "disabled"; 1224 1225 lanes { 1226 sata-0 { 1227 status = "disabled"; 1228 #phy-cells = <0>; 1229 }; 1230 }; 1231 }; 1232 }; 1233 1234 ports { 1235 usb2-0 { 1236 status = "disabled"; 1237 }; 1238 1239 usb2-1 { 1240 status = "disabled"; 1241 }; 1242 1243 usb2-2 { 1244 status = "disabled"; 1245 }; 1246 1247 usb2-3 { 1248 status = "disabled"; 1249 }; 1250 1251 hsic-0 { 1252 status = "disabled"; 1253 }; 1254 1255 usb3-0 { 1256 status = "disabled"; 1257 }; 1258 1259 usb3-1 { 1260 status = "disabled"; 1261 }; 1262 1263 usb3-2 { 1264 status = "disabled"; 1265 }; 1266 1267 usb3-3 { 1268 status = "disabled"; 1269 }; 1270 }; 1271 }; 1272 1273 mmc@700b0000 { 1274 compatible = "nvidia,tegra210-sdhci"; 1275 reg = <0x0 0x700b0000 0x0 0x200>; 1276 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1277 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, 1278 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1279 clock-names = "sdhci", "tmclk"; 1280 resets = <&tegra_car 14>; 1281 reset-names = "sdhci"; 1282 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1283 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1284 pinctrl-0 = <&sdmmc1_3v3>; 1285 pinctrl-1 = <&sdmmc1_1v8>; 1286 pinctrl-2 = <&sdmmc1_3v3_drv>; 1287 pinctrl-3 = <&sdmmc1_1v8_drv>; 1288 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1289 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1290 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1291 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1292 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x0>; 1293 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x0>; 1294 nvidia,default-tap = <0x2>; 1295 nvidia,default-trim = <0x4>; 1296 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1297 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1298 <&tegra_car TEGRA210_CLK_PLL_C4>; 1299 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1300 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1301 status = "disabled"; 1302 }; 1303 1304 mmc@700b0200 { 1305 compatible = "nvidia,tegra210-sdhci"; 1306 reg = <0x0 0x700b0200 0x0 0x200>; 1307 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1308 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, 1309 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1310 clock-names = "sdhci", "tmclk"; 1311 resets = <&tegra_car 9>; 1312 reset-names = "sdhci"; 1313 pinctrl-names = "sdmmc-1v8-drv"; 1314 pinctrl-0 = <&sdmmc2_1v8_drv>; 1315 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1316 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1317 nvidia,default-tap = <0x8>; 1318 nvidia,default-trim = <0x0>; 1319 status = "disabled"; 1320 }; 1321 1322 mmc@700b0400 { 1323 compatible = "nvidia,tegra210-sdhci"; 1324 reg = <0x0 0x700b0400 0x0 0x200>; 1325 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1326 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, 1327 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1328 clock-names = "sdhci", "tmclk"; 1329 resets = <&tegra_car 69>; 1330 reset-names = "sdhci"; 1331 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1332 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1333 pinctrl-0 = <&sdmmc3_3v3>; 1334 pinctrl-1 = <&sdmmc3_1v8>; 1335 pinctrl-2 = <&sdmmc3_3v3_drv>; 1336 pinctrl-3 = <&sdmmc3_1v8_drv>; 1337 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1338 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1339 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1340 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1341 nvidia,default-tap = <0x3>; 1342 nvidia,default-trim = <0x3>; 1343 status = "disabled"; 1344 }; 1345 1346 mmc@700b0600 { 1347 compatible = "nvidia,tegra210-sdhci"; 1348 reg = <0x0 0x700b0600 0x0 0x200>; 1349 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1350 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1351 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1352 clock-names = "sdhci", "tmclk"; 1353 resets = <&tegra_car 15>; 1354 reset-names = "sdhci"; 1355 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1356 pinctrl-0 = <&sdmmc4_1v8_drv>; 1357 pinctrl-1 = <&sdmmc4_1v8_drv>; 1358 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1359 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1360 nvidia,default-tap = <0x8>; 1361 nvidia,default-trim = <0x0>; 1362 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1363 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1364 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1365 nvidia,dqs-trim = <40>; 1366 mmc-hs400-1_8v; 1367 status = "disabled"; 1368 }; 1369 1370 usb@700d0000 { 1371 compatible = "nvidia,tegra210-xudc"; 1372 reg = <0x0 0x700d0000 0x0 0x8000>, 1373 <0x0 0x700d8000 0x0 0x1000>, 1374 <0x0 0x700d9000 0x0 0x1000>; 1375 reg-names = "base", "fpci", "ipfs"; 1376 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1377 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1378 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1379 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1380 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1381 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1382 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1383 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1384 power-domain-names = "dev", "ss"; 1385 nvidia,xusb-padctl = <&padctl>; 1386 status = "disabled"; 1387 }; 1388 1389 soctherm: thermal-sensor@700e2000 { 1390 compatible = "nvidia,tegra210-soctherm"; 1391 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1392 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1393 reg-names = "soctherm-reg", "car-reg"; 1394 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1396 interrupt-names = "thermal", "edp"; 1397 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1398 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1399 clock-names = "tsensor", "soctherm"; 1400 resets = <&tegra_car 78>; 1401 reset-names = "soctherm"; 1402 #thermal-sensor-cells = <1>; 1403 1404 throttle-cfgs { 1405 throttle_heavy: heavy { 1406 nvidia,priority = <100>; 1407 nvidia,cpu-throt-percent = <85>; 1408 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 1409 1410 #cooling-cells = <2>; 1411 }; 1412 }; 1413 }; 1414 1415 mipi: mipi@700e3000 { 1416 compatible = "nvidia,tegra210-mipi"; 1417 reg = <0x0 0x700e3000 0x0 0x100>; 1418 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1419 clock-names = "mipi-cal"; 1420 power-domains = <&pd_sor>; 1421 #nvidia,mipi-calibrate-cells = <1>; 1422 }; 1423 1424 dfll: clock@70110000 { 1425 compatible = "nvidia,tegra210-dfll"; 1426 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1427 <0 0x70110000 0 0x100>, /* I2C output control */ 1428 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1429 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1430 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1431 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1432 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1433 <&tegra_car TEGRA210_CLK_I2C5>; 1434 clock-names = "soc", "ref", "i2c"; 1435 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, 1436 <&tegra_car 155>; 1437 reset-names = "dvco", "dfll"; 1438 #clock-cells = <0>; 1439 clock-output-names = "dfllCPU_out"; 1440 status = "disabled"; 1441 }; 1442 1443 aconnect@702c0000 { 1444 compatible = "nvidia,tegra210-aconnect"; 1445 clocks = <&tegra_car TEGRA210_CLK_APE>, 1446 <&tegra_car TEGRA210_CLK_APB2APE>; 1447 clock-names = "ape", "apb2ape"; 1448 power-domains = <&pd_audio>; 1449 #address-cells = <1>; 1450 #size-cells = <1>; 1451 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1452 status = "disabled"; 1453 1454 tegra_ahub: ahub@702d0800 { 1455 compatible = "nvidia,tegra210-ahub"; 1456 reg = <0x702d0800 0x800>; 1457 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1458 clock-names = "ahub"; 1459 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1460 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>; 1461 assigned-clock-rates = <81600000>; 1462 #address-cells = <1>; 1463 #size-cells = <1>; 1464 ranges = <0x702d0000 0x702d0000 0x0000e400>; 1465 status = "disabled"; 1466 1467 tegra_admaif: admaif@702d0000 { 1468 compatible = "nvidia,tegra210-admaif"; 1469 reg = <0x702d0000 0x800>; 1470 dmas = <&adma 1>, <&adma 1>, 1471 <&adma 2>, <&adma 2>, 1472 <&adma 3>, <&adma 3>, 1473 <&adma 4>, <&adma 4>, 1474 <&adma 5>, <&adma 5>, 1475 <&adma 6>, <&adma 6>, 1476 <&adma 7>, <&adma 7>, 1477 <&adma 8>, <&adma 8>, 1478 <&adma 9>, <&adma 9>, 1479 <&adma 10>, <&adma 10>; 1480 dma-names = "rx1", "tx1", 1481 "rx2", "tx2", 1482 "rx3", "tx3", 1483 "rx4", "tx4", 1484 "rx5", "tx5", 1485 "rx6", "tx6", 1486 "rx7", "tx7", 1487 "rx8", "tx8", 1488 "rx9", "tx9", 1489 "rx10", "tx10"; 1490 status = "disabled"; 1491 1492 ports { 1493 #address-cells = <1>; 1494 #size-cells = <0>; 1495 1496 admaif1_port: port@0 { 1497 reg = <0>; 1498 1499 admaif1_ep: endpoint { 1500 remote-endpoint = <&xbar_admaif1_ep>; 1501 }; 1502 }; 1503 1504 admaif2_port: port@1 { 1505 reg = <1>; 1506 1507 admaif2_ep: endpoint { 1508 remote-endpoint = <&xbar_admaif2_ep>; 1509 }; 1510 }; 1511 1512 admaif3_port: port@2 { 1513 reg = <2>; 1514 1515 admaif3_ep: endpoint { 1516 remote-endpoint = <&xbar_admaif3_ep>; 1517 }; 1518 }; 1519 1520 admaif4_port: port@3 { 1521 reg = <3>; 1522 1523 admaif4_ep: endpoint { 1524 remote-endpoint = <&xbar_admaif4_ep>; 1525 }; 1526 }; 1527 1528 admaif5_port: port@4 { 1529 reg = <4>; 1530 1531 admaif5_ep: endpoint { 1532 remote-endpoint = <&xbar_admaif5_ep>; 1533 }; 1534 }; 1535 1536 admaif6_port: port@5 { 1537 reg = <5>; 1538 1539 admaif6_ep: endpoint { 1540 remote-endpoint = <&xbar_admaif6_ep>; 1541 }; 1542 }; 1543 1544 admaif7_port: port@6 { 1545 reg = <6>; 1546 1547 admaif7_ep: endpoint { 1548 remote-endpoint = <&xbar_admaif7_ep>; 1549 }; 1550 }; 1551 1552 admaif8_port: port@7 { 1553 reg = <7>; 1554 1555 admaif8_ep: endpoint { 1556 remote-endpoint = <&xbar_admaif8_ep>; 1557 }; 1558 }; 1559 1560 admaif9_port: port@8 { 1561 reg = <8>; 1562 1563 admaif9_ep: endpoint { 1564 remote-endpoint = <&xbar_admaif9_ep>; 1565 }; 1566 }; 1567 1568 admaif10_port: port@9 { 1569 reg = <9>; 1570 1571 admaif10_ep: endpoint { 1572 remote-endpoint = <&xbar_admaif10_ep>; 1573 }; 1574 }; 1575 }; 1576 }; 1577 1578 tegra_i2s1: i2s@702d1000 { 1579 compatible = "nvidia,tegra210-i2s"; 1580 reg = <0x702d1000 0x100>; 1581 clocks = <&tegra_car TEGRA210_CLK_I2S0>, 1582 <&tegra_car TEGRA210_CLK_I2S0_SYNC>; 1583 clock-names = "i2s", "sync_input"; 1584 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; 1585 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1586 assigned-clock-rates = <1536000>; 1587 sound-name-prefix = "I2S1"; 1588 status = "disabled"; 1589 }; 1590 1591 tegra_i2s2: i2s@702d1100 { 1592 compatible = "nvidia,tegra210-i2s"; 1593 reg = <0x702d1100 0x100>; 1594 clocks = <&tegra_car TEGRA210_CLK_I2S1>, 1595 <&tegra_car TEGRA210_CLK_I2S1_SYNC>; 1596 clock-names = "i2s", "sync_input"; 1597 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; 1598 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1599 assigned-clock-rates = <1536000>; 1600 sound-name-prefix = "I2S2"; 1601 status = "disabled"; 1602 }; 1603 1604 tegra_i2s3: i2s@702d1200 { 1605 compatible = "nvidia,tegra210-i2s"; 1606 reg = <0x702d1200 0x100>; 1607 clocks = <&tegra_car TEGRA210_CLK_I2S2>, 1608 <&tegra_car TEGRA210_CLK_I2S2_SYNC>; 1609 clock-names = "i2s", "sync_input"; 1610 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; 1611 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1612 assigned-clock-rates = <1536000>; 1613 sound-name-prefix = "I2S3"; 1614 status = "disabled"; 1615 }; 1616 1617 tegra_i2s4: i2s@702d1300 { 1618 compatible = "nvidia,tegra210-i2s"; 1619 reg = <0x702d1300 0x100>; 1620 clocks = <&tegra_car TEGRA210_CLK_I2S3>, 1621 <&tegra_car TEGRA210_CLK_I2S3_SYNC>; 1622 clock-names = "i2s", "sync_input"; 1623 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; 1624 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1625 assigned-clock-rates = <1536000>; 1626 sound-name-prefix = "I2S4"; 1627 status = "disabled"; 1628 }; 1629 1630 tegra_i2s5: i2s@702d1400 { 1631 compatible = "nvidia,tegra210-i2s"; 1632 reg = <0x702d1400 0x100>; 1633 clocks = <&tegra_car TEGRA210_CLK_I2S4>, 1634 <&tegra_car TEGRA210_CLK_I2S4_SYNC>; 1635 clock-names = "i2s", "sync_input"; 1636 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; 1637 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1638 assigned-clock-rates = <1536000>; 1639 sound-name-prefix = "I2S5"; 1640 status = "disabled"; 1641 }; 1642 1643 tegra_sfc1: sfc@702d2000 { 1644 compatible = "nvidia,tegra210-sfc"; 1645 reg = <0x702d2000 0x200>; 1646 sound-name-prefix = "SFC1"; 1647 status = "disabled"; 1648 }; 1649 1650 tegra_sfc2: sfc@702d2200 { 1651 compatible = "nvidia,tegra210-sfc"; 1652 reg = <0x702d2200 0x200>; 1653 sound-name-prefix = "SFC2"; 1654 status = "disabled"; 1655 }; 1656 1657 tegra_sfc3: sfc@702d2400 { 1658 compatible = "nvidia,tegra210-sfc"; 1659 reg = <0x702d2400 0x200>; 1660 sound-name-prefix = "SFC3"; 1661 status = "disabled"; 1662 }; 1663 1664 tegra_sfc4: sfc@702d2600 { 1665 compatible = "nvidia,tegra210-sfc"; 1666 reg = <0x702d2600 0x200>; 1667 sound-name-prefix = "SFC4"; 1668 status = "disabled"; 1669 }; 1670 1671 tegra_amx1: amx@702d3000 { 1672 compatible = "nvidia,tegra210-amx"; 1673 reg = <0x702d3000 0x100>; 1674 sound-name-prefix = "AMX1"; 1675 status = "disabled"; 1676 }; 1677 1678 tegra_amx2: amx@702d3100 { 1679 compatible = "nvidia,tegra210-amx"; 1680 reg = <0x702d3100 0x100>; 1681 sound-name-prefix = "AMX2"; 1682 status = "disabled"; 1683 }; 1684 1685 tegra_adx1: adx@702d3800 { 1686 compatible = "nvidia,tegra210-adx"; 1687 reg = <0x702d3800 0x100>; 1688 sound-name-prefix = "ADX1"; 1689 status = "disabled"; 1690 }; 1691 1692 tegra_adx2: adx@702d3900 { 1693 compatible = "nvidia,tegra210-adx"; 1694 reg = <0x702d3900 0x100>; 1695 sound-name-prefix = "ADX2"; 1696 status = "disabled"; 1697 }; 1698 1699 tegra_dmic1: dmic@702d4000 { 1700 compatible = "nvidia,tegra210-dmic"; 1701 reg = <0x702d4000 0x100>; 1702 clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1703 clock-names = "dmic"; 1704 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1705 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1706 assigned-clock-rates = <3072000>; 1707 sound-name-prefix = "DMIC1"; 1708 status = "disabled"; 1709 }; 1710 1711 tegra_dmic2: dmic@702d4100 { 1712 compatible = "nvidia,tegra210-dmic"; 1713 reg = <0x702d4100 0x100>; 1714 clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1715 clock-names = "dmic"; 1716 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1717 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1718 assigned-clock-rates = <3072000>; 1719 sound-name-prefix = "DMIC2"; 1720 status = "disabled"; 1721 }; 1722 1723 tegra_dmic3: dmic@702d4200 { 1724 compatible = "nvidia,tegra210-dmic"; 1725 reg = <0x702d4200 0x100>; 1726 clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1727 clock-names = "dmic"; 1728 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1729 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1730 assigned-clock-rates = <3072000>; 1731 sound-name-prefix = "DMIC3"; 1732 status = "disabled"; 1733 }; 1734 1735 tegra_ope1: processing-engine@702d8000 { 1736 compatible = "nvidia,tegra210-ope"; 1737 reg = <0x702d8000 0x100>; 1738 #address-cells = <1>; 1739 #size-cells = <1>; 1740 ranges; 1741 sound-name-prefix = "OPE1"; 1742 status = "disabled"; 1743 1744 equalizer@702d8100 { 1745 compatible = "nvidia,tegra210-peq"; 1746 reg = <0x702d8100 0x100>; 1747 }; 1748 1749 dynamic-range-compressor@702d8200 { 1750 compatible = "nvidia,tegra210-mbdrc"; 1751 reg = <0x702d8200 0x200>; 1752 }; 1753 }; 1754 1755 tegra_ope2: processing-engine@702d8400 { 1756 compatible = "nvidia,tegra210-ope"; 1757 reg = <0x702d8400 0x100>; 1758 #address-cells = <1>; 1759 #size-cells = <1>; 1760 ranges; 1761 sound-name-prefix = "OPE2"; 1762 status = "disabled"; 1763 1764 equalizer@702d8500 { 1765 compatible = "nvidia,tegra210-peq"; 1766 reg = <0x702d8500 0x100>; 1767 }; 1768 1769 dynamic-range-compressor@702d8600 { 1770 compatible = "nvidia,tegra210-mbdrc"; 1771 reg = <0x702d8600 0x200>; 1772 }; 1773 }; 1774 1775 tegra_mvc1: mvc@702da000 { 1776 compatible = "nvidia,tegra210-mvc"; 1777 reg = <0x702da000 0x200>; 1778 sound-name-prefix = "MVC1"; 1779 status = "disabled"; 1780 }; 1781 1782 tegra_mvc2: mvc@702da200 { 1783 compatible = "nvidia,tegra210-mvc"; 1784 reg = <0x702da200 0x200>; 1785 sound-name-prefix = "MVC2"; 1786 status = "disabled"; 1787 }; 1788 1789 tegra_amixer: amixer@702dbb00 { 1790 compatible = "nvidia,tegra210-amixer"; 1791 reg = <0x702dbb00 0x800>; 1792 sound-name-prefix = "MIXER1"; 1793 status = "disabled"; 1794 }; 1795 1796 ports { 1797 #address-cells = <1>; 1798 #size-cells = <0>; 1799 1800 port@0 { 1801 reg = <0x0>; 1802 1803 xbar_admaif1_ep: endpoint { 1804 remote-endpoint = <&admaif1_ep>; 1805 }; 1806 }; 1807 1808 port@1 { 1809 reg = <0x1>; 1810 1811 xbar_admaif2_ep: endpoint { 1812 remote-endpoint = <&admaif2_ep>; 1813 }; 1814 }; 1815 1816 port@2 { 1817 reg = <0x2>; 1818 1819 xbar_admaif3_ep: endpoint { 1820 remote-endpoint = <&admaif3_ep>; 1821 }; 1822 }; 1823 1824 port@3 { 1825 reg = <0x3>; 1826 1827 xbar_admaif4_ep: endpoint { 1828 remote-endpoint = <&admaif4_ep>; 1829 }; 1830 }; 1831 1832 port@4 { 1833 reg = <0x4>; 1834 xbar_admaif5_ep: endpoint { 1835 remote-endpoint = <&admaif5_ep>; 1836 }; 1837 }; 1838 port@5 { 1839 reg = <0x5>; 1840 1841 xbar_admaif6_ep: endpoint { 1842 remote-endpoint = <&admaif6_ep>; 1843 }; 1844 }; 1845 1846 port@6 { 1847 reg = <0x6>; 1848 1849 xbar_admaif7_ep: endpoint { 1850 remote-endpoint = <&admaif7_ep>; 1851 }; 1852 }; 1853 1854 port@7 { 1855 reg = <0x7>; 1856 1857 xbar_admaif8_ep: endpoint { 1858 remote-endpoint = <&admaif8_ep>; 1859 }; 1860 }; 1861 1862 port@8 { 1863 reg = <0x8>; 1864 1865 xbar_admaif9_ep: endpoint { 1866 remote-endpoint = <&admaif9_ep>; 1867 }; 1868 }; 1869 1870 port@9 { 1871 reg = <0x9>; 1872 1873 xbar_admaif10_ep: endpoint { 1874 remote-endpoint = <&admaif10_ep>; 1875 }; 1876 }; 1877 }; 1878 }; 1879 1880 adma: dma-controller@702e2000 { 1881 compatible = "nvidia,tegra210-adma"; 1882 reg = <0x702e2000 0x2000>; 1883 interrupt-parent = <&agic>; 1884 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1906 #dma-cells = <1>; 1907 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1908 clock-names = "d_audio"; 1909 status = "disabled"; 1910 }; 1911 1912 agic: interrupt-controller@702f9000 { 1913 compatible = "nvidia,tegra210-agic"; 1914 #interrupt-cells = <3>; 1915 interrupt-controller; 1916 reg = <0x702f9000 0x1000>, 1917 <0x702fa000 0x2000>; 1918 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1919 clocks = <&tegra_car TEGRA210_CLK_APE>; 1920 clock-names = "clk"; 1921 status = "disabled"; 1922 }; 1923 }; 1924 1925 spi@70410000 { 1926 compatible = "nvidia,tegra210-qspi"; 1927 reg = <0x0 0x70410000 0x0 0x1000>; 1928 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1929 #address-cells = <1>; 1930 #size-cells = <0>; 1931 clocks = <&tegra_car TEGRA210_CLK_QSPI>, 1932 <&tegra_car TEGRA210_CLK_QSPI_PM>; 1933 clock-names = "qspi", "qspi_out"; 1934 resets = <&tegra_car 211>; 1935 dmas = <&apbdma 5>, <&apbdma 5>; 1936 dma-names = "rx", "tx"; 1937 status = "disabled"; 1938 }; 1939 1940 usb@7d000000 { 1941 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1942 reg = <0x0 0x7d000000 0x0 0x4000>; 1943 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1944 phy_type = "utmi"; 1945 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1946 clock-names = "usb"; 1947 resets = <&tegra_car 22>; 1948 reset-names = "usb"; 1949 nvidia,phy = <&phy1>; 1950 status = "disabled"; 1951 }; 1952 1953 phy1: usb-phy@7d000000 { 1954 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1955 reg = <0x0 0x7d000000 0x0 0x4000>, 1956 <0x0 0x7d000000 0x0 0x4000>; 1957 phy_type = "utmi"; 1958 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1959 <&tegra_car TEGRA210_CLK_PLL_U>, 1960 <&tegra_car TEGRA210_CLK_USBD>; 1961 clock-names = "reg", "pll_u", "utmi-pads"; 1962 resets = <&tegra_car 22>, <&tegra_car 22>; 1963 reset-names = "usb", "utmi-pads"; 1964 nvidia,hssync-start-delay = <0>; 1965 nvidia,idle-wait-delay = <17>; 1966 nvidia,elastic-limit = <16>; 1967 nvidia,term-range-adj = <6>; 1968 nvidia,xcvr-setup = <9>; 1969 nvidia,xcvr-lsfslew = <0>; 1970 nvidia,xcvr-lsrslew = <3>; 1971 nvidia,hssquelch-level = <2>; 1972 nvidia,hsdiscon-level = <5>; 1973 nvidia,xcvr-hsslew = <12>; 1974 nvidia,has-utmi-pad-registers; 1975 status = "disabled"; 1976 }; 1977 1978 usb@7d004000 { 1979 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1980 reg = <0x0 0x7d004000 0x0 0x4000>; 1981 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1982 phy_type = "utmi"; 1983 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1984 clock-names = "usb"; 1985 resets = <&tegra_car 58>; 1986 reset-names = "usb"; 1987 nvidia,phy = <&phy2>; 1988 status = "disabled"; 1989 }; 1990 1991 phy2: usb-phy@7d004000 { 1992 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1993 reg = <0x0 0x7d004000 0x0 0x4000>, 1994 <0x0 0x7d000000 0x0 0x4000>; 1995 phy_type = "utmi"; 1996 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1997 <&tegra_car TEGRA210_CLK_PLL_U>, 1998 <&tegra_car TEGRA210_CLK_USBD>; 1999 clock-names = "reg", "pll_u", "utmi-pads"; 2000 resets = <&tegra_car 58>, <&tegra_car 22>; 2001 reset-names = "usb", "utmi-pads"; 2002 nvidia,hssync-start-delay = <0>; 2003 nvidia,idle-wait-delay = <17>; 2004 nvidia,elastic-limit = <16>; 2005 nvidia,term-range-adj = <6>; 2006 nvidia,xcvr-setup = <9>; 2007 nvidia,xcvr-lsfslew = <0>; 2008 nvidia,xcvr-lsrslew = <3>; 2009 nvidia,hssquelch-level = <2>; 2010 nvidia,hsdiscon-level = <5>; 2011 nvidia,xcvr-hsslew = <12>; 2012 status = "disabled"; 2013 }; 2014 2015 cpus { 2016 #address-cells = <1>; 2017 #size-cells = <0>; 2018 2019 cpu@0 { 2020 device_type = "cpu"; 2021 compatible = "arm,cortex-a57"; 2022 reg = <0>; 2023 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 2024 <&tegra_car TEGRA210_CLK_PLL_X>, 2025 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 2026 <&dfll>; 2027 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 2028 clock-latency = <300000>; 2029 cpu-idle-states = <&CPU_SLEEP>; 2030 next-level-cache = <&L2>; 2031 }; 2032 2033 cpu@1 { 2034 device_type = "cpu"; 2035 compatible = "arm,cortex-a57"; 2036 reg = <1>; 2037 cpu-idle-states = <&CPU_SLEEP>; 2038 next-level-cache = <&L2>; 2039 }; 2040 2041 cpu@2 { 2042 device_type = "cpu"; 2043 compatible = "arm,cortex-a57"; 2044 reg = <2>; 2045 cpu-idle-states = <&CPU_SLEEP>; 2046 next-level-cache = <&L2>; 2047 }; 2048 2049 cpu@3 { 2050 device_type = "cpu"; 2051 compatible = "arm,cortex-a57"; 2052 reg = <3>; 2053 cpu-idle-states = <&CPU_SLEEP>; 2054 next-level-cache = <&L2>; 2055 }; 2056 2057 idle-states { 2058 entry-method = "psci"; 2059 2060 CPU_SLEEP: cpu-sleep { 2061 compatible = "arm,idle-state"; 2062 arm,psci-suspend-param = <0x40000007>; 2063 entry-latency-us = <100>; 2064 exit-latency-us = <30>; 2065 min-residency-us = <1000>; 2066 wakeup-latency-us = <130>; 2067 idle-state-name = "cpu-sleep"; 2068 status = "disabled"; 2069 }; 2070 }; 2071 2072 L2: l2-cache { 2073 compatible = "cache"; 2074 cache-level = <2>; 2075 cache-unified; 2076 }; 2077 }; 2078 2079 pmu { 2080 compatible = "arm,cortex-a57-pmu"; 2081 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2083 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2085 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 2086 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 2087 }; 2088 2089 sound { 2090 status = "disabled"; 2091 2092 clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2093 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2094 clock-names = "pll_a", "plla_out0"; 2095 2096 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2097 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>, 2098 <&tegra_car TEGRA210_CLK_EXTERN1>; 2099 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2100 assigned-clock-rates = <368640000>, <49152000>, <12288000>; 2101 }; 2102 2103 thermal-zones { 2104 cpu-thermal { 2105 polling-delay-passive = <1000>; 2106 polling-delay = <0>; 2107 2108 thermal-sensors = 2109 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 2110 2111 trips { 2112 cpu-shutdown-trip { 2113 temperature = <102500>; 2114 hysteresis = <0>; 2115 type = "critical"; 2116 }; 2117 2118 cpu_throttle_trip: throttle-trip { 2119 temperature = <98500>; 2120 hysteresis = <1000>; 2121 type = "hot"; 2122 }; 2123 }; 2124 2125 cooling-maps { 2126 map0 { 2127 trip = <&cpu_throttle_trip>; 2128 cooling-device = <&throttle_heavy 1 1>; 2129 }; 2130 }; 2131 }; 2132 2133 mem-thermal { 2134 polling-delay-passive = <0>; 2135 polling-delay = <0>; 2136 2137 thermal-sensors = 2138 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 2139 2140 trips { 2141 dram_nominal: mem-nominal-trip { 2142 temperature = <50000>; 2143 hysteresis = <1000>; 2144 type = "passive"; 2145 }; 2146 2147 dram_throttle: mem-throttle-trip { 2148 temperature = <70000>; 2149 hysteresis = <1000>; 2150 type = "active"; 2151 }; 2152 2153 mem-hot-trip { 2154 temperature = <100000>; 2155 hysteresis = <1000>; 2156 type = "hot"; 2157 }; 2158 2159 mem-shutdown-trip { 2160 temperature = <103000>; 2161 hysteresis = <0>; 2162 type = "critical"; 2163 }; 2164 }; 2165 2166 cooling-maps { 2167 dram-passive { 2168 cooling-device = <&emc 0 0>; 2169 trip = <&dram_nominal>; 2170 }; 2171 2172 dram-active { 2173 cooling-device = <&emc 1 1>; 2174 trip = <&dram_throttle>; 2175 }; 2176 }; 2177 }; 2178 2179 gpu-thermal { 2180 polling-delay-passive = <1000>; 2181 polling-delay = <0>; 2182 2183 thermal-sensors = 2184 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 2185 2186 trips { 2187 gpu-shutdown-trip { 2188 temperature = <103000>; 2189 hysteresis = <0>; 2190 type = "critical"; 2191 }; 2192 2193 gpu_throttle_trip: throttle-trip { 2194 temperature = <100000>; 2195 hysteresis = <1000>; 2196 type = "hot"; 2197 }; 2198 }; 2199 2200 cooling-maps { 2201 map0 { 2202 trip = <&gpu_throttle_trip>; 2203 cooling-device = <&throttle_heavy 1 1>; 2204 }; 2205 }; 2206 }; 2207 2208 pllx-thermal { 2209 polling-delay-passive = <0>; 2210 polling-delay = <0>; 2211 2212 thermal-sensors = 2213 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 2214 2215 trips { 2216 pllx-shutdown-trip { 2217 temperature = <103000>; 2218 hysteresis = <0>; 2219 type = "critical"; 2220 }; 2221 2222 pllx-throttle-trip { 2223 temperature = <100000>; 2224 hysteresis = <1000>; 2225 type = "hot"; 2226 }; 2227 }; 2228 2229 cooling-maps { 2230 /* 2231 * There are currently no cooling maps, 2232 * because there are no cooling devices. 2233 */ 2234 }; 2235 }; 2236 }; 2237 2238 timer { 2239 compatible = "arm,armv8-timer"; 2240 interrupts = <GIC_PPI 13 2241 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2242 <GIC_PPI 14 2243 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2244 <GIC_PPI 11 2245 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2246 <GIC_PPI 10 2247 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2248 interrupt-parent = <&gic>; 2249 arm,no-tick-in-suspend; 2250 }; 2251}; 2252