1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 26 27 apbmisc: misc@100000 { 28 compatible = "nvidia,tegra194-misc"; 29 reg = <0x0 0x00100000 0x0 0xf000>, 30 <0x0 0x0010f000 0x0 0x1000>; 31 }; 32 33 gpio: gpio@2200000 { 34 compatible = "nvidia,tegra194-gpio"; 35 reg-names = "security", "gpio"; 36 reg = <0x0 0x2200000 0x0 0x10000>, 37 <0x0 0x2210000 0x0 0x10000>; 38 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 86 #interrupt-cells = <2>; 87 interrupt-controller; 88 #gpio-cells = <2>; 89 gpio-controller; 90 gpio-ranges = <&pinmux 0 0 169>; 91 }; 92 93 cbb-noc@2300000 { 94 compatible = "nvidia,tegra194-cbb-noc"; 95 reg = <0x0 0x02300000 0x0 0x1000>; 96 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 98 nvidia,axi2apb = <&axi2apb>; 99 nvidia,apbmisc = <&apbmisc>; 100 }; 101 102 axi2apb: axi2apb@2390000 { 103 compatible = "nvidia,tegra194-axi2apb"; 104 reg = <0x0 0x2390000 0x0 0x1000>, 105 <0x0 0x23a0000 0x0 0x1000>, 106 <0x0 0x23b0000 0x0 0x1000>, 107 <0x0 0x23c0000 0x0 0x1000>, 108 <0x0 0x23d0000 0x0 0x1000>, 109 <0x0 0x23e0000 0x0 0x1000>; 110 }; 111 112 pinmux: pinmux@2430000 { 113 compatible = "nvidia,tegra194-pinmux"; 114 reg = <0x0 0x2430000 0x0 0x17000>; 115 116 pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir { 117 clkreq { 118 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 119 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 120 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 121 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 122 nvidia,tristate = <TEGRA_PIN_DISABLE>; 123 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 124 }; 125 }; 126 127 pex_rst_c5_out_state: pinmux-pex-rst-c5-out { 128 pex_rst { 129 nvidia,pins = "pex_l5_rst_n_pgg1"; 130 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 131 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 132 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 133 nvidia,tristate = <TEGRA_PIN_DISABLE>; 134 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 135 }; 136 }; 137 }; 138 139 ethernet@2490000 { 140 compatible = "nvidia,tegra194-eqos", 141 "nvidia,tegra186-eqos", 142 "snps,dwc-qos-ethernet-4.10"; 143 reg = <0x0 0x02490000 0x0 0x10000>; 144 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 146 <&bpmp TEGRA194_CLK_EQOS_AXI>, 147 <&bpmp TEGRA194_CLK_EQOS_RX>, 148 <&bpmp TEGRA194_CLK_EQOS_TX>, 149 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 150 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 151 resets = <&bpmp TEGRA194_RESET_EQOS>; 152 reset-names = "eqos"; 153 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 154 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 155 interconnect-names = "dma-mem", "write"; 156 iommus = <&smmu TEGRA194_SID_EQOS>; 157 status = "disabled"; 158 159 snps,write-requests = <1>; 160 snps,read-requests = <3>; 161 snps,burst-map = <0x7>; 162 snps,txpbl = <16>; 163 snps,rxpbl = <8>; 164 }; 165 166 gpcdma: dma-controller@2600000 { 167 compatible = "nvidia,tegra194-gpcdma", 168 "nvidia,tegra186-gpcdma"; 169 reg = <0x0 0x2600000 0x0 0x210000>; 170 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 171 reset-names = "gpcdma"; 172 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 204 #dma-cells = <1>; 205 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 206 dma-coherent; 207 dma-channel-mask = <0xfffffffe>; 208 }; 209 210 aconnect@2900000 { 211 compatible = "nvidia,tegra194-aconnect", 212 "nvidia,tegra210-aconnect"; 213 clocks = <&bpmp TEGRA194_CLK_APE>, 214 <&bpmp TEGRA194_CLK_APB2APE>; 215 clock-names = "ape", "apb2ape"; 216 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 217 status = "disabled"; 218 219 #address-cells = <2>; 220 #size-cells = <2>; 221 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 222 223 tegra_ahub: ahub@2900800 { 224 compatible = "nvidia,tegra194-ahub", 225 "nvidia,tegra186-ahub"; 226 reg = <0x0 0x02900800 0x0 0x800>; 227 clocks = <&bpmp TEGRA194_CLK_AHUB>; 228 clock-names = "ahub"; 229 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 230 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLP_OUT0>; 231 assigned-clock-rates = <81600000>; 232 status = "disabled"; 233 234 #address-cells = <2>; 235 #size-cells = <2>; 236 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 237 238 tegra_i2s1: i2s@2901000 { 239 compatible = "nvidia,tegra194-i2s", 240 "nvidia,tegra210-i2s"; 241 reg = <0x0 0x2901000 0x0 0x100>; 242 clocks = <&bpmp TEGRA194_CLK_I2S1>, 243 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 244 clock-names = "i2s", "sync_input"; 245 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 246 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 247 assigned-clock-rates = <1536000>; 248 sound-name-prefix = "I2S1"; 249 status = "disabled"; 250 }; 251 252 tegra_i2s2: i2s@2901100 { 253 compatible = "nvidia,tegra194-i2s", 254 "nvidia,tegra210-i2s"; 255 reg = <0x0 0x2901100 0x0 0x100>; 256 clocks = <&bpmp TEGRA194_CLK_I2S2>, 257 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 258 clock-names = "i2s", "sync_input"; 259 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 260 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 261 assigned-clock-rates = <1536000>; 262 sound-name-prefix = "I2S2"; 263 status = "disabled"; 264 }; 265 266 tegra_i2s3: i2s@2901200 { 267 compatible = "nvidia,tegra194-i2s", 268 "nvidia,tegra210-i2s"; 269 reg = <0x0 0x2901200 0x0 0x100>; 270 clocks = <&bpmp TEGRA194_CLK_I2S3>, 271 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 272 clock-names = "i2s", "sync_input"; 273 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 274 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 275 assigned-clock-rates = <1536000>; 276 sound-name-prefix = "I2S3"; 277 status = "disabled"; 278 }; 279 280 tegra_i2s4: i2s@2901300 { 281 compatible = "nvidia,tegra194-i2s", 282 "nvidia,tegra210-i2s"; 283 reg = <0x0 0x2901300 0x0 0x100>; 284 clocks = <&bpmp TEGRA194_CLK_I2S4>, 285 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 286 clock-names = "i2s", "sync_input"; 287 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 288 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 289 assigned-clock-rates = <1536000>; 290 sound-name-prefix = "I2S4"; 291 status = "disabled"; 292 }; 293 294 tegra_i2s5: i2s@2901400 { 295 compatible = "nvidia,tegra194-i2s", 296 "nvidia,tegra210-i2s"; 297 reg = <0x0 0x2901400 0x0 0x100>; 298 clocks = <&bpmp TEGRA194_CLK_I2S5>, 299 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 300 clock-names = "i2s", "sync_input"; 301 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 302 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 303 assigned-clock-rates = <1536000>; 304 sound-name-prefix = "I2S5"; 305 status = "disabled"; 306 }; 307 308 tegra_i2s6: i2s@2901500 { 309 compatible = "nvidia,tegra194-i2s", 310 "nvidia,tegra210-i2s"; 311 reg = <0x0 0x2901500 0x0 0x100>; 312 clocks = <&bpmp TEGRA194_CLK_I2S6>, 313 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 314 clock-names = "i2s", "sync_input"; 315 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 316 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 317 assigned-clock-rates = <1536000>; 318 sound-name-prefix = "I2S6"; 319 status = "disabled"; 320 }; 321 322 tegra_sfc1: sfc@2902000 { 323 compatible = "nvidia,tegra194-sfc", 324 "nvidia,tegra210-sfc"; 325 reg = <0x0 0x2902000 0x0 0x200>; 326 sound-name-prefix = "SFC1"; 327 status = "disabled"; 328 }; 329 330 tegra_sfc2: sfc@2902200 { 331 compatible = "nvidia,tegra194-sfc", 332 "nvidia,tegra210-sfc"; 333 reg = <0x0 0x2902200 0x0 0x200>; 334 sound-name-prefix = "SFC2"; 335 status = "disabled"; 336 }; 337 338 tegra_sfc3: sfc@2902400 { 339 compatible = "nvidia,tegra194-sfc", 340 "nvidia,tegra210-sfc"; 341 reg = <0x0 0x2902400 0x0 0x200>; 342 sound-name-prefix = "SFC3"; 343 status = "disabled"; 344 }; 345 346 tegra_sfc4: sfc@2902600 { 347 compatible = "nvidia,tegra194-sfc", 348 "nvidia,tegra210-sfc"; 349 reg = <0x0 0x2902600 0x0 0x200>; 350 sound-name-prefix = "SFC4"; 351 status = "disabled"; 352 }; 353 354 tegra_amx1: amx@2903000 { 355 compatible = "nvidia,tegra194-amx"; 356 reg = <0x0 0x2903000 0x0 0x100>; 357 sound-name-prefix = "AMX1"; 358 status = "disabled"; 359 }; 360 361 tegra_amx2: amx@2903100 { 362 compatible = "nvidia,tegra194-amx"; 363 reg = <0x0 0x2903100 0x0 0x100>; 364 sound-name-prefix = "AMX2"; 365 status = "disabled"; 366 }; 367 368 tegra_amx3: amx@2903200 { 369 compatible = "nvidia,tegra194-amx"; 370 reg = <0x0 0x2903200 0x0 0x100>; 371 sound-name-prefix = "AMX3"; 372 status = "disabled"; 373 }; 374 375 tegra_amx4: amx@2903300 { 376 compatible = "nvidia,tegra194-amx"; 377 reg = <0x0 0x2903300 0x0 0x100>; 378 sound-name-prefix = "AMX4"; 379 status = "disabled"; 380 }; 381 382 tegra_adx1: adx@2903800 { 383 compatible = "nvidia,tegra194-adx", 384 "nvidia,tegra210-adx"; 385 reg = <0x0 0x2903800 0x0 0x100>; 386 sound-name-prefix = "ADX1"; 387 status = "disabled"; 388 }; 389 390 tegra_adx2: adx@2903900 { 391 compatible = "nvidia,tegra194-adx", 392 "nvidia,tegra210-adx"; 393 reg = <0x0 0x2903900 0x0 0x100>; 394 sound-name-prefix = "ADX2"; 395 status = "disabled"; 396 }; 397 398 tegra_adx3: adx@2903a00 { 399 compatible = "nvidia,tegra194-adx", 400 "nvidia,tegra210-adx"; 401 reg = <0x0 0x2903a00 0x0 0x100>; 402 sound-name-prefix = "ADX3"; 403 status = "disabled"; 404 }; 405 406 tegra_adx4: adx@2903b00 { 407 compatible = "nvidia,tegra194-adx", 408 "nvidia,tegra210-adx"; 409 reg = <0x0 0x2903b00 0x0 0x100>; 410 sound-name-prefix = "ADX4"; 411 status = "disabled"; 412 }; 413 414 tegra_dmic1: dmic@2904000 { 415 compatible = "nvidia,tegra194-dmic", 416 "nvidia,tegra210-dmic"; 417 reg = <0x0 0x2904000 0x0 0x100>; 418 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 419 clock-names = "dmic"; 420 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 421 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 422 assigned-clock-rates = <3072000>; 423 sound-name-prefix = "DMIC1"; 424 status = "disabled"; 425 }; 426 427 tegra_dmic2: dmic@2904100 { 428 compatible = "nvidia,tegra194-dmic", 429 "nvidia,tegra210-dmic"; 430 reg = <0x0 0x2904100 0x0 0x100>; 431 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 432 clock-names = "dmic"; 433 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 434 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 435 assigned-clock-rates = <3072000>; 436 sound-name-prefix = "DMIC2"; 437 status = "disabled"; 438 }; 439 440 tegra_dmic3: dmic@2904200 { 441 compatible = "nvidia,tegra194-dmic", 442 "nvidia,tegra210-dmic"; 443 reg = <0x0 0x2904200 0x0 0x100>; 444 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 445 clock-names = "dmic"; 446 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 447 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 448 assigned-clock-rates = <3072000>; 449 sound-name-prefix = "DMIC3"; 450 status = "disabled"; 451 }; 452 453 tegra_dmic4: dmic@2904300 { 454 compatible = "nvidia,tegra194-dmic", 455 "nvidia,tegra210-dmic"; 456 reg = <0x0 0x2904300 0x0 0x100>; 457 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 458 clock-names = "dmic"; 459 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 460 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 461 assigned-clock-rates = <3072000>; 462 sound-name-prefix = "DMIC4"; 463 status = "disabled"; 464 }; 465 466 tegra_dspk1: dspk@2905000 { 467 compatible = "nvidia,tegra194-dspk", 468 "nvidia,tegra186-dspk"; 469 reg = <0x0 0x2905000 0x0 0x100>; 470 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 471 clock-names = "dspk"; 472 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 473 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 474 assigned-clock-rates = <12288000>; 475 sound-name-prefix = "DSPK1"; 476 status = "disabled"; 477 }; 478 479 tegra_dspk2: dspk@2905100 { 480 compatible = "nvidia,tegra194-dspk", 481 "nvidia,tegra186-dspk"; 482 reg = <0x0 0x2905100 0x0 0x100>; 483 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 484 clock-names = "dspk"; 485 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 486 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 487 assigned-clock-rates = <12288000>; 488 sound-name-prefix = "DSPK2"; 489 status = "disabled"; 490 }; 491 492 tegra_ope1: processing-engine@2908000 { 493 compatible = "nvidia,tegra194-ope", 494 "nvidia,tegra210-ope"; 495 reg = <0x0 0x2908000 0x0 0x100>; 496 sound-name-prefix = "OPE1"; 497 status = "disabled"; 498 499 #address-cells = <2>; 500 #size-cells = <2>; 501 ranges; 502 503 equalizer@2908100 { 504 compatible = "nvidia,tegra194-peq", 505 "nvidia,tegra210-peq"; 506 reg = <0x0 0x2908100 0x0 0x100>; 507 }; 508 509 dynamic-range-compressor@2908200 { 510 compatible = "nvidia,tegra194-mbdrc", 511 "nvidia,tegra210-mbdrc"; 512 reg = <0x0 0x2908200 0x0 0x200>; 513 }; 514 }; 515 516 tegra_mvc1: mvc@290a000 { 517 compatible = "nvidia,tegra194-mvc", 518 "nvidia,tegra210-mvc"; 519 reg = <0x0 0x290a000 0x0 0x200>; 520 sound-name-prefix = "MVC1"; 521 status = "disabled"; 522 }; 523 524 tegra_mvc2: mvc@290a200 { 525 compatible = "nvidia,tegra194-mvc", 526 "nvidia,tegra210-mvc"; 527 reg = <0x0 0x290a200 0x0 0x200>; 528 sound-name-prefix = "MVC2"; 529 status = "disabled"; 530 }; 531 532 tegra_amixer: amixer@290bb00 { 533 compatible = "nvidia,tegra194-amixer", 534 "nvidia,tegra210-amixer"; 535 reg = <0x0 0x290bb00 0x0 0x800>; 536 sound-name-prefix = "MIXER1"; 537 status = "disabled"; 538 }; 539 540 tegra_admaif: admaif@290f000 { 541 compatible = "nvidia,tegra194-admaif", 542 "nvidia,tegra186-admaif"; 543 reg = <0x0 0x0290f000 0x0 0x1000>; 544 dmas = <&adma 1>, <&adma 1>, 545 <&adma 2>, <&adma 2>, 546 <&adma 3>, <&adma 3>, 547 <&adma 4>, <&adma 4>, 548 <&adma 5>, <&adma 5>, 549 <&adma 6>, <&adma 6>, 550 <&adma 7>, <&adma 7>, 551 <&adma 8>, <&adma 8>, 552 <&adma 9>, <&adma 9>, 553 <&adma 10>, <&adma 10>, 554 <&adma 11>, <&adma 11>, 555 <&adma 12>, <&adma 12>, 556 <&adma 13>, <&adma 13>, 557 <&adma 14>, <&adma 14>, 558 <&adma 15>, <&adma 15>, 559 <&adma 16>, <&adma 16>, 560 <&adma 17>, <&adma 17>, 561 <&adma 18>, <&adma 18>, 562 <&adma 19>, <&adma 19>, 563 <&adma 20>, <&adma 20>; 564 dma-names = "rx1", "tx1", 565 "rx2", "tx2", 566 "rx3", "tx3", 567 "rx4", "tx4", 568 "rx5", "tx5", 569 "rx6", "tx6", 570 "rx7", "tx7", 571 "rx8", "tx8", 572 "rx9", "tx9", 573 "rx10", "tx10", 574 "rx11", "tx11", 575 "rx12", "tx12", 576 "rx13", "tx13", 577 "rx14", "tx14", 578 "rx15", "tx15", 579 "rx16", "tx16", 580 "rx17", "tx17", 581 "rx18", "tx18", 582 "rx19", "tx19", 583 "rx20", "tx20"; 584 status = "disabled"; 585 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 586 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 587 interconnect-names = "dma-mem", "write"; 588 iommus = <&smmu TEGRA194_SID_APE>; 589 }; 590 591 tegra_asrc: asrc@2910000 { 592 compatible = "nvidia,tegra194-asrc", 593 "nvidia,tegra186-asrc"; 594 reg = <0x0 0x2910000 0x0 0x2000>; 595 sound-name-prefix = "ASRC1"; 596 status = "disabled"; 597 }; 598 }; 599 600 adma: dma-controller@2930000 { 601 compatible = "nvidia,tegra194-adma", 602 "nvidia,tegra186-adma"; 603 reg = <0x0 0x02930000 0x0 0x20000>; 604 interrupt-parent = <&agic>; 605 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 637 #dma-cells = <1>; 638 clocks = <&bpmp TEGRA194_CLK_AHUB>; 639 clock-names = "d_audio"; 640 status = "disabled"; 641 }; 642 643 agic: interrupt-controller@2a40000 { 644 compatible = "nvidia,tegra194-agic", 645 "nvidia,tegra210-agic"; 646 #interrupt-cells = <3>; 647 interrupt-controller; 648 reg = <0x0 0x02a41000 0x0 0x1000>, 649 <0x0 0x02a42000 0x0 0x2000>; 650 interrupts = <GIC_SPI 145 651 (GIC_CPU_MASK_SIMPLE(4) | 652 IRQ_TYPE_LEVEL_HIGH)>; 653 clocks = <&bpmp TEGRA194_CLK_APE>; 654 clock-names = "clk"; 655 status = "disabled"; 656 }; 657 }; 658 659 mc: memory-controller@2c00000 { 660 compatible = "nvidia,tegra194-mc"; 661 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 662 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 663 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 664 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 665 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 666 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 667 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 668 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 669 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 670 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 671 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 672 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 673 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 674 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 675 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 676 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 677 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 678 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 679 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 680 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 681 "ch11", "ch12", "ch13", "ch14", "ch15"; 682 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 683 #interconnect-cells = <1>; 684 status = "disabled"; 685 686 #address-cells = <2>; 687 #size-cells = <2>; 688 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 689 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 690 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 691 692 /* 693 * Bit 39 of addresses passing through the memory 694 * controller selects the XBAR format used when memory 695 * is accessed. This is used to transparently access 696 * memory in the XBAR format used by the discrete GPU 697 * (bit 39 set) or Tegra (bit 39 clear). 698 * 699 * As a consequence, the operating system must ensure 700 * that bit 39 is never used implicitly, for example 701 * via an I/O virtual address mapping of an IOMMU. If 702 * devices require access to the XBAR switch, their 703 * drivers must set this bit explicitly. 704 * 705 * Limit the DMA range for memory clients to [38:0]. 706 */ 707 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 708 709 emc: external-memory-controller@2c60000 { 710 compatible = "nvidia,tegra194-emc"; 711 reg = <0x0 0x02c60000 0x0 0x90000>, 712 <0x0 0x01780000 0x0 0x80000>; 713 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&bpmp TEGRA194_CLK_EMC>; 715 clock-names = "emc"; 716 717 #interconnect-cells = <0>; 718 719 nvidia,bpmp = <&bpmp>; 720 }; 721 }; 722 723 timer@3010000 { 724 compatible = "nvidia,tegra186-timer"; 725 reg = <0x0 0x03010000 0x0 0x000e0000>; 726 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 736 }; 737 738 uarta: serial@3100000 { 739 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 740 reg = <0x0 0x03100000 0x0 0x40>; 741 reg-shift = <2>; 742 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&bpmp TEGRA194_CLK_UARTA>; 744 resets = <&bpmp TEGRA194_RESET_UARTA>; 745 dmas = <&gpcdma 8>, <&gpcdma 8>; 746 dma-names = "rx", "tx"; 747 status = "disabled"; 748 }; 749 750 uartb: serial@3110000 { 751 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 752 reg = <0x0 0x03110000 0x0 0x40>; 753 reg-shift = <2>; 754 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&bpmp TEGRA194_CLK_UARTB>; 756 resets = <&bpmp TEGRA194_RESET_UARTB>; 757 dmas = <&gpcdma 9>, <&gpcdma 9>; 758 dma-names = "rx", "tx"; 759 status = "disabled"; 760 }; 761 762 uartd: serial@3130000 { 763 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 764 reg = <0x0 0x03130000 0x0 0x40>; 765 reg-shift = <2>; 766 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&bpmp TEGRA194_CLK_UARTD>; 768 resets = <&bpmp TEGRA194_RESET_UARTD>; 769 dmas = <&gpcdma 19>, <&gpcdma 19>; 770 dma-names = "rx", "tx"; 771 status = "disabled"; 772 }; 773 774 uarte: serial@3140000 { 775 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 776 reg = <0x0 0x03140000 0x0 0x40>; 777 reg-shift = <2>; 778 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&bpmp TEGRA194_CLK_UARTE>; 780 resets = <&bpmp TEGRA194_RESET_UARTE>; 781 dmas = <&gpcdma 20>, <&gpcdma 20>; 782 dma-names = "rx", "tx"; 783 status = "disabled"; 784 }; 785 786 uartf: serial@3150000 { 787 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 788 reg = <0x0 0x03150000 0x0 0x40>; 789 reg-shift = <2>; 790 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&bpmp TEGRA194_CLK_UARTF>; 792 resets = <&bpmp TEGRA194_RESET_UARTF>; 793 dmas = <&gpcdma 12>, <&gpcdma 12>; 794 dma-names = "rx", "tx"; 795 status = "disabled"; 796 }; 797 798 gen1_i2c: i2c@3160000 { 799 compatible = "nvidia,tegra194-i2c"; 800 reg = <0x0 0x03160000 0x0 0x10000>; 801 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 clocks = <&bpmp TEGRA194_CLK_I2C1>; 805 clock-names = "div-clk"; 806 resets = <&bpmp TEGRA194_RESET_I2C1>; 807 reset-names = "i2c"; 808 dmas = <&gpcdma 21>, <&gpcdma 21>; 809 dma-names = "rx", "tx"; 810 status = "disabled"; 811 }; 812 813 uarth: serial@3170000 { 814 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 815 reg = <0x0 0x03170000 0x0 0x40>; 816 reg-shift = <2>; 817 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&bpmp TEGRA194_CLK_UARTH>; 819 resets = <&bpmp TEGRA194_RESET_UARTH>; 820 dmas = <&gpcdma 13>, <&gpcdma 13>; 821 dma-names = "rx", "tx"; 822 status = "disabled"; 823 }; 824 825 cam_i2c: i2c@3180000 { 826 compatible = "nvidia,tegra194-i2c"; 827 reg = <0x0 0x03180000 0x0 0x10000>; 828 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 clocks = <&bpmp TEGRA194_CLK_I2C3>; 832 clock-names = "div-clk"; 833 resets = <&bpmp TEGRA194_RESET_I2C3>; 834 reset-names = "i2c"; 835 dmas = <&gpcdma 23>, <&gpcdma 23>; 836 dma-names = "rx", "tx"; 837 status = "disabled"; 838 }; 839 840 /* shares pads with dpaux1 */ 841 dp_aux_ch1_i2c: i2c@3190000 { 842 compatible = "nvidia,tegra194-i2c"; 843 reg = <0x0 0x03190000 0x0 0x10000>; 844 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 clocks = <&bpmp TEGRA194_CLK_I2C4>; 848 clock-names = "div-clk"; 849 resets = <&bpmp TEGRA194_RESET_I2C4>; 850 reset-names = "i2c"; 851 pinctrl-0 = <&state_dpaux1_i2c>; 852 pinctrl-1 = <&state_dpaux1_off>; 853 pinctrl-names = "default", "idle"; 854 dmas = <&gpcdma 26>, <&gpcdma 26>; 855 dma-names = "rx", "tx"; 856 status = "disabled"; 857 }; 858 859 /* shares pads with dpaux0 */ 860 dp_aux_ch0_i2c: i2c@31b0000 { 861 compatible = "nvidia,tegra194-i2c"; 862 reg = <0x0 0x031b0000 0x0 0x10000>; 863 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 clocks = <&bpmp TEGRA194_CLK_I2C6>; 867 clock-names = "div-clk"; 868 resets = <&bpmp TEGRA194_RESET_I2C6>; 869 reset-names = "i2c"; 870 pinctrl-0 = <&state_dpaux0_i2c>; 871 pinctrl-1 = <&state_dpaux0_off>; 872 pinctrl-names = "default", "idle"; 873 dmas = <&gpcdma 30>, <&gpcdma 30>; 874 dma-names = "rx", "tx"; 875 status = "disabled"; 876 }; 877 878 /* shares pads with dpaux2 */ 879 dp_aux_ch2_i2c: i2c@31c0000 { 880 compatible = "nvidia,tegra194-i2c"; 881 reg = <0x0 0x031c0000 0x0 0x10000>; 882 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 883 #address-cells = <1>; 884 #size-cells = <0>; 885 clocks = <&bpmp TEGRA194_CLK_I2C7>; 886 clock-names = "div-clk"; 887 resets = <&bpmp TEGRA194_RESET_I2C7>; 888 reset-names = "i2c"; 889 pinctrl-0 = <&state_dpaux2_i2c>; 890 pinctrl-1 = <&state_dpaux2_off>; 891 pinctrl-names = "default", "idle"; 892 dmas = <&gpcdma 27>, <&gpcdma 27>; 893 dma-names = "rx", "tx"; 894 status = "disabled"; 895 }; 896 897 /* shares pads with dpaux3 */ 898 dp_aux_ch3_i2c: i2c@31e0000 { 899 compatible = "nvidia,tegra194-i2c"; 900 reg = <0x0 0x031e0000 0x0 0x10000>; 901 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 clocks = <&bpmp TEGRA194_CLK_I2C9>; 905 clock-names = "div-clk"; 906 resets = <&bpmp TEGRA194_RESET_I2C9>; 907 reset-names = "i2c"; 908 pinctrl-0 = <&state_dpaux3_i2c>; 909 pinctrl-1 = <&state_dpaux3_off>; 910 pinctrl-names = "default", "idle"; 911 dmas = <&gpcdma 31>, <&gpcdma 31>; 912 dma-names = "rx", "tx"; 913 status = "disabled"; 914 }; 915 916 spi@3270000 { 917 compatible = "nvidia,tegra194-qspi"; 918 reg = <0x0 0x3270000 0x0 0x1000>; 919 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 923 <&bpmp TEGRA194_CLK_QSPI0_PM>; 924 clock-names = "qspi", "qspi_out"; 925 resets = <&bpmp TEGRA194_RESET_QSPI0>; 926 status = "disabled"; 927 }; 928 929 pwm1: pwm@3280000 { 930 compatible = "nvidia,tegra194-pwm", 931 "nvidia,tegra186-pwm"; 932 reg = <0x0 0x3280000 0x0 0x10000>; 933 clocks = <&bpmp TEGRA194_CLK_PWM1>; 934 resets = <&bpmp TEGRA194_RESET_PWM1>; 935 reset-names = "pwm"; 936 status = "disabled"; 937 #pwm-cells = <2>; 938 }; 939 940 pwm2: pwm@3290000 { 941 compatible = "nvidia,tegra194-pwm", 942 "nvidia,tegra186-pwm"; 943 reg = <0x0 0x3290000 0x0 0x10000>; 944 clocks = <&bpmp TEGRA194_CLK_PWM2>; 945 resets = <&bpmp TEGRA194_RESET_PWM2>; 946 reset-names = "pwm"; 947 status = "disabled"; 948 #pwm-cells = <2>; 949 }; 950 951 pwm3: pwm@32a0000 { 952 compatible = "nvidia,tegra194-pwm", 953 "nvidia,tegra186-pwm"; 954 reg = <0x0 0x32a0000 0x0 0x10000>; 955 clocks = <&bpmp TEGRA194_CLK_PWM3>; 956 resets = <&bpmp TEGRA194_RESET_PWM3>; 957 reset-names = "pwm"; 958 status = "disabled"; 959 #pwm-cells = <2>; 960 }; 961 962 pwm5: pwm@32c0000 { 963 compatible = "nvidia,tegra194-pwm", 964 "nvidia,tegra186-pwm"; 965 reg = <0x0 0x32c0000 0x0 0x10000>; 966 clocks = <&bpmp TEGRA194_CLK_PWM5>; 967 resets = <&bpmp TEGRA194_RESET_PWM5>; 968 reset-names = "pwm"; 969 status = "disabled"; 970 #pwm-cells = <2>; 971 }; 972 973 pwm6: pwm@32d0000 { 974 compatible = "nvidia,tegra194-pwm", 975 "nvidia,tegra186-pwm"; 976 reg = <0x0 0x32d0000 0x0 0x10000>; 977 clocks = <&bpmp TEGRA194_CLK_PWM6>; 978 resets = <&bpmp TEGRA194_RESET_PWM6>; 979 reset-names = "pwm"; 980 status = "disabled"; 981 #pwm-cells = <2>; 982 }; 983 984 pwm7: pwm@32e0000 { 985 compatible = "nvidia,tegra194-pwm", 986 "nvidia,tegra186-pwm"; 987 reg = <0x0 0x32e0000 0x0 0x10000>; 988 clocks = <&bpmp TEGRA194_CLK_PWM7>; 989 resets = <&bpmp TEGRA194_RESET_PWM7>; 990 reset-names = "pwm"; 991 status = "disabled"; 992 #pwm-cells = <2>; 993 }; 994 995 pwm8: pwm@32f0000 { 996 compatible = "nvidia,tegra194-pwm", 997 "nvidia,tegra186-pwm"; 998 reg = <0x0 0x32f0000 0x0 0x10000>; 999 clocks = <&bpmp TEGRA194_CLK_PWM8>; 1000 resets = <&bpmp TEGRA194_RESET_PWM8>; 1001 reset-names = "pwm"; 1002 status = "disabled"; 1003 #pwm-cells = <2>; 1004 }; 1005 1006 spi@3300000 { 1007 compatible = "nvidia,tegra194-qspi"; 1008 reg = <0x0 0x3300000 0x0 0x1000>; 1009 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 1013 <&bpmp TEGRA194_CLK_QSPI1_PM>; 1014 clock-names = "qspi", "qspi_out"; 1015 resets = <&bpmp TEGRA194_RESET_QSPI1>; 1016 status = "disabled"; 1017 }; 1018 1019 sdmmc1: mmc@3400000 { 1020 compatible = "nvidia,tegra194-sdhci"; 1021 reg = <0x0 0x03400000 0x0 0x10000>; 1022 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1024 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1025 clock-names = "sdhci", "tmclk"; 1026 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1027 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1028 assigned-clock-parents = 1029 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1030 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1031 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 1032 reset-names = "sdhci"; 1033 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1034 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1035 interconnect-names = "dma-mem", "write"; 1036 iommus = <&smmu TEGRA194_SID_SDMMC1>; 1037 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1038 pinctrl-0 = <&sdmmc1_3v3>; 1039 pinctrl-1 = <&sdmmc1_1v8>; 1040 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 1041 <0x07>; 1042 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1043 <0x07>; 1044 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1045 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1046 <0x07>; 1047 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1048 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1049 nvidia,default-tap = <0x9>; 1050 nvidia,default-trim = <0x5>; 1051 sd-uhs-sdr25; 1052 sd-uhs-sdr50; 1053 sd-uhs-ddr50; 1054 sd-uhs-sdr104; 1055 status = "disabled"; 1056 }; 1057 1058 sdmmc3: mmc@3440000 { 1059 compatible = "nvidia,tegra194-sdhci"; 1060 reg = <0x0 0x03440000 0x0 0x10000>; 1061 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1063 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1064 clock-names = "sdhci", "tmclk"; 1065 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1066 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1067 assigned-clock-parents = 1068 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1069 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1070 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 1071 reset-names = "sdhci"; 1072 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1073 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1074 interconnect-names = "dma-mem", "write"; 1075 iommus = <&smmu TEGRA194_SID_SDMMC3>; 1076 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1077 pinctrl-0 = <&sdmmc3_3v3>; 1078 pinctrl-1 = <&sdmmc3_1v8>; 1079 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 1080 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1081 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1082 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1083 <0x07>; 1084 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1085 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1086 <0x07>; 1087 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1088 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1089 nvidia,default-tap = <0x9>; 1090 nvidia,default-trim = <0x5>; 1091 sd-uhs-sdr25; 1092 sd-uhs-sdr50; 1093 sd-uhs-ddr50; 1094 sd-uhs-sdr104; 1095 status = "disabled"; 1096 }; 1097 1098 sdmmc4: mmc@3460000 { 1099 compatible = "nvidia,tegra194-sdhci"; 1100 reg = <0x0 0x03460000 0x0 0x10000>; 1101 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1102 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1103 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1104 clock-names = "sdhci", "tmclk"; 1105 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1106 <&bpmp TEGRA194_CLK_PLLC4>; 1107 assigned-clock-parents = 1108 <&bpmp TEGRA194_CLK_PLLC4>; 1109 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1110 reset-names = "sdhci"; 1111 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1112 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1113 interconnect-names = "dma-mem", "write"; 1114 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1115 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1116 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1117 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1118 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1119 <0x0a>; 1120 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1121 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1122 <0x0a>; 1123 nvidia,default-tap = <0x8>; 1124 nvidia,default-trim = <0x14>; 1125 nvidia,dqs-trim = <40>; 1126 cap-mmc-highspeed; 1127 mmc-ddr-1_8v; 1128 mmc-hs200-1_8v; 1129 mmc-hs400-1_8v; 1130 mmc-hs400-enhanced-strobe; 1131 supports-cqe; 1132 status = "disabled"; 1133 }; 1134 1135 hda@3510000 { 1136 compatible = "nvidia,tegra194-hda"; 1137 reg = <0x0 0x3510000 0x0 0x10000>; 1138 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1139 clocks = <&bpmp TEGRA194_CLK_HDA>, 1140 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1141 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1142 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1143 resets = <&bpmp TEGRA194_RESET_HDA>, 1144 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1145 reset-names = "hda", "hda2hdmi"; 1146 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1147 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1148 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1149 interconnect-names = "dma-mem", "write"; 1150 iommus = <&smmu TEGRA194_SID_HDA>; 1151 status = "disabled"; 1152 }; 1153 1154 xusb_padctl: padctl@3520000 { 1155 compatible = "nvidia,tegra194-xusb-padctl"; 1156 reg = <0x0 0x03520000 0x0 0x1000>, 1157 <0x0 0x03540000 0x0 0x1000>; 1158 reg-names = "padctl", "ao"; 1159 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1160 1161 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1162 reset-names = "padctl"; 1163 1164 status = "disabled"; 1165 1166 pads { 1167 usb2 { 1168 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1169 clock-names = "trk"; 1170 1171 lanes { 1172 usb2-0 { 1173 nvidia,function = "xusb"; 1174 status = "disabled"; 1175 #phy-cells = <0>; 1176 }; 1177 1178 usb2-1 { 1179 nvidia,function = "xusb"; 1180 status = "disabled"; 1181 #phy-cells = <0>; 1182 }; 1183 1184 usb2-2 { 1185 nvidia,function = "xusb"; 1186 status = "disabled"; 1187 #phy-cells = <0>; 1188 }; 1189 1190 usb2-3 { 1191 nvidia,function = "xusb"; 1192 status = "disabled"; 1193 #phy-cells = <0>; 1194 }; 1195 }; 1196 }; 1197 1198 usb3 { 1199 lanes { 1200 usb3-0 { 1201 nvidia,function = "xusb"; 1202 status = "disabled"; 1203 #phy-cells = <0>; 1204 }; 1205 1206 usb3-1 { 1207 nvidia,function = "xusb"; 1208 status = "disabled"; 1209 #phy-cells = <0>; 1210 }; 1211 1212 usb3-2 { 1213 nvidia,function = "xusb"; 1214 status = "disabled"; 1215 #phy-cells = <0>; 1216 }; 1217 1218 usb3-3 { 1219 nvidia,function = "xusb"; 1220 status = "disabled"; 1221 #phy-cells = <0>; 1222 }; 1223 }; 1224 }; 1225 }; 1226 1227 ports { 1228 usb2-0 { 1229 status = "disabled"; 1230 }; 1231 1232 usb2-1 { 1233 status = "disabled"; 1234 }; 1235 1236 usb2-2 { 1237 status = "disabled"; 1238 }; 1239 1240 usb2-3 { 1241 status = "disabled"; 1242 }; 1243 1244 usb3-0 { 1245 status = "disabled"; 1246 }; 1247 1248 usb3-1 { 1249 status = "disabled"; 1250 }; 1251 1252 usb3-2 { 1253 status = "disabled"; 1254 }; 1255 1256 usb3-3 { 1257 status = "disabled"; 1258 }; 1259 }; 1260 }; 1261 1262 usb@3550000 { 1263 compatible = "nvidia,tegra194-xudc"; 1264 reg = <0x0 0x03550000 0x0 0x8000>, 1265 <0x0 0x03558000 0x0 0x1000>; 1266 reg-names = "base", "fpci"; 1267 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1268 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1269 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1270 <&bpmp TEGRA194_CLK_XUSB_SS>, 1271 <&bpmp TEGRA194_CLK_XUSB_FS>; 1272 clock-names = "dev", "ss", "ss_src", "fs_src"; 1273 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1274 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1275 interconnect-names = "dma-mem", "write"; 1276 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1277 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1278 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1279 power-domain-names = "dev", "ss"; 1280 nvidia,xusb-padctl = <&xusb_padctl>; 1281 dma-coherent; 1282 status = "disabled"; 1283 }; 1284 1285 usb@3610000 { 1286 compatible = "nvidia,tegra194-xusb"; 1287 reg = <0x0 0x03610000 0x0 0x40000>, 1288 <0x0 0x03600000 0x0 0x10000>; 1289 reg-names = "hcd", "fpci"; 1290 1291 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1293 1294 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1295 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1296 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1297 <&bpmp TEGRA194_CLK_XUSB_SS>, 1298 <&bpmp TEGRA194_CLK_CLK_M>, 1299 <&bpmp TEGRA194_CLK_XUSB_FS>, 1300 <&bpmp TEGRA194_CLK_UTMIPLL>, 1301 <&bpmp TEGRA194_CLK_CLK_M>, 1302 <&bpmp TEGRA194_CLK_PLLE>; 1303 clock-names = "xusb_host", "xusb_falcon_src", 1304 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1305 "xusb_fs_src", "pll_u_480m", "clk_m", 1306 "pll_e"; 1307 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1308 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1309 interconnect-names = "dma-mem", "write"; 1310 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1311 1312 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1313 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1314 power-domain-names = "xusb_host", "xusb_ss"; 1315 1316 nvidia,xusb-padctl = <&xusb_padctl>; 1317 status = "disabled"; 1318 }; 1319 1320 fuse@3820000 { 1321 compatible = "nvidia,tegra194-efuse"; 1322 reg = <0x0 0x03820000 0x0 0x10000>; 1323 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1324 clock-names = "fuse"; 1325 }; 1326 1327 gic: interrupt-controller@3881000 { 1328 compatible = "arm,gic-400"; 1329 #address-cells = <0>; 1330 #interrupt-cells = <3>; 1331 interrupt-controller; 1332 reg = <0x0 0x03881000 0x0 0x1000>, 1333 <0x0 0x03882000 0x0 0x2000>, 1334 <0x0 0x03884000 0x0 0x2000>, 1335 <0x0 0x03886000 0x0 0x2000>; 1336 interrupts = <GIC_PPI 9 1337 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1338 interrupt-parent = <&gic>; 1339 }; 1340 1341 cec@3960000 { 1342 compatible = "nvidia,tegra194-cec", "nvidia,tegra210-cec"; 1343 reg = <0x0 0x03960000 0x0 0x10000>; 1344 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1345 clocks = <&bpmp TEGRA194_CLK_CEC>; 1346 clock-names = "cec"; 1347 status = "disabled"; 1348 }; 1349 1350 hte_lic: hardware-timestamp@3aa0000 { 1351 compatible = "nvidia,tegra194-gte-lic"; 1352 reg = <0x0 0x3aa0000 0x0 0x10000>; 1353 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1354 nvidia,int-threshold = <1>; 1355 nvidia,slices = <11>; 1356 #timestamp-cells = <1>; 1357 }; 1358 1359 hsp_top0: hsp@3c00000 { 1360 compatible = "nvidia,tegra194-hsp"; 1361 reg = <0x0 0x03c00000 0x0 0xa0000>; 1362 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1371 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1372 "shared3", "shared4", "shared5", "shared6", 1373 "shared7"; 1374 #mbox-cells = <2>; 1375 }; 1376 1377 p2u_hsio_0: phy@3e10000 { 1378 compatible = "nvidia,tegra194-p2u"; 1379 reg = <0x0 0x03e10000 0x0 0x10000>; 1380 reg-names = "ctl"; 1381 1382 #phy-cells = <0>; 1383 }; 1384 1385 p2u_hsio_1: phy@3e20000 { 1386 compatible = "nvidia,tegra194-p2u"; 1387 reg = <0x0 0x03e20000 0x0 0x10000>; 1388 reg-names = "ctl"; 1389 1390 #phy-cells = <0>; 1391 }; 1392 1393 p2u_hsio_2: phy@3e30000 { 1394 compatible = "nvidia,tegra194-p2u"; 1395 reg = <0x0 0x03e30000 0x0 0x10000>; 1396 reg-names = "ctl"; 1397 1398 #phy-cells = <0>; 1399 }; 1400 1401 p2u_hsio_3: phy@3e40000 { 1402 compatible = "nvidia,tegra194-p2u"; 1403 reg = <0x0 0x03e40000 0x0 0x10000>; 1404 reg-names = "ctl"; 1405 1406 #phy-cells = <0>; 1407 }; 1408 1409 p2u_hsio_4: phy@3e50000 { 1410 compatible = "nvidia,tegra194-p2u"; 1411 reg = <0x0 0x03e50000 0x0 0x10000>; 1412 reg-names = "ctl"; 1413 1414 #phy-cells = <0>; 1415 }; 1416 1417 p2u_hsio_5: phy@3e60000 { 1418 compatible = "nvidia,tegra194-p2u"; 1419 reg = <0x0 0x03e60000 0x0 0x10000>; 1420 reg-names = "ctl"; 1421 1422 #phy-cells = <0>; 1423 }; 1424 1425 p2u_hsio_6: phy@3e70000 { 1426 compatible = "nvidia,tegra194-p2u"; 1427 reg = <0x0 0x03e70000 0x0 0x10000>; 1428 reg-names = "ctl"; 1429 1430 #phy-cells = <0>; 1431 }; 1432 1433 p2u_hsio_7: phy@3e80000 { 1434 compatible = "nvidia,tegra194-p2u"; 1435 reg = <0x0 0x03e80000 0x0 0x10000>; 1436 reg-names = "ctl"; 1437 1438 #phy-cells = <0>; 1439 }; 1440 1441 p2u_hsio_8: phy@3e90000 { 1442 compatible = "nvidia,tegra194-p2u"; 1443 reg = <0x0 0x03e90000 0x0 0x10000>; 1444 reg-names = "ctl"; 1445 1446 #phy-cells = <0>; 1447 }; 1448 1449 p2u_hsio_9: phy@3ea0000 { 1450 compatible = "nvidia,tegra194-p2u"; 1451 reg = <0x0 0x03ea0000 0x0 0x10000>; 1452 reg-names = "ctl"; 1453 1454 #phy-cells = <0>; 1455 }; 1456 1457 p2u_nvhs_0: phy@3eb0000 { 1458 compatible = "nvidia,tegra194-p2u"; 1459 reg = <0x0 0x03eb0000 0x0 0x10000>; 1460 reg-names = "ctl"; 1461 1462 #phy-cells = <0>; 1463 }; 1464 1465 p2u_nvhs_1: phy@3ec0000 { 1466 compatible = "nvidia,tegra194-p2u"; 1467 reg = <0x0 0x03ec0000 0x0 0x10000>; 1468 reg-names = "ctl"; 1469 1470 #phy-cells = <0>; 1471 }; 1472 1473 p2u_nvhs_2: phy@3ed0000 { 1474 compatible = "nvidia,tegra194-p2u"; 1475 reg = <0x0 0x03ed0000 0x0 0x10000>; 1476 reg-names = "ctl"; 1477 1478 #phy-cells = <0>; 1479 }; 1480 1481 p2u_nvhs_3: phy@3ee0000 { 1482 compatible = "nvidia,tegra194-p2u"; 1483 reg = <0x0 0x03ee0000 0x0 0x10000>; 1484 reg-names = "ctl"; 1485 1486 #phy-cells = <0>; 1487 }; 1488 1489 p2u_nvhs_4: phy@3ef0000 { 1490 compatible = "nvidia,tegra194-p2u"; 1491 reg = <0x0 0x03ef0000 0x0 0x10000>; 1492 reg-names = "ctl"; 1493 1494 #phy-cells = <0>; 1495 }; 1496 1497 p2u_nvhs_5: phy@3f00000 { 1498 compatible = "nvidia,tegra194-p2u"; 1499 reg = <0x0 0x03f00000 0x0 0x10000>; 1500 reg-names = "ctl"; 1501 1502 #phy-cells = <0>; 1503 }; 1504 1505 p2u_nvhs_6: phy@3f10000 { 1506 compatible = "nvidia,tegra194-p2u"; 1507 reg = <0x0 0x03f10000 0x0 0x10000>; 1508 reg-names = "ctl"; 1509 1510 #phy-cells = <0>; 1511 }; 1512 1513 p2u_nvhs_7: phy@3f20000 { 1514 compatible = "nvidia,tegra194-p2u"; 1515 reg = <0x0 0x03f20000 0x0 0x10000>; 1516 reg-names = "ctl"; 1517 1518 #phy-cells = <0>; 1519 }; 1520 1521 p2u_hsio_10: phy@3f30000 { 1522 compatible = "nvidia,tegra194-p2u"; 1523 reg = <0x0 0x03f30000 0x0 0x10000>; 1524 reg-names = "ctl"; 1525 1526 #phy-cells = <0>; 1527 }; 1528 1529 p2u_hsio_11: phy@3f40000 { 1530 compatible = "nvidia,tegra194-p2u"; 1531 reg = <0x0 0x03f40000 0x0 0x10000>; 1532 reg-names = "ctl"; 1533 1534 #phy-cells = <0>; 1535 }; 1536 1537 sce-noc@b600000 { 1538 compatible = "nvidia,tegra194-sce-noc"; 1539 reg = <0x0 0xb600000 0x0 0x1000>; 1540 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1542 nvidia,axi2apb = <&axi2apb>; 1543 nvidia,apbmisc = <&apbmisc>; 1544 }; 1545 1546 rce-noc@be00000 { 1547 compatible = "nvidia,tegra194-rce-noc"; 1548 reg = <0x0 0xbe00000 0x0 0x1000>; 1549 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1550 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1551 nvidia,axi2apb = <&axi2apb>; 1552 nvidia,apbmisc = <&apbmisc>; 1553 }; 1554 1555 hsp_aon: hsp@c150000 { 1556 compatible = "nvidia,tegra194-hsp"; 1557 reg = <0x0 0x0c150000 0x0 0x90000>; 1558 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1562 /* 1563 * Shared interrupt 0 is routed only to AON/SPE, so 1564 * we only have 4 shared interrupts for the CCPLEX. 1565 */ 1566 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1567 #mbox-cells = <2>; 1568 }; 1569 1570 hte_aon: hardware-timestamp@c1e0000 { 1571 compatible = "nvidia,tegra194-gte-aon"; 1572 reg = <0x0 0xc1e0000 0x0 0x10000>; 1573 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1574 nvidia,int-threshold = <1>; 1575 nvidia,slices = <3>; 1576 #timestamp-cells = <1>; 1577 }; 1578 1579 gen2_i2c: i2c@c240000 { 1580 compatible = "nvidia,tegra194-i2c"; 1581 reg = <0x0 0x0c240000 0x0 0x10000>; 1582 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1583 #address-cells = <1>; 1584 #size-cells = <0>; 1585 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1586 clock-names = "div-clk"; 1587 resets = <&bpmp TEGRA194_RESET_I2C2>; 1588 reset-names = "i2c"; 1589 dmas = <&gpcdma 22>, <&gpcdma 22>; 1590 dma-names = "rx", "tx"; 1591 status = "disabled"; 1592 }; 1593 1594 gen8_i2c: i2c@c250000 { 1595 compatible = "nvidia,tegra194-i2c"; 1596 reg = <0x0 0x0c250000 0x0 0x10000>; 1597 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1601 clock-names = "div-clk"; 1602 resets = <&bpmp TEGRA194_RESET_I2C8>; 1603 reset-names = "i2c"; 1604 dmas = <&gpcdma 0>, <&gpcdma 0>; 1605 dma-names = "rx", "tx"; 1606 status = "disabled"; 1607 }; 1608 1609 uartc: serial@c280000 { 1610 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1611 reg = <0x0 0x0c280000 0x0 0x40>; 1612 reg-shift = <2>; 1613 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1614 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1615 resets = <&bpmp TEGRA194_RESET_UARTC>; 1616 dmas = <&gpcdma 3>, <&gpcdma 3>; 1617 dma-names = "rx", "tx"; 1618 status = "disabled"; 1619 }; 1620 1621 uartg: serial@c290000 { 1622 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1623 reg = <0x0 0x0c290000 0x0 0x40>; 1624 reg-shift = <2>; 1625 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1626 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1627 resets = <&bpmp TEGRA194_RESET_UARTG>; 1628 dmas = <&gpcdma 2>, <&gpcdma 2>; 1629 dma-names = "rx", "tx"; 1630 status = "disabled"; 1631 }; 1632 1633 rtc: rtc@c2a0000 { 1634 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1635 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1636 interrupt-parent = <&pmc>; 1637 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1638 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1639 clock-names = "rtc"; 1640 status = "disabled"; 1641 }; 1642 1643 gpio_aon: gpio@c2f0000 { 1644 compatible = "nvidia,tegra194-gpio-aon"; 1645 reg-names = "security", "gpio"; 1646 reg = <0x0 0xc2f0000 0x0 0x1000>, 1647 <0x0 0xc2f1000 0x0 0x1000>; 1648 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1652 gpio-controller; 1653 #gpio-cells = <2>; 1654 interrupt-controller; 1655 #interrupt-cells = <2>; 1656 gpio-ranges = <&pinmux_aon 0 0 30>; 1657 }; 1658 1659 pinmux_aon: pinmux@c300000 { 1660 compatible = "nvidia,tegra194-pinmux-aon"; 1661 reg = <0x0 0xc300000 0x0 0x4000>; 1662 }; 1663 1664 pwm4: pwm@c340000 { 1665 compatible = "nvidia,tegra194-pwm", 1666 "nvidia,tegra186-pwm"; 1667 reg = <0x0 0xc340000 0x0 0x10000>; 1668 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1669 resets = <&bpmp TEGRA194_RESET_PWM4>; 1670 reset-names = "pwm"; 1671 status = "disabled"; 1672 #pwm-cells = <2>; 1673 }; 1674 1675 pmc: pmc@c360000 { 1676 compatible = "nvidia,tegra194-pmc"; 1677 reg = <0x0 0x0c360000 0x0 0x10000>, 1678 <0x0 0x0c370000 0x0 0x10000>, 1679 <0x0 0x0c380000 0x0 0x10000>, 1680 <0x0 0x0c390000 0x0 0x10000>, 1681 <0x0 0x0c3a0000 0x0 0x10000>; 1682 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1683 1684 #interrupt-cells = <2>; 1685 interrupt-controller; 1686 1687 sdmmc1_1v8: sdmmc1-1v8 { 1688 pins = "sdmmc1-hv"; 1689 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1690 }; 1691 1692 sdmmc1_3v3: sdmmc1-3v3 { 1693 pins = "sdmmc1-hv"; 1694 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1695 }; 1696 1697 sdmmc3_1v8: sdmmc3-1v8 { 1698 pins = "sdmmc3-hv"; 1699 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1700 }; 1701 1702 sdmmc3_3v3: sdmmc3-3v3 { 1703 pins = "sdmmc3-hv"; 1704 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1705 }; 1706 }; 1707 1708 aon-noc@c600000 { 1709 compatible = "nvidia,tegra194-aon-noc"; 1710 reg = <0x0 0xc600000 0x0 0x1000>; 1711 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1713 nvidia,apbmisc = <&apbmisc>; 1714 }; 1715 1716 bpmp-noc@d600000 { 1717 compatible = "nvidia,tegra194-bpmp-noc"; 1718 reg = <0x0 0xd600000 0x0 0x1000>; 1719 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1720 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1721 nvidia,axi2apb = <&axi2apb>; 1722 nvidia,apbmisc = <&apbmisc>; 1723 }; 1724 1725 iommu@10000000 { 1726 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1727 reg = <0x0 0x10000000 0x0 0x800000>; 1728 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1793 stream-match-mask = <0x7f80>; 1794 #global-interrupts = <1>; 1795 #iommu-cells = <1>; 1796 1797 nvidia,memory-controller = <&mc>; 1798 status = "disabled"; 1799 }; 1800 1801 smmu: iommu@12000000 { 1802 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1803 reg = <0x0 0x12000000 0x0 0x800000>, 1804 <0x0 0x11000000 0x0 0x800000>; 1805 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1871 stream-match-mask = <0x7f80>; 1872 #global-interrupts = <2>; 1873 #iommu-cells = <1>; 1874 1875 nvidia,memory-controller = <&mc>; 1876 }; 1877 1878 host1x@13e00000 { 1879 compatible = "nvidia,tegra194-host1x"; 1880 reg = <0x0 0x13e00000 0x0 0x10000>, 1881 <0x0 0x13e10000 0x0 0x10000>; 1882 reg-names = "hypervisor", "vm"; 1883 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1885 interrupt-names = "syncpt", "host1x"; 1886 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1887 clock-names = "host1x"; 1888 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1889 reset-names = "host1x"; 1890 1891 #address-cells = <2>; 1892 #size-cells = <2>; 1893 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>; 1894 1895 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1896 interconnect-names = "dma-mem"; 1897 iommus = <&smmu TEGRA194_SID_HOST1X>; 1898 dma-coherent; 1899 1900 /* Context isolation domains */ 1901 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1902 <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1903 <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1904 <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1905 <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1906 <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1907 <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1908 <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1909 1910 nvdec@15140000 { 1911 compatible = "nvidia,tegra194-nvdec"; 1912 reg = <0x0 0x15140000 0x0 0x00040000>; 1913 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1914 clock-names = "nvdec"; 1915 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1916 reset-names = "nvdec"; 1917 1918 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1919 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1920 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1921 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1922 interconnect-names = "dma-mem", "read-1", "write"; 1923 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1924 dma-coherent; 1925 1926 nvidia,host1x-class = <0xf5>; 1927 }; 1928 1929 display-hub@15200000 { 1930 compatible = "nvidia,tegra194-display"; 1931 reg = <0x0 0x15200000 0x0 0x00040000>; 1932 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1933 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1934 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1935 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1936 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1937 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1938 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1939 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1940 "wgrp3", "wgrp4", "wgrp5"; 1941 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1942 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1943 clock-names = "disp", "hub"; 1944 status = "disabled"; 1945 1946 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1947 1948 #address-cells = <2>; 1949 #size-cells = <2>; 1950 ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>; 1951 1952 display@15200000 { 1953 compatible = "nvidia,tegra194-dc"; 1954 reg = <0x0 0x15200000 0x0 0x10000>; 1955 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1956 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1957 clock-names = "dc"; 1958 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1959 reset-names = "dc"; 1960 1961 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1962 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1963 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1964 interconnect-names = "dma-mem", "read-1"; 1965 1966 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1967 nvidia,head = <0>; 1968 }; 1969 1970 display@15210000 { 1971 compatible = "nvidia,tegra194-dc"; 1972 reg = <0x0 0x15210000 0x0 0x10000>; 1973 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1974 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1975 clock-names = "dc"; 1976 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1977 reset-names = "dc"; 1978 1979 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1980 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1981 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1982 interconnect-names = "dma-mem", "read-1"; 1983 1984 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1985 nvidia,head = <1>; 1986 }; 1987 1988 display@15220000 { 1989 compatible = "nvidia,tegra194-dc"; 1990 reg = <0x0 0x15220000 0x0 0x10000>; 1991 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1992 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1993 clock-names = "dc"; 1994 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1995 reset-names = "dc"; 1996 1997 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1998 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1999 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2000 interconnect-names = "dma-mem", "read-1"; 2001 2002 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2003 nvidia,head = <2>; 2004 }; 2005 2006 display@15230000 { 2007 compatible = "nvidia,tegra194-dc"; 2008 reg = <0x0 0x15230000 0x0 0x10000>; 2009 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2010 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 2011 clock-names = "dc"; 2012 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 2013 reset-names = "dc"; 2014 2015 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2016 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2017 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2018 interconnect-names = "dma-mem", "read-1"; 2019 2020 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2021 nvidia,head = <3>; 2022 }; 2023 }; 2024 2025 vic@15340000 { 2026 compatible = "nvidia,tegra194-vic"; 2027 reg = <0x0 0x15340000 0x0 0x00040000>; 2028 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2029 clocks = <&bpmp TEGRA194_CLK_VIC>; 2030 clock-names = "vic"; 2031 resets = <&bpmp TEGRA194_RESET_VIC>; 2032 reset-names = "vic"; 2033 2034 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2035 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2036 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2037 interconnect-names = "dma-mem", "write"; 2038 iommus = <&smmu TEGRA194_SID_VIC>; 2039 dma-coherent; 2040 }; 2041 2042 nvjpg@15380000 { 2043 compatible = "nvidia,tegra194-nvjpg"; 2044 reg = <0x0 0x15380000 0x0 0x40000>; 2045 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2046 clock-names = "nvjpg"; 2047 resets = <&bpmp TEGRA194_RESET_NVJPG>; 2048 reset-names = "nvjpg"; 2049 2050 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2051 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2052 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2053 interconnect-names = "dma-mem", "write"; 2054 iommus = <&smmu TEGRA194_SID_NVJPG>; 2055 dma-coherent; 2056 }; 2057 2058 nvdec@15480000 { 2059 compatible = "nvidia,tegra194-nvdec"; 2060 reg = <0x0 0x15480000 0x0 0x00040000>; 2061 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 2062 clock-names = "nvdec"; 2063 resets = <&bpmp TEGRA194_RESET_NVDEC>; 2064 reset-names = "nvdec"; 2065 2066 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 2067 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 2068 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 2069 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 2070 interconnect-names = "dma-mem", "read-1", "write"; 2071 iommus = <&smmu TEGRA194_SID_NVDEC>; 2072 dma-coherent; 2073 2074 nvidia,host1x-class = <0xf0>; 2075 }; 2076 2077 nvenc@154c0000 { 2078 compatible = "nvidia,tegra194-nvenc"; 2079 reg = <0x0 0x154c0000 0x0 0x40000>; 2080 clocks = <&bpmp TEGRA194_CLK_NVENC>; 2081 clock-names = "nvenc"; 2082 resets = <&bpmp TEGRA194_RESET_NVENC>; 2083 reset-names = "nvenc"; 2084 2085 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2086 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2087 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2088 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2089 interconnect-names = "dma-mem", "read-1", "write"; 2090 iommus = <&smmu TEGRA194_SID_NVENC>; 2091 dma-coherent; 2092 2093 nvidia,host1x-class = <0x21>; 2094 }; 2095 2096 dpaux0: dpaux@155c0000 { 2097 compatible = "nvidia,tegra194-dpaux"; 2098 reg = <0x0 0x155c0000 0x0 0x10000>; 2099 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 2100 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 2101 <&bpmp TEGRA194_CLK_PLLDP>; 2102 clock-names = "dpaux", "parent"; 2103 resets = <&bpmp TEGRA194_RESET_DPAUX>; 2104 reset-names = "dpaux"; 2105 status = "disabled"; 2106 2107 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2108 2109 state_dpaux0_aux: pinmux-aux { 2110 groups = "dpaux-io"; 2111 function = "aux"; 2112 }; 2113 2114 state_dpaux0_i2c: pinmux-i2c { 2115 groups = "dpaux-io"; 2116 function = "i2c"; 2117 }; 2118 2119 state_dpaux0_off: pinmux-off { 2120 groups = "dpaux-io"; 2121 function = "off"; 2122 }; 2123 2124 i2c-bus { 2125 #address-cells = <1>; 2126 #size-cells = <0>; 2127 }; 2128 }; 2129 2130 dpaux1: dpaux@155d0000 { 2131 compatible = "nvidia,tegra194-dpaux"; 2132 reg = <0x0 0x155d0000 0x0 0x10000>; 2133 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2134 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 2135 <&bpmp TEGRA194_CLK_PLLDP>; 2136 clock-names = "dpaux", "parent"; 2137 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 2138 reset-names = "dpaux"; 2139 status = "disabled"; 2140 2141 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2142 2143 state_dpaux1_aux: pinmux-aux { 2144 groups = "dpaux-io"; 2145 function = "aux"; 2146 }; 2147 2148 state_dpaux1_i2c: pinmux-i2c { 2149 groups = "dpaux-io"; 2150 function = "i2c"; 2151 }; 2152 2153 state_dpaux1_off: pinmux-off { 2154 groups = "dpaux-io"; 2155 function = "off"; 2156 }; 2157 2158 i2c-bus { 2159 #address-cells = <1>; 2160 #size-cells = <0>; 2161 }; 2162 }; 2163 2164 dpaux2: dpaux@155e0000 { 2165 compatible = "nvidia,tegra194-dpaux"; 2166 reg = <0x0 0x155e0000 0x0 0x10000>; 2167 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2168 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2169 <&bpmp TEGRA194_CLK_PLLDP>; 2170 clock-names = "dpaux", "parent"; 2171 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2172 reset-names = "dpaux"; 2173 status = "disabled"; 2174 2175 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2176 2177 state_dpaux2_aux: pinmux-aux { 2178 groups = "dpaux-io"; 2179 function = "aux"; 2180 }; 2181 2182 state_dpaux2_i2c: pinmux-i2c { 2183 groups = "dpaux-io"; 2184 function = "i2c"; 2185 }; 2186 2187 state_dpaux2_off: pinmux-off { 2188 groups = "dpaux-io"; 2189 function = "off"; 2190 }; 2191 2192 i2c-bus { 2193 #address-cells = <1>; 2194 #size-cells = <0>; 2195 }; 2196 }; 2197 2198 dpaux3: dpaux@155f0000 { 2199 compatible = "nvidia,tegra194-dpaux"; 2200 reg = <0x0 0x155f0000 0x0 0x10000>; 2201 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2202 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2203 <&bpmp TEGRA194_CLK_PLLDP>; 2204 clock-names = "dpaux", "parent"; 2205 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2206 reset-names = "dpaux"; 2207 status = "disabled"; 2208 2209 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2210 2211 state_dpaux3_aux: pinmux-aux { 2212 groups = "dpaux-io"; 2213 function = "aux"; 2214 }; 2215 2216 state_dpaux3_i2c: pinmux-i2c { 2217 groups = "dpaux-io"; 2218 function = "i2c"; 2219 }; 2220 2221 state_dpaux3_off: pinmux-off { 2222 groups = "dpaux-io"; 2223 function = "off"; 2224 }; 2225 2226 i2c-bus { 2227 #address-cells = <1>; 2228 #size-cells = <0>; 2229 }; 2230 }; 2231 2232 nvenc@15a80000 { 2233 compatible = "nvidia,tegra194-nvenc"; 2234 reg = <0x0 0x15a80000 0x0 0x00040000>; 2235 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2236 clock-names = "nvenc"; 2237 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2238 reset-names = "nvenc"; 2239 2240 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2241 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2242 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2243 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2244 interconnect-names = "dma-mem", "read-1", "write"; 2245 iommus = <&smmu TEGRA194_SID_NVENC1>; 2246 dma-coherent; 2247 2248 nvidia,host1x-class = <0x22>; 2249 }; 2250 2251 sor0: sor@15b00000 { 2252 compatible = "nvidia,tegra194-sor"; 2253 reg = <0x0 0x15b00000 0x0 0x40000>; 2254 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2255 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2256 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2257 <&bpmp TEGRA194_CLK_PLLD>, 2258 <&bpmp TEGRA194_CLK_PLLDP>, 2259 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2260 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2261 clock-names = "sor", "out", "parent", "dp", "safe", 2262 "pad"; 2263 resets = <&bpmp TEGRA194_RESET_SOR0>; 2264 reset-names = "sor"; 2265 pinctrl-0 = <&state_dpaux0_aux>; 2266 pinctrl-1 = <&state_dpaux0_i2c>; 2267 pinctrl-2 = <&state_dpaux0_off>; 2268 pinctrl-names = "aux", "i2c", "off"; 2269 status = "disabled"; 2270 2271 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2272 nvidia,interface = <0>; 2273 }; 2274 2275 sor1: sor@15b40000 { 2276 compatible = "nvidia,tegra194-sor"; 2277 reg = <0x0 0x15b40000 0x0 0x40000>; 2278 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2279 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2280 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2281 <&bpmp TEGRA194_CLK_PLLD2>, 2282 <&bpmp TEGRA194_CLK_PLLDP>, 2283 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2284 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2285 clock-names = "sor", "out", "parent", "dp", "safe", 2286 "pad"; 2287 resets = <&bpmp TEGRA194_RESET_SOR1>; 2288 reset-names = "sor"; 2289 pinctrl-0 = <&state_dpaux1_aux>; 2290 pinctrl-1 = <&state_dpaux1_i2c>; 2291 pinctrl-2 = <&state_dpaux1_off>; 2292 pinctrl-names = "aux", "i2c", "off"; 2293 status = "disabled"; 2294 2295 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2296 nvidia,interface = <1>; 2297 }; 2298 2299 sor2: sor@15b80000 { 2300 compatible = "nvidia,tegra194-sor"; 2301 reg = <0x0 0x15b80000 0x0 0x40000>; 2302 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2303 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2304 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2305 <&bpmp TEGRA194_CLK_PLLD3>, 2306 <&bpmp TEGRA194_CLK_PLLDP>, 2307 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2308 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2309 clock-names = "sor", "out", "parent", "dp", "safe", 2310 "pad"; 2311 resets = <&bpmp TEGRA194_RESET_SOR2>; 2312 reset-names = "sor"; 2313 pinctrl-0 = <&state_dpaux2_aux>; 2314 pinctrl-1 = <&state_dpaux2_i2c>; 2315 pinctrl-2 = <&state_dpaux2_off>; 2316 pinctrl-names = "aux", "i2c", "off"; 2317 status = "disabled"; 2318 2319 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2320 nvidia,interface = <2>; 2321 }; 2322 2323 sor3: sor@15bc0000 { 2324 compatible = "nvidia,tegra194-sor"; 2325 reg = <0x0 0x15bc0000 0x0 0x40000>; 2326 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2327 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2328 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2329 <&bpmp TEGRA194_CLK_PLLD4>, 2330 <&bpmp TEGRA194_CLK_PLLDP>, 2331 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2332 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2333 clock-names = "sor", "out", "parent", "dp", "safe", 2334 "pad"; 2335 resets = <&bpmp TEGRA194_RESET_SOR3>; 2336 reset-names = "sor"; 2337 pinctrl-0 = <&state_dpaux3_aux>; 2338 pinctrl-1 = <&state_dpaux3_i2c>; 2339 pinctrl-2 = <&state_dpaux3_off>; 2340 pinctrl-names = "aux", "i2c", "off"; 2341 status = "disabled"; 2342 2343 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2344 nvidia,interface = <3>; 2345 }; 2346 }; 2347 2348 pcie@14100000 { 2349 compatible = "nvidia,tegra194-pcie"; 2350 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2351 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2352 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2353 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2354 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2355 reg-names = "appl", "config", "atu_dma", "dbi"; 2356 2357 status = "disabled"; 2358 2359 #address-cells = <3>; 2360 #size-cells = <2>; 2361 device_type = "pci"; 2362 num-lanes = <1>; 2363 linux,pci-domain = <1>; 2364 2365 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2366 clock-names = "core"; 2367 2368 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2369 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2370 reset-names = "apb", "core"; 2371 2372 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2373 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2374 interrupt-names = "intr", "msi"; 2375 2376 #interrupt-cells = <1>; 2377 interrupt-map-mask = <0 0 0 0>; 2378 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2379 2380 nvidia,bpmp = <&bpmp 1>; 2381 2382 nvidia,aspm-cmrt-us = <60>; 2383 nvidia,aspm-pwr-on-t-us = <20>; 2384 nvidia,aspm-l0s-entrance-latency-us = <3>; 2385 2386 bus-range = <0x0 0xff>; 2387 2388 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2389 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2390 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2391 2392 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2393 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2394 interconnect-names = "dma-mem", "write"; 2395 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2396 iommu-map-mask = <0x0>; 2397 dma-coherent; 2398 }; 2399 2400 pcie@14120000 { 2401 compatible = "nvidia,tegra194-pcie"; 2402 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2403 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2404 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2405 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2406 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2407 reg-names = "appl", "config", "atu_dma", "dbi"; 2408 2409 status = "disabled"; 2410 2411 #address-cells = <3>; 2412 #size-cells = <2>; 2413 device_type = "pci"; 2414 num-lanes = <1>; 2415 linux,pci-domain = <2>; 2416 2417 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2418 clock-names = "core"; 2419 2420 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2421 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2422 reset-names = "apb", "core"; 2423 2424 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2425 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2426 interrupt-names = "intr", "msi"; 2427 2428 #interrupt-cells = <1>; 2429 interrupt-map-mask = <0 0 0 0>; 2430 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2431 2432 nvidia,bpmp = <&bpmp 2>; 2433 2434 nvidia,aspm-cmrt-us = <60>; 2435 nvidia,aspm-pwr-on-t-us = <20>; 2436 nvidia,aspm-l0s-entrance-latency-us = <3>; 2437 2438 bus-range = <0x0 0xff>; 2439 2440 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2441 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2442 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2443 2444 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2445 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2446 interconnect-names = "dma-mem", "write"; 2447 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2448 iommu-map-mask = <0x0>; 2449 dma-coherent; 2450 }; 2451 2452 pcie@14140000 { 2453 compatible = "nvidia,tegra194-pcie"; 2454 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2455 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2456 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2457 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2458 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2459 reg-names = "appl", "config", "atu_dma", "dbi"; 2460 2461 status = "disabled"; 2462 2463 #address-cells = <3>; 2464 #size-cells = <2>; 2465 device_type = "pci"; 2466 num-lanes = <1>; 2467 linux,pci-domain = <3>; 2468 2469 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2470 clock-names = "core"; 2471 2472 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2473 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2474 reset-names = "apb", "core"; 2475 2476 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2477 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2478 interrupt-names = "intr", "msi"; 2479 2480 #interrupt-cells = <1>; 2481 interrupt-map-mask = <0 0 0 0>; 2482 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2483 2484 nvidia,bpmp = <&bpmp 3>; 2485 2486 nvidia,aspm-cmrt-us = <60>; 2487 nvidia,aspm-pwr-on-t-us = <20>; 2488 nvidia,aspm-l0s-entrance-latency-us = <3>; 2489 2490 bus-range = <0x0 0xff>; 2491 2492 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2493 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2494 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2495 2496 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2497 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2498 interconnect-names = "dma-mem", "write"; 2499 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2500 iommu-map-mask = <0x0>; 2501 dma-coherent; 2502 }; 2503 2504 pcie@14160000 { 2505 compatible = "nvidia,tegra194-pcie"; 2506 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2507 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2508 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2509 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2510 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2511 reg-names = "appl", "config", "atu_dma", "dbi"; 2512 2513 status = "disabled"; 2514 2515 #address-cells = <3>; 2516 #size-cells = <2>; 2517 device_type = "pci"; 2518 num-lanes = <4>; 2519 linux,pci-domain = <4>; 2520 2521 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2522 clock-names = "core"; 2523 2524 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2525 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2526 reset-names = "apb", "core"; 2527 2528 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2529 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2530 interrupt-names = "intr", "msi"; 2531 2532 #interrupt-cells = <1>; 2533 interrupt-map-mask = <0 0 0 0>; 2534 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2535 2536 nvidia,bpmp = <&bpmp 4>; 2537 2538 nvidia,aspm-cmrt-us = <60>; 2539 nvidia,aspm-pwr-on-t-us = <20>; 2540 nvidia,aspm-l0s-entrance-latency-us = <3>; 2541 2542 bus-range = <0x0 0xff>; 2543 2544 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2545 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2546 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2547 2548 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2549 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2550 interconnect-names = "dma-mem", "write"; 2551 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2552 iommu-map-mask = <0x0>; 2553 dma-coherent; 2554 }; 2555 2556 pcie-ep@14160000 { 2557 compatible = "nvidia,tegra194-pcie-ep"; 2558 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2559 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2560 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2561 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2562 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2563 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2564 2565 status = "disabled"; 2566 2567 num-lanes = <4>; 2568 num-ib-windows = <2>; 2569 num-ob-windows = <8>; 2570 2571 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2572 clock-names = "core"; 2573 2574 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2575 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2576 reset-names = "apb", "core"; 2577 2578 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2579 interrupt-names = "intr"; 2580 2581 nvidia,bpmp = <&bpmp 4>; 2582 2583 nvidia,aspm-cmrt-us = <60>; 2584 nvidia,aspm-pwr-on-t-us = <20>; 2585 nvidia,aspm-l0s-entrance-latency-us = <3>; 2586 2587 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2588 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2589 interconnect-names = "dma-mem", "write"; 2590 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2591 iommu-map-mask = <0x0>; 2592 dma-coherent; 2593 }; 2594 2595 pcie@14180000 { 2596 compatible = "nvidia,tegra194-pcie"; 2597 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2598 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2599 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2600 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2601 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2602 reg-names = "appl", "config", "atu_dma", "dbi"; 2603 2604 status = "disabled"; 2605 2606 #address-cells = <3>; 2607 #size-cells = <2>; 2608 device_type = "pci"; 2609 num-lanes = <8>; 2610 linux,pci-domain = <0>; 2611 2612 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2613 clock-names = "core"; 2614 2615 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2616 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2617 reset-names = "apb", "core"; 2618 2619 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2620 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2621 interrupt-names = "intr", "msi"; 2622 2623 #interrupt-cells = <1>; 2624 interrupt-map-mask = <0 0 0 0>; 2625 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2626 2627 nvidia,bpmp = <&bpmp 0>; 2628 2629 nvidia,aspm-cmrt-us = <60>; 2630 nvidia,aspm-pwr-on-t-us = <20>; 2631 nvidia,aspm-l0s-entrance-latency-us = <3>; 2632 2633 bus-range = <0x0 0xff>; 2634 2635 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2636 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2637 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2638 2639 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2640 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2641 interconnect-names = "dma-mem", "write"; 2642 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2643 iommu-map-mask = <0x0>; 2644 dma-coherent; 2645 }; 2646 2647 pcie-ep@14180000 { 2648 compatible = "nvidia,tegra194-pcie-ep"; 2649 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2650 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2651 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2652 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2653 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2654 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2655 2656 status = "disabled"; 2657 2658 num-lanes = <8>; 2659 num-ib-windows = <2>; 2660 num-ob-windows = <8>; 2661 2662 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2663 clock-names = "core"; 2664 2665 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2666 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2667 reset-names = "apb", "core"; 2668 2669 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2670 interrupt-names = "intr"; 2671 2672 nvidia,bpmp = <&bpmp 0>; 2673 2674 nvidia,aspm-cmrt-us = <60>; 2675 nvidia,aspm-pwr-on-t-us = <20>; 2676 nvidia,aspm-l0s-entrance-latency-us = <3>; 2677 2678 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2679 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2680 interconnect-names = "dma-mem", "write"; 2681 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2682 iommu-map-mask = <0x0>; 2683 dma-coherent; 2684 }; 2685 2686 pcie@141a0000 { 2687 compatible = "nvidia,tegra194-pcie"; 2688 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2689 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2690 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2691 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2692 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2693 reg-names = "appl", "config", "atu_dma", "dbi"; 2694 2695 status = "disabled"; 2696 2697 #address-cells = <3>; 2698 #size-cells = <2>; 2699 device_type = "pci"; 2700 num-lanes = <8>; 2701 linux,pci-domain = <5>; 2702 2703 pinctrl-names = "default"; 2704 pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>; 2705 2706 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2707 clock-names = "core"; 2708 2709 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2710 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2711 reset-names = "apb", "core"; 2712 2713 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2714 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2715 interrupt-names = "intr", "msi"; 2716 2717 nvidia,bpmp = <&bpmp 5>; 2718 2719 #interrupt-cells = <1>; 2720 interrupt-map-mask = <0 0 0 0>; 2721 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2722 2723 nvidia,aspm-cmrt-us = <60>; 2724 nvidia,aspm-pwr-on-t-us = <20>; 2725 nvidia,aspm-l0s-entrance-latency-us = <3>; 2726 2727 bus-range = <0x0 0xff>; 2728 2729 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2730 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2731 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2732 2733 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2734 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2735 interconnect-names = "dma-mem", "write"; 2736 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2737 iommu-map-mask = <0x0>; 2738 dma-coherent; 2739 }; 2740 2741 pcie-ep@141a0000 { 2742 compatible = "nvidia,tegra194-pcie-ep"; 2743 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2744 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2745 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2746 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2747 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2748 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2749 2750 status = "disabled"; 2751 2752 num-lanes = <8>; 2753 num-ib-windows = <2>; 2754 num-ob-windows = <8>; 2755 2756 pinctrl-names = "default"; 2757 pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>; 2758 2759 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2760 clock-names = "core"; 2761 2762 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2763 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2764 reset-names = "apb", "core"; 2765 2766 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2767 interrupt-names = "intr"; 2768 2769 nvidia,bpmp = <&bpmp 5>; 2770 2771 nvidia,aspm-cmrt-us = <60>; 2772 nvidia,aspm-pwr-on-t-us = <20>; 2773 nvidia,aspm-l0s-entrance-latency-us = <3>; 2774 2775 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2776 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2777 interconnect-names = "dma-mem", "write"; 2778 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2779 iommu-map-mask = <0x0>; 2780 dma-coherent; 2781 }; 2782 2783 gpu@17000000 { 2784 compatible = "nvidia,gv11b"; 2785 reg = <0x0 0x17000000 0x0 0x1000000>, 2786 <0x0 0x18000000 0x0 0x1000000>; 2787 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2788 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2789 interrupt-names = "stall", "nonstall"; 2790 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2791 <&bpmp TEGRA194_CLK_GPU_PWR>, 2792 <&bpmp TEGRA194_CLK_FUSE>; 2793 clock-names = "gpu", "pwr", "fuse"; 2794 resets = <&bpmp TEGRA194_RESET_GPU>; 2795 reset-names = "gpu"; 2796 dma-coherent; 2797 2798 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2799 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2800 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2801 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2802 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2803 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2804 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2805 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2806 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2807 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2808 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2809 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2810 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2811 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2812 "read-1", "read-1-hp", "write-1", 2813 "read-2", "read-2-hp", "write-2", 2814 "read-3", "read-3-hp", "write-3"; 2815 }; 2816 }; 2817 2818 sram@40000000 { 2819 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2820 reg = <0x0 0x40000000 0x0 0x50000>; 2821 2822 #address-cells = <1>; 2823 #size-cells = <1>; 2824 ranges = <0x0 0x0 0x40000000 0x50000>; 2825 2826 no-memory-wc; 2827 2828 cpu_bpmp_tx: sram@4e000 { 2829 reg = <0x4e000 0x1000>; 2830 label = "cpu-bpmp-tx"; 2831 pool; 2832 }; 2833 2834 cpu_bpmp_rx: sram@4f000 { 2835 reg = <0x4f000 0x1000>; 2836 label = "cpu-bpmp-rx"; 2837 pool; 2838 }; 2839 }; 2840 2841 bpmp: bpmp { 2842 compatible = "nvidia,tegra186-bpmp"; 2843 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2844 TEGRA_HSP_DB_MASTER_BPMP>; 2845 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2846 #clock-cells = <1>; 2847 #reset-cells = <1>; 2848 #power-domain-cells = <1>; 2849 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2850 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2851 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2852 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2853 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2854 iommus = <&smmu TEGRA194_SID_BPMP>; 2855 2856 bpmp_i2c: i2c { 2857 compatible = "nvidia,tegra186-bpmp-i2c"; 2858 nvidia,bpmp-bus-id = <5>; 2859 #address-cells = <1>; 2860 #size-cells = <0>; 2861 }; 2862 2863 bpmp_thermal: thermal { 2864 compatible = "nvidia,tegra186-bpmp-thermal"; 2865 #thermal-sensor-cells = <1>; 2866 }; 2867 }; 2868 2869 cpus { 2870 compatible = "nvidia,tegra194-ccplex"; 2871 nvidia,bpmp = <&bpmp>; 2872 #address-cells = <1>; 2873 #size-cells = <0>; 2874 2875 cpu0_0: cpu@0 { 2876 compatible = "nvidia,tegra194-carmel"; 2877 device_type = "cpu"; 2878 reg = <0x000>; 2879 enable-method = "psci"; 2880 i-cache-size = <131072>; 2881 i-cache-line-size = <64>; 2882 i-cache-sets = <512>; 2883 d-cache-size = <65536>; 2884 d-cache-line-size = <64>; 2885 d-cache-sets = <256>; 2886 next-level-cache = <&l2c_0>; 2887 }; 2888 2889 cpu0_1: cpu@1 { 2890 compatible = "nvidia,tegra194-carmel"; 2891 device_type = "cpu"; 2892 reg = <0x001>; 2893 enable-method = "psci"; 2894 i-cache-size = <131072>; 2895 i-cache-line-size = <64>; 2896 i-cache-sets = <512>; 2897 d-cache-size = <65536>; 2898 d-cache-line-size = <64>; 2899 d-cache-sets = <256>; 2900 next-level-cache = <&l2c_0>; 2901 }; 2902 2903 cpu1_0: cpu@100 { 2904 compatible = "nvidia,tegra194-carmel"; 2905 device_type = "cpu"; 2906 reg = <0x100>; 2907 enable-method = "psci"; 2908 i-cache-size = <131072>; 2909 i-cache-line-size = <64>; 2910 i-cache-sets = <512>; 2911 d-cache-size = <65536>; 2912 d-cache-line-size = <64>; 2913 d-cache-sets = <256>; 2914 next-level-cache = <&l2c_1>; 2915 }; 2916 2917 cpu1_1: cpu@101 { 2918 compatible = "nvidia,tegra194-carmel"; 2919 device_type = "cpu"; 2920 reg = <0x101>; 2921 enable-method = "psci"; 2922 i-cache-size = <131072>; 2923 i-cache-line-size = <64>; 2924 i-cache-sets = <512>; 2925 d-cache-size = <65536>; 2926 d-cache-line-size = <64>; 2927 d-cache-sets = <256>; 2928 next-level-cache = <&l2c_1>; 2929 }; 2930 2931 cpu2_0: cpu@200 { 2932 compatible = "nvidia,tegra194-carmel"; 2933 device_type = "cpu"; 2934 reg = <0x200>; 2935 enable-method = "psci"; 2936 i-cache-size = <131072>; 2937 i-cache-line-size = <64>; 2938 i-cache-sets = <512>; 2939 d-cache-size = <65536>; 2940 d-cache-line-size = <64>; 2941 d-cache-sets = <256>; 2942 next-level-cache = <&l2c_2>; 2943 }; 2944 2945 cpu2_1: cpu@201 { 2946 compatible = "nvidia,tegra194-carmel"; 2947 device_type = "cpu"; 2948 reg = <0x201>; 2949 enable-method = "psci"; 2950 i-cache-size = <131072>; 2951 i-cache-line-size = <64>; 2952 i-cache-sets = <512>; 2953 d-cache-size = <65536>; 2954 d-cache-line-size = <64>; 2955 d-cache-sets = <256>; 2956 next-level-cache = <&l2c_2>; 2957 }; 2958 2959 cpu3_0: cpu@300 { 2960 compatible = "nvidia,tegra194-carmel"; 2961 device_type = "cpu"; 2962 reg = <0x300>; 2963 enable-method = "psci"; 2964 i-cache-size = <131072>; 2965 i-cache-line-size = <64>; 2966 i-cache-sets = <512>; 2967 d-cache-size = <65536>; 2968 d-cache-line-size = <64>; 2969 d-cache-sets = <256>; 2970 next-level-cache = <&l2c_3>; 2971 }; 2972 2973 cpu3_1: cpu@301 { 2974 compatible = "nvidia,tegra194-carmel"; 2975 device_type = "cpu"; 2976 reg = <0x301>; 2977 enable-method = "psci"; 2978 i-cache-size = <131072>; 2979 i-cache-line-size = <64>; 2980 i-cache-sets = <512>; 2981 d-cache-size = <65536>; 2982 d-cache-line-size = <64>; 2983 d-cache-sets = <256>; 2984 next-level-cache = <&l2c_3>; 2985 }; 2986 2987 cpu-map { 2988 cluster0 { 2989 core0 { 2990 cpu = <&cpu0_0>; 2991 }; 2992 2993 core1 { 2994 cpu = <&cpu0_1>; 2995 }; 2996 }; 2997 2998 cluster1 { 2999 core0 { 3000 cpu = <&cpu1_0>; 3001 }; 3002 3003 core1 { 3004 cpu = <&cpu1_1>; 3005 }; 3006 }; 3007 3008 cluster2 { 3009 core0 { 3010 cpu = <&cpu2_0>; 3011 }; 3012 3013 core1 { 3014 cpu = <&cpu2_1>; 3015 }; 3016 }; 3017 3018 cluster3 { 3019 core0 { 3020 cpu = <&cpu3_0>; 3021 }; 3022 3023 core1 { 3024 cpu = <&cpu3_1>; 3025 }; 3026 }; 3027 }; 3028 3029 l2c_0: l2-cache0 { 3030 compatible = "cache"; 3031 cache-unified; 3032 cache-size = <2097152>; 3033 cache-line-size = <64>; 3034 cache-sets = <2048>; 3035 cache-level = <2>; 3036 next-level-cache = <&l3c>; 3037 }; 3038 3039 l2c_1: l2-cache1 { 3040 compatible = "cache"; 3041 cache-unified; 3042 cache-size = <2097152>; 3043 cache-line-size = <64>; 3044 cache-sets = <2048>; 3045 cache-level = <2>; 3046 next-level-cache = <&l3c>; 3047 }; 3048 3049 l2c_2: l2-cache2 { 3050 compatible = "cache"; 3051 cache-unified; 3052 cache-size = <2097152>; 3053 cache-line-size = <64>; 3054 cache-sets = <2048>; 3055 cache-level = <2>; 3056 next-level-cache = <&l3c>; 3057 }; 3058 3059 l2c_3: l2-cache3 { 3060 compatible = "cache"; 3061 cache-unified; 3062 cache-size = <2097152>; 3063 cache-line-size = <64>; 3064 cache-sets = <2048>; 3065 cache-level = <2>; 3066 next-level-cache = <&l3c>; 3067 }; 3068 3069 l3c: l3-cache { 3070 compatible = "cache"; 3071 cache-unified; 3072 cache-size = <4194304>; 3073 cache-line-size = <64>; 3074 cache-level = <3>; 3075 cache-sets = <4096>; 3076 }; 3077 }; 3078 3079 pmu { 3080 compatible = "nvidia,carmel-pmu"; 3081 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 3082 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 3083 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 3087 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 3088 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 3089 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 3090 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 3091 }; 3092 3093 psci { 3094 compatible = "arm,psci-1.0"; 3095 method = "smc"; 3096 }; 3097 3098 tcu: serial { 3099 compatible = "nvidia,tegra194-tcu"; 3100 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3101 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3102 mbox-names = "rx", "tx"; 3103 }; 3104 3105 sound { 3106 status = "disabled"; 3107 3108 clocks = <&bpmp TEGRA194_CLK_PLLA>, 3109 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3110 clock-names = "pll_a", "plla_out0"; 3111 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 3112 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 3113 <&bpmp TEGRA194_CLK_AUD_MCLK>; 3114 assigned-clock-parents = <0>, 3115 <&bpmp TEGRA194_CLK_PLLA>, 3116 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3117 /* 3118 * PLLA supports dynamic ramp. Below initial rate is chosen 3119 * for this to work and oscillate between base rates required 3120 * for 8x and 11.025x sample rate streams. 3121 */ 3122 assigned-clock-rates = <258000000>; 3123 }; 3124 3125 thermal-zones { 3126 cpu-thermal { 3127 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3128 status = "disabled"; 3129 }; 3130 3131 gpu-thermal { 3132 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3133 status = "disabled"; 3134 }; 3135 3136 aux-thermal { 3137 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3138 status = "disabled"; 3139 }; 3140 3141 pllx-thermal { 3142 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3143 status = "disabled"; 3144 }; 3145 3146 ao-thermal { 3147 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3148 status = "disabled"; 3149 }; 3150 3151 tj-thermal { 3152 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3153 status = "disabled"; 3154 }; 3155 }; 3156 3157 timer { 3158 compatible = "arm,armv8-timer"; 3159 interrupts = <GIC_PPI 13 3160 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3161 <GIC_PPI 14 3162 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3163 <GIC_PPI 11 3164 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3165 <GIC_PPI 10 3166 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3167 interrupt-parent = <&gic>; 3168 always-on; 3169 }; 3170}; 3171