1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 26 27 apbmisc: misc@100000 { 28 compatible = "nvidia,tegra194-misc"; 29 reg = <0x0 0x00100000 0x0 0xf000>, 30 <0x0 0x0010f000 0x0 0x1000>; 31 }; 32 33 gpio: gpio@2200000 { 34 compatible = "nvidia,tegra194-gpio"; 35 reg-names = "security", "gpio"; 36 reg = <0x0 0x2200000 0x0 0x10000>, 37 <0x0 0x2210000 0x0 0x10000>; 38 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 86 #interrupt-cells = <2>; 87 interrupt-controller; 88 #gpio-cells = <2>; 89 gpio-controller; 90 gpio-ranges = <&pinmux 0 0 169>; 91 }; 92 93 cbb-noc@2300000 { 94 compatible = "nvidia,tegra194-cbb-noc"; 95 reg = <0x0 0x02300000 0x0 0x1000>; 96 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 98 nvidia,axi2apb = <&axi2apb>; 99 nvidia,apbmisc = <&apbmisc>; 100 status = "okay"; 101 }; 102 103 axi2apb: axi2apb@2390000 { 104 compatible = "nvidia,tegra194-axi2apb"; 105 reg = <0x0 0x2390000 0x0 0x1000>, 106 <0x0 0x23a0000 0x0 0x1000>, 107 <0x0 0x23b0000 0x0 0x1000>, 108 <0x0 0x23c0000 0x0 0x1000>, 109 <0x0 0x23d0000 0x0 0x1000>, 110 <0x0 0x23e0000 0x0 0x1000>; 111 status = "okay"; 112 }; 113 114 pinmux: pinmux@2430000 { 115 compatible = "nvidia,tegra194-pinmux"; 116 reg = <0x0 0x2430000 0x0 0x17000>; 117 status = "okay"; 118 119 pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir { 120 clkreq { 121 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 122 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 123 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 124 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 125 nvidia,tristate = <TEGRA_PIN_DISABLE>; 126 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 127 }; 128 }; 129 130 pex_rst_c5_out_state: pinmux-pex-rst-c5-out { 131 pex_rst { 132 nvidia,pins = "pex_l5_rst_n_pgg1"; 133 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 134 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 135 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 136 nvidia,tristate = <TEGRA_PIN_DISABLE>; 137 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 138 }; 139 }; 140 }; 141 142 ethernet@2490000 { 143 compatible = "nvidia,tegra194-eqos", 144 "nvidia,tegra186-eqos", 145 "snps,dwc-qos-ethernet-4.10"; 146 reg = <0x0 0x02490000 0x0 0x10000>; 147 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 149 <&bpmp TEGRA194_CLK_EQOS_AXI>, 150 <&bpmp TEGRA194_CLK_EQOS_RX>, 151 <&bpmp TEGRA194_CLK_EQOS_TX>, 152 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 153 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 154 resets = <&bpmp TEGRA194_RESET_EQOS>; 155 reset-names = "eqos"; 156 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 157 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 158 interconnect-names = "dma-mem", "write"; 159 iommus = <&smmu TEGRA194_SID_EQOS>; 160 status = "disabled"; 161 162 snps,write-requests = <1>; 163 snps,read-requests = <3>; 164 snps,burst-map = <0x7>; 165 snps,txpbl = <16>; 166 snps,rxpbl = <8>; 167 }; 168 169 gpcdma: dma-controller@2600000 { 170 compatible = "nvidia,tegra194-gpcdma", 171 "nvidia,tegra186-gpcdma"; 172 reg = <0x0 0x2600000 0x0 0x210000>; 173 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 174 reset-names = "gpcdma"; 175 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 207 #dma-cells = <1>; 208 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 209 dma-coherent; 210 dma-channel-mask = <0xfffffffe>; 211 status = "okay"; 212 }; 213 214 aconnect@2900000 { 215 compatible = "nvidia,tegra194-aconnect", 216 "nvidia,tegra210-aconnect"; 217 clocks = <&bpmp TEGRA194_CLK_APE>, 218 <&bpmp TEGRA194_CLK_APB2APE>; 219 clock-names = "ape", "apb2ape"; 220 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 221 status = "disabled"; 222 223 #address-cells = <2>; 224 #size-cells = <2>; 225 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 226 227 tegra_ahub: ahub@2900800 { 228 compatible = "nvidia,tegra194-ahub", 229 "nvidia,tegra186-ahub"; 230 reg = <0x0 0x02900800 0x0 0x800>; 231 clocks = <&bpmp TEGRA194_CLK_AHUB>; 232 clock-names = "ahub"; 233 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 234 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 235 status = "disabled"; 236 237 #address-cells = <2>; 238 #size-cells = <2>; 239 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 240 241 tegra_i2s1: i2s@2901000 { 242 compatible = "nvidia,tegra194-i2s", 243 "nvidia,tegra210-i2s"; 244 reg = <0x0 0x2901000 0x0 0x100>; 245 clocks = <&bpmp TEGRA194_CLK_I2S1>, 246 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 247 clock-names = "i2s", "sync_input"; 248 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 249 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 250 assigned-clock-rates = <1536000>; 251 sound-name-prefix = "I2S1"; 252 status = "disabled"; 253 }; 254 255 tegra_i2s2: i2s@2901100 { 256 compatible = "nvidia,tegra194-i2s", 257 "nvidia,tegra210-i2s"; 258 reg = <0x0 0x2901100 0x0 0x100>; 259 clocks = <&bpmp TEGRA194_CLK_I2S2>, 260 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 261 clock-names = "i2s", "sync_input"; 262 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 263 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 264 assigned-clock-rates = <1536000>; 265 sound-name-prefix = "I2S2"; 266 status = "disabled"; 267 }; 268 269 tegra_i2s3: i2s@2901200 { 270 compatible = "nvidia,tegra194-i2s", 271 "nvidia,tegra210-i2s"; 272 reg = <0x0 0x2901200 0x0 0x100>; 273 clocks = <&bpmp TEGRA194_CLK_I2S3>, 274 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 275 clock-names = "i2s", "sync_input"; 276 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 277 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 278 assigned-clock-rates = <1536000>; 279 sound-name-prefix = "I2S3"; 280 status = "disabled"; 281 }; 282 283 tegra_i2s4: i2s@2901300 { 284 compatible = "nvidia,tegra194-i2s", 285 "nvidia,tegra210-i2s"; 286 reg = <0x0 0x2901300 0x0 0x100>; 287 clocks = <&bpmp TEGRA194_CLK_I2S4>, 288 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 289 clock-names = "i2s", "sync_input"; 290 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 291 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 292 assigned-clock-rates = <1536000>; 293 sound-name-prefix = "I2S4"; 294 status = "disabled"; 295 }; 296 297 tegra_i2s5: i2s@2901400 { 298 compatible = "nvidia,tegra194-i2s", 299 "nvidia,tegra210-i2s"; 300 reg = <0x0 0x2901400 0x0 0x100>; 301 clocks = <&bpmp TEGRA194_CLK_I2S5>, 302 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 303 clock-names = "i2s", "sync_input"; 304 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 305 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 306 assigned-clock-rates = <1536000>; 307 sound-name-prefix = "I2S5"; 308 status = "disabled"; 309 }; 310 311 tegra_i2s6: i2s@2901500 { 312 compatible = "nvidia,tegra194-i2s", 313 "nvidia,tegra210-i2s"; 314 reg = <0x0 0x2901500 0x0 0x100>; 315 clocks = <&bpmp TEGRA194_CLK_I2S6>, 316 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 317 clock-names = "i2s", "sync_input"; 318 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 319 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 320 assigned-clock-rates = <1536000>; 321 sound-name-prefix = "I2S6"; 322 status = "disabled"; 323 }; 324 325 tegra_sfc1: sfc@2902000 { 326 compatible = "nvidia,tegra194-sfc", 327 "nvidia,tegra210-sfc"; 328 reg = <0x0 0x2902000 0x0 0x200>; 329 sound-name-prefix = "SFC1"; 330 status = "disabled"; 331 }; 332 333 tegra_sfc2: sfc@2902200 { 334 compatible = "nvidia,tegra194-sfc", 335 "nvidia,tegra210-sfc"; 336 reg = <0x0 0x2902200 0x0 0x200>; 337 sound-name-prefix = "SFC2"; 338 status = "disabled"; 339 }; 340 341 tegra_sfc3: sfc@2902400 { 342 compatible = "nvidia,tegra194-sfc", 343 "nvidia,tegra210-sfc"; 344 reg = <0x0 0x2902400 0x0 0x200>; 345 sound-name-prefix = "SFC3"; 346 status = "disabled"; 347 }; 348 349 tegra_sfc4: sfc@2902600 { 350 compatible = "nvidia,tegra194-sfc", 351 "nvidia,tegra210-sfc"; 352 reg = <0x0 0x2902600 0x0 0x200>; 353 sound-name-prefix = "SFC4"; 354 status = "disabled"; 355 }; 356 357 tegra_amx1: amx@2903000 { 358 compatible = "nvidia,tegra194-amx"; 359 reg = <0x0 0x2903000 0x0 0x100>; 360 sound-name-prefix = "AMX1"; 361 status = "disabled"; 362 }; 363 364 tegra_amx2: amx@2903100 { 365 compatible = "nvidia,tegra194-amx"; 366 reg = <0x0 0x2903100 0x0 0x100>; 367 sound-name-prefix = "AMX2"; 368 status = "disabled"; 369 }; 370 371 tegra_amx3: amx@2903200 { 372 compatible = "nvidia,tegra194-amx"; 373 reg = <0x0 0x2903200 0x0 0x100>; 374 sound-name-prefix = "AMX3"; 375 status = "disabled"; 376 }; 377 378 tegra_amx4: amx@2903300 { 379 compatible = "nvidia,tegra194-amx"; 380 reg = <0x0 0x2903300 0x0 0x100>; 381 sound-name-prefix = "AMX4"; 382 status = "disabled"; 383 }; 384 385 tegra_adx1: adx@2903800 { 386 compatible = "nvidia,tegra194-adx", 387 "nvidia,tegra210-adx"; 388 reg = <0x0 0x2903800 0x0 0x100>; 389 sound-name-prefix = "ADX1"; 390 status = "disabled"; 391 }; 392 393 tegra_adx2: adx@2903900 { 394 compatible = "nvidia,tegra194-adx", 395 "nvidia,tegra210-adx"; 396 reg = <0x0 0x2903900 0x0 0x100>; 397 sound-name-prefix = "ADX2"; 398 status = "disabled"; 399 }; 400 401 tegra_adx3: adx@2903a00 { 402 compatible = "nvidia,tegra194-adx", 403 "nvidia,tegra210-adx"; 404 reg = <0x0 0x2903a00 0x0 0x100>; 405 sound-name-prefix = "ADX3"; 406 status = "disabled"; 407 }; 408 409 tegra_adx4: adx@2903b00 { 410 compatible = "nvidia,tegra194-adx", 411 "nvidia,tegra210-adx"; 412 reg = <0x0 0x2903b00 0x0 0x100>; 413 sound-name-prefix = "ADX4"; 414 status = "disabled"; 415 }; 416 417 tegra_dmic1: dmic@2904000 { 418 compatible = "nvidia,tegra194-dmic", 419 "nvidia,tegra210-dmic"; 420 reg = <0x0 0x2904000 0x0 0x100>; 421 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 422 clock-names = "dmic"; 423 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 424 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 425 assigned-clock-rates = <3072000>; 426 sound-name-prefix = "DMIC1"; 427 status = "disabled"; 428 }; 429 430 tegra_dmic2: dmic@2904100 { 431 compatible = "nvidia,tegra194-dmic", 432 "nvidia,tegra210-dmic"; 433 reg = <0x0 0x2904100 0x0 0x100>; 434 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 435 clock-names = "dmic"; 436 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 437 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 438 assigned-clock-rates = <3072000>; 439 sound-name-prefix = "DMIC2"; 440 status = "disabled"; 441 }; 442 443 tegra_dmic3: dmic@2904200 { 444 compatible = "nvidia,tegra194-dmic", 445 "nvidia,tegra210-dmic"; 446 reg = <0x0 0x2904200 0x0 0x100>; 447 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 448 clock-names = "dmic"; 449 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 450 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 451 assigned-clock-rates = <3072000>; 452 sound-name-prefix = "DMIC3"; 453 status = "disabled"; 454 }; 455 456 tegra_dmic4: dmic@2904300 { 457 compatible = "nvidia,tegra194-dmic", 458 "nvidia,tegra210-dmic"; 459 reg = <0x0 0x2904300 0x0 0x100>; 460 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 461 clock-names = "dmic"; 462 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 463 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 464 assigned-clock-rates = <3072000>; 465 sound-name-prefix = "DMIC4"; 466 status = "disabled"; 467 }; 468 469 tegra_dspk1: dspk@2905000 { 470 compatible = "nvidia,tegra194-dspk", 471 "nvidia,tegra186-dspk"; 472 reg = <0x0 0x2905000 0x0 0x100>; 473 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 474 clock-names = "dspk"; 475 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 476 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 477 assigned-clock-rates = <12288000>; 478 sound-name-prefix = "DSPK1"; 479 status = "disabled"; 480 }; 481 482 tegra_dspk2: dspk@2905100 { 483 compatible = "nvidia,tegra194-dspk", 484 "nvidia,tegra186-dspk"; 485 reg = <0x0 0x2905100 0x0 0x100>; 486 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 487 clock-names = "dspk"; 488 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 489 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 490 assigned-clock-rates = <12288000>; 491 sound-name-prefix = "DSPK2"; 492 status = "disabled"; 493 }; 494 495 tegra_ope1: processing-engine@2908000 { 496 compatible = "nvidia,tegra194-ope", 497 "nvidia,tegra210-ope"; 498 reg = <0x0 0x2908000 0x0 0x100>; 499 sound-name-prefix = "OPE1"; 500 status = "disabled"; 501 502 #address-cells = <2>; 503 #size-cells = <2>; 504 ranges; 505 506 equalizer@2908100 { 507 compatible = "nvidia,tegra194-peq", 508 "nvidia,tegra210-peq"; 509 reg = <0x0 0x2908100 0x0 0x100>; 510 }; 511 512 dynamic-range-compressor@2908200 { 513 compatible = "nvidia,tegra194-mbdrc", 514 "nvidia,tegra210-mbdrc"; 515 reg = <0x0 0x2908200 0x0 0x200>; 516 }; 517 }; 518 519 tegra_mvc1: mvc@290a000 { 520 compatible = "nvidia,tegra194-mvc", 521 "nvidia,tegra210-mvc"; 522 reg = <0x0 0x290a000 0x0 0x200>; 523 sound-name-prefix = "MVC1"; 524 status = "disabled"; 525 }; 526 527 tegra_mvc2: mvc@290a200 { 528 compatible = "nvidia,tegra194-mvc", 529 "nvidia,tegra210-mvc"; 530 reg = <0x0 0x290a200 0x0 0x200>; 531 sound-name-prefix = "MVC2"; 532 status = "disabled"; 533 }; 534 535 tegra_amixer: amixer@290bb00 { 536 compatible = "nvidia,tegra194-amixer", 537 "nvidia,tegra210-amixer"; 538 reg = <0x0 0x290bb00 0x0 0x800>; 539 sound-name-prefix = "MIXER1"; 540 status = "disabled"; 541 }; 542 543 tegra_admaif: admaif@290f000 { 544 compatible = "nvidia,tegra194-admaif", 545 "nvidia,tegra186-admaif"; 546 reg = <0x0 0x0290f000 0x0 0x1000>; 547 dmas = <&adma 1>, <&adma 1>, 548 <&adma 2>, <&adma 2>, 549 <&adma 3>, <&adma 3>, 550 <&adma 4>, <&adma 4>, 551 <&adma 5>, <&adma 5>, 552 <&adma 6>, <&adma 6>, 553 <&adma 7>, <&adma 7>, 554 <&adma 8>, <&adma 8>, 555 <&adma 9>, <&adma 9>, 556 <&adma 10>, <&adma 10>, 557 <&adma 11>, <&adma 11>, 558 <&adma 12>, <&adma 12>, 559 <&adma 13>, <&adma 13>, 560 <&adma 14>, <&adma 14>, 561 <&adma 15>, <&adma 15>, 562 <&adma 16>, <&adma 16>, 563 <&adma 17>, <&adma 17>, 564 <&adma 18>, <&adma 18>, 565 <&adma 19>, <&adma 19>, 566 <&adma 20>, <&adma 20>; 567 dma-names = "rx1", "tx1", 568 "rx2", "tx2", 569 "rx3", "tx3", 570 "rx4", "tx4", 571 "rx5", "tx5", 572 "rx6", "tx6", 573 "rx7", "tx7", 574 "rx8", "tx8", 575 "rx9", "tx9", 576 "rx10", "tx10", 577 "rx11", "tx11", 578 "rx12", "tx12", 579 "rx13", "tx13", 580 "rx14", "tx14", 581 "rx15", "tx15", 582 "rx16", "tx16", 583 "rx17", "tx17", 584 "rx18", "tx18", 585 "rx19", "tx19", 586 "rx20", "tx20"; 587 status = "disabled"; 588 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 589 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 590 interconnect-names = "dma-mem", "write"; 591 iommus = <&smmu TEGRA194_SID_APE>; 592 }; 593 594 tegra_asrc: asrc@2910000 { 595 compatible = "nvidia,tegra194-asrc", 596 "nvidia,tegra186-asrc"; 597 reg = <0x0 0x2910000 0x0 0x2000>; 598 sound-name-prefix = "ASRC1"; 599 status = "disabled"; 600 }; 601 }; 602 603 adma: dma-controller@2930000 { 604 compatible = "nvidia,tegra194-adma", 605 "nvidia,tegra186-adma"; 606 reg = <0x0 0x02930000 0x0 0x20000>; 607 interrupt-parent = <&agic>; 608 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 640 #dma-cells = <1>; 641 clocks = <&bpmp TEGRA194_CLK_AHUB>; 642 clock-names = "d_audio"; 643 status = "disabled"; 644 }; 645 646 agic: interrupt-controller@2a40000 { 647 compatible = "nvidia,tegra194-agic", 648 "nvidia,tegra210-agic"; 649 #interrupt-cells = <3>; 650 interrupt-controller; 651 reg = <0x0 0x02a41000 0x0 0x1000>, 652 <0x0 0x02a42000 0x0 0x2000>; 653 interrupts = <GIC_SPI 145 654 (GIC_CPU_MASK_SIMPLE(4) | 655 IRQ_TYPE_LEVEL_HIGH)>; 656 clocks = <&bpmp TEGRA194_CLK_APE>; 657 clock-names = "clk"; 658 status = "disabled"; 659 }; 660 }; 661 662 mc: memory-controller@2c00000 { 663 compatible = "nvidia,tegra194-mc"; 664 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 665 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 666 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 667 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 668 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 669 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 670 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 671 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 672 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 673 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 674 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 675 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 676 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 677 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 678 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 679 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 680 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 681 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 682 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 683 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 684 "ch11", "ch12", "ch13", "ch14", "ch15"; 685 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 686 #interconnect-cells = <1>; 687 status = "disabled"; 688 689 #address-cells = <2>; 690 #size-cells = <2>; 691 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 692 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 693 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 694 695 /* 696 * Bit 39 of addresses passing through the memory 697 * controller selects the XBAR format used when memory 698 * is accessed. This is used to transparently access 699 * memory in the XBAR format used by the discrete GPU 700 * (bit 39 set) or Tegra (bit 39 clear). 701 * 702 * As a consequence, the operating system must ensure 703 * that bit 39 is never used implicitly, for example 704 * via an I/O virtual address mapping of an IOMMU. If 705 * devices require access to the XBAR switch, their 706 * drivers must set this bit explicitly. 707 * 708 * Limit the DMA range for memory clients to [38:0]. 709 */ 710 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 711 712 emc: external-memory-controller@2c60000 { 713 compatible = "nvidia,tegra194-emc"; 714 reg = <0x0 0x02c60000 0x0 0x90000>, 715 <0x0 0x01780000 0x0 0x80000>; 716 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&bpmp TEGRA194_CLK_EMC>; 718 clock-names = "emc"; 719 720 #interconnect-cells = <0>; 721 722 nvidia,bpmp = <&bpmp>; 723 }; 724 }; 725 726 timer@3010000 { 727 compatible = "nvidia,tegra186-timer"; 728 reg = <0x0 0x03010000 0x0 0x000e0000>; 729 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 739 status = "okay"; 740 }; 741 742 uarta: serial@3100000 { 743 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 744 reg = <0x0 0x03100000 0x0 0x40>; 745 reg-shift = <2>; 746 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&bpmp TEGRA194_CLK_UARTA>; 748 resets = <&bpmp TEGRA194_RESET_UARTA>; 749 status = "disabled"; 750 }; 751 752 uartb: serial@3110000 { 753 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 754 reg = <0x0 0x03110000 0x0 0x40>; 755 reg-shift = <2>; 756 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&bpmp TEGRA194_CLK_UARTB>; 758 resets = <&bpmp TEGRA194_RESET_UARTB>; 759 status = "disabled"; 760 }; 761 762 uartd: serial@3130000 { 763 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 764 reg = <0x0 0x03130000 0x0 0x40>; 765 reg-shift = <2>; 766 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&bpmp TEGRA194_CLK_UARTD>; 768 clock-names = "serial"; 769 resets = <&bpmp TEGRA194_RESET_UARTD>; 770 reset-names = "serial"; 771 status = "disabled"; 772 }; 773 774 uarte: serial@3140000 { 775 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 776 reg = <0x0 0x03140000 0x0 0x40>; 777 reg-shift = <2>; 778 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&bpmp TEGRA194_CLK_UARTE>; 780 clock-names = "serial"; 781 resets = <&bpmp TEGRA194_RESET_UARTE>; 782 reset-names = "serial"; 783 status = "disabled"; 784 }; 785 786 uartf: serial@3150000 { 787 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 788 reg = <0x0 0x03150000 0x0 0x40>; 789 reg-shift = <2>; 790 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&bpmp TEGRA194_CLK_UARTF>; 792 clock-names = "serial"; 793 resets = <&bpmp TEGRA194_RESET_UARTF>; 794 reset-names = "serial"; 795 status = "disabled"; 796 }; 797 798 gen1_i2c: i2c@3160000 { 799 compatible = "nvidia,tegra194-i2c"; 800 reg = <0x0 0x03160000 0x0 0x10000>; 801 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 clocks = <&bpmp TEGRA194_CLK_I2C1>; 805 clock-names = "div-clk"; 806 resets = <&bpmp TEGRA194_RESET_I2C1>; 807 reset-names = "i2c"; 808 dmas = <&gpcdma 21>, <&gpcdma 21>; 809 dma-names = "rx", "tx"; 810 status = "disabled"; 811 }; 812 813 uarth: serial@3170000 { 814 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 815 reg = <0x0 0x03170000 0x0 0x40>; 816 reg-shift = <2>; 817 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&bpmp TEGRA194_CLK_UARTH>; 819 clock-names = "serial"; 820 resets = <&bpmp TEGRA194_RESET_UARTH>; 821 reset-names = "serial"; 822 status = "disabled"; 823 }; 824 825 cam_i2c: i2c@3180000 { 826 compatible = "nvidia,tegra194-i2c"; 827 reg = <0x0 0x03180000 0x0 0x10000>; 828 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 clocks = <&bpmp TEGRA194_CLK_I2C3>; 832 clock-names = "div-clk"; 833 resets = <&bpmp TEGRA194_RESET_I2C3>; 834 reset-names = "i2c"; 835 dmas = <&gpcdma 23>, <&gpcdma 23>; 836 dma-names = "rx", "tx"; 837 status = "disabled"; 838 }; 839 840 /* shares pads with dpaux1 */ 841 dp_aux_ch1_i2c: i2c@3190000 { 842 compatible = "nvidia,tegra194-i2c"; 843 reg = <0x0 0x03190000 0x0 0x10000>; 844 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 clocks = <&bpmp TEGRA194_CLK_I2C4>; 848 clock-names = "div-clk"; 849 resets = <&bpmp TEGRA194_RESET_I2C4>; 850 reset-names = "i2c"; 851 pinctrl-0 = <&state_dpaux1_i2c>; 852 pinctrl-1 = <&state_dpaux1_off>; 853 pinctrl-names = "default", "idle"; 854 dmas = <&gpcdma 26>, <&gpcdma 26>; 855 dma-names = "rx", "tx"; 856 status = "disabled"; 857 }; 858 859 /* shares pads with dpaux0 */ 860 dp_aux_ch0_i2c: i2c@31b0000 { 861 compatible = "nvidia,tegra194-i2c"; 862 reg = <0x0 0x031b0000 0x0 0x10000>; 863 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 clocks = <&bpmp TEGRA194_CLK_I2C6>; 867 clock-names = "div-clk"; 868 resets = <&bpmp TEGRA194_RESET_I2C6>; 869 reset-names = "i2c"; 870 pinctrl-0 = <&state_dpaux0_i2c>; 871 pinctrl-1 = <&state_dpaux0_off>; 872 pinctrl-names = "default", "idle"; 873 dmas = <&gpcdma 30>, <&gpcdma 30>; 874 dma-names = "rx", "tx"; 875 status = "disabled"; 876 }; 877 878 /* shares pads with dpaux2 */ 879 dp_aux_ch2_i2c: i2c@31c0000 { 880 compatible = "nvidia,tegra194-i2c"; 881 reg = <0x0 0x031c0000 0x0 0x10000>; 882 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 883 #address-cells = <1>; 884 #size-cells = <0>; 885 clocks = <&bpmp TEGRA194_CLK_I2C7>; 886 clock-names = "div-clk"; 887 resets = <&bpmp TEGRA194_RESET_I2C7>; 888 reset-names = "i2c"; 889 pinctrl-0 = <&state_dpaux2_i2c>; 890 pinctrl-1 = <&state_dpaux2_off>; 891 pinctrl-names = "default", "idle"; 892 dmas = <&gpcdma 27>, <&gpcdma 27>; 893 dma-names = "rx", "tx"; 894 status = "disabled"; 895 }; 896 897 /* shares pads with dpaux3 */ 898 dp_aux_ch3_i2c: i2c@31e0000 { 899 compatible = "nvidia,tegra194-i2c"; 900 reg = <0x0 0x031e0000 0x0 0x10000>; 901 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 clocks = <&bpmp TEGRA194_CLK_I2C9>; 905 clock-names = "div-clk"; 906 resets = <&bpmp TEGRA194_RESET_I2C9>; 907 reset-names = "i2c"; 908 pinctrl-0 = <&state_dpaux3_i2c>; 909 pinctrl-1 = <&state_dpaux3_off>; 910 pinctrl-names = "default", "idle"; 911 dmas = <&gpcdma 31>, <&gpcdma 31>; 912 dma-names = "rx", "tx"; 913 status = "disabled"; 914 }; 915 916 spi@3270000 { 917 compatible = "nvidia,tegra194-qspi"; 918 reg = <0x0 0x3270000 0x0 0x1000>; 919 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 923 <&bpmp TEGRA194_CLK_QSPI0_PM>; 924 clock-names = "qspi", "qspi_out"; 925 resets = <&bpmp TEGRA194_RESET_QSPI0>; 926 status = "disabled"; 927 }; 928 929 pwm1: pwm@3280000 { 930 compatible = "nvidia,tegra194-pwm", 931 "nvidia,tegra186-pwm"; 932 reg = <0x0 0x3280000 0x0 0x10000>; 933 clocks = <&bpmp TEGRA194_CLK_PWM1>; 934 resets = <&bpmp TEGRA194_RESET_PWM1>; 935 reset-names = "pwm"; 936 status = "disabled"; 937 #pwm-cells = <2>; 938 }; 939 940 pwm2: pwm@3290000 { 941 compatible = "nvidia,tegra194-pwm", 942 "nvidia,tegra186-pwm"; 943 reg = <0x0 0x3290000 0x0 0x10000>; 944 clocks = <&bpmp TEGRA194_CLK_PWM2>; 945 resets = <&bpmp TEGRA194_RESET_PWM2>; 946 reset-names = "pwm"; 947 status = "disabled"; 948 #pwm-cells = <2>; 949 }; 950 951 pwm3: pwm@32a0000 { 952 compatible = "nvidia,tegra194-pwm", 953 "nvidia,tegra186-pwm"; 954 reg = <0x0 0x32a0000 0x0 0x10000>; 955 clocks = <&bpmp TEGRA194_CLK_PWM3>; 956 resets = <&bpmp TEGRA194_RESET_PWM3>; 957 reset-names = "pwm"; 958 status = "disabled"; 959 #pwm-cells = <2>; 960 }; 961 962 pwm5: pwm@32c0000 { 963 compatible = "nvidia,tegra194-pwm", 964 "nvidia,tegra186-pwm"; 965 reg = <0x0 0x32c0000 0x0 0x10000>; 966 clocks = <&bpmp TEGRA194_CLK_PWM5>; 967 resets = <&bpmp TEGRA194_RESET_PWM5>; 968 reset-names = "pwm"; 969 status = "disabled"; 970 #pwm-cells = <2>; 971 }; 972 973 pwm6: pwm@32d0000 { 974 compatible = "nvidia,tegra194-pwm", 975 "nvidia,tegra186-pwm"; 976 reg = <0x0 0x32d0000 0x0 0x10000>; 977 clocks = <&bpmp TEGRA194_CLK_PWM6>; 978 resets = <&bpmp TEGRA194_RESET_PWM6>; 979 reset-names = "pwm"; 980 status = "disabled"; 981 #pwm-cells = <2>; 982 }; 983 984 pwm7: pwm@32e0000 { 985 compatible = "nvidia,tegra194-pwm", 986 "nvidia,tegra186-pwm"; 987 reg = <0x0 0x32e0000 0x0 0x10000>; 988 clocks = <&bpmp TEGRA194_CLK_PWM7>; 989 resets = <&bpmp TEGRA194_RESET_PWM7>; 990 reset-names = "pwm"; 991 status = "disabled"; 992 #pwm-cells = <2>; 993 }; 994 995 pwm8: pwm@32f0000 { 996 compatible = "nvidia,tegra194-pwm", 997 "nvidia,tegra186-pwm"; 998 reg = <0x0 0x32f0000 0x0 0x10000>; 999 clocks = <&bpmp TEGRA194_CLK_PWM8>; 1000 resets = <&bpmp TEGRA194_RESET_PWM8>; 1001 reset-names = "pwm"; 1002 status = "disabled"; 1003 #pwm-cells = <2>; 1004 }; 1005 1006 spi@3300000 { 1007 compatible = "nvidia,tegra194-qspi"; 1008 reg = <0x0 0x3300000 0x0 0x1000>; 1009 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 1013 <&bpmp TEGRA194_CLK_QSPI1_PM>; 1014 clock-names = "qspi", "qspi_out"; 1015 resets = <&bpmp TEGRA194_RESET_QSPI1>; 1016 status = "disabled"; 1017 }; 1018 1019 sdmmc1: mmc@3400000 { 1020 compatible = "nvidia,tegra194-sdhci"; 1021 reg = <0x0 0x03400000 0x0 0x10000>; 1022 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1024 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1025 clock-names = "sdhci", "tmclk"; 1026 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1027 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1028 assigned-clock-parents = 1029 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1030 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1031 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 1032 reset-names = "sdhci"; 1033 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1034 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1035 interconnect-names = "dma-mem", "write"; 1036 iommus = <&smmu TEGRA194_SID_SDMMC1>; 1037 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1038 pinctrl-0 = <&sdmmc1_3v3>; 1039 pinctrl-1 = <&sdmmc1_1v8>; 1040 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 1041 <0x07>; 1042 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1043 <0x07>; 1044 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1045 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1046 <0x07>; 1047 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1048 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1049 nvidia,default-tap = <0x9>; 1050 nvidia,default-trim = <0x5>; 1051 sd-uhs-sdr25; 1052 sd-uhs-sdr50; 1053 sd-uhs-ddr50; 1054 sd-uhs-sdr104; 1055 status = "disabled"; 1056 }; 1057 1058 sdmmc3: mmc@3440000 { 1059 compatible = "nvidia,tegra194-sdhci"; 1060 reg = <0x0 0x03440000 0x0 0x10000>; 1061 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1063 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1064 clock-names = "sdhci", "tmclk"; 1065 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1066 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1067 assigned-clock-parents = 1068 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1069 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1070 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 1071 reset-names = "sdhci"; 1072 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1073 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1074 interconnect-names = "dma-mem", "write"; 1075 iommus = <&smmu TEGRA194_SID_SDMMC3>; 1076 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1077 pinctrl-0 = <&sdmmc3_3v3>; 1078 pinctrl-1 = <&sdmmc3_1v8>; 1079 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 1080 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1081 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1082 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1083 <0x07>; 1084 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1085 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1086 <0x07>; 1087 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1088 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1089 nvidia,default-tap = <0x9>; 1090 nvidia,default-trim = <0x5>; 1091 sd-uhs-sdr25; 1092 sd-uhs-sdr50; 1093 sd-uhs-ddr50; 1094 sd-uhs-sdr104; 1095 status = "disabled"; 1096 }; 1097 1098 sdmmc4: mmc@3460000 { 1099 compatible = "nvidia,tegra194-sdhci"; 1100 reg = <0x0 0x03460000 0x0 0x10000>; 1101 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1102 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1103 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1104 clock-names = "sdhci", "tmclk"; 1105 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1106 <&bpmp TEGRA194_CLK_PLLC4>; 1107 assigned-clock-parents = 1108 <&bpmp TEGRA194_CLK_PLLC4>; 1109 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1110 reset-names = "sdhci"; 1111 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1112 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1113 interconnect-names = "dma-mem", "write"; 1114 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1115 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1116 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1117 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1118 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1119 <0x0a>; 1120 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1121 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1122 <0x0a>; 1123 nvidia,default-tap = <0x8>; 1124 nvidia,default-trim = <0x14>; 1125 nvidia,dqs-trim = <40>; 1126 cap-mmc-highspeed; 1127 mmc-ddr-1_8v; 1128 mmc-hs200-1_8v; 1129 mmc-hs400-1_8v; 1130 mmc-hs400-enhanced-strobe; 1131 supports-cqe; 1132 status = "disabled"; 1133 }; 1134 1135 hda@3510000 { 1136 compatible = "nvidia,tegra194-hda"; 1137 reg = <0x0 0x3510000 0x0 0x10000>; 1138 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1139 clocks = <&bpmp TEGRA194_CLK_HDA>, 1140 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1141 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1142 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1143 resets = <&bpmp TEGRA194_RESET_HDA>, 1144 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1145 reset-names = "hda", "hda2hdmi"; 1146 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1147 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1148 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1149 interconnect-names = "dma-mem", "write"; 1150 iommus = <&smmu TEGRA194_SID_HDA>; 1151 status = "disabled"; 1152 }; 1153 1154 xusb_padctl: padctl@3520000 { 1155 compatible = "nvidia,tegra194-xusb-padctl"; 1156 reg = <0x0 0x03520000 0x0 0x1000>, 1157 <0x0 0x03540000 0x0 0x1000>; 1158 reg-names = "padctl", "ao"; 1159 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1160 1161 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1162 reset-names = "padctl"; 1163 1164 status = "disabled"; 1165 1166 pads { 1167 usb2 { 1168 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1169 clock-names = "trk"; 1170 1171 lanes { 1172 usb2-0 { 1173 nvidia,function = "xusb"; 1174 status = "disabled"; 1175 #phy-cells = <0>; 1176 }; 1177 1178 usb2-1 { 1179 nvidia,function = "xusb"; 1180 status = "disabled"; 1181 #phy-cells = <0>; 1182 }; 1183 1184 usb2-2 { 1185 nvidia,function = "xusb"; 1186 status = "disabled"; 1187 #phy-cells = <0>; 1188 }; 1189 1190 usb2-3 { 1191 nvidia,function = "xusb"; 1192 status = "disabled"; 1193 #phy-cells = <0>; 1194 }; 1195 }; 1196 }; 1197 1198 usb3 { 1199 lanes { 1200 usb3-0 { 1201 nvidia,function = "xusb"; 1202 status = "disabled"; 1203 #phy-cells = <0>; 1204 }; 1205 1206 usb3-1 { 1207 nvidia,function = "xusb"; 1208 status = "disabled"; 1209 #phy-cells = <0>; 1210 }; 1211 1212 usb3-2 { 1213 nvidia,function = "xusb"; 1214 status = "disabled"; 1215 #phy-cells = <0>; 1216 }; 1217 1218 usb3-3 { 1219 nvidia,function = "xusb"; 1220 status = "disabled"; 1221 #phy-cells = <0>; 1222 }; 1223 }; 1224 }; 1225 }; 1226 1227 ports { 1228 usb2-0 { 1229 status = "disabled"; 1230 }; 1231 1232 usb2-1 { 1233 status = "disabled"; 1234 }; 1235 1236 usb2-2 { 1237 status = "disabled"; 1238 }; 1239 1240 usb2-3 { 1241 status = "disabled"; 1242 }; 1243 1244 usb3-0 { 1245 status = "disabled"; 1246 }; 1247 1248 usb3-1 { 1249 status = "disabled"; 1250 }; 1251 1252 usb3-2 { 1253 status = "disabled"; 1254 }; 1255 1256 usb3-3 { 1257 status = "disabled"; 1258 }; 1259 }; 1260 }; 1261 1262 usb@3550000 { 1263 compatible = "nvidia,tegra194-xudc"; 1264 reg = <0x0 0x03550000 0x0 0x8000>, 1265 <0x0 0x03558000 0x0 0x1000>; 1266 reg-names = "base", "fpci"; 1267 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1268 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1269 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1270 <&bpmp TEGRA194_CLK_XUSB_SS>, 1271 <&bpmp TEGRA194_CLK_XUSB_FS>; 1272 clock-names = "dev", "ss", "ss_src", "fs_src"; 1273 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1274 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1275 interconnect-names = "dma-mem", "write"; 1276 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1277 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1278 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1279 power-domain-names = "dev", "ss"; 1280 nvidia,xusb-padctl = <&xusb_padctl>; 1281 dma-coherent; 1282 status = "disabled"; 1283 }; 1284 1285 usb@3610000 { 1286 compatible = "nvidia,tegra194-xusb"; 1287 reg = <0x0 0x03610000 0x0 0x40000>, 1288 <0x0 0x03600000 0x0 0x10000>; 1289 reg-names = "hcd", "fpci"; 1290 1291 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1293 1294 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1295 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1296 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1297 <&bpmp TEGRA194_CLK_XUSB_SS>, 1298 <&bpmp TEGRA194_CLK_CLK_M>, 1299 <&bpmp TEGRA194_CLK_XUSB_FS>, 1300 <&bpmp TEGRA194_CLK_UTMIPLL>, 1301 <&bpmp TEGRA194_CLK_CLK_M>, 1302 <&bpmp TEGRA194_CLK_PLLE>; 1303 clock-names = "xusb_host", "xusb_falcon_src", 1304 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1305 "xusb_fs_src", "pll_u_480m", "clk_m", 1306 "pll_e"; 1307 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1308 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1309 interconnect-names = "dma-mem", "write"; 1310 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1311 1312 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1313 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1314 power-domain-names = "xusb_host", "xusb_ss"; 1315 1316 nvidia,xusb-padctl = <&xusb_padctl>; 1317 status = "disabled"; 1318 }; 1319 1320 fuse@3820000 { 1321 compatible = "nvidia,tegra194-efuse"; 1322 reg = <0x0 0x03820000 0x0 0x10000>; 1323 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1324 clock-names = "fuse"; 1325 }; 1326 1327 gic: interrupt-controller@3881000 { 1328 compatible = "arm,gic-400"; 1329 #interrupt-cells = <3>; 1330 interrupt-controller; 1331 reg = <0x0 0x03881000 0x0 0x1000>, 1332 <0x0 0x03882000 0x0 0x2000>, 1333 <0x0 0x03884000 0x0 0x2000>, 1334 <0x0 0x03886000 0x0 0x2000>; 1335 interrupts = <GIC_PPI 9 1336 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1337 interrupt-parent = <&gic>; 1338 }; 1339 1340 cec@3960000 { 1341 compatible = "nvidia,tegra194-cec"; 1342 reg = <0x0 0x03960000 0x0 0x10000>; 1343 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1344 clocks = <&bpmp TEGRA194_CLK_CEC>; 1345 clock-names = "cec"; 1346 status = "disabled"; 1347 }; 1348 1349 hte_lic: hardware-timestamp@3aa0000 { 1350 compatible = "nvidia,tegra194-gte-lic"; 1351 reg = <0x0 0x3aa0000 0x0 0x10000>; 1352 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1353 nvidia,int-threshold = <1>; 1354 nvidia,slices = <11>; 1355 #timestamp-cells = <1>; 1356 status = "okay"; 1357 }; 1358 1359 hsp_top0: hsp@3c00000 { 1360 compatible = "nvidia,tegra194-hsp"; 1361 reg = <0x0 0x03c00000 0x0 0xa0000>; 1362 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1371 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1372 "shared3", "shared4", "shared5", "shared6", 1373 "shared7"; 1374 #mbox-cells = <2>; 1375 }; 1376 1377 p2u_hsio_0: phy@3e10000 { 1378 compatible = "nvidia,tegra194-p2u"; 1379 reg = <0x0 0x03e10000 0x0 0x10000>; 1380 reg-names = "ctl"; 1381 1382 #phy-cells = <0>; 1383 }; 1384 1385 p2u_hsio_1: phy@3e20000 { 1386 compatible = "nvidia,tegra194-p2u"; 1387 reg = <0x0 0x03e20000 0x0 0x10000>; 1388 reg-names = "ctl"; 1389 1390 #phy-cells = <0>; 1391 }; 1392 1393 p2u_hsio_2: phy@3e30000 { 1394 compatible = "nvidia,tegra194-p2u"; 1395 reg = <0x0 0x03e30000 0x0 0x10000>; 1396 reg-names = "ctl"; 1397 1398 #phy-cells = <0>; 1399 }; 1400 1401 p2u_hsio_3: phy@3e40000 { 1402 compatible = "nvidia,tegra194-p2u"; 1403 reg = <0x0 0x03e40000 0x0 0x10000>; 1404 reg-names = "ctl"; 1405 1406 #phy-cells = <0>; 1407 }; 1408 1409 p2u_hsio_4: phy@3e50000 { 1410 compatible = "nvidia,tegra194-p2u"; 1411 reg = <0x0 0x03e50000 0x0 0x10000>; 1412 reg-names = "ctl"; 1413 1414 #phy-cells = <0>; 1415 }; 1416 1417 p2u_hsio_5: phy@3e60000 { 1418 compatible = "nvidia,tegra194-p2u"; 1419 reg = <0x0 0x03e60000 0x0 0x10000>; 1420 reg-names = "ctl"; 1421 1422 #phy-cells = <0>; 1423 }; 1424 1425 p2u_hsio_6: phy@3e70000 { 1426 compatible = "nvidia,tegra194-p2u"; 1427 reg = <0x0 0x03e70000 0x0 0x10000>; 1428 reg-names = "ctl"; 1429 1430 #phy-cells = <0>; 1431 }; 1432 1433 p2u_hsio_7: phy@3e80000 { 1434 compatible = "nvidia,tegra194-p2u"; 1435 reg = <0x0 0x03e80000 0x0 0x10000>; 1436 reg-names = "ctl"; 1437 1438 #phy-cells = <0>; 1439 }; 1440 1441 p2u_hsio_8: phy@3e90000 { 1442 compatible = "nvidia,tegra194-p2u"; 1443 reg = <0x0 0x03e90000 0x0 0x10000>; 1444 reg-names = "ctl"; 1445 1446 #phy-cells = <0>; 1447 }; 1448 1449 p2u_hsio_9: phy@3ea0000 { 1450 compatible = "nvidia,tegra194-p2u"; 1451 reg = <0x0 0x03ea0000 0x0 0x10000>; 1452 reg-names = "ctl"; 1453 1454 #phy-cells = <0>; 1455 }; 1456 1457 p2u_nvhs_0: phy@3eb0000 { 1458 compatible = "nvidia,tegra194-p2u"; 1459 reg = <0x0 0x03eb0000 0x0 0x10000>; 1460 reg-names = "ctl"; 1461 1462 #phy-cells = <0>; 1463 }; 1464 1465 p2u_nvhs_1: phy@3ec0000 { 1466 compatible = "nvidia,tegra194-p2u"; 1467 reg = <0x0 0x03ec0000 0x0 0x10000>; 1468 reg-names = "ctl"; 1469 1470 #phy-cells = <0>; 1471 }; 1472 1473 p2u_nvhs_2: phy@3ed0000 { 1474 compatible = "nvidia,tegra194-p2u"; 1475 reg = <0x0 0x03ed0000 0x0 0x10000>; 1476 reg-names = "ctl"; 1477 1478 #phy-cells = <0>; 1479 }; 1480 1481 p2u_nvhs_3: phy@3ee0000 { 1482 compatible = "nvidia,tegra194-p2u"; 1483 reg = <0x0 0x03ee0000 0x0 0x10000>; 1484 reg-names = "ctl"; 1485 1486 #phy-cells = <0>; 1487 }; 1488 1489 p2u_nvhs_4: phy@3ef0000 { 1490 compatible = "nvidia,tegra194-p2u"; 1491 reg = <0x0 0x03ef0000 0x0 0x10000>; 1492 reg-names = "ctl"; 1493 1494 #phy-cells = <0>; 1495 }; 1496 1497 p2u_nvhs_5: phy@3f00000 { 1498 compatible = "nvidia,tegra194-p2u"; 1499 reg = <0x0 0x03f00000 0x0 0x10000>; 1500 reg-names = "ctl"; 1501 1502 #phy-cells = <0>; 1503 }; 1504 1505 p2u_nvhs_6: phy@3f10000 { 1506 compatible = "nvidia,tegra194-p2u"; 1507 reg = <0x0 0x03f10000 0x0 0x10000>; 1508 reg-names = "ctl"; 1509 1510 #phy-cells = <0>; 1511 }; 1512 1513 p2u_nvhs_7: phy@3f20000 { 1514 compatible = "nvidia,tegra194-p2u"; 1515 reg = <0x0 0x03f20000 0x0 0x10000>; 1516 reg-names = "ctl"; 1517 1518 #phy-cells = <0>; 1519 }; 1520 1521 p2u_hsio_10: phy@3f30000 { 1522 compatible = "nvidia,tegra194-p2u"; 1523 reg = <0x0 0x03f30000 0x0 0x10000>; 1524 reg-names = "ctl"; 1525 1526 #phy-cells = <0>; 1527 }; 1528 1529 p2u_hsio_11: phy@3f40000 { 1530 compatible = "nvidia,tegra194-p2u"; 1531 reg = <0x0 0x03f40000 0x0 0x10000>; 1532 reg-names = "ctl"; 1533 1534 #phy-cells = <0>; 1535 }; 1536 1537 sce-noc@b600000 { 1538 compatible = "nvidia,tegra194-sce-noc"; 1539 reg = <0x0 0xb600000 0x0 0x1000>; 1540 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1542 nvidia,axi2apb = <&axi2apb>; 1543 nvidia,apbmisc = <&apbmisc>; 1544 status = "okay"; 1545 }; 1546 1547 rce-noc@be00000 { 1548 compatible = "nvidia,tegra194-rce-noc"; 1549 reg = <0x0 0xbe00000 0x0 0x1000>; 1550 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1551 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1552 nvidia,axi2apb = <&axi2apb>; 1553 nvidia,apbmisc = <&apbmisc>; 1554 status = "okay"; 1555 }; 1556 1557 hsp_aon: hsp@c150000 { 1558 compatible = "nvidia,tegra194-hsp"; 1559 reg = <0x0 0x0c150000 0x0 0x90000>; 1560 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1564 /* 1565 * Shared interrupt 0 is routed only to AON/SPE, so 1566 * we only have 4 shared interrupts for the CCPLEX. 1567 */ 1568 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1569 #mbox-cells = <2>; 1570 }; 1571 1572 hte_aon: hardware-timestamp@c1e0000 { 1573 compatible = "nvidia,tegra194-gte-aon"; 1574 reg = <0x0 0xc1e0000 0x0 0x10000>; 1575 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1576 nvidia,int-threshold = <1>; 1577 nvidia,slices = <3>; 1578 #timestamp-cells = <1>; 1579 status = "okay"; 1580 }; 1581 1582 gen2_i2c: i2c@c240000 { 1583 compatible = "nvidia,tegra194-i2c"; 1584 reg = <0x0 0x0c240000 0x0 0x10000>; 1585 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1589 clock-names = "div-clk"; 1590 resets = <&bpmp TEGRA194_RESET_I2C2>; 1591 reset-names = "i2c"; 1592 dmas = <&gpcdma 22>, <&gpcdma 22>; 1593 dma-names = "rx", "tx"; 1594 status = "disabled"; 1595 }; 1596 1597 gen8_i2c: i2c@c250000 { 1598 compatible = "nvidia,tegra194-i2c"; 1599 reg = <0x0 0x0c250000 0x0 0x10000>; 1600 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1601 #address-cells = <1>; 1602 #size-cells = <0>; 1603 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1604 clock-names = "div-clk"; 1605 resets = <&bpmp TEGRA194_RESET_I2C8>; 1606 reset-names = "i2c"; 1607 dmas = <&gpcdma 0>, <&gpcdma 0>; 1608 dma-names = "rx", "tx"; 1609 status = "disabled"; 1610 }; 1611 1612 uartc: serial@c280000 { 1613 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1614 reg = <0x0 0x0c280000 0x0 0x40>; 1615 reg-shift = <2>; 1616 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1617 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1618 clock-names = "serial"; 1619 resets = <&bpmp TEGRA194_RESET_UARTC>; 1620 reset-names = "serial"; 1621 status = "disabled"; 1622 }; 1623 1624 uartg: serial@c290000 { 1625 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1626 reg = <0x0 0x0c290000 0x0 0x40>; 1627 reg-shift = <2>; 1628 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1629 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1630 clock-names = "serial"; 1631 resets = <&bpmp TEGRA194_RESET_UARTG>; 1632 reset-names = "serial"; 1633 status = "disabled"; 1634 }; 1635 1636 rtc: rtc@c2a0000 { 1637 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1638 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1639 interrupt-parent = <&pmc>; 1640 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1641 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1642 clock-names = "rtc"; 1643 status = "disabled"; 1644 }; 1645 1646 gpio_aon: gpio@c2f0000 { 1647 compatible = "nvidia,tegra194-gpio-aon"; 1648 reg-names = "security", "gpio"; 1649 reg = <0x0 0xc2f0000 0x0 0x1000>, 1650 <0x0 0xc2f1000 0x0 0x1000>; 1651 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1655 gpio-controller; 1656 #gpio-cells = <2>; 1657 interrupt-controller; 1658 #interrupt-cells = <2>; 1659 gpio-ranges = <&pinmux_aon 0 0 30>; 1660 }; 1661 1662 pinmux_aon: pinmux@c300000 { 1663 compatible = "nvidia,tegra194-pinmux-aon"; 1664 reg = <0x0 0xc300000 0x0 0x4000>; 1665 1666 status = "okay"; 1667 }; 1668 1669 pwm4: pwm@c340000 { 1670 compatible = "nvidia,tegra194-pwm", 1671 "nvidia,tegra186-pwm"; 1672 reg = <0x0 0xc340000 0x0 0x10000>; 1673 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1674 resets = <&bpmp TEGRA194_RESET_PWM4>; 1675 reset-names = "pwm"; 1676 status = "disabled"; 1677 #pwm-cells = <2>; 1678 }; 1679 1680 pmc: pmc@c360000 { 1681 compatible = "nvidia,tegra194-pmc"; 1682 reg = <0x0 0x0c360000 0x0 0x10000>, 1683 <0x0 0x0c370000 0x0 0x10000>, 1684 <0x0 0x0c380000 0x0 0x10000>, 1685 <0x0 0x0c390000 0x0 0x10000>, 1686 <0x0 0x0c3a0000 0x0 0x10000>; 1687 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1688 1689 #interrupt-cells = <2>; 1690 interrupt-controller; 1691 1692 sdmmc1_1v8: sdmmc1-1v8 { 1693 pins = "sdmmc1-hv"; 1694 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1695 }; 1696 1697 sdmmc1_3v3: sdmmc1-3v3 { 1698 pins = "sdmmc1-hv"; 1699 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1700 }; 1701 1702 sdmmc3_1v8: sdmmc3-1v8 { 1703 pins = "sdmmc3-hv"; 1704 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1705 }; 1706 1707 sdmmc3_3v3: sdmmc3-3v3 { 1708 pins = "sdmmc3-hv"; 1709 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1710 }; 1711 }; 1712 1713 aon-noc@c600000 { 1714 compatible = "nvidia,tegra194-aon-noc"; 1715 reg = <0x0 0xc600000 0x0 0x1000>; 1716 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1717 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1718 nvidia,apbmisc = <&apbmisc>; 1719 status = "okay"; 1720 }; 1721 1722 bpmp-noc@d600000 { 1723 compatible = "nvidia,tegra194-bpmp-noc"; 1724 reg = <0x0 0xd600000 0x0 0x1000>; 1725 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1727 nvidia,axi2apb = <&axi2apb>; 1728 nvidia,apbmisc = <&apbmisc>; 1729 status = "okay"; 1730 }; 1731 1732 iommu@10000000 { 1733 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1734 reg = <0x0 0x10000000 0x0 0x800000>; 1735 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1800 stream-match-mask = <0x7f80>; 1801 #global-interrupts = <1>; 1802 #iommu-cells = <1>; 1803 1804 nvidia,memory-controller = <&mc>; 1805 status = "disabled"; 1806 }; 1807 1808 smmu: iommu@12000000 { 1809 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1810 reg = <0x0 0x12000000 0x0 0x800000>, 1811 <0x0 0x11000000 0x0 0x800000>; 1812 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1878 stream-match-mask = <0x7f80>; 1879 #global-interrupts = <2>; 1880 #iommu-cells = <1>; 1881 1882 nvidia,memory-controller = <&mc>; 1883 status = "okay"; 1884 }; 1885 1886 host1x@13e00000 { 1887 compatible = "nvidia,tegra194-host1x"; 1888 reg = <0x0 0x13e00000 0x0 0x10000>, 1889 <0x0 0x13e10000 0x0 0x10000>; 1890 reg-names = "hypervisor", "vm"; 1891 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1893 interrupt-names = "syncpt", "host1x"; 1894 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1895 clock-names = "host1x"; 1896 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1897 reset-names = "host1x"; 1898 1899 #address-cells = <2>; 1900 #size-cells = <2>; 1901 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>; 1902 1903 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1904 interconnect-names = "dma-mem"; 1905 iommus = <&smmu TEGRA194_SID_HOST1X>; 1906 dma-coherent; 1907 1908 /* Context isolation domains */ 1909 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1910 <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1911 <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1912 <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1913 <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1914 <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1915 <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1916 <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1917 1918 nvdec@15140000 { 1919 compatible = "nvidia,tegra194-nvdec"; 1920 reg = <0x0 0x15140000 0x0 0x00040000>; 1921 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1922 clock-names = "nvdec"; 1923 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1924 reset-names = "nvdec"; 1925 1926 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1927 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1928 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1929 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1930 interconnect-names = "dma-mem", "read-1", "write"; 1931 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1932 dma-coherent; 1933 1934 nvidia,host1x-class = <0xf5>; 1935 }; 1936 1937 display-hub@15200000 { 1938 compatible = "nvidia,tegra194-display"; 1939 reg = <0x0 0x15200000 0x0 0x00040000>; 1940 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1941 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1942 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1943 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1944 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1945 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1946 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1947 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1948 "wgrp3", "wgrp4", "wgrp5"; 1949 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1950 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1951 clock-names = "disp", "hub"; 1952 status = "disabled"; 1953 1954 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1955 1956 #address-cells = <2>; 1957 #size-cells = <2>; 1958 ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>; 1959 1960 display@15200000 { 1961 compatible = "nvidia,tegra194-dc"; 1962 reg = <0x0 0x15200000 0x0 0x10000>; 1963 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1964 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1965 clock-names = "dc"; 1966 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1967 reset-names = "dc"; 1968 1969 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1970 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1971 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1972 interconnect-names = "dma-mem", "read-1"; 1973 1974 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1975 nvidia,head = <0>; 1976 }; 1977 1978 display@15210000 { 1979 compatible = "nvidia,tegra194-dc"; 1980 reg = <0x0 0x15210000 0x0 0x10000>; 1981 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1982 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1983 clock-names = "dc"; 1984 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1985 reset-names = "dc"; 1986 1987 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1988 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1989 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1990 interconnect-names = "dma-mem", "read-1"; 1991 1992 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1993 nvidia,head = <1>; 1994 }; 1995 1996 display@15220000 { 1997 compatible = "nvidia,tegra194-dc"; 1998 reg = <0x0 0x15220000 0x0 0x10000>; 1999 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2000 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 2001 clock-names = "dc"; 2002 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 2003 reset-names = "dc"; 2004 2005 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2006 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2007 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2008 interconnect-names = "dma-mem", "read-1"; 2009 2010 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2011 nvidia,head = <2>; 2012 }; 2013 2014 display@15230000 { 2015 compatible = "nvidia,tegra194-dc"; 2016 reg = <0x0 0x15230000 0x0 0x10000>; 2017 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2018 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 2019 clock-names = "dc"; 2020 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 2021 reset-names = "dc"; 2022 2023 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2024 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2025 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2026 interconnect-names = "dma-mem", "read-1"; 2027 2028 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2029 nvidia,head = <3>; 2030 }; 2031 }; 2032 2033 vic@15340000 { 2034 compatible = "nvidia,tegra194-vic"; 2035 reg = <0x0 0x15340000 0x0 0x00040000>; 2036 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2037 clocks = <&bpmp TEGRA194_CLK_VIC>; 2038 clock-names = "vic"; 2039 resets = <&bpmp TEGRA194_RESET_VIC>; 2040 reset-names = "vic"; 2041 2042 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2043 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2044 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2045 interconnect-names = "dma-mem", "write"; 2046 iommus = <&smmu TEGRA194_SID_VIC>; 2047 dma-coherent; 2048 }; 2049 2050 nvjpg@15380000 { 2051 compatible = "nvidia,tegra194-nvjpg"; 2052 reg = <0x0 0x15380000 0x0 0x40000>; 2053 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2054 clock-names = "nvjpg"; 2055 resets = <&bpmp TEGRA194_RESET_NVJPG>; 2056 reset-names = "nvjpg"; 2057 2058 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2059 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2060 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2061 interconnect-names = "dma-mem", "write"; 2062 iommus = <&smmu TEGRA194_SID_NVJPG>; 2063 dma-coherent; 2064 }; 2065 2066 nvdec@15480000 { 2067 compatible = "nvidia,tegra194-nvdec"; 2068 reg = <0x0 0x15480000 0x0 0x00040000>; 2069 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 2070 clock-names = "nvdec"; 2071 resets = <&bpmp TEGRA194_RESET_NVDEC>; 2072 reset-names = "nvdec"; 2073 2074 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 2075 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 2076 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 2077 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 2078 interconnect-names = "dma-mem", "read-1", "write"; 2079 iommus = <&smmu TEGRA194_SID_NVDEC>; 2080 dma-coherent; 2081 2082 nvidia,host1x-class = <0xf0>; 2083 }; 2084 2085 nvenc@154c0000 { 2086 compatible = "nvidia,tegra194-nvenc"; 2087 reg = <0x0 0x154c0000 0x0 0x40000>; 2088 clocks = <&bpmp TEGRA194_CLK_NVENC>; 2089 clock-names = "nvenc"; 2090 resets = <&bpmp TEGRA194_RESET_NVENC>; 2091 reset-names = "nvenc"; 2092 2093 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2094 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2095 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2096 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2097 interconnect-names = "dma-mem", "read-1", "write"; 2098 iommus = <&smmu TEGRA194_SID_NVENC>; 2099 dma-coherent; 2100 2101 nvidia,host1x-class = <0x21>; 2102 }; 2103 2104 dpaux0: dpaux@155c0000 { 2105 compatible = "nvidia,tegra194-dpaux"; 2106 reg = <0x0 0x155c0000 0x0 0x10000>; 2107 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 2108 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 2109 <&bpmp TEGRA194_CLK_PLLDP>; 2110 clock-names = "dpaux", "parent"; 2111 resets = <&bpmp TEGRA194_RESET_DPAUX>; 2112 reset-names = "dpaux"; 2113 status = "disabled"; 2114 2115 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2116 2117 state_dpaux0_aux: pinmux-aux { 2118 groups = "dpaux-io"; 2119 function = "aux"; 2120 }; 2121 2122 state_dpaux0_i2c: pinmux-i2c { 2123 groups = "dpaux-io"; 2124 function = "i2c"; 2125 }; 2126 2127 state_dpaux0_off: pinmux-off { 2128 groups = "dpaux-io"; 2129 function = "off"; 2130 }; 2131 2132 i2c-bus { 2133 #address-cells = <1>; 2134 #size-cells = <0>; 2135 }; 2136 }; 2137 2138 dpaux1: dpaux@155d0000 { 2139 compatible = "nvidia,tegra194-dpaux"; 2140 reg = <0x0 0x155d0000 0x0 0x10000>; 2141 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2142 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 2143 <&bpmp TEGRA194_CLK_PLLDP>; 2144 clock-names = "dpaux", "parent"; 2145 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 2146 reset-names = "dpaux"; 2147 status = "disabled"; 2148 2149 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2150 2151 state_dpaux1_aux: pinmux-aux { 2152 groups = "dpaux-io"; 2153 function = "aux"; 2154 }; 2155 2156 state_dpaux1_i2c: pinmux-i2c { 2157 groups = "dpaux-io"; 2158 function = "i2c"; 2159 }; 2160 2161 state_dpaux1_off: pinmux-off { 2162 groups = "dpaux-io"; 2163 function = "off"; 2164 }; 2165 2166 i2c-bus { 2167 #address-cells = <1>; 2168 #size-cells = <0>; 2169 }; 2170 }; 2171 2172 dpaux2: dpaux@155e0000 { 2173 compatible = "nvidia,tegra194-dpaux"; 2174 reg = <0x0 0x155e0000 0x0 0x10000>; 2175 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2176 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2177 <&bpmp TEGRA194_CLK_PLLDP>; 2178 clock-names = "dpaux", "parent"; 2179 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2180 reset-names = "dpaux"; 2181 status = "disabled"; 2182 2183 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2184 2185 state_dpaux2_aux: pinmux-aux { 2186 groups = "dpaux-io"; 2187 function = "aux"; 2188 }; 2189 2190 state_dpaux2_i2c: pinmux-i2c { 2191 groups = "dpaux-io"; 2192 function = "i2c"; 2193 }; 2194 2195 state_dpaux2_off: pinmux-off { 2196 groups = "dpaux-io"; 2197 function = "off"; 2198 }; 2199 2200 i2c-bus { 2201 #address-cells = <1>; 2202 #size-cells = <0>; 2203 }; 2204 }; 2205 2206 dpaux3: dpaux@155f0000 { 2207 compatible = "nvidia,tegra194-dpaux"; 2208 reg = <0x0 0x155f0000 0x0 0x10000>; 2209 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2210 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2211 <&bpmp TEGRA194_CLK_PLLDP>; 2212 clock-names = "dpaux", "parent"; 2213 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2214 reset-names = "dpaux"; 2215 status = "disabled"; 2216 2217 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2218 2219 state_dpaux3_aux: pinmux-aux { 2220 groups = "dpaux-io"; 2221 function = "aux"; 2222 }; 2223 2224 state_dpaux3_i2c: pinmux-i2c { 2225 groups = "dpaux-io"; 2226 function = "i2c"; 2227 }; 2228 2229 state_dpaux3_off: pinmux-off { 2230 groups = "dpaux-io"; 2231 function = "off"; 2232 }; 2233 2234 i2c-bus { 2235 #address-cells = <1>; 2236 #size-cells = <0>; 2237 }; 2238 }; 2239 2240 nvenc@15a80000 { 2241 compatible = "nvidia,tegra194-nvenc"; 2242 reg = <0x0 0x15a80000 0x0 0x00040000>; 2243 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2244 clock-names = "nvenc"; 2245 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2246 reset-names = "nvenc"; 2247 2248 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2249 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2250 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2251 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2252 interconnect-names = "dma-mem", "read-1", "write"; 2253 iommus = <&smmu TEGRA194_SID_NVENC1>; 2254 dma-coherent; 2255 2256 nvidia,host1x-class = <0x22>; 2257 }; 2258 2259 sor0: sor@15b00000 { 2260 compatible = "nvidia,tegra194-sor"; 2261 reg = <0x0 0x15b00000 0x0 0x40000>; 2262 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2263 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2264 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2265 <&bpmp TEGRA194_CLK_PLLD>, 2266 <&bpmp TEGRA194_CLK_PLLDP>, 2267 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2268 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2269 clock-names = "sor", "out", "parent", "dp", "safe", 2270 "pad"; 2271 resets = <&bpmp TEGRA194_RESET_SOR0>; 2272 reset-names = "sor"; 2273 pinctrl-0 = <&state_dpaux0_aux>; 2274 pinctrl-1 = <&state_dpaux0_i2c>; 2275 pinctrl-2 = <&state_dpaux0_off>; 2276 pinctrl-names = "aux", "i2c", "off"; 2277 status = "disabled"; 2278 2279 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2280 nvidia,interface = <0>; 2281 }; 2282 2283 sor1: sor@15b40000 { 2284 compatible = "nvidia,tegra194-sor"; 2285 reg = <0x0 0x15b40000 0x0 0x40000>; 2286 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2287 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2288 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2289 <&bpmp TEGRA194_CLK_PLLD2>, 2290 <&bpmp TEGRA194_CLK_PLLDP>, 2291 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2292 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2293 clock-names = "sor", "out", "parent", "dp", "safe", 2294 "pad"; 2295 resets = <&bpmp TEGRA194_RESET_SOR1>; 2296 reset-names = "sor"; 2297 pinctrl-0 = <&state_dpaux1_aux>; 2298 pinctrl-1 = <&state_dpaux1_i2c>; 2299 pinctrl-2 = <&state_dpaux1_off>; 2300 pinctrl-names = "aux", "i2c", "off"; 2301 status = "disabled"; 2302 2303 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2304 nvidia,interface = <1>; 2305 }; 2306 2307 sor2: sor@15b80000 { 2308 compatible = "nvidia,tegra194-sor"; 2309 reg = <0x0 0x15b80000 0x0 0x40000>; 2310 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2311 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2312 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2313 <&bpmp TEGRA194_CLK_PLLD3>, 2314 <&bpmp TEGRA194_CLK_PLLDP>, 2315 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2316 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2317 clock-names = "sor", "out", "parent", "dp", "safe", 2318 "pad"; 2319 resets = <&bpmp TEGRA194_RESET_SOR2>; 2320 reset-names = "sor"; 2321 pinctrl-0 = <&state_dpaux2_aux>; 2322 pinctrl-1 = <&state_dpaux2_i2c>; 2323 pinctrl-2 = <&state_dpaux2_off>; 2324 pinctrl-names = "aux", "i2c", "off"; 2325 status = "disabled"; 2326 2327 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2328 nvidia,interface = <2>; 2329 }; 2330 2331 sor3: sor@15bc0000 { 2332 compatible = "nvidia,tegra194-sor"; 2333 reg = <0x0 0x15bc0000 0x0 0x40000>; 2334 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2335 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2336 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2337 <&bpmp TEGRA194_CLK_PLLD4>, 2338 <&bpmp TEGRA194_CLK_PLLDP>, 2339 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2340 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2341 clock-names = "sor", "out", "parent", "dp", "safe", 2342 "pad"; 2343 resets = <&bpmp TEGRA194_RESET_SOR3>; 2344 reset-names = "sor"; 2345 pinctrl-0 = <&state_dpaux3_aux>; 2346 pinctrl-1 = <&state_dpaux3_i2c>; 2347 pinctrl-2 = <&state_dpaux3_off>; 2348 pinctrl-names = "aux", "i2c", "off"; 2349 status = "disabled"; 2350 2351 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2352 nvidia,interface = <3>; 2353 }; 2354 }; 2355 2356 pcie@14100000 { 2357 compatible = "nvidia,tegra194-pcie"; 2358 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2359 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2360 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2361 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2362 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2363 reg-names = "appl", "config", "atu_dma", "dbi"; 2364 2365 status = "disabled"; 2366 2367 #address-cells = <3>; 2368 #size-cells = <2>; 2369 device_type = "pci"; 2370 num-lanes = <1>; 2371 linux,pci-domain = <1>; 2372 2373 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2374 clock-names = "core"; 2375 2376 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2377 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2378 reset-names = "apb", "core"; 2379 2380 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2381 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2382 interrupt-names = "intr", "msi"; 2383 2384 #interrupt-cells = <1>; 2385 interrupt-map-mask = <0 0 0 0>; 2386 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2387 2388 nvidia,bpmp = <&bpmp 1>; 2389 2390 nvidia,aspm-cmrt-us = <60>; 2391 nvidia,aspm-pwr-on-t-us = <20>; 2392 nvidia,aspm-l0s-entrance-latency-us = <3>; 2393 2394 bus-range = <0x0 0xff>; 2395 2396 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2397 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2398 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2399 2400 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2401 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2402 interconnect-names = "dma-mem", "write"; 2403 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2404 iommu-map-mask = <0x0>; 2405 dma-coherent; 2406 }; 2407 2408 pcie@14120000 { 2409 compatible = "nvidia,tegra194-pcie"; 2410 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2411 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2412 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2413 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2414 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2415 reg-names = "appl", "config", "atu_dma", "dbi"; 2416 2417 status = "disabled"; 2418 2419 #address-cells = <3>; 2420 #size-cells = <2>; 2421 device_type = "pci"; 2422 num-lanes = <1>; 2423 linux,pci-domain = <2>; 2424 2425 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2426 clock-names = "core"; 2427 2428 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2429 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2430 reset-names = "apb", "core"; 2431 2432 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2433 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2434 interrupt-names = "intr", "msi"; 2435 2436 #interrupt-cells = <1>; 2437 interrupt-map-mask = <0 0 0 0>; 2438 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2439 2440 nvidia,bpmp = <&bpmp 2>; 2441 2442 nvidia,aspm-cmrt-us = <60>; 2443 nvidia,aspm-pwr-on-t-us = <20>; 2444 nvidia,aspm-l0s-entrance-latency-us = <3>; 2445 2446 bus-range = <0x0 0xff>; 2447 2448 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2449 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2450 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2451 2452 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2453 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2454 interconnect-names = "dma-mem", "write"; 2455 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2456 iommu-map-mask = <0x0>; 2457 dma-coherent; 2458 }; 2459 2460 pcie@14140000 { 2461 compatible = "nvidia,tegra194-pcie"; 2462 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2463 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2464 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2465 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2466 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2467 reg-names = "appl", "config", "atu_dma", "dbi"; 2468 2469 status = "disabled"; 2470 2471 #address-cells = <3>; 2472 #size-cells = <2>; 2473 device_type = "pci"; 2474 num-lanes = <1>; 2475 linux,pci-domain = <3>; 2476 2477 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2478 clock-names = "core"; 2479 2480 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2481 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2482 reset-names = "apb", "core"; 2483 2484 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2485 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2486 interrupt-names = "intr", "msi"; 2487 2488 #interrupt-cells = <1>; 2489 interrupt-map-mask = <0 0 0 0>; 2490 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2491 2492 nvidia,bpmp = <&bpmp 3>; 2493 2494 nvidia,aspm-cmrt-us = <60>; 2495 nvidia,aspm-pwr-on-t-us = <20>; 2496 nvidia,aspm-l0s-entrance-latency-us = <3>; 2497 2498 bus-range = <0x0 0xff>; 2499 2500 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2501 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2502 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2503 2504 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2505 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2506 interconnect-names = "dma-mem", "write"; 2507 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2508 iommu-map-mask = <0x0>; 2509 dma-coherent; 2510 }; 2511 2512 pcie@14160000 { 2513 compatible = "nvidia,tegra194-pcie"; 2514 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2515 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2516 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2517 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2518 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2519 reg-names = "appl", "config", "atu_dma", "dbi"; 2520 2521 status = "disabled"; 2522 2523 #address-cells = <3>; 2524 #size-cells = <2>; 2525 device_type = "pci"; 2526 num-lanes = <4>; 2527 linux,pci-domain = <4>; 2528 2529 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2530 clock-names = "core"; 2531 2532 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2533 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2534 reset-names = "apb", "core"; 2535 2536 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2537 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2538 interrupt-names = "intr", "msi"; 2539 2540 #interrupt-cells = <1>; 2541 interrupt-map-mask = <0 0 0 0>; 2542 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2543 2544 nvidia,bpmp = <&bpmp 4>; 2545 2546 nvidia,aspm-cmrt-us = <60>; 2547 nvidia,aspm-pwr-on-t-us = <20>; 2548 nvidia,aspm-l0s-entrance-latency-us = <3>; 2549 2550 bus-range = <0x0 0xff>; 2551 2552 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2553 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2554 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2555 2556 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2557 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2558 interconnect-names = "dma-mem", "write"; 2559 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2560 iommu-map-mask = <0x0>; 2561 dma-coherent; 2562 }; 2563 2564 pcie-ep@14160000 { 2565 compatible = "nvidia,tegra194-pcie-ep"; 2566 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2567 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2568 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2569 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2570 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2571 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2572 2573 status = "disabled"; 2574 2575 num-lanes = <4>; 2576 num-ib-windows = <2>; 2577 num-ob-windows = <8>; 2578 2579 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2580 clock-names = "core"; 2581 2582 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2583 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2584 reset-names = "apb", "core"; 2585 2586 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2587 interrupt-names = "intr"; 2588 2589 nvidia,bpmp = <&bpmp 4>; 2590 2591 nvidia,aspm-cmrt-us = <60>; 2592 nvidia,aspm-pwr-on-t-us = <20>; 2593 nvidia,aspm-l0s-entrance-latency-us = <3>; 2594 2595 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2596 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2597 interconnect-names = "dma-mem", "write"; 2598 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2599 iommu-map-mask = <0x0>; 2600 dma-coherent; 2601 }; 2602 2603 pcie@14180000 { 2604 compatible = "nvidia,tegra194-pcie"; 2605 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2606 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2607 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2608 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2609 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2610 reg-names = "appl", "config", "atu_dma", "dbi"; 2611 2612 status = "disabled"; 2613 2614 #address-cells = <3>; 2615 #size-cells = <2>; 2616 device_type = "pci"; 2617 num-lanes = <8>; 2618 linux,pci-domain = <0>; 2619 2620 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2621 clock-names = "core"; 2622 2623 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2624 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2625 reset-names = "apb", "core"; 2626 2627 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2628 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2629 interrupt-names = "intr", "msi"; 2630 2631 #interrupt-cells = <1>; 2632 interrupt-map-mask = <0 0 0 0>; 2633 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2634 2635 nvidia,bpmp = <&bpmp 0>; 2636 2637 nvidia,aspm-cmrt-us = <60>; 2638 nvidia,aspm-pwr-on-t-us = <20>; 2639 nvidia,aspm-l0s-entrance-latency-us = <3>; 2640 2641 bus-range = <0x0 0xff>; 2642 2643 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2644 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2645 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2646 2647 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2648 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2649 interconnect-names = "dma-mem", "write"; 2650 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2651 iommu-map-mask = <0x0>; 2652 dma-coherent; 2653 }; 2654 2655 pcie-ep@14180000 { 2656 compatible = "nvidia,tegra194-pcie-ep"; 2657 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2658 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2659 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2660 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2661 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2662 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2663 2664 status = "disabled"; 2665 2666 num-lanes = <8>; 2667 num-ib-windows = <2>; 2668 num-ob-windows = <8>; 2669 2670 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2671 clock-names = "core"; 2672 2673 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2674 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2675 reset-names = "apb", "core"; 2676 2677 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2678 interrupt-names = "intr"; 2679 2680 nvidia,bpmp = <&bpmp 0>; 2681 2682 nvidia,aspm-cmrt-us = <60>; 2683 nvidia,aspm-pwr-on-t-us = <20>; 2684 nvidia,aspm-l0s-entrance-latency-us = <3>; 2685 2686 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2687 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2688 interconnect-names = "dma-mem", "write"; 2689 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2690 iommu-map-mask = <0x0>; 2691 dma-coherent; 2692 }; 2693 2694 pcie@141a0000 { 2695 compatible = "nvidia,tegra194-pcie"; 2696 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2697 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2698 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2699 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2700 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2701 reg-names = "appl", "config", "atu_dma", "dbi"; 2702 2703 status = "disabled"; 2704 2705 #address-cells = <3>; 2706 #size-cells = <2>; 2707 device_type = "pci"; 2708 num-lanes = <8>; 2709 linux,pci-domain = <5>; 2710 2711 pinctrl-names = "default"; 2712 pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>; 2713 2714 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2715 clock-names = "core"; 2716 2717 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2718 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2719 reset-names = "apb", "core"; 2720 2721 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2722 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2723 interrupt-names = "intr", "msi"; 2724 2725 nvidia,bpmp = <&bpmp 5>; 2726 2727 #interrupt-cells = <1>; 2728 interrupt-map-mask = <0 0 0 0>; 2729 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2730 2731 nvidia,aspm-cmrt-us = <60>; 2732 nvidia,aspm-pwr-on-t-us = <20>; 2733 nvidia,aspm-l0s-entrance-latency-us = <3>; 2734 2735 bus-range = <0x0 0xff>; 2736 2737 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2738 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2739 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2740 2741 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2742 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2743 interconnect-names = "dma-mem", "write"; 2744 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2745 iommu-map-mask = <0x0>; 2746 dma-coherent; 2747 }; 2748 2749 pcie-ep@141a0000 { 2750 compatible = "nvidia,tegra194-pcie-ep"; 2751 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2752 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2753 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2754 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2755 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2756 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2757 2758 status = "disabled"; 2759 2760 num-lanes = <8>; 2761 num-ib-windows = <2>; 2762 num-ob-windows = <8>; 2763 2764 pinctrl-names = "default"; 2765 pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>; 2766 2767 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2768 clock-names = "core"; 2769 2770 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2771 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2772 reset-names = "apb", "core"; 2773 2774 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2775 interrupt-names = "intr"; 2776 2777 nvidia,bpmp = <&bpmp 5>; 2778 2779 nvidia,aspm-cmrt-us = <60>; 2780 nvidia,aspm-pwr-on-t-us = <20>; 2781 nvidia,aspm-l0s-entrance-latency-us = <3>; 2782 2783 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2784 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2785 interconnect-names = "dma-mem", "write"; 2786 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2787 iommu-map-mask = <0x0>; 2788 dma-coherent; 2789 }; 2790 2791 gpu@17000000 { 2792 compatible = "nvidia,gv11b"; 2793 reg = <0x0 0x17000000 0x0 0x1000000>, 2794 <0x0 0x18000000 0x0 0x1000000>; 2795 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2796 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2797 interrupt-names = "stall", "nonstall"; 2798 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2799 <&bpmp TEGRA194_CLK_GPU_PWR>, 2800 <&bpmp TEGRA194_CLK_FUSE>; 2801 clock-names = "gpu", "pwr", "fuse"; 2802 resets = <&bpmp TEGRA194_RESET_GPU>; 2803 reset-names = "gpu"; 2804 dma-coherent; 2805 2806 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2807 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2808 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2809 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2810 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2811 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2812 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2813 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2814 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2815 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2816 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2817 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2818 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2819 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2820 "read-1", "read-1-hp", "write-1", 2821 "read-2", "read-2-hp", "write-2", 2822 "read-3", "read-3-hp", "write-3"; 2823 }; 2824 }; 2825 2826 sram@40000000 { 2827 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2828 reg = <0x0 0x40000000 0x0 0x50000>; 2829 2830 #address-cells = <1>; 2831 #size-cells = <1>; 2832 ranges = <0x0 0x0 0x40000000 0x50000>; 2833 2834 no-memory-wc; 2835 2836 cpu_bpmp_tx: sram@4e000 { 2837 reg = <0x4e000 0x1000>; 2838 label = "cpu-bpmp-tx"; 2839 pool; 2840 }; 2841 2842 cpu_bpmp_rx: sram@4f000 { 2843 reg = <0x4f000 0x1000>; 2844 label = "cpu-bpmp-rx"; 2845 pool; 2846 }; 2847 }; 2848 2849 bpmp: bpmp { 2850 compatible = "nvidia,tegra186-bpmp"; 2851 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2852 TEGRA_HSP_DB_MASTER_BPMP>; 2853 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2854 #clock-cells = <1>; 2855 #reset-cells = <1>; 2856 #power-domain-cells = <1>; 2857 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2858 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2859 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2860 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2861 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2862 iommus = <&smmu TEGRA194_SID_BPMP>; 2863 2864 bpmp_i2c: i2c { 2865 compatible = "nvidia,tegra186-bpmp-i2c"; 2866 nvidia,bpmp-bus-id = <5>; 2867 #address-cells = <1>; 2868 #size-cells = <0>; 2869 }; 2870 2871 bpmp_thermal: thermal { 2872 compatible = "nvidia,tegra186-bpmp-thermal"; 2873 #thermal-sensor-cells = <1>; 2874 }; 2875 }; 2876 2877 cpus { 2878 compatible = "nvidia,tegra194-ccplex"; 2879 nvidia,bpmp = <&bpmp>; 2880 #address-cells = <1>; 2881 #size-cells = <0>; 2882 2883 cpu0_0: cpu@0 { 2884 compatible = "nvidia,tegra194-carmel"; 2885 device_type = "cpu"; 2886 reg = <0x000>; 2887 enable-method = "psci"; 2888 i-cache-size = <131072>; 2889 i-cache-line-size = <64>; 2890 i-cache-sets = <512>; 2891 d-cache-size = <65536>; 2892 d-cache-line-size = <64>; 2893 d-cache-sets = <256>; 2894 next-level-cache = <&l2c_0>; 2895 }; 2896 2897 cpu0_1: cpu@1 { 2898 compatible = "nvidia,tegra194-carmel"; 2899 device_type = "cpu"; 2900 reg = <0x001>; 2901 enable-method = "psci"; 2902 i-cache-size = <131072>; 2903 i-cache-line-size = <64>; 2904 i-cache-sets = <512>; 2905 d-cache-size = <65536>; 2906 d-cache-line-size = <64>; 2907 d-cache-sets = <256>; 2908 next-level-cache = <&l2c_0>; 2909 }; 2910 2911 cpu1_0: cpu@100 { 2912 compatible = "nvidia,tegra194-carmel"; 2913 device_type = "cpu"; 2914 reg = <0x100>; 2915 enable-method = "psci"; 2916 i-cache-size = <131072>; 2917 i-cache-line-size = <64>; 2918 i-cache-sets = <512>; 2919 d-cache-size = <65536>; 2920 d-cache-line-size = <64>; 2921 d-cache-sets = <256>; 2922 next-level-cache = <&l2c_1>; 2923 }; 2924 2925 cpu1_1: cpu@101 { 2926 compatible = "nvidia,tegra194-carmel"; 2927 device_type = "cpu"; 2928 reg = <0x101>; 2929 enable-method = "psci"; 2930 i-cache-size = <131072>; 2931 i-cache-line-size = <64>; 2932 i-cache-sets = <512>; 2933 d-cache-size = <65536>; 2934 d-cache-line-size = <64>; 2935 d-cache-sets = <256>; 2936 next-level-cache = <&l2c_1>; 2937 }; 2938 2939 cpu2_0: cpu@200 { 2940 compatible = "nvidia,tegra194-carmel"; 2941 device_type = "cpu"; 2942 reg = <0x200>; 2943 enable-method = "psci"; 2944 i-cache-size = <131072>; 2945 i-cache-line-size = <64>; 2946 i-cache-sets = <512>; 2947 d-cache-size = <65536>; 2948 d-cache-line-size = <64>; 2949 d-cache-sets = <256>; 2950 next-level-cache = <&l2c_2>; 2951 }; 2952 2953 cpu2_1: cpu@201 { 2954 compatible = "nvidia,tegra194-carmel"; 2955 device_type = "cpu"; 2956 reg = <0x201>; 2957 enable-method = "psci"; 2958 i-cache-size = <131072>; 2959 i-cache-line-size = <64>; 2960 i-cache-sets = <512>; 2961 d-cache-size = <65536>; 2962 d-cache-line-size = <64>; 2963 d-cache-sets = <256>; 2964 next-level-cache = <&l2c_2>; 2965 }; 2966 2967 cpu3_0: cpu@300 { 2968 compatible = "nvidia,tegra194-carmel"; 2969 device_type = "cpu"; 2970 reg = <0x300>; 2971 enable-method = "psci"; 2972 i-cache-size = <131072>; 2973 i-cache-line-size = <64>; 2974 i-cache-sets = <512>; 2975 d-cache-size = <65536>; 2976 d-cache-line-size = <64>; 2977 d-cache-sets = <256>; 2978 next-level-cache = <&l2c_3>; 2979 }; 2980 2981 cpu3_1: cpu@301 { 2982 compatible = "nvidia,tegra194-carmel"; 2983 device_type = "cpu"; 2984 reg = <0x301>; 2985 enable-method = "psci"; 2986 i-cache-size = <131072>; 2987 i-cache-line-size = <64>; 2988 i-cache-sets = <512>; 2989 d-cache-size = <65536>; 2990 d-cache-line-size = <64>; 2991 d-cache-sets = <256>; 2992 next-level-cache = <&l2c_3>; 2993 }; 2994 2995 cpu-map { 2996 cluster0 { 2997 core0 { 2998 cpu = <&cpu0_0>; 2999 }; 3000 3001 core1 { 3002 cpu = <&cpu0_1>; 3003 }; 3004 }; 3005 3006 cluster1 { 3007 core0 { 3008 cpu = <&cpu1_0>; 3009 }; 3010 3011 core1 { 3012 cpu = <&cpu1_1>; 3013 }; 3014 }; 3015 3016 cluster2 { 3017 core0 { 3018 cpu = <&cpu2_0>; 3019 }; 3020 3021 core1 { 3022 cpu = <&cpu2_1>; 3023 }; 3024 }; 3025 3026 cluster3 { 3027 core0 { 3028 cpu = <&cpu3_0>; 3029 }; 3030 3031 core1 { 3032 cpu = <&cpu3_1>; 3033 }; 3034 }; 3035 }; 3036 3037 l2c_0: l2-cache0 { 3038 compatible = "cache"; 3039 cache-unified; 3040 cache-size = <2097152>; 3041 cache-line-size = <64>; 3042 cache-sets = <2048>; 3043 cache-level = <2>; 3044 next-level-cache = <&l3c>; 3045 }; 3046 3047 l2c_1: l2-cache1 { 3048 compatible = "cache"; 3049 cache-unified; 3050 cache-size = <2097152>; 3051 cache-line-size = <64>; 3052 cache-sets = <2048>; 3053 cache-level = <2>; 3054 next-level-cache = <&l3c>; 3055 }; 3056 3057 l2c_2: l2-cache2 { 3058 compatible = "cache"; 3059 cache-unified; 3060 cache-size = <2097152>; 3061 cache-line-size = <64>; 3062 cache-sets = <2048>; 3063 cache-level = <2>; 3064 next-level-cache = <&l3c>; 3065 }; 3066 3067 l2c_3: l2-cache3 { 3068 compatible = "cache"; 3069 cache-unified; 3070 cache-size = <2097152>; 3071 cache-line-size = <64>; 3072 cache-sets = <2048>; 3073 cache-level = <2>; 3074 next-level-cache = <&l3c>; 3075 }; 3076 3077 l3c: l3-cache { 3078 compatible = "cache"; 3079 cache-unified; 3080 cache-size = <4194304>; 3081 cache-line-size = <64>; 3082 cache-level = <3>; 3083 cache-sets = <4096>; 3084 }; 3085 }; 3086 3087 pmu { 3088 compatible = "nvidia,carmel-pmu"; 3089 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 3090 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 3091 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 3092 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 3093 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 3094 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 3095 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 3096 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 3097 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 3098 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 3099 }; 3100 3101 psci { 3102 compatible = "arm,psci-1.0"; 3103 status = "okay"; 3104 method = "smc"; 3105 }; 3106 3107 tcu: serial { 3108 compatible = "nvidia,tegra194-tcu"; 3109 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3110 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3111 mbox-names = "rx", "tx"; 3112 }; 3113 3114 sound { 3115 status = "disabled"; 3116 3117 clocks = <&bpmp TEGRA194_CLK_PLLA>, 3118 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3119 clock-names = "pll_a", "plla_out0"; 3120 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 3121 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 3122 <&bpmp TEGRA194_CLK_AUD_MCLK>; 3123 assigned-clock-parents = <0>, 3124 <&bpmp TEGRA194_CLK_PLLA>, 3125 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3126 /* 3127 * PLLA supports dynamic ramp. Below initial rate is chosen 3128 * for this to work and oscillate between base rates required 3129 * for 8x and 11.025x sample rate streams. 3130 */ 3131 assigned-clock-rates = <258000000>; 3132 }; 3133 3134 thermal-zones { 3135 cpu-thermal { 3136 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3137 status = "disabled"; 3138 }; 3139 3140 gpu-thermal { 3141 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3142 status = "disabled"; 3143 }; 3144 3145 aux-thermal { 3146 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3147 status = "disabled"; 3148 }; 3149 3150 pllx-thermal { 3151 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3152 status = "disabled"; 3153 }; 3154 3155 ao-thermal { 3156 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3157 status = "disabled"; 3158 }; 3159 3160 tj-thermal { 3161 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3162 status = "disabled"; 3163 }; 3164 }; 3165 3166 timer { 3167 compatible = "arm,armv8-timer"; 3168 interrupts = <GIC_PPI 13 3169 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3170 <GIC_PPI 14 3171 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3172 <GIC_PPI 11 3173 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3174 <GIC_PPI 10 3175 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3176 interrupt-parent = <&gic>; 3177 always-on; 3178 }; 3179}; 3180