1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/reset/tegra194-reset.h> 9#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10#include <dt-bindings/memory/tegra194-mc.h> 11 12/ { 13 compatible = "nvidia,tegra194"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* control backbone */ 19 bus@0 { 20 compatible = "simple-bus"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges = <0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra194-misc"; 27 reg = <0x00100000 0xf000>, 28 <0x0010f000 0x1000>; 29 }; 30 31 gpio: gpio@2200000 { 32 compatible = "nvidia,tegra194-gpio"; 33 reg-names = "security", "gpio"; 34 reg = <0x2200000 0x10000>, 35 <0x2210000 0x10000>; 36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 42 #interrupt-cells = <2>; 43 interrupt-controller; 44 #gpio-cells = <2>; 45 gpio-controller; 46 }; 47 48 ethernet@2490000 { 49 compatible = "nvidia,tegra194-eqos", 50 "nvidia,tegra186-eqos", 51 "snps,dwc-qos-ethernet-4.10"; 52 reg = <0x02490000 0x10000>; 53 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 54 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 55 <&bpmp TEGRA194_CLK_EQOS_AXI>, 56 <&bpmp TEGRA194_CLK_EQOS_RX>, 57 <&bpmp TEGRA194_CLK_EQOS_TX>, 58 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60 resets = <&bpmp TEGRA194_RESET_EQOS>; 61 reset-names = "eqos"; 62 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 63 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 64 interconnect-names = "dma-mem", "write"; 65 status = "disabled"; 66 67 snps,write-requests = <1>; 68 snps,read-requests = <3>; 69 snps,burst-map = <0x7>; 70 snps,txpbl = <16>; 71 snps,rxpbl = <8>; 72 }; 73 74 aconnect@2900000 { 75 compatible = "nvidia,tegra194-aconnect", 76 "nvidia,tegra210-aconnect"; 77 clocks = <&bpmp TEGRA194_CLK_APE>, 78 <&bpmp TEGRA194_CLK_APB2APE>; 79 clock-names = "ape", "apb2ape"; 80 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges = <0x02900000 0x02900000 0x200000>; 84 status = "disabled"; 85 86 adma: dma-controller@2930000 { 87 compatible = "nvidia,tegra194-adma", 88 "nvidia,tegra186-adma"; 89 reg = <0x02930000 0x20000>; 90 interrupt-parent = <&agic>; 91 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 123 #dma-cells = <1>; 124 clocks = <&bpmp TEGRA194_CLK_AHUB>; 125 clock-names = "d_audio"; 126 status = "disabled"; 127 }; 128 129 agic: interrupt-controller@2a40000 { 130 compatible = "nvidia,tegra194-agic", 131 "nvidia,tegra210-agic"; 132 #interrupt-cells = <3>; 133 interrupt-controller; 134 reg = <0x02a41000 0x1000>, 135 <0x02a42000 0x2000>; 136 interrupts = <GIC_SPI 145 137 (GIC_CPU_MASK_SIMPLE(4) | 138 IRQ_TYPE_LEVEL_HIGH)>; 139 clocks = <&bpmp TEGRA194_CLK_APE>; 140 clock-names = "clk"; 141 status = "disabled"; 142 }; 143 144 tegra_ahub: ahub@2900800 { 145 compatible = "nvidia,tegra194-ahub", 146 "nvidia,tegra186-ahub"; 147 reg = <0x02900800 0x800>; 148 clocks = <&bpmp TEGRA194_CLK_AHUB>; 149 clock-names = "ahub"; 150 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 151 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 152 #address-cells = <1>; 153 #size-cells = <1>; 154 ranges = <0x02900800 0x02900800 0x11800>; 155 status = "disabled"; 156 157 tegra_admaif: admaif@290f000 { 158 compatible = "nvidia,tegra194-admaif", 159 "nvidia,tegra186-admaif"; 160 reg = <0x0290f000 0x1000>; 161 dmas = <&adma 1>, <&adma 1>, 162 <&adma 2>, <&adma 2>, 163 <&adma 3>, <&adma 3>, 164 <&adma 4>, <&adma 4>, 165 <&adma 5>, <&adma 5>, 166 <&adma 6>, <&adma 6>, 167 <&adma 7>, <&adma 7>, 168 <&adma 8>, <&adma 8>, 169 <&adma 9>, <&adma 9>, 170 <&adma 10>, <&adma 10>, 171 <&adma 11>, <&adma 11>, 172 <&adma 12>, <&adma 12>, 173 <&adma 13>, <&adma 13>, 174 <&adma 14>, <&adma 14>, 175 <&adma 15>, <&adma 15>, 176 <&adma 16>, <&adma 16>, 177 <&adma 17>, <&adma 17>, 178 <&adma 18>, <&adma 18>, 179 <&adma 19>, <&adma 19>, 180 <&adma 20>, <&adma 20>; 181 dma-names = "rx1", "tx1", 182 "rx2", "tx2", 183 "rx3", "tx3", 184 "rx4", "tx4", 185 "rx5", "tx5", 186 "rx6", "tx6", 187 "rx7", "tx7", 188 "rx8", "tx8", 189 "rx9", "tx9", 190 "rx10", "tx10", 191 "rx11", "tx11", 192 "rx12", "tx12", 193 "rx13", "tx13", 194 "rx14", "tx14", 195 "rx15", "tx15", 196 "rx16", "tx16", 197 "rx17", "tx17", 198 "rx18", "tx18", 199 "rx19", "tx19", 200 "rx20", "tx20"; 201 status = "disabled"; 202 }; 203 204 tegra_i2s1: i2s@2901000 { 205 compatible = "nvidia,tegra194-i2s", 206 "nvidia,tegra210-i2s"; 207 reg = <0x2901000 0x100>; 208 clocks = <&bpmp TEGRA194_CLK_I2S1>, 209 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 210 clock-names = "i2s", "sync_input"; 211 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 212 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 213 assigned-clock-rates = <1536000>; 214 sound-name-prefix = "I2S1"; 215 status = "disabled"; 216 }; 217 218 tegra_i2s2: i2s@2901100 { 219 compatible = "nvidia,tegra194-i2s", 220 "nvidia,tegra210-i2s"; 221 reg = <0x2901100 0x100>; 222 clocks = <&bpmp TEGRA194_CLK_I2S2>, 223 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 224 clock-names = "i2s", "sync_input"; 225 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 226 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 227 assigned-clock-rates = <1536000>; 228 sound-name-prefix = "I2S2"; 229 status = "disabled"; 230 }; 231 232 tegra_i2s3: i2s@2901200 { 233 compatible = "nvidia,tegra194-i2s", 234 "nvidia,tegra210-i2s"; 235 reg = <0x2901200 0x100>; 236 clocks = <&bpmp TEGRA194_CLK_I2S3>, 237 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 238 clock-names = "i2s", "sync_input"; 239 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 240 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 241 assigned-clock-rates = <1536000>; 242 sound-name-prefix = "I2S3"; 243 status = "disabled"; 244 }; 245 246 tegra_i2s4: i2s@2901300 { 247 compatible = "nvidia,tegra194-i2s", 248 "nvidia,tegra210-i2s"; 249 reg = <0x2901300 0x100>; 250 clocks = <&bpmp TEGRA194_CLK_I2S4>, 251 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 252 clock-names = "i2s", "sync_input"; 253 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 254 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 255 assigned-clock-rates = <1536000>; 256 sound-name-prefix = "I2S4"; 257 status = "disabled"; 258 }; 259 260 tegra_i2s5: i2s@2901400 { 261 compatible = "nvidia,tegra194-i2s", 262 "nvidia,tegra210-i2s"; 263 reg = <0x2901400 0x100>; 264 clocks = <&bpmp TEGRA194_CLK_I2S5>, 265 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 266 clock-names = "i2s", "sync_input"; 267 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 268 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 269 assigned-clock-rates = <1536000>; 270 sound-name-prefix = "I2S5"; 271 status = "disabled"; 272 }; 273 274 tegra_i2s6: i2s@2901500 { 275 compatible = "nvidia,tegra194-i2s", 276 "nvidia,tegra210-i2s"; 277 reg = <0x2901500 0x100>; 278 clocks = <&bpmp TEGRA194_CLK_I2S6>, 279 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 280 clock-names = "i2s", "sync_input"; 281 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 282 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 283 assigned-clock-rates = <1536000>; 284 sound-name-prefix = "I2S6"; 285 status = "disabled"; 286 }; 287 288 tegra_dmic1: dmic@2904000 { 289 compatible = "nvidia,tegra194-dmic", 290 "nvidia,tegra210-dmic"; 291 reg = <0x2904000 0x100>; 292 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 293 clock-names = "dmic"; 294 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 295 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 296 assigned-clock-rates = <3072000>; 297 sound-name-prefix = "DMIC1"; 298 status = "disabled"; 299 }; 300 301 tegra_dmic2: dmic@2904100 { 302 compatible = "nvidia,tegra194-dmic", 303 "nvidia,tegra210-dmic"; 304 reg = <0x2904100 0x100>; 305 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 306 clock-names = "dmic"; 307 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 308 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 309 assigned-clock-rates = <3072000>; 310 sound-name-prefix = "DMIC2"; 311 status = "disabled"; 312 }; 313 314 tegra_dmic3: dmic@2904200 { 315 compatible = "nvidia,tegra194-dmic", 316 "nvidia,tegra210-dmic"; 317 reg = <0x2904200 0x100>; 318 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 319 clock-names = "dmic"; 320 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 321 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 322 assigned-clock-rates = <3072000>; 323 sound-name-prefix = "DMIC3"; 324 status = "disabled"; 325 }; 326 327 tegra_dmic4: dmic@2904300 { 328 compatible = "nvidia,tegra194-dmic", 329 "nvidia,tegra210-dmic"; 330 reg = <0x2904300 0x100>; 331 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 332 clock-names = "dmic"; 333 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 334 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 335 assigned-clock-rates = <3072000>; 336 sound-name-prefix = "DMIC4"; 337 status = "disabled"; 338 }; 339 340 tegra_dspk1: dspk@2905000 { 341 compatible = "nvidia,tegra194-dspk", 342 "nvidia,tegra186-dspk"; 343 reg = <0x2905000 0x100>; 344 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 345 clock-names = "dspk"; 346 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 347 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 348 assigned-clock-rates = <12288000>; 349 sound-name-prefix = "DSPK1"; 350 status = "disabled"; 351 }; 352 353 tegra_dspk2: dspk@2905100 { 354 compatible = "nvidia,tegra194-dspk", 355 "nvidia,tegra186-dspk"; 356 reg = <0x2905100 0x100>; 357 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 358 clock-names = "dspk"; 359 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 360 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 361 assigned-clock-rates = <12288000>; 362 sound-name-prefix = "DSPK2"; 363 status = "disabled"; 364 }; 365 }; 366 }; 367 368 pinmux: pinmux@2430000 { 369 compatible = "nvidia,tegra194-pinmux"; 370 reg = <0x2430000 0x17000>, 371 <0xc300000 0x4000>; 372 373 status = "okay"; 374 375 pex_rst_c5_out_state: pex_rst_c5_out { 376 pex_rst { 377 nvidia,pins = "pex_l5_rst_n_pgg1"; 378 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 379 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 380 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 381 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 382 nvidia,tristate = <TEGRA_PIN_DISABLE>; 383 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 384 }; 385 }; 386 387 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 388 clkreq { 389 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 390 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 391 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 392 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 393 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 394 nvidia,tristate = <TEGRA_PIN_DISABLE>; 395 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 396 }; 397 }; 398 }; 399 400 mc: memory-controller@2c00000 { 401 compatible = "nvidia,tegra194-mc"; 402 reg = <0x02c00000 0x100000>, 403 <0x02b80000 0x040000>, 404 <0x01700000 0x100000>; 405 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 406 #interconnect-cells = <1>; 407 status = "disabled"; 408 409 #address-cells = <2>; 410 #size-cells = <2>; 411 412 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 413 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 414 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 415 416 /* 417 * Bit 39 of addresses passing through the memory 418 * controller selects the XBAR format used when memory 419 * is accessed. This is used to transparently access 420 * memory in the XBAR format used by the discrete GPU 421 * (bit 39 set) or Tegra (bit 39 clear). 422 * 423 * As a consequence, the operating system must ensure 424 * that bit 39 is never used implicitly, for example 425 * via an I/O virtual address mapping of an IOMMU. If 426 * devices require access to the XBAR switch, their 427 * drivers must set this bit explicitly. 428 * 429 * Limit the DMA range for memory clients to [38:0]. 430 */ 431 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 432 433 emc: external-memory-controller@2c60000 { 434 compatible = "nvidia,tegra194-emc"; 435 reg = <0x0 0x02c60000 0x0 0x90000>, 436 <0x0 0x01780000 0x0 0x80000>; 437 clocks = <&bpmp TEGRA194_CLK_EMC>; 438 clock-names = "emc"; 439 440 #interconnect-cells = <0>; 441 442 nvidia,bpmp = <&bpmp>; 443 }; 444 }; 445 446 uarta: serial@3100000 { 447 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 448 reg = <0x03100000 0x40>; 449 reg-shift = <2>; 450 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&bpmp TEGRA194_CLK_UARTA>; 452 clock-names = "serial"; 453 resets = <&bpmp TEGRA194_RESET_UARTA>; 454 reset-names = "serial"; 455 status = "disabled"; 456 }; 457 458 uartb: serial@3110000 { 459 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 460 reg = <0x03110000 0x40>; 461 reg-shift = <2>; 462 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&bpmp TEGRA194_CLK_UARTB>; 464 clock-names = "serial"; 465 resets = <&bpmp TEGRA194_RESET_UARTB>; 466 reset-names = "serial"; 467 status = "disabled"; 468 }; 469 470 uartd: serial@3130000 { 471 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 472 reg = <0x03130000 0x40>; 473 reg-shift = <2>; 474 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&bpmp TEGRA194_CLK_UARTD>; 476 clock-names = "serial"; 477 resets = <&bpmp TEGRA194_RESET_UARTD>; 478 reset-names = "serial"; 479 status = "disabled"; 480 }; 481 482 uarte: serial@3140000 { 483 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 484 reg = <0x03140000 0x40>; 485 reg-shift = <2>; 486 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&bpmp TEGRA194_CLK_UARTE>; 488 clock-names = "serial"; 489 resets = <&bpmp TEGRA194_RESET_UARTE>; 490 reset-names = "serial"; 491 status = "disabled"; 492 }; 493 494 uartf: serial@3150000 { 495 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 496 reg = <0x03150000 0x40>; 497 reg-shift = <2>; 498 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&bpmp TEGRA194_CLK_UARTF>; 500 clock-names = "serial"; 501 resets = <&bpmp TEGRA194_RESET_UARTF>; 502 reset-names = "serial"; 503 status = "disabled"; 504 }; 505 506 gen1_i2c: i2c@3160000 { 507 compatible = "nvidia,tegra194-i2c"; 508 reg = <0x03160000 0x10000>; 509 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 clocks = <&bpmp TEGRA194_CLK_I2C1>; 513 clock-names = "div-clk"; 514 resets = <&bpmp TEGRA194_RESET_I2C1>; 515 reset-names = "i2c"; 516 status = "disabled"; 517 }; 518 519 uarth: serial@3170000 { 520 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 521 reg = <0x03170000 0x40>; 522 reg-shift = <2>; 523 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&bpmp TEGRA194_CLK_UARTH>; 525 clock-names = "serial"; 526 resets = <&bpmp TEGRA194_RESET_UARTH>; 527 reset-names = "serial"; 528 status = "disabled"; 529 }; 530 531 cam_i2c: i2c@3180000 { 532 compatible = "nvidia,tegra194-i2c"; 533 reg = <0x03180000 0x10000>; 534 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 clocks = <&bpmp TEGRA194_CLK_I2C3>; 538 clock-names = "div-clk"; 539 resets = <&bpmp TEGRA194_RESET_I2C3>; 540 reset-names = "i2c"; 541 status = "disabled"; 542 }; 543 544 /* shares pads with dpaux1 */ 545 dp_aux_ch1_i2c: i2c@3190000 { 546 compatible = "nvidia,tegra194-i2c"; 547 reg = <0x03190000 0x10000>; 548 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 clocks = <&bpmp TEGRA194_CLK_I2C4>; 552 clock-names = "div-clk"; 553 resets = <&bpmp TEGRA194_RESET_I2C4>; 554 reset-names = "i2c"; 555 pinctrl-0 = <&state_dpaux1_i2c>; 556 pinctrl-1 = <&state_dpaux1_off>; 557 pinctrl-names = "default", "idle"; 558 status = "disabled"; 559 }; 560 561 /* shares pads with dpaux0 */ 562 dp_aux_ch0_i2c: i2c@31b0000 { 563 compatible = "nvidia,tegra194-i2c"; 564 reg = <0x031b0000 0x10000>; 565 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 clocks = <&bpmp TEGRA194_CLK_I2C6>; 569 clock-names = "div-clk"; 570 resets = <&bpmp TEGRA194_RESET_I2C6>; 571 reset-names = "i2c"; 572 pinctrl-0 = <&state_dpaux0_i2c>; 573 pinctrl-1 = <&state_dpaux0_off>; 574 pinctrl-names = "default", "idle"; 575 status = "disabled"; 576 }; 577 578 /* shares pads with dpaux2 */ 579 dp_aux_ch2_i2c: i2c@31c0000 { 580 compatible = "nvidia,tegra194-i2c"; 581 reg = <0x031c0000 0x10000>; 582 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 clocks = <&bpmp TEGRA194_CLK_I2C7>; 586 clock-names = "div-clk"; 587 resets = <&bpmp TEGRA194_RESET_I2C7>; 588 reset-names = "i2c"; 589 pinctrl-0 = <&state_dpaux2_i2c>; 590 pinctrl-1 = <&state_dpaux2_off>; 591 pinctrl-names = "default", "idle"; 592 status = "disabled"; 593 }; 594 595 /* shares pads with dpaux3 */ 596 dp_aux_ch3_i2c: i2c@31e0000 { 597 compatible = "nvidia,tegra194-i2c"; 598 reg = <0x031e0000 0x10000>; 599 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 clocks = <&bpmp TEGRA194_CLK_I2C9>; 603 clock-names = "div-clk"; 604 resets = <&bpmp TEGRA194_RESET_I2C9>; 605 reset-names = "i2c"; 606 pinctrl-0 = <&state_dpaux3_i2c>; 607 pinctrl-1 = <&state_dpaux3_off>; 608 pinctrl-names = "default", "idle"; 609 status = "disabled"; 610 }; 611 612 pwm1: pwm@3280000 { 613 compatible = "nvidia,tegra194-pwm", 614 "nvidia,tegra186-pwm"; 615 reg = <0x3280000 0x10000>; 616 clocks = <&bpmp TEGRA194_CLK_PWM1>; 617 clock-names = "pwm"; 618 resets = <&bpmp TEGRA194_RESET_PWM1>; 619 reset-names = "pwm"; 620 status = "disabled"; 621 #pwm-cells = <2>; 622 }; 623 624 pwm2: pwm@3290000 { 625 compatible = "nvidia,tegra194-pwm", 626 "nvidia,tegra186-pwm"; 627 reg = <0x3290000 0x10000>; 628 clocks = <&bpmp TEGRA194_CLK_PWM2>; 629 clock-names = "pwm"; 630 resets = <&bpmp TEGRA194_RESET_PWM2>; 631 reset-names = "pwm"; 632 status = "disabled"; 633 #pwm-cells = <2>; 634 }; 635 636 pwm3: pwm@32a0000 { 637 compatible = "nvidia,tegra194-pwm", 638 "nvidia,tegra186-pwm"; 639 reg = <0x32a0000 0x10000>; 640 clocks = <&bpmp TEGRA194_CLK_PWM3>; 641 clock-names = "pwm"; 642 resets = <&bpmp TEGRA194_RESET_PWM3>; 643 reset-names = "pwm"; 644 status = "disabled"; 645 #pwm-cells = <2>; 646 }; 647 648 pwm5: pwm@32c0000 { 649 compatible = "nvidia,tegra194-pwm", 650 "nvidia,tegra186-pwm"; 651 reg = <0x32c0000 0x10000>; 652 clocks = <&bpmp TEGRA194_CLK_PWM5>; 653 clock-names = "pwm"; 654 resets = <&bpmp TEGRA194_RESET_PWM5>; 655 reset-names = "pwm"; 656 status = "disabled"; 657 #pwm-cells = <2>; 658 }; 659 660 pwm6: pwm@32d0000 { 661 compatible = "nvidia,tegra194-pwm", 662 "nvidia,tegra186-pwm"; 663 reg = <0x32d0000 0x10000>; 664 clocks = <&bpmp TEGRA194_CLK_PWM6>; 665 clock-names = "pwm"; 666 resets = <&bpmp TEGRA194_RESET_PWM6>; 667 reset-names = "pwm"; 668 status = "disabled"; 669 #pwm-cells = <2>; 670 }; 671 672 pwm7: pwm@32e0000 { 673 compatible = "nvidia,tegra194-pwm", 674 "nvidia,tegra186-pwm"; 675 reg = <0x32e0000 0x10000>; 676 clocks = <&bpmp TEGRA194_CLK_PWM7>; 677 clock-names = "pwm"; 678 resets = <&bpmp TEGRA194_RESET_PWM7>; 679 reset-names = "pwm"; 680 status = "disabled"; 681 #pwm-cells = <2>; 682 }; 683 684 pwm8: pwm@32f0000 { 685 compatible = "nvidia,tegra194-pwm", 686 "nvidia,tegra186-pwm"; 687 reg = <0x32f0000 0x10000>; 688 clocks = <&bpmp TEGRA194_CLK_PWM8>; 689 clock-names = "pwm"; 690 resets = <&bpmp TEGRA194_RESET_PWM8>; 691 reset-names = "pwm"; 692 status = "disabled"; 693 #pwm-cells = <2>; 694 }; 695 696 sdmmc1: mmc@3400000 { 697 compatible = "nvidia,tegra194-sdhci"; 698 reg = <0x03400000 0x10000>; 699 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 701 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 702 clock-names = "sdhci", "tmclk"; 703 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 704 reset-names = "sdhci"; 705 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 706 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 707 interconnect-names = "dma-mem", "write"; 708 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 709 <0x07>; 710 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 711 <0x07>; 712 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 713 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 714 <0x07>; 715 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 716 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 717 nvidia,default-tap = <0x9>; 718 nvidia,default-trim = <0x5>; 719 status = "disabled"; 720 }; 721 722 sdmmc3: mmc@3440000 { 723 compatible = "nvidia,tegra194-sdhci"; 724 reg = <0x03440000 0x10000>; 725 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 727 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 728 clock-names = "sdhci", "tmclk"; 729 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 730 reset-names = "sdhci"; 731 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 732 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 733 interconnect-names = "dma-mem", "write"; 734 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 735 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 736 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 737 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 738 <0x07>; 739 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 740 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 741 <0x07>; 742 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 743 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 744 nvidia,default-tap = <0x9>; 745 nvidia,default-trim = <0x5>; 746 status = "disabled"; 747 }; 748 749 sdmmc4: mmc@3460000 { 750 compatible = "nvidia,tegra194-sdhci"; 751 reg = <0x03460000 0x10000>; 752 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 754 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 755 clock-names = "sdhci", "tmclk"; 756 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 757 <&bpmp TEGRA194_CLK_PLLC4>; 758 assigned-clock-parents = 759 <&bpmp TEGRA194_CLK_PLLC4>; 760 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 761 reset-names = "sdhci"; 762 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 763 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 764 interconnect-names = "dma-mem", "write"; 765 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 766 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 767 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 768 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 769 <0x0a>; 770 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 771 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 772 <0x0a>; 773 nvidia,default-tap = <0x8>; 774 nvidia,default-trim = <0x14>; 775 nvidia,dqs-trim = <40>; 776 supports-cqe; 777 status = "disabled"; 778 }; 779 780 hda@3510000 { 781 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 782 reg = <0x3510000 0x10000>; 783 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 784 clocks = <&bpmp TEGRA194_CLK_HDA>, 785 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 786 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 787 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 788 resets = <&bpmp TEGRA194_RESET_HDA>, 789 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>, 790 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>; 791 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 792 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 793 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 794 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 795 interconnect-names = "dma-mem", "write"; 796 status = "disabled"; 797 }; 798 799 xusb_padctl: padctl@3520000 { 800 compatible = "nvidia,tegra194-xusb-padctl"; 801 reg = <0x03520000 0x1000>, 802 <0x03540000 0x1000>; 803 reg-names = "padctl", "ao"; 804 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 805 806 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 807 reset-names = "padctl"; 808 809 status = "disabled"; 810 811 pads { 812 usb2 { 813 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 814 clock-names = "trk"; 815 816 lanes { 817 usb2-0 { 818 nvidia,function = "xusb"; 819 status = "disabled"; 820 #phy-cells = <0>; 821 }; 822 823 usb2-1 { 824 nvidia,function = "xusb"; 825 status = "disabled"; 826 #phy-cells = <0>; 827 }; 828 829 usb2-2 { 830 nvidia,function = "xusb"; 831 status = "disabled"; 832 #phy-cells = <0>; 833 }; 834 835 usb2-3 { 836 nvidia,function = "xusb"; 837 status = "disabled"; 838 #phy-cells = <0>; 839 }; 840 }; 841 }; 842 843 usb3 { 844 lanes { 845 usb3-0 { 846 nvidia,function = "xusb"; 847 status = "disabled"; 848 #phy-cells = <0>; 849 }; 850 851 usb3-1 { 852 nvidia,function = "xusb"; 853 status = "disabled"; 854 #phy-cells = <0>; 855 }; 856 857 usb3-2 { 858 nvidia,function = "xusb"; 859 status = "disabled"; 860 #phy-cells = <0>; 861 }; 862 863 usb3-3 { 864 nvidia,function = "xusb"; 865 status = "disabled"; 866 #phy-cells = <0>; 867 }; 868 }; 869 }; 870 }; 871 872 ports { 873 usb2-0 { 874 status = "disabled"; 875 }; 876 877 usb2-1 { 878 status = "disabled"; 879 }; 880 881 usb2-2 { 882 status = "disabled"; 883 }; 884 885 usb2-3 { 886 status = "disabled"; 887 }; 888 889 usb3-0 { 890 status = "disabled"; 891 }; 892 893 usb3-1 { 894 status = "disabled"; 895 }; 896 897 usb3-2 { 898 status = "disabled"; 899 }; 900 901 usb3-3 { 902 status = "disabled"; 903 }; 904 }; 905 }; 906 907 usb@3550000 { 908 compatible = "nvidia,tegra194-xudc"; 909 reg = <0x03550000 0x8000>, 910 <0x03558000 0x1000>; 911 reg-names = "base", "fpci"; 912 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 914 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 915 <&bpmp TEGRA194_CLK_XUSB_SS>, 916 <&bpmp TEGRA194_CLK_XUSB_FS>; 917 clock-names = "dev", "ss", "ss_src", "fs_src"; 918 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 919 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 920 power-domain-names = "dev", "ss"; 921 nvidia,xusb-padctl = <&xusb_padctl>; 922 status = "disabled"; 923 }; 924 925 usb@3610000 { 926 compatible = "nvidia,tegra194-xusb"; 927 reg = <0x03610000 0x40000>, 928 <0x03600000 0x10000>; 929 reg-names = "hcd", "fpci"; 930 931 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 933 934 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 935 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 936 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 937 <&bpmp TEGRA194_CLK_XUSB_SS>, 938 <&bpmp TEGRA194_CLK_CLK_M>, 939 <&bpmp TEGRA194_CLK_XUSB_FS>, 940 <&bpmp TEGRA194_CLK_UTMIPLL>, 941 <&bpmp TEGRA194_CLK_CLK_M>, 942 <&bpmp TEGRA194_CLK_PLLE>; 943 clock-names = "xusb_host", "xusb_falcon_src", 944 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 945 "xusb_fs_src", "pll_u_480m", "clk_m", 946 "pll_e"; 947 948 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 949 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 950 power-domain-names = "xusb_host", "xusb_ss"; 951 952 nvidia,xusb-padctl = <&xusb_padctl>; 953 status = "disabled"; 954 }; 955 956 fuse@3820000 { 957 compatible = "nvidia,tegra194-efuse"; 958 reg = <0x03820000 0x10000>; 959 clocks = <&bpmp TEGRA194_CLK_FUSE>; 960 clock-names = "fuse"; 961 }; 962 963 gic: interrupt-controller@3881000 { 964 compatible = "arm,gic-400"; 965 #interrupt-cells = <3>; 966 interrupt-controller; 967 reg = <0x03881000 0x1000>, 968 <0x03882000 0x2000>, 969 <0x03884000 0x2000>, 970 <0x03886000 0x2000>; 971 interrupts = <GIC_PPI 9 972 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 973 interrupt-parent = <&gic>; 974 }; 975 976 cec@3960000 { 977 compatible = "nvidia,tegra194-cec"; 978 reg = <0x03960000 0x10000>; 979 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&bpmp TEGRA194_CLK_CEC>; 981 clock-names = "cec"; 982 status = "disabled"; 983 }; 984 985 hsp_top0: hsp@3c00000 { 986 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 987 reg = <0x03c00000 0xa0000>; 988 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 997 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 998 "shared3", "shared4", "shared5", "shared6", 999 "shared7"; 1000 #mbox-cells = <2>; 1001 }; 1002 1003 p2u_hsio_0: phy@3e10000 { 1004 compatible = "nvidia,tegra194-p2u"; 1005 reg = <0x03e10000 0x10000>; 1006 reg-names = "ctl"; 1007 1008 #phy-cells = <0>; 1009 }; 1010 1011 p2u_hsio_1: phy@3e20000 { 1012 compatible = "nvidia,tegra194-p2u"; 1013 reg = <0x03e20000 0x10000>; 1014 reg-names = "ctl"; 1015 1016 #phy-cells = <0>; 1017 }; 1018 1019 p2u_hsio_2: phy@3e30000 { 1020 compatible = "nvidia,tegra194-p2u"; 1021 reg = <0x03e30000 0x10000>; 1022 reg-names = "ctl"; 1023 1024 #phy-cells = <0>; 1025 }; 1026 1027 p2u_hsio_3: phy@3e40000 { 1028 compatible = "nvidia,tegra194-p2u"; 1029 reg = <0x03e40000 0x10000>; 1030 reg-names = "ctl"; 1031 1032 #phy-cells = <0>; 1033 }; 1034 1035 p2u_hsio_4: phy@3e50000 { 1036 compatible = "nvidia,tegra194-p2u"; 1037 reg = <0x03e50000 0x10000>; 1038 reg-names = "ctl"; 1039 1040 #phy-cells = <0>; 1041 }; 1042 1043 p2u_hsio_5: phy@3e60000 { 1044 compatible = "nvidia,tegra194-p2u"; 1045 reg = <0x03e60000 0x10000>; 1046 reg-names = "ctl"; 1047 1048 #phy-cells = <0>; 1049 }; 1050 1051 p2u_hsio_6: phy@3e70000 { 1052 compatible = "nvidia,tegra194-p2u"; 1053 reg = <0x03e70000 0x10000>; 1054 reg-names = "ctl"; 1055 1056 #phy-cells = <0>; 1057 }; 1058 1059 p2u_hsio_7: phy@3e80000 { 1060 compatible = "nvidia,tegra194-p2u"; 1061 reg = <0x03e80000 0x10000>; 1062 reg-names = "ctl"; 1063 1064 #phy-cells = <0>; 1065 }; 1066 1067 p2u_hsio_8: phy@3e90000 { 1068 compatible = "nvidia,tegra194-p2u"; 1069 reg = <0x03e90000 0x10000>; 1070 reg-names = "ctl"; 1071 1072 #phy-cells = <0>; 1073 }; 1074 1075 p2u_hsio_9: phy@3ea0000 { 1076 compatible = "nvidia,tegra194-p2u"; 1077 reg = <0x03ea0000 0x10000>; 1078 reg-names = "ctl"; 1079 1080 #phy-cells = <0>; 1081 }; 1082 1083 p2u_nvhs_0: phy@3eb0000 { 1084 compatible = "nvidia,tegra194-p2u"; 1085 reg = <0x03eb0000 0x10000>; 1086 reg-names = "ctl"; 1087 1088 #phy-cells = <0>; 1089 }; 1090 1091 p2u_nvhs_1: phy@3ec0000 { 1092 compatible = "nvidia,tegra194-p2u"; 1093 reg = <0x03ec0000 0x10000>; 1094 reg-names = "ctl"; 1095 1096 #phy-cells = <0>; 1097 }; 1098 1099 p2u_nvhs_2: phy@3ed0000 { 1100 compatible = "nvidia,tegra194-p2u"; 1101 reg = <0x03ed0000 0x10000>; 1102 reg-names = "ctl"; 1103 1104 #phy-cells = <0>; 1105 }; 1106 1107 p2u_nvhs_3: phy@3ee0000 { 1108 compatible = "nvidia,tegra194-p2u"; 1109 reg = <0x03ee0000 0x10000>; 1110 reg-names = "ctl"; 1111 1112 #phy-cells = <0>; 1113 }; 1114 1115 p2u_nvhs_4: phy@3ef0000 { 1116 compatible = "nvidia,tegra194-p2u"; 1117 reg = <0x03ef0000 0x10000>; 1118 reg-names = "ctl"; 1119 1120 #phy-cells = <0>; 1121 }; 1122 1123 p2u_nvhs_5: phy@3f00000 { 1124 compatible = "nvidia,tegra194-p2u"; 1125 reg = <0x03f00000 0x10000>; 1126 reg-names = "ctl"; 1127 1128 #phy-cells = <0>; 1129 }; 1130 1131 p2u_nvhs_6: phy@3f10000 { 1132 compatible = "nvidia,tegra194-p2u"; 1133 reg = <0x03f10000 0x10000>; 1134 reg-names = "ctl"; 1135 1136 #phy-cells = <0>; 1137 }; 1138 1139 p2u_nvhs_7: phy@3f20000 { 1140 compatible = "nvidia,tegra194-p2u"; 1141 reg = <0x03f20000 0x10000>; 1142 reg-names = "ctl"; 1143 1144 #phy-cells = <0>; 1145 }; 1146 1147 p2u_hsio_10: phy@3f30000 { 1148 compatible = "nvidia,tegra194-p2u"; 1149 reg = <0x03f30000 0x10000>; 1150 reg-names = "ctl"; 1151 1152 #phy-cells = <0>; 1153 }; 1154 1155 p2u_hsio_11: phy@3f40000 { 1156 compatible = "nvidia,tegra194-p2u"; 1157 reg = <0x03f40000 0x10000>; 1158 reg-names = "ctl"; 1159 1160 #phy-cells = <0>; 1161 }; 1162 1163 hsp_aon: hsp@c150000 { 1164 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 1165 reg = <0x0c150000 0x90000>; 1166 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1170 /* 1171 * Shared interrupt 0 is routed only to AON/SPE, so 1172 * we only have 4 shared interrupts for the CCPLEX. 1173 */ 1174 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1175 #mbox-cells = <2>; 1176 }; 1177 1178 gen2_i2c: i2c@c240000 { 1179 compatible = "nvidia,tegra194-i2c"; 1180 reg = <0x0c240000 0x10000>; 1181 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1185 clock-names = "div-clk"; 1186 resets = <&bpmp TEGRA194_RESET_I2C2>; 1187 reset-names = "i2c"; 1188 status = "disabled"; 1189 }; 1190 1191 gen8_i2c: i2c@c250000 { 1192 compatible = "nvidia,tegra194-i2c"; 1193 reg = <0x0c250000 0x10000>; 1194 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1198 clock-names = "div-clk"; 1199 resets = <&bpmp TEGRA194_RESET_I2C8>; 1200 reset-names = "i2c"; 1201 status = "disabled"; 1202 }; 1203 1204 uartc: serial@c280000 { 1205 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1206 reg = <0x0c280000 0x40>; 1207 reg-shift = <2>; 1208 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1209 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1210 clock-names = "serial"; 1211 resets = <&bpmp TEGRA194_RESET_UARTC>; 1212 reset-names = "serial"; 1213 status = "disabled"; 1214 }; 1215 1216 uartg: serial@c290000 { 1217 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1218 reg = <0x0c290000 0x40>; 1219 reg-shift = <2>; 1220 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1221 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1222 clock-names = "serial"; 1223 resets = <&bpmp TEGRA194_RESET_UARTG>; 1224 reset-names = "serial"; 1225 status = "disabled"; 1226 }; 1227 1228 rtc: rtc@c2a0000 { 1229 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1230 reg = <0x0c2a0000 0x10000>; 1231 interrupt-parent = <&pmc>; 1232 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1233 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1234 clock-names = "rtc"; 1235 status = "disabled"; 1236 }; 1237 1238 gpio_aon: gpio@c2f0000 { 1239 compatible = "nvidia,tegra194-gpio-aon"; 1240 reg-names = "security", "gpio"; 1241 reg = <0xc2f0000 0x1000>, 1242 <0xc2f1000 0x1000>; 1243 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1244 gpio-controller; 1245 #gpio-cells = <2>; 1246 interrupt-controller; 1247 #interrupt-cells = <2>; 1248 }; 1249 1250 pwm4: pwm@c340000 { 1251 compatible = "nvidia,tegra194-pwm", 1252 "nvidia,tegra186-pwm"; 1253 reg = <0xc340000 0x10000>; 1254 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1255 clock-names = "pwm"; 1256 resets = <&bpmp TEGRA194_RESET_PWM4>; 1257 reset-names = "pwm"; 1258 status = "disabled"; 1259 #pwm-cells = <2>; 1260 }; 1261 1262 pmc: pmc@c360000 { 1263 compatible = "nvidia,tegra194-pmc"; 1264 reg = <0x0c360000 0x10000>, 1265 <0x0c370000 0x10000>, 1266 <0x0c380000 0x10000>, 1267 <0x0c390000 0x10000>, 1268 <0x0c3a0000 0x10000>; 1269 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1270 1271 #interrupt-cells = <2>; 1272 interrupt-controller; 1273 }; 1274 1275 host1x@13e00000 { 1276 compatible = "nvidia,tegra194-host1x"; 1277 reg = <0x13e00000 0x10000>, 1278 <0x13e10000 0x10000>; 1279 reg-names = "hypervisor", "vm"; 1280 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1281 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1282 interrupt-names = "syncpt", "host1x"; 1283 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1284 clock-names = "host1x"; 1285 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1286 reset-names = "host1x"; 1287 1288 #address-cells = <1>; 1289 #size-cells = <1>; 1290 1291 ranges = <0x15000000 0x15000000 0x01000000>; 1292 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1293 interconnect-names = "dma-mem"; 1294 1295 display-hub@15200000 { 1296 compatible = "nvidia,tegra194-display"; 1297 reg = <0x15200000 0x00040000>; 1298 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1299 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1300 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1301 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1302 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1303 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1304 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1305 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1306 "wgrp3", "wgrp4", "wgrp5"; 1307 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1308 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1309 clock-names = "disp", "hub"; 1310 status = "disabled"; 1311 1312 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1313 1314 #address-cells = <1>; 1315 #size-cells = <1>; 1316 1317 ranges = <0x15200000 0x15200000 0x40000>; 1318 1319 display@15200000 { 1320 compatible = "nvidia,tegra194-dc"; 1321 reg = <0x15200000 0x10000>; 1322 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1323 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1324 clock-names = "dc"; 1325 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1326 reset-names = "dc"; 1327 1328 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1329 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1330 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1331 interconnect-names = "dma-mem", "read-1"; 1332 1333 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1334 nvidia,head = <0>; 1335 }; 1336 1337 display@15210000 { 1338 compatible = "nvidia,tegra194-dc"; 1339 reg = <0x15210000 0x10000>; 1340 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1341 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1342 clock-names = "dc"; 1343 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1344 reset-names = "dc"; 1345 1346 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1347 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1348 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1349 interconnect-names = "dma-mem", "read-1"; 1350 1351 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1352 nvidia,head = <1>; 1353 }; 1354 1355 display@15220000 { 1356 compatible = "nvidia,tegra194-dc"; 1357 reg = <0x15220000 0x10000>; 1358 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1359 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1360 clock-names = "dc"; 1361 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1362 reset-names = "dc"; 1363 1364 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1365 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1366 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1367 interconnect-names = "dma-mem", "read-1"; 1368 1369 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1370 nvidia,head = <2>; 1371 }; 1372 1373 display@15230000 { 1374 compatible = "nvidia,tegra194-dc"; 1375 reg = <0x15230000 0x10000>; 1376 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1377 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1378 clock-names = "dc"; 1379 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1380 reset-names = "dc"; 1381 1382 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1383 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1384 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1385 interconnect-names = "dma-mem", "read-1"; 1386 1387 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1388 nvidia,head = <3>; 1389 }; 1390 }; 1391 1392 vic@15340000 { 1393 compatible = "nvidia,tegra194-vic"; 1394 reg = <0x15340000 0x00040000>; 1395 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1396 clocks = <&bpmp TEGRA194_CLK_VIC>; 1397 clock-names = "vic"; 1398 resets = <&bpmp TEGRA194_RESET_VIC>; 1399 reset-names = "vic"; 1400 1401 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1402 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1403 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1404 interconnect-names = "dma-mem", "write"; 1405 }; 1406 1407 dpaux0: dpaux@155c0000 { 1408 compatible = "nvidia,tegra194-dpaux"; 1409 reg = <0x155c0000 0x10000>; 1410 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1411 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1412 <&bpmp TEGRA194_CLK_PLLDP>; 1413 clock-names = "dpaux", "parent"; 1414 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1415 reset-names = "dpaux"; 1416 status = "disabled"; 1417 1418 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1419 1420 state_dpaux0_aux: pinmux-aux { 1421 groups = "dpaux-io"; 1422 function = "aux"; 1423 }; 1424 1425 state_dpaux0_i2c: pinmux-i2c { 1426 groups = "dpaux-io"; 1427 function = "i2c"; 1428 }; 1429 1430 state_dpaux0_off: pinmux-off { 1431 groups = "dpaux-io"; 1432 function = "off"; 1433 }; 1434 1435 i2c-bus { 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 }; 1439 }; 1440 1441 dpaux1: dpaux@155d0000 { 1442 compatible = "nvidia,tegra194-dpaux"; 1443 reg = <0x155d0000 0x10000>; 1444 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1445 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1446 <&bpmp TEGRA194_CLK_PLLDP>; 1447 clock-names = "dpaux", "parent"; 1448 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1449 reset-names = "dpaux"; 1450 status = "disabled"; 1451 1452 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1453 1454 state_dpaux1_aux: pinmux-aux { 1455 groups = "dpaux-io"; 1456 function = "aux"; 1457 }; 1458 1459 state_dpaux1_i2c: pinmux-i2c { 1460 groups = "dpaux-io"; 1461 function = "i2c"; 1462 }; 1463 1464 state_dpaux1_off: pinmux-off { 1465 groups = "dpaux-io"; 1466 function = "off"; 1467 }; 1468 1469 i2c-bus { 1470 #address-cells = <1>; 1471 #size-cells = <0>; 1472 }; 1473 }; 1474 1475 dpaux2: dpaux@155e0000 { 1476 compatible = "nvidia,tegra194-dpaux"; 1477 reg = <0x155e0000 0x10000>; 1478 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1479 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1480 <&bpmp TEGRA194_CLK_PLLDP>; 1481 clock-names = "dpaux", "parent"; 1482 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1483 reset-names = "dpaux"; 1484 status = "disabled"; 1485 1486 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1487 1488 state_dpaux2_aux: pinmux-aux { 1489 groups = "dpaux-io"; 1490 function = "aux"; 1491 }; 1492 1493 state_dpaux2_i2c: pinmux-i2c { 1494 groups = "dpaux-io"; 1495 function = "i2c"; 1496 }; 1497 1498 state_dpaux2_off: pinmux-off { 1499 groups = "dpaux-io"; 1500 function = "off"; 1501 }; 1502 1503 i2c-bus { 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 }; 1507 }; 1508 1509 dpaux3: dpaux@155f0000 { 1510 compatible = "nvidia,tegra194-dpaux"; 1511 reg = <0x155f0000 0x10000>; 1512 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1513 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1514 <&bpmp TEGRA194_CLK_PLLDP>; 1515 clock-names = "dpaux", "parent"; 1516 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1517 reset-names = "dpaux"; 1518 status = "disabled"; 1519 1520 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1521 1522 state_dpaux3_aux: pinmux-aux { 1523 groups = "dpaux-io"; 1524 function = "aux"; 1525 }; 1526 1527 state_dpaux3_i2c: pinmux-i2c { 1528 groups = "dpaux-io"; 1529 function = "i2c"; 1530 }; 1531 1532 state_dpaux3_off: pinmux-off { 1533 groups = "dpaux-io"; 1534 function = "off"; 1535 }; 1536 1537 i2c-bus { 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 }; 1541 }; 1542 1543 sor0: sor@15b00000 { 1544 compatible = "nvidia,tegra194-sor"; 1545 reg = <0x15b00000 0x40000>; 1546 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1547 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 1548 <&bpmp TEGRA194_CLK_SOR0_OUT>, 1549 <&bpmp TEGRA194_CLK_PLLD>, 1550 <&bpmp TEGRA194_CLK_PLLDP>, 1551 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1552 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 1553 clock-names = "sor", "out", "parent", "dp", "safe", 1554 "pad"; 1555 resets = <&bpmp TEGRA194_RESET_SOR0>; 1556 reset-names = "sor"; 1557 pinctrl-0 = <&state_dpaux0_aux>; 1558 pinctrl-1 = <&state_dpaux0_i2c>; 1559 pinctrl-2 = <&state_dpaux0_off>; 1560 pinctrl-names = "aux", "i2c", "off"; 1561 status = "disabled"; 1562 1563 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1564 nvidia,interface = <0>; 1565 }; 1566 1567 sor1: sor@15b40000 { 1568 compatible = "nvidia,tegra194-sor"; 1569 reg = <0x15b40000 0x40000>; 1570 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1571 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 1572 <&bpmp TEGRA194_CLK_SOR1_OUT>, 1573 <&bpmp TEGRA194_CLK_PLLD2>, 1574 <&bpmp TEGRA194_CLK_PLLDP>, 1575 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1576 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 1577 clock-names = "sor", "out", "parent", "dp", "safe", 1578 "pad"; 1579 resets = <&bpmp TEGRA194_RESET_SOR1>; 1580 reset-names = "sor"; 1581 pinctrl-0 = <&state_dpaux1_aux>; 1582 pinctrl-1 = <&state_dpaux1_i2c>; 1583 pinctrl-2 = <&state_dpaux1_off>; 1584 pinctrl-names = "aux", "i2c", "off"; 1585 status = "disabled"; 1586 1587 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1588 nvidia,interface = <1>; 1589 }; 1590 1591 sor2: sor@15b80000 { 1592 compatible = "nvidia,tegra194-sor"; 1593 reg = <0x15b80000 0x40000>; 1594 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1595 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 1596 <&bpmp TEGRA194_CLK_SOR2_OUT>, 1597 <&bpmp TEGRA194_CLK_PLLD3>, 1598 <&bpmp TEGRA194_CLK_PLLDP>, 1599 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1600 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 1601 clock-names = "sor", "out", "parent", "dp", "safe", 1602 "pad"; 1603 resets = <&bpmp TEGRA194_RESET_SOR2>; 1604 reset-names = "sor"; 1605 pinctrl-0 = <&state_dpaux2_aux>; 1606 pinctrl-1 = <&state_dpaux2_i2c>; 1607 pinctrl-2 = <&state_dpaux2_off>; 1608 pinctrl-names = "aux", "i2c", "off"; 1609 status = "disabled"; 1610 1611 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1612 nvidia,interface = <2>; 1613 }; 1614 1615 sor3: sor@15bc0000 { 1616 compatible = "nvidia,tegra194-sor"; 1617 reg = <0x15bc0000 0x40000>; 1618 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1619 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 1620 <&bpmp TEGRA194_CLK_SOR3_OUT>, 1621 <&bpmp TEGRA194_CLK_PLLD4>, 1622 <&bpmp TEGRA194_CLK_PLLDP>, 1623 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1624 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 1625 clock-names = "sor", "out", "parent", "dp", "safe", 1626 "pad"; 1627 resets = <&bpmp TEGRA194_RESET_SOR3>; 1628 reset-names = "sor"; 1629 pinctrl-0 = <&state_dpaux3_aux>; 1630 pinctrl-1 = <&state_dpaux3_i2c>; 1631 pinctrl-2 = <&state_dpaux3_off>; 1632 pinctrl-names = "aux", "i2c", "off"; 1633 status = "disabled"; 1634 1635 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1636 nvidia,interface = <3>; 1637 }; 1638 }; 1639 1640 gpu@17000000 { 1641 compatible = "nvidia,gv11b"; 1642 reg = <0x17000000 0x1000000>, 1643 <0x18000000 0x1000000>; 1644 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1646 interrupt-names = "stall", "nonstall"; 1647 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 1648 <&bpmp TEGRA194_CLK_GPU_PWR>, 1649 <&bpmp TEGRA194_CLK_FUSE>; 1650 clock-names = "gpu", "pwr", "fuse"; 1651 resets = <&bpmp TEGRA194_RESET_GPU>; 1652 reset-names = "gpu"; 1653 dma-coherent; 1654 1655 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 1656 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 1657 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 1658 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 1659 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 1660 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 1661 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 1662 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 1663 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 1664 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 1665 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 1666 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 1667 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 1668 interconnect-names = "dma-mem", "read-0-hp", "write-0", 1669 "read-1", "read-1-hp", "write-1", 1670 "read-2", "read-2-hp", "write-2", 1671 "read-3", "read-3-hp", "write-3"; 1672 }; 1673 }; 1674 1675 pcie@14100000 { 1676 compatible = "nvidia,tegra194-pcie"; 1677 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1678 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1679 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1680 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1681 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1682 reg-names = "appl", "config", "atu_dma", "dbi"; 1683 1684 status = "disabled"; 1685 1686 #address-cells = <3>; 1687 #size-cells = <2>; 1688 device_type = "pci"; 1689 num-lanes = <1>; 1690 num-viewport = <8>; 1691 linux,pci-domain = <1>; 1692 1693 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 1694 clock-names = "core"; 1695 1696 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 1697 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 1698 reset-names = "apb", "core"; 1699 1700 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1701 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1702 interrupt-names = "intr", "msi"; 1703 1704 #interrupt-cells = <1>; 1705 interrupt-map-mask = <0 0 0 0>; 1706 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1707 1708 nvidia,bpmp = <&bpmp 1>; 1709 1710 nvidia,aspm-cmrt-us = <60>; 1711 nvidia,aspm-pwr-on-t-us = <20>; 1712 nvidia,aspm-l0s-entrance-latency-us = <3>; 1713 1714 bus-range = <0x0 0xff>; 1715 1716 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1717 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 1718 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1719 1720 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 1721 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 1722 interconnect-names = "read", "write"; 1723 }; 1724 1725 pcie@14120000 { 1726 compatible = "nvidia,tegra194-pcie"; 1727 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1728 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 1729 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 1730 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1731 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1732 reg-names = "appl", "config", "atu_dma", "dbi"; 1733 1734 status = "disabled"; 1735 1736 #address-cells = <3>; 1737 #size-cells = <2>; 1738 device_type = "pci"; 1739 num-lanes = <1>; 1740 num-viewport = <8>; 1741 linux,pci-domain = <2>; 1742 1743 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 1744 clock-names = "core"; 1745 1746 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 1747 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 1748 reset-names = "apb", "core"; 1749 1750 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1751 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1752 interrupt-names = "intr", "msi"; 1753 1754 #interrupt-cells = <1>; 1755 interrupt-map-mask = <0 0 0 0>; 1756 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1757 1758 nvidia,bpmp = <&bpmp 2>; 1759 1760 nvidia,aspm-cmrt-us = <60>; 1761 nvidia,aspm-pwr-on-t-us = <20>; 1762 nvidia,aspm-l0s-entrance-latency-us = <3>; 1763 1764 bus-range = <0x0 0xff>; 1765 1766 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1767 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 1768 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1769 1770 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 1771 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 1772 interconnect-names = "read", "write"; 1773 }; 1774 1775 pcie@14140000 { 1776 compatible = "nvidia,tegra194-pcie"; 1777 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1778 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 1779 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 1780 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1781 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1782 reg-names = "appl", "config", "atu_dma", "dbi"; 1783 1784 status = "disabled"; 1785 1786 #address-cells = <3>; 1787 #size-cells = <2>; 1788 device_type = "pci"; 1789 num-lanes = <1>; 1790 num-viewport = <8>; 1791 linux,pci-domain = <3>; 1792 1793 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 1794 clock-names = "core"; 1795 1796 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 1797 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 1798 reset-names = "apb", "core"; 1799 1800 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1801 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1802 interrupt-names = "intr", "msi"; 1803 1804 #interrupt-cells = <1>; 1805 interrupt-map-mask = <0 0 0 0>; 1806 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1807 1808 nvidia,bpmp = <&bpmp 3>; 1809 1810 nvidia,aspm-cmrt-us = <60>; 1811 nvidia,aspm-pwr-on-t-us = <20>; 1812 nvidia,aspm-l0s-entrance-latency-us = <3>; 1813 1814 bus-range = <0x0 0xff>; 1815 1816 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1817 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 1818 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1819 1820 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 1821 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 1822 interconnect-names = "read", "write"; 1823 }; 1824 1825 pcie@14160000 { 1826 compatible = "nvidia,tegra194-pcie"; 1827 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1828 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1829 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 1830 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1831 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1832 reg-names = "appl", "config", "atu_dma", "dbi"; 1833 1834 status = "disabled"; 1835 1836 #address-cells = <3>; 1837 #size-cells = <2>; 1838 device_type = "pci"; 1839 num-lanes = <4>; 1840 num-viewport = <8>; 1841 linux,pci-domain = <4>; 1842 1843 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1844 clock-names = "core"; 1845 1846 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1847 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1848 reset-names = "apb", "core"; 1849 1850 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1851 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1852 interrupt-names = "intr", "msi"; 1853 1854 #interrupt-cells = <1>; 1855 interrupt-map-mask = <0 0 0 0>; 1856 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1857 1858 nvidia,bpmp = <&bpmp 4>; 1859 1860 nvidia,aspm-cmrt-us = <60>; 1861 nvidia,aspm-pwr-on-t-us = <20>; 1862 nvidia,aspm-l0s-entrance-latency-us = <3>; 1863 1864 bus-range = <0x0 0xff>; 1865 1866 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1867 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1868 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1869 1870 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 1871 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 1872 interconnect-names = "read", "write"; 1873 }; 1874 1875 pcie@14180000 { 1876 compatible = "nvidia,tegra194-pcie"; 1877 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1878 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 1879 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 1880 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1881 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1882 reg-names = "appl", "config", "atu_dma", "dbi"; 1883 1884 status = "disabled"; 1885 1886 #address-cells = <3>; 1887 #size-cells = <2>; 1888 device_type = "pci"; 1889 num-lanes = <8>; 1890 num-viewport = <8>; 1891 linux,pci-domain = <0>; 1892 1893 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1894 clock-names = "core"; 1895 1896 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1897 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1898 reset-names = "apb", "core"; 1899 1900 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1901 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1902 interrupt-names = "intr", "msi"; 1903 1904 #interrupt-cells = <1>; 1905 interrupt-map-mask = <0 0 0 0>; 1906 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1907 1908 nvidia,bpmp = <&bpmp 0>; 1909 1910 nvidia,aspm-cmrt-us = <60>; 1911 nvidia,aspm-pwr-on-t-us = <20>; 1912 nvidia,aspm-l0s-entrance-latency-us = <3>; 1913 1914 bus-range = <0x0 0xff>; 1915 1916 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1917 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1918 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1919 1920 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 1921 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 1922 interconnect-names = "read", "write"; 1923 }; 1924 1925 pcie@141a0000 { 1926 compatible = "nvidia,tegra194-pcie"; 1927 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1928 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 1929 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 1930 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1931 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1932 reg-names = "appl", "config", "atu_dma", "dbi"; 1933 1934 status = "disabled"; 1935 1936 #address-cells = <3>; 1937 #size-cells = <2>; 1938 device_type = "pci"; 1939 num-lanes = <8>; 1940 num-viewport = <8>; 1941 linux,pci-domain = <5>; 1942 1943 pinctrl-names = "default"; 1944 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1945 1946 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 1947 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 1948 clock-names = "core", "core_m"; 1949 1950 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1951 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1952 reset-names = "apb", "core"; 1953 1954 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1955 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1956 interrupt-names = "intr", "msi"; 1957 1958 nvidia,bpmp = <&bpmp 5>; 1959 1960 #interrupt-cells = <1>; 1961 interrupt-map-mask = <0 0 0 0>; 1962 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1963 1964 nvidia,aspm-cmrt-us = <60>; 1965 nvidia,aspm-pwr-on-t-us = <20>; 1966 nvidia,aspm-l0s-entrance-latency-us = <3>; 1967 1968 bus-range = <0x0 0xff>; 1969 1970 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1971 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1972 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1973 1974 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 1975 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 1976 interconnect-names = "read", "write"; 1977 }; 1978 1979 pcie_ep@14160000 { 1980 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1981 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1982 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1983 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1984 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1985 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1986 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1987 1988 status = "disabled"; 1989 1990 num-lanes = <4>; 1991 num-ib-windows = <2>; 1992 num-ob-windows = <8>; 1993 1994 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1995 clock-names = "core"; 1996 1997 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1998 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1999 reset-names = "apb", "core"; 2000 2001 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2002 interrupt-names = "intr"; 2003 2004 nvidia,bpmp = <&bpmp 4>; 2005 2006 nvidia,aspm-cmrt-us = <60>; 2007 nvidia,aspm-pwr-on-t-us = <20>; 2008 nvidia,aspm-l0s-entrance-latency-us = <3>; 2009 }; 2010 2011 pcie_ep@14180000 { 2012 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 2013 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2014 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2015 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2016 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2017 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2018 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2019 2020 status = "disabled"; 2021 2022 num-lanes = <8>; 2023 num-ib-windows = <2>; 2024 num-ob-windows = <8>; 2025 2026 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2027 clock-names = "core"; 2028 2029 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2030 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2031 reset-names = "apb", "core"; 2032 2033 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2034 interrupt-names = "intr"; 2035 2036 nvidia,bpmp = <&bpmp 0>; 2037 2038 nvidia,aspm-cmrt-us = <60>; 2039 nvidia,aspm-pwr-on-t-us = <20>; 2040 nvidia,aspm-l0s-entrance-latency-us = <3>; 2041 }; 2042 2043 pcie_ep@141a0000 { 2044 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 2045 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2046 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2047 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2048 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2049 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2050 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2051 2052 status = "disabled"; 2053 2054 num-lanes = <8>; 2055 num-ib-windows = <2>; 2056 num-ob-windows = <8>; 2057 2058 pinctrl-names = "default"; 2059 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2060 2061 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2062 clock-names = "core"; 2063 2064 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2065 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2066 reset-names = "apb", "core"; 2067 2068 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2069 interrupt-names = "intr"; 2070 2071 nvidia,bpmp = <&bpmp 5>; 2072 2073 nvidia,aspm-cmrt-us = <60>; 2074 nvidia,aspm-pwr-on-t-us = <20>; 2075 nvidia,aspm-l0s-entrance-latency-us = <3>; 2076 }; 2077 2078 sram@40000000 { 2079 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2080 reg = <0x0 0x40000000 0x0 0x50000>; 2081 #address-cells = <1>; 2082 #size-cells = <1>; 2083 ranges = <0x0 0x0 0x40000000 0x50000>; 2084 2085 cpu_bpmp_tx: sram@4e000 { 2086 reg = <0x4e000 0x1000>; 2087 label = "cpu-bpmp-tx"; 2088 pool; 2089 }; 2090 2091 cpu_bpmp_rx: sram@4f000 { 2092 reg = <0x4f000 0x1000>; 2093 label = "cpu-bpmp-rx"; 2094 pool; 2095 }; 2096 }; 2097 2098 bpmp: bpmp { 2099 compatible = "nvidia,tegra186-bpmp"; 2100 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2101 TEGRA_HSP_DB_MASTER_BPMP>; 2102 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 2103 #clock-cells = <1>; 2104 #reset-cells = <1>; 2105 #power-domain-cells = <1>; 2106 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2107 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2108 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2109 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2110 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2111 2112 bpmp_i2c: i2c { 2113 compatible = "nvidia,tegra186-bpmp-i2c"; 2114 nvidia,bpmp-bus-id = <5>; 2115 #address-cells = <1>; 2116 #size-cells = <0>; 2117 }; 2118 2119 bpmp_thermal: thermal { 2120 compatible = "nvidia,tegra186-bpmp-thermal"; 2121 #thermal-sensor-cells = <1>; 2122 }; 2123 }; 2124 2125 cpus { 2126 compatible = "nvidia,tegra194-ccplex"; 2127 nvidia,bpmp = <&bpmp>; 2128 #address-cells = <1>; 2129 #size-cells = <0>; 2130 2131 cpu0_0: cpu@0 { 2132 compatible = "nvidia,tegra194-carmel"; 2133 device_type = "cpu"; 2134 reg = <0x000>; 2135 enable-method = "psci"; 2136 i-cache-size = <131072>; 2137 i-cache-line-size = <64>; 2138 i-cache-sets = <512>; 2139 d-cache-size = <65536>; 2140 d-cache-line-size = <64>; 2141 d-cache-sets = <256>; 2142 next-level-cache = <&l2c_0>; 2143 }; 2144 2145 cpu0_1: cpu@1 { 2146 compatible = "nvidia,tegra194-carmel"; 2147 device_type = "cpu"; 2148 reg = <0x001>; 2149 enable-method = "psci"; 2150 i-cache-size = <131072>; 2151 i-cache-line-size = <64>; 2152 i-cache-sets = <512>; 2153 d-cache-size = <65536>; 2154 d-cache-line-size = <64>; 2155 d-cache-sets = <256>; 2156 next-level-cache = <&l2c_0>; 2157 }; 2158 2159 cpu1_0: cpu@100 { 2160 compatible = "nvidia,tegra194-carmel"; 2161 device_type = "cpu"; 2162 reg = <0x100>; 2163 enable-method = "psci"; 2164 i-cache-size = <131072>; 2165 i-cache-line-size = <64>; 2166 i-cache-sets = <512>; 2167 d-cache-size = <65536>; 2168 d-cache-line-size = <64>; 2169 d-cache-sets = <256>; 2170 next-level-cache = <&l2c_1>; 2171 }; 2172 2173 cpu1_1: cpu@101 { 2174 compatible = "nvidia,tegra194-carmel"; 2175 device_type = "cpu"; 2176 reg = <0x101>; 2177 enable-method = "psci"; 2178 i-cache-size = <131072>; 2179 i-cache-line-size = <64>; 2180 i-cache-sets = <512>; 2181 d-cache-size = <65536>; 2182 d-cache-line-size = <64>; 2183 d-cache-sets = <256>; 2184 next-level-cache = <&l2c_1>; 2185 }; 2186 2187 cpu2_0: cpu@200 { 2188 compatible = "nvidia,tegra194-carmel"; 2189 device_type = "cpu"; 2190 reg = <0x200>; 2191 enable-method = "psci"; 2192 i-cache-size = <131072>; 2193 i-cache-line-size = <64>; 2194 i-cache-sets = <512>; 2195 d-cache-size = <65536>; 2196 d-cache-line-size = <64>; 2197 d-cache-sets = <256>; 2198 next-level-cache = <&l2c_2>; 2199 }; 2200 2201 cpu2_1: cpu@201 { 2202 compatible = "nvidia,tegra194-carmel"; 2203 device_type = "cpu"; 2204 reg = <0x201>; 2205 enable-method = "psci"; 2206 i-cache-size = <131072>; 2207 i-cache-line-size = <64>; 2208 i-cache-sets = <512>; 2209 d-cache-size = <65536>; 2210 d-cache-line-size = <64>; 2211 d-cache-sets = <256>; 2212 next-level-cache = <&l2c_2>; 2213 }; 2214 2215 cpu3_0: cpu@300 { 2216 compatible = "nvidia,tegra194-carmel"; 2217 device_type = "cpu"; 2218 reg = <0x300>; 2219 enable-method = "psci"; 2220 i-cache-size = <131072>; 2221 i-cache-line-size = <64>; 2222 i-cache-sets = <512>; 2223 d-cache-size = <65536>; 2224 d-cache-line-size = <64>; 2225 d-cache-sets = <256>; 2226 next-level-cache = <&l2c_3>; 2227 }; 2228 2229 cpu3_1: cpu@301 { 2230 compatible = "nvidia,tegra194-carmel"; 2231 device_type = "cpu"; 2232 reg = <0x301>; 2233 enable-method = "psci"; 2234 i-cache-size = <131072>; 2235 i-cache-line-size = <64>; 2236 i-cache-sets = <512>; 2237 d-cache-size = <65536>; 2238 d-cache-line-size = <64>; 2239 d-cache-sets = <256>; 2240 next-level-cache = <&l2c_3>; 2241 }; 2242 2243 cpu-map { 2244 cluster0 { 2245 core0 { 2246 cpu = <&cpu0_0>; 2247 }; 2248 2249 core1 { 2250 cpu = <&cpu0_1>; 2251 }; 2252 }; 2253 2254 cluster1 { 2255 core0 { 2256 cpu = <&cpu1_0>; 2257 }; 2258 2259 core1 { 2260 cpu = <&cpu1_1>; 2261 }; 2262 }; 2263 2264 cluster2 { 2265 core0 { 2266 cpu = <&cpu2_0>; 2267 }; 2268 2269 core1 { 2270 cpu = <&cpu2_1>; 2271 }; 2272 }; 2273 2274 cluster3 { 2275 core0 { 2276 cpu = <&cpu3_0>; 2277 }; 2278 2279 core1 { 2280 cpu = <&cpu3_1>; 2281 }; 2282 }; 2283 }; 2284 2285 l2c_0: l2-cache0 { 2286 cache-size = <2097152>; 2287 cache-line-size = <64>; 2288 cache-sets = <2048>; 2289 next-level-cache = <&l3c>; 2290 }; 2291 2292 l2c_1: l2-cache1 { 2293 cache-size = <2097152>; 2294 cache-line-size = <64>; 2295 cache-sets = <2048>; 2296 next-level-cache = <&l3c>; 2297 }; 2298 2299 l2c_2: l2-cache2 { 2300 cache-size = <2097152>; 2301 cache-line-size = <64>; 2302 cache-sets = <2048>; 2303 next-level-cache = <&l3c>; 2304 }; 2305 2306 l2c_3: l2-cache3 { 2307 cache-size = <2097152>; 2308 cache-line-size = <64>; 2309 cache-sets = <2048>; 2310 next-level-cache = <&l3c>; 2311 }; 2312 2313 l3c: l3-cache { 2314 cache-size = <4194304>; 2315 cache-line-size = <64>; 2316 cache-sets = <4096>; 2317 }; 2318 }; 2319 2320 psci { 2321 compatible = "arm,psci-1.0"; 2322 status = "okay"; 2323 method = "smc"; 2324 }; 2325 2326 tcu: tcu { 2327 compatible = "nvidia,tegra194-tcu"; 2328 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2329 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2330 mbox-names = "rx", "tx"; 2331 }; 2332 2333 thermal-zones { 2334 cpu { 2335 thermal-sensors = <&{/bpmp/thermal} 2336 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2337 status = "disabled"; 2338 }; 2339 2340 gpu { 2341 thermal-sensors = <&{/bpmp/thermal} 2342 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2343 status = "disabled"; 2344 }; 2345 2346 aux { 2347 thermal-sensors = <&{/bpmp/thermal} 2348 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2349 status = "disabled"; 2350 }; 2351 2352 pllx { 2353 thermal-sensors = <&{/bpmp/thermal} 2354 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2355 status = "disabled"; 2356 }; 2357 2358 ao { 2359 thermal-sensors = <&{/bpmp/thermal} 2360 TEGRA194_BPMP_THERMAL_ZONE_AO>; 2361 status = "disabled"; 2362 }; 2363 2364 tj { 2365 thermal-sensors = <&{/bpmp/thermal} 2366 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2367 status = "disabled"; 2368 }; 2369 }; 2370 2371 timer { 2372 compatible = "arm,armv8-timer"; 2373 interrupts = <GIC_PPI 13 2374 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2375 <GIC_PPI 14 2376 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2377 <GIC_PPI 11 2378 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2379 <GIC_PPI 10 2380 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2381 interrupt-parent = <&gic>; 2382 always-on; 2383 }; 2384}; 2385