1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65 interconnect-names = "dma-mem", "write"; 66 iommus = <&smmu TEGRA186_SID_EQOS>; 67 status = "disabled"; 68 69 snps,write-requests = <1>; 70 snps,read-requests = <3>; 71 snps,burst-map = <0x7>; 72 snps,txpbl = <32>; 73 snps,rxpbl = <8>; 74 }; 75 76 gpcdma: dma-controller@2600000 { 77 compatible = "nvidia,tegra186-gpcdma"; 78 reg = <0x0 0x2600000 0x0 0x210000>; 79 resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80 reset-names = "gpcdma"; 81 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 112 #dma-cells = <1>; 113 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 114 dma-coherent; 115 status = "okay"; 116 }; 117 118 aconnect@2900000 { 119 compatible = "nvidia,tegra186-aconnect", 120 "nvidia,tegra210-aconnect"; 121 clocks = <&bpmp TEGRA186_CLK_APE>, 122 <&bpmp TEGRA186_CLK_APB2APE>; 123 clock-names = "ape", "apb2ape"; 124 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges = <0x02900000 0x0 0x02900000 0x200000>; 128 status = "disabled"; 129 130 adma: dma-controller@2930000 { 131 compatible = "nvidia,tegra186-adma"; 132 reg = <0x02930000 0x20000>; 133 interrupt-parent = <&agic>; 134 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 166 #dma-cells = <1>; 167 clocks = <&bpmp TEGRA186_CLK_AHUB>; 168 clock-names = "d_audio"; 169 status = "disabled"; 170 }; 171 172 agic: interrupt-controller@2a40000 { 173 compatible = "nvidia,tegra186-agic", 174 "nvidia,tegra210-agic"; 175 #interrupt-cells = <3>; 176 interrupt-controller; 177 reg = <0x02a41000 0x1000>, 178 <0x02a42000 0x2000>; 179 interrupts = <GIC_SPI 145 180 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 181 clocks = <&bpmp TEGRA186_CLK_APE>; 182 clock-names = "clk"; 183 status = "disabled"; 184 }; 185 186 tegra_ahub: ahub@2900800 { 187 compatible = "nvidia,tegra186-ahub"; 188 reg = <0x02900800 0x800>; 189 clocks = <&bpmp TEGRA186_CLK_AHUB>; 190 clock-names = "ahub"; 191 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 192 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 193 #address-cells = <1>; 194 #size-cells = <1>; 195 ranges = <0x02900800 0x02900800 0x11800>; 196 status = "disabled"; 197 198 tegra_admaif: admaif@290f000 { 199 compatible = "nvidia,tegra186-admaif"; 200 reg = <0x0290f000 0x1000>; 201 dmas = <&adma 1>, <&adma 1>, 202 <&adma 2>, <&adma 2>, 203 <&adma 3>, <&adma 3>, 204 <&adma 4>, <&adma 4>, 205 <&adma 5>, <&adma 5>, 206 <&adma 6>, <&adma 6>, 207 <&adma 7>, <&adma 7>, 208 <&adma 8>, <&adma 8>, 209 <&adma 9>, <&adma 9>, 210 <&adma 10>, <&adma 10>, 211 <&adma 11>, <&adma 11>, 212 <&adma 12>, <&adma 12>, 213 <&adma 13>, <&adma 13>, 214 <&adma 14>, <&adma 14>, 215 <&adma 15>, <&adma 15>, 216 <&adma 16>, <&adma 16>, 217 <&adma 17>, <&adma 17>, 218 <&adma 18>, <&adma 18>, 219 <&adma 19>, <&adma 19>, 220 <&adma 20>, <&adma 20>; 221 dma-names = "rx1", "tx1", 222 "rx2", "tx2", 223 "rx3", "tx3", 224 "rx4", "tx4", 225 "rx5", "tx5", 226 "rx6", "tx6", 227 "rx7", "tx7", 228 "rx8", "tx8", 229 "rx9", "tx9", 230 "rx10", "tx10", 231 "rx11", "tx11", 232 "rx12", "tx12", 233 "rx13", "tx13", 234 "rx14", "tx14", 235 "rx15", "tx15", 236 "rx16", "tx16", 237 "rx17", "tx17", 238 "rx18", "tx18", 239 "rx19", "tx19", 240 "rx20", "tx20"; 241 status = "disabled"; 242 }; 243 244 tegra_i2s1: i2s@2901000 { 245 compatible = "nvidia,tegra186-i2s", 246 "nvidia,tegra210-i2s"; 247 reg = <0x2901000 0x100>; 248 clocks = <&bpmp TEGRA186_CLK_I2S1>, 249 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 250 clock-names = "i2s", "sync_input"; 251 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 252 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 253 assigned-clock-rates = <1536000>; 254 sound-name-prefix = "I2S1"; 255 status = "disabled"; 256 }; 257 258 tegra_i2s2: i2s@2901100 { 259 compatible = "nvidia,tegra186-i2s", 260 "nvidia,tegra210-i2s"; 261 reg = <0x2901100 0x100>; 262 clocks = <&bpmp TEGRA186_CLK_I2S2>, 263 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 264 clock-names = "i2s", "sync_input"; 265 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 266 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 267 assigned-clock-rates = <1536000>; 268 sound-name-prefix = "I2S2"; 269 status = "disabled"; 270 }; 271 272 tegra_i2s3: i2s@2901200 { 273 compatible = "nvidia,tegra186-i2s", 274 "nvidia,tegra210-i2s"; 275 reg = <0x2901200 0x100>; 276 clocks = <&bpmp TEGRA186_CLK_I2S3>, 277 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 278 clock-names = "i2s", "sync_input"; 279 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 280 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 281 assigned-clock-rates = <1536000>; 282 sound-name-prefix = "I2S3"; 283 status = "disabled"; 284 }; 285 286 tegra_i2s4: i2s@2901300 { 287 compatible = "nvidia,tegra186-i2s", 288 "nvidia,tegra210-i2s"; 289 reg = <0x2901300 0x100>; 290 clocks = <&bpmp TEGRA186_CLK_I2S4>, 291 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 292 clock-names = "i2s", "sync_input"; 293 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 294 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 295 assigned-clock-rates = <1536000>; 296 sound-name-prefix = "I2S4"; 297 status = "disabled"; 298 }; 299 300 tegra_i2s5: i2s@2901400 { 301 compatible = "nvidia,tegra186-i2s", 302 "nvidia,tegra210-i2s"; 303 reg = <0x2901400 0x100>; 304 clocks = <&bpmp TEGRA186_CLK_I2S5>, 305 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 306 clock-names = "i2s", "sync_input"; 307 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 308 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 309 assigned-clock-rates = <1536000>; 310 sound-name-prefix = "I2S5"; 311 status = "disabled"; 312 }; 313 314 tegra_i2s6: i2s@2901500 { 315 compatible = "nvidia,tegra186-i2s", 316 "nvidia,tegra210-i2s"; 317 reg = <0x2901500 0x100>; 318 clocks = <&bpmp TEGRA186_CLK_I2S6>, 319 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 320 clock-names = "i2s", "sync_input"; 321 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 322 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 323 assigned-clock-rates = <1536000>; 324 sound-name-prefix = "I2S6"; 325 status = "disabled"; 326 }; 327 328 tegra_dmic1: dmic@2904000 { 329 compatible = "nvidia,tegra210-dmic"; 330 reg = <0x2904000 0x100>; 331 clocks = <&bpmp TEGRA186_CLK_DMIC1>; 332 clock-names = "dmic"; 333 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 334 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 335 assigned-clock-rates = <3072000>; 336 sound-name-prefix = "DMIC1"; 337 status = "disabled"; 338 }; 339 340 tegra_dmic2: dmic@2904100 { 341 compatible = "nvidia,tegra210-dmic"; 342 reg = <0x2904100 0x100>; 343 clocks = <&bpmp TEGRA186_CLK_DMIC2>; 344 clock-names = "dmic"; 345 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 346 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 347 assigned-clock-rates = <3072000>; 348 sound-name-prefix = "DMIC2"; 349 status = "disabled"; 350 }; 351 352 tegra_dmic3: dmic@2904200 { 353 compatible = "nvidia,tegra210-dmic"; 354 reg = <0x2904200 0x100>; 355 clocks = <&bpmp TEGRA186_CLK_DMIC3>; 356 clock-names = "dmic"; 357 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 358 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 359 assigned-clock-rates = <3072000>; 360 sound-name-prefix = "DMIC3"; 361 status = "disabled"; 362 }; 363 364 tegra_dmic4: dmic@2904300 { 365 compatible = "nvidia,tegra210-dmic"; 366 reg = <0x2904300 0x100>; 367 clocks = <&bpmp TEGRA186_CLK_DMIC4>; 368 clock-names = "dmic"; 369 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 370 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 371 assigned-clock-rates = <3072000>; 372 sound-name-prefix = "DMIC4"; 373 status = "disabled"; 374 }; 375 376 tegra_dspk1: dspk@2905000 { 377 compatible = "nvidia,tegra186-dspk"; 378 reg = <0x2905000 0x100>; 379 clocks = <&bpmp TEGRA186_CLK_DSPK1>; 380 clock-names = "dspk"; 381 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 382 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 383 assigned-clock-rates = <12288000>; 384 sound-name-prefix = "DSPK1"; 385 status = "disabled"; 386 }; 387 388 tegra_dspk2: dspk@2905100 { 389 compatible = "nvidia,tegra186-dspk"; 390 reg = <0x2905100 0x100>; 391 clocks = <&bpmp TEGRA186_CLK_DSPK2>; 392 clock-names = "dspk"; 393 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 394 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 395 assigned-clock-rates = <12288000>; 396 sound-name-prefix = "DSPK2"; 397 status = "disabled"; 398 }; 399 400 tegra_sfc1: sfc@2902000 { 401 compatible = "nvidia,tegra186-sfc", 402 "nvidia,tegra210-sfc"; 403 reg = <0x2902000 0x200>; 404 sound-name-prefix = "SFC1"; 405 status = "disabled"; 406 }; 407 408 tegra_sfc2: sfc@2902200 { 409 compatible = "nvidia,tegra186-sfc", 410 "nvidia,tegra210-sfc"; 411 reg = <0x2902200 0x200>; 412 sound-name-prefix = "SFC2"; 413 status = "disabled"; 414 }; 415 416 tegra_sfc3: sfc@2902400 { 417 compatible = "nvidia,tegra186-sfc", 418 "nvidia,tegra210-sfc"; 419 reg = <0x2902400 0x200>; 420 sound-name-prefix = "SFC3"; 421 status = "disabled"; 422 }; 423 424 tegra_sfc4: sfc@2902600 { 425 compatible = "nvidia,tegra186-sfc", 426 "nvidia,tegra210-sfc"; 427 reg = <0x2902600 0x200>; 428 sound-name-prefix = "SFC4"; 429 status = "disabled"; 430 }; 431 432 tegra_mvc1: mvc@290a000 { 433 compatible = "nvidia,tegra186-mvc", 434 "nvidia,tegra210-mvc"; 435 reg = <0x290a000 0x200>; 436 sound-name-prefix = "MVC1"; 437 status = "disabled"; 438 }; 439 440 tegra_mvc2: mvc@290a200 { 441 compatible = "nvidia,tegra186-mvc", 442 "nvidia,tegra210-mvc"; 443 reg = <0x290a200 0x200>; 444 sound-name-prefix = "MVC2"; 445 status = "disabled"; 446 }; 447 448 tegra_amx1: amx@2903000 { 449 compatible = "nvidia,tegra186-amx", 450 "nvidia,tegra210-amx"; 451 reg = <0x2903000 0x100>; 452 sound-name-prefix = "AMX1"; 453 status = "disabled"; 454 }; 455 456 tegra_amx2: amx@2903100 { 457 compatible = "nvidia,tegra186-amx", 458 "nvidia,tegra210-amx"; 459 reg = <0x2903100 0x100>; 460 sound-name-prefix = "AMX2"; 461 status = "disabled"; 462 }; 463 464 tegra_amx3: amx@2903200 { 465 compatible = "nvidia,tegra186-amx", 466 "nvidia,tegra210-amx"; 467 reg = <0x2903200 0x100>; 468 sound-name-prefix = "AMX3"; 469 status = "disabled"; 470 }; 471 472 tegra_amx4: amx@2903300 { 473 compatible = "nvidia,tegra186-amx", 474 "nvidia,tegra210-amx"; 475 reg = <0x2903300 0x100>; 476 sound-name-prefix = "AMX4"; 477 status = "disabled"; 478 }; 479 480 tegra_adx1: adx@2903800 { 481 compatible = "nvidia,tegra186-adx", 482 "nvidia,tegra210-adx"; 483 reg = <0x2903800 0x100>; 484 sound-name-prefix = "ADX1"; 485 status = "disabled"; 486 }; 487 488 tegra_adx2: adx@2903900 { 489 compatible = "nvidia,tegra186-adx", 490 "nvidia,tegra210-adx"; 491 reg = <0x2903900 0x100>; 492 sound-name-prefix = "ADX2"; 493 status = "disabled"; 494 }; 495 496 tegra_adx3: adx@2903a00 { 497 compatible = "nvidia,tegra186-adx", 498 "nvidia,tegra210-adx"; 499 reg = <0x2903a00 0x100>; 500 sound-name-prefix = "ADX3"; 501 status = "disabled"; 502 }; 503 504 tegra_adx4: adx@2903b00 { 505 compatible = "nvidia,tegra186-adx", 506 "nvidia,tegra210-adx"; 507 reg = <0x2903b00 0x100>; 508 sound-name-prefix = "ADX4"; 509 status = "disabled"; 510 }; 511 512 tegra_ope1: processing-engine@2908000 { 513 compatible = "nvidia,tegra186-ope", 514 "nvidia,tegra210-ope"; 515 reg = <0x2908000 0x100>; 516 #address-cells = <1>; 517 #size-cells = <1>; 518 ranges; 519 sound-name-prefix = "OPE1"; 520 status = "disabled"; 521 522 equalizer@2908100 { 523 compatible = "nvidia,tegra186-peq", 524 "nvidia,tegra210-peq"; 525 reg = <0x2908100 0x100>; 526 }; 527 528 dynamic-range-compressor@2908200 { 529 compatible = "nvidia,tegra186-mbdrc", 530 "nvidia,tegra210-mbdrc"; 531 reg = <0x2908200 0x200>; 532 }; 533 }; 534 535 tegra_amixer: amixer@290bb00 { 536 compatible = "nvidia,tegra186-amixer", 537 "nvidia,tegra210-amixer"; 538 reg = <0x290bb00 0x800>; 539 sound-name-prefix = "MIXER1"; 540 status = "disabled"; 541 }; 542 543 tegra_asrc: asrc@2910000 { 544 compatible = "nvidia,tegra186-asrc"; 545 reg = <0x2910000 0x2000>; 546 sound-name-prefix = "ASRC1"; 547 status = "disabled"; 548 }; 549 }; 550 }; 551 552 mc: memory-controller@2c00000 { 553 compatible = "nvidia,tegra186-mc"; 554 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 555 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 556 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 557 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 558 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 559 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 560 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; 561 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 562 status = "disabled"; 563 564 #interconnect-cells = <1>; 565 #address-cells = <2>; 566 #size-cells = <2>; 567 568 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 569 570 /* 571 * Memory clients have access to all 40 bits that the memory 572 * controller can address. 573 */ 574 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 575 576 emc: external-memory-controller@2c60000 { 577 compatible = "nvidia,tegra186-emc"; 578 reg = <0x0 0x02c60000 0x0 0x50000>; 579 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&bpmp TEGRA186_CLK_EMC>; 581 clock-names = "emc"; 582 583 #interconnect-cells = <0>; 584 585 nvidia,bpmp = <&bpmp>; 586 }; 587 }; 588 589 timer@3010000 { 590 compatible = "nvidia,tegra186-timer"; 591 reg = <0x0 0x03010000 0x0 0x000e0000>; 592 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 602 status = "okay"; 603 }; 604 605 uarta: serial@3100000 { 606 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 607 reg = <0x0 0x03100000 0x0 0x40>; 608 reg-shift = <2>; 609 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&bpmp TEGRA186_CLK_UARTA>; 611 clock-names = "serial"; 612 resets = <&bpmp TEGRA186_RESET_UARTA>; 613 reset-names = "serial"; 614 status = "disabled"; 615 }; 616 617 uartb: serial@3110000 { 618 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 619 reg = <0x0 0x03110000 0x0 0x40>; 620 reg-shift = <2>; 621 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&bpmp TEGRA186_CLK_UARTB>; 623 clock-names = "serial"; 624 resets = <&bpmp TEGRA186_RESET_UARTB>; 625 reset-names = "serial"; 626 status = "disabled"; 627 }; 628 629 uartd: serial@3130000 { 630 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 631 reg = <0x0 0x03130000 0x0 0x40>; 632 reg-shift = <2>; 633 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&bpmp TEGRA186_CLK_UARTD>; 635 clock-names = "serial"; 636 resets = <&bpmp TEGRA186_RESET_UARTD>; 637 reset-names = "serial"; 638 status = "disabled"; 639 }; 640 641 uarte: serial@3140000 { 642 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 643 reg = <0x0 0x03140000 0x0 0x40>; 644 reg-shift = <2>; 645 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&bpmp TEGRA186_CLK_UARTE>; 647 clock-names = "serial"; 648 resets = <&bpmp TEGRA186_RESET_UARTE>; 649 reset-names = "serial"; 650 status = "disabled"; 651 }; 652 653 uartf: serial@3150000 { 654 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 655 reg = <0x0 0x03150000 0x0 0x40>; 656 reg-shift = <2>; 657 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&bpmp TEGRA186_CLK_UARTF>; 659 clock-names = "serial"; 660 resets = <&bpmp TEGRA186_RESET_UARTF>; 661 reset-names = "serial"; 662 status = "disabled"; 663 }; 664 665 gen1_i2c: i2c@3160000 { 666 compatible = "nvidia,tegra186-i2c"; 667 reg = <0x0 0x03160000 0x0 0x10000>; 668 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 clocks = <&bpmp TEGRA186_CLK_I2C1>; 672 clock-names = "div-clk"; 673 resets = <&bpmp TEGRA186_RESET_I2C1>; 674 reset-names = "i2c"; 675 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 676 dma-coherent; 677 dmas = <&gpcdma 21>, <&gpcdma 21>; 678 dma-names = "rx", "tx"; 679 status = "disabled"; 680 }; 681 682 cam_i2c: i2c@3180000 { 683 compatible = "nvidia,tegra186-i2c"; 684 reg = <0x0 0x03180000 0x0 0x10000>; 685 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 686 #address-cells = <1>; 687 #size-cells = <0>; 688 clocks = <&bpmp TEGRA186_CLK_I2C3>; 689 clock-names = "div-clk"; 690 resets = <&bpmp TEGRA186_RESET_I2C3>; 691 reset-names = "i2c"; 692 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 693 dma-coherent; 694 dmas = <&gpcdma 23>, <&gpcdma 23>; 695 dma-names = "rx", "tx"; 696 status = "disabled"; 697 }; 698 699 /* shares pads with dpaux1 */ 700 dp_aux_ch1_i2c: i2c@3190000 { 701 compatible = "nvidia,tegra186-i2c"; 702 reg = <0x0 0x03190000 0x0 0x10000>; 703 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 clocks = <&bpmp TEGRA186_CLK_I2C4>; 707 clock-names = "div-clk"; 708 resets = <&bpmp TEGRA186_RESET_I2C4>; 709 reset-names = "i2c"; 710 pinctrl-names = "default", "idle"; 711 pinctrl-0 = <&state_dpaux1_i2c>; 712 pinctrl-1 = <&state_dpaux1_off>; 713 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 714 dma-coherent; 715 dmas = <&gpcdma 26>, <&gpcdma 26>; 716 dma-names = "rx", "tx"; 717 status = "disabled"; 718 }; 719 720 /* controlled by BPMP, should not be enabled */ 721 pwr_i2c: i2c@31a0000 { 722 compatible = "nvidia,tegra186-i2c"; 723 reg = <0x0 0x031a0000 0x0 0x10000>; 724 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 725 #address-cells = <1>; 726 #size-cells = <0>; 727 clocks = <&bpmp TEGRA186_CLK_I2C5>; 728 clock-names = "div-clk"; 729 resets = <&bpmp TEGRA186_RESET_I2C5>; 730 reset-names = "i2c"; 731 status = "disabled"; 732 }; 733 734 /* shares pads with dpaux0 */ 735 dp_aux_ch0_i2c: i2c@31b0000 { 736 compatible = "nvidia,tegra186-i2c"; 737 reg = <0x0 0x031b0000 0x0 0x10000>; 738 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 739 #address-cells = <1>; 740 #size-cells = <0>; 741 clocks = <&bpmp TEGRA186_CLK_I2C6>; 742 clock-names = "div-clk"; 743 resets = <&bpmp TEGRA186_RESET_I2C6>; 744 reset-names = "i2c"; 745 pinctrl-names = "default", "idle"; 746 pinctrl-0 = <&state_dpaux_i2c>; 747 pinctrl-1 = <&state_dpaux_off>; 748 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 749 dma-coherent; 750 dmas = <&gpcdma 30>, <&gpcdma 30>; 751 dma-names = "rx", "tx"; 752 status = "disabled"; 753 }; 754 755 gen7_i2c: i2c@31c0000 { 756 compatible = "nvidia,tegra186-i2c"; 757 reg = <0x0 0x031c0000 0x0 0x10000>; 758 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 clocks = <&bpmp TEGRA186_CLK_I2C7>; 762 clock-names = "div-clk"; 763 resets = <&bpmp TEGRA186_RESET_I2C7>; 764 reset-names = "i2c"; 765 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 766 dma-coherent; 767 dmas = <&gpcdma 27>, <&gpcdma 27>; 768 dma-names = "rx", "tx"; 769 status = "disabled"; 770 }; 771 772 gen9_i2c: i2c@31e0000 { 773 compatible = "nvidia,tegra186-i2c"; 774 reg = <0x0 0x031e0000 0x0 0x10000>; 775 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 776 #address-cells = <1>; 777 #size-cells = <0>; 778 clocks = <&bpmp TEGRA186_CLK_I2C9>; 779 clock-names = "div-clk"; 780 resets = <&bpmp TEGRA186_RESET_I2C9>; 781 reset-names = "i2c"; 782 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 783 dma-coherent; 784 dmas = <&gpcdma 31>, <&gpcdma 31>; 785 dma-names = "rx", "tx"; 786 status = "disabled"; 787 }; 788 789 pwm1: pwm@3280000 { 790 compatible = "nvidia,tegra186-pwm"; 791 reg = <0x0 0x3280000 0x0 0x10000>; 792 clocks = <&bpmp TEGRA186_CLK_PWM1>; 793 clock-names = "pwm"; 794 resets = <&bpmp TEGRA186_RESET_PWM1>; 795 reset-names = "pwm"; 796 status = "disabled"; 797 #pwm-cells = <2>; 798 }; 799 800 pwm2: pwm@3290000 { 801 compatible = "nvidia,tegra186-pwm"; 802 reg = <0x0 0x3290000 0x0 0x10000>; 803 clocks = <&bpmp TEGRA186_CLK_PWM2>; 804 clock-names = "pwm"; 805 resets = <&bpmp TEGRA186_RESET_PWM2>; 806 reset-names = "pwm"; 807 status = "disabled"; 808 #pwm-cells = <2>; 809 }; 810 811 pwm3: pwm@32a0000 { 812 compatible = "nvidia,tegra186-pwm"; 813 reg = <0x0 0x32a0000 0x0 0x10000>; 814 clocks = <&bpmp TEGRA186_CLK_PWM3>; 815 clock-names = "pwm"; 816 resets = <&bpmp TEGRA186_RESET_PWM3>; 817 reset-names = "pwm"; 818 status = "disabled"; 819 #pwm-cells = <2>; 820 }; 821 822 pwm5: pwm@32c0000 { 823 compatible = "nvidia,tegra186-pwm"; 824 reg = <0x0 0x32c0000 0x0 0x10000>; 825 clocks = <&bpmp TEGRA186_CLK_PWM5>; 826 clock-names = "pwm"; 827 resets = <&bpmp TEGRA186_RESET_PWM5>; 828 reset-names = "pwm"; 829 status = "disabled"; 830 #pwm-cells = <2>; 831 }; 832 833 pwm6: pwm@32d0000 { 834 compatible = "nvidia,tegra186-pwm"; 835 reg = <0x0 0x32d0000 0x0 0x10000>; 836 clocks = <&bpmp TEGRA186_CLK_PWM6>; 837 clock-names = "pwm"; 838 resets = <&bpmp TEGRA186_RESET_PWM6>; 839 reset-names = "pwm"; 840 status = "disabled"; 841 #pwm-cells = <2>; 842 }; 843 844 pwm7: pwm@32e0000 { 845 compatible = "nvidia,tegra186-pwm"; 846 reg = <0x0 0x32e0000 0x0 0x10000>; 847 clocks = <&bpmp TEGRA186_CLK_PWM7>; 848 clock-names = "pwm"; 849 resets = <&bpmp TEGRA186_RESET_PWM7>; 850 reset-names = "pwm"; 851 status = "disabled"; 852 #pwm-cells = <2>; 853 }; 854 855 pwm8: pwm@32f0000 { 856 compatible = "nvidia,tegra186-pwm"; 857 reg = <0x0 0x32f0000 0x0 0x10000>; 858 clocks = <&bpmp TEGRA186_CLK_PWM8>; 859 clock-names = "pwm"; 860 resets = <&bpmp TEGRA186_RESET_PWM8>; 861 reset-names = "pwm"; 862 status = "disabled"; 863 #pwm-cells = <2>; 864 }; 865 866 sdmmc1: mmc@3400000 { 867 compatible = "nvidia,tegra186-sdhci"; 868 reg = <0x0 0x03400000 0x0 0x10000>; 869 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 871 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 872 clock-names = "sdhci", "tmclk"; 873 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 874 reset-names = "sdhci"; 875 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 876 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 877 interconnect-names = "dma-mem", "write"; 878 iommus = <&smmu TEGRA186_SID_SDMMC1>; 879 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 880 pinctrl-0 = <&sdmmc1_3v3>; 881 pinctrl-1 = <&sdmmc1_1v8>; 882 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 883 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 884 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 885 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 886 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 887 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 888 nvidia,default-tap = <0x5>; 889 nvidia,default-trim = <0xb>; 890 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 891 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 892 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 893 status = "disabled"; 894 }; 895 896 sdmmc2: mmc@3420000 { 897 compatible = "nvidia,tegra186-sdhci"; 898 reg = <0x0 0x03420000 0x0 0x10000>; 899 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 901 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 902 clock-names = "sdhci", "tmclk"; 903 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 904 reset-names = "sdhci"; 905 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 906 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 907 interconnect-names = "dma-mem", "write"; 908 iommus = <&smmu TEGRA186_SID_SDMMC2>; 909 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 910 pinctrl-0 = <&sdmmc2_3v3>; 911 pinctrl-1 = <&sdmmc2_1v8>; 912 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 913 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 914 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 915 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 916 nvidia,default-tap = <0x5>; 917 nvidia,default-trim = <0xb>; 918 status = "disabled"; 919 }; 920 921 sdmmc3: mmc@3440000 { 922 compatible = "nvidia,tegra186-sdhci"; 923 reg = <0x0 0x03440000 0x0 0x10000>; 924 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 926 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 927 clock-names = "sdhci", "tmclk"; 928 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 929 reset-names = "sdhci"; 930 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 931 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 932 interconnect-names = "dma-mem", "write"; 933 iommus = <&smmu TEGRA186_SID_SDMMC3>; 934 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 935 pinctrl-0 = <&sdmmc3_3v3>; 936 pinctrl-1 = <&sdmmc3_1v8>; 937 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 938 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 939 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 940 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 941 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 942 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 943 nvidia,default-tap = <0x5>; 944 nvidia,default-trim = <0xb>; 945 status = "disabled"; 946 }; 947 948 sdmmc4: mmc@3460000 { 949 compatible = "nvidia,tegra186-sdhci"; 950 reg = <0x0 0x03460000 0x0 0x10000>; 951 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 952 clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 953 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 954 clock-names = "sdhci", "tmclk"; 955 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 956 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 957 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 958 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 959 reset-names = "sdhci"; 960 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 961 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 962 interconnect-names = "dma-mem", "write"; 963 iommus = <&smmu TEGRA186_SID_SDMMC4>; 964 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 965 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 966 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 967 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 968 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 969 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 970 nvidia,default-tap = <0x9>; 971 nvidia,default-trim = <0x5>; 972 nvidia,dqs-trim = <63>; 973 mmc-hs400-1_8v; 974 supports-cqe; 975 status = "disabled"; 976 }; 977 978 hda@3510000 { 979 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 980 reg = <0x0 0x03510000 0x0 0x10000>; 981 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&bpmp TEGRA186_CLK_HDA>, 983 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 984 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 985 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 986 resets = <&bpmp TEGRA186_RESET_HDA>, 987 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 988 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 989 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 990 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 991 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 992 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 993 interconnect-names = "dma-mem", "write"; 994 iommus = <&smmu TEGRA186_SID_HDA>; 995 status = "disabled"; 996 }; 997 998 padctl: padctl@3520000 { 999 compatible = "nvidia,tegra186-xusb-padctl"; 1000 reg = <0x0 0x03520000 0x0 0x1000>, 1001 <0x0 0x03540000 0x0 0x1000>; 1002 reg-names = "padctl", "ao"; 1003 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1004 1005 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 1006 reset-names = "padctl"; 1007 1008 status = "disabled"; 1009 1010 pads { 1011 usb2 { 1012 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 1013 clock-names = "trk"; 1014 status = "disabled"; 1015 1016 lanes { 1017 usb2-0 { 1018 status = "disabled"; 1019 #phy-cells = <0>; 1020 }; 1021 1022 usb2-1 { 1023 status = "disabled"; 1024 #phy-cells = <0>; 1025 }; 1026 1027 usb2-2 { 1028 status = "disabled"; 1029 #phy-cells = <0>; 1030 }; 1031 }; 1032 }; 1033 1034 hsic { 1035 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 1036 clock-names = "trk"; 1037 status = "disabled"; 1038 1039 lanes { 1040 hsic-0 { 1041 status = "disabled"; 1042 #phy-cells = <0>; 1043 }; 1044 }; 1045 }; 1046 1047 usb3 { 1048 status = "disabled"; 1049 1050 lanes { 1051 usb3-0 { 1052 status = "disabled"; 1053 #phy-cells = <0>; 1054 }; 1055 1056 usb3-1 { 1057 status = "disabled"; 1058 #phy-cells = <0>; 1059 }; 1060 1061 usb3-2 { 1062 status = "disabled"; 1063 #phy-cells = <0>; 1064 }; 1065 }; 1066 }; 1067 }; 1068 1069 ports { 1070 usb2-0 { 1071 status = "disabled"; 1072 }; 1073 1074 usb2-1 { 1075 status = "disabled"; 1076 }; 1077 1078 usb2-2 { 1079 status = "disabled"; 1080 }; 1081 1082 hsic-0 { 1083 status = "disabled"; 1084 }; 1085 1086 usb3-0 { 1087 status = "disabled"; 1088 }; 1089 1090 usb3-1 { 1091 status = "disabled"; 1092 }; 1093 1094 usb3-2 { 1095 status = "disabled"; 1096 }; 1097 }; 1098 }; 1099 1100 usb@3530000 { 1101 compatible = "nvidia,tegra186-xusb"; 1102 reg = <0x0 0x03530000 0x0 0x8000>, 1103 <0x0 0x03538000 0x0 0x1000>; 1104 reg-names = "hcd", "fpci"; 1105 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1107 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 1108 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 1109 <&bpmp TEGRA186_CLK_XUSB_SS>, 1110 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1111 <&bpmp TEGRA186_CLK_CLK_M>, 1112 <&bpmp TEGRA186_CLK_XUSB_FS>, 1113 <&bpmp TEGRA186_CLK_PLLU>, 1114 <&bpmp TEGRA186_CLK_CLK_M>, 1115 <&bpmp TEGRA186_CLK_PLLE>; 1116 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 1117 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 1118 "pll_u_480m", "clk_m", "pll_e"; 1119 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 1120 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1121 power-domain-names = "xusb_host", "xusb_ss"; 1122 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1123 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1124 interconnect-names = "dma-mem", "write"; 1125 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 status = "disabled"; 1129 1130 nvidia,xusb-padctl = <&padctl>; 1131 }; 1132 1133 usb@3550000 { 1134 compatible = "nvidia,tegra186-xudc"; 1135 reg = <0x0 0x03550000 0x0 0x8000>, 1136 <0x0 0x03558000 0x0 0x1000>; 1137 reg-names = "base", "fpci"; 1138 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1139 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1140 <&bpmp TEGRA186_CLK_XUSB_SS>, 1141 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1142 <&bpmp TEGRA186_CLK_XUSB_FS>; 1143 clock-names = "dev", "ss", "ss_src", "fs_src"; 1144 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1145 <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1146 interconnect-names = "dma-mem", "write"; 1147 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1148 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1149 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1150 power-domain-names = "dev", "ss"; 1151 nvidia,xusb-padctl = <&padctl>; 1152 status = "disabled"; 1153 }; 1154 1155 fuse@3820000 { 1156 compatible = "nvidia,tegra186-efuse"; 1157 reg = <0x0 0x03820000 0x0 0x10000>; 1158 clocks = <&bpmp TEGRA186_CLK_FUSE>; 1159 clock-names = "fuse"; 1160 }; 1161 1162 gic: interrupt-controller@3881000 { 1163 compatible = "arm,gic-400"; 1164 #interrupt-cells = <3>; 1165 interrupt-controller; 1166 reg = <0x0 0x03881000 0x0 0x1000>, 1167 <0x0 0x03882000 0x0 0x2000>, 1168 <0x0 0x03884000 0x0 0x2000>, 1169 <0x0 0x03886000 0x0 0x2000>; 1170 interrupts = <GIC_PPI 9 1171 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1172 interrupt-parent = <&gic>; 1173 }; 1174 1175 cec@3960000 { 1176 compatible = "nvidia,tegra186-cec"; 1177 reg = <0x0 0x03960000 0x0 0x10000>; 1178 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1179 clocks = <&bpmp TEGRA186_CLK_CEC>; 1180 clock-names = "cec"; 1181 status = "disabled"; 1182 }; 1183 1184 hsp_top0: hsp@3c00000 { 1185 compatible = "nvidia,tegra186-hsp"; 1186 reg = <0x0 0x03c00000 0x0 0xa0000>; 1187 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1188 interrupt-names = "doorbell"; 1189 #mbox-cells = <2>; 1190 status = "disabled"; 1191 }; 1192 1193 gen2_i2c: i2c@c240000 { 1194 compatible = "nvidia,tegra186-i2c"; 1195 reg = <0x0 0x0c240000 0x0 0x10000>; 1196 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 clocks = <&bpmp TEGRA186_CLK_I2C2>; 1200 clock-names = "div-clk"; 1201 resets = <&bpmp TEGRA186_RESET_I2C2>; 1202 reset-names = "i2c"; 1203 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 1204 dma-coherent; 1205 dmas = <&gpcdma 22>, <&gpcdma 22>; 1206 dma-names = "rx", "tx"; 1207 status = "disabled"; 1208 }; 1209 1210 gen8_i2c: i2c@c250000 { 1211 compatible = "nvidia,tegra186-i2c"; 1212 reg = <0x0 0x0c250000 0x0 0x10000>; 1213 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 clocks = <&bpmp TEGRA186_CLK_I2C8>; 1217 clock-names = "div-clk"; 1218 resets = <&bpmp TEGRA186_RESET_I2C8>; 1219 reset-names = "i2c"; 1220 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 1221 dma-coherent; 1222 dmas = <&gpcdma 0>, <&gpcdma 0>; 1223 dma-names = "rx", "tx"; 1224 status = "disabled"; 1225 }; 1226 1227 uartc: serial@c280000 { 1228 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1229 reg = <0x0 0x0c280000 0x0 0x40>; 1230 reg-shift = <2>; 1231 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1232 clocks = <&bpmp TEGRA186_CLK_UARTC>; 1233 clock-names = "serial"; 1234 resets = <&bpmp TEGRA186_RESET_UARTC>; 1235 reset-names = "serial"; 1236 status = "disabled"; 1237 }; 1238 1239 uartg: serial@c290000 { 1240 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1241 reg = <0x0 0x0c290000 0x0 0x40>; 1242 reg-shift = <2>; 1243 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1244 clocks = <&bpmp TEGRA186_CLK_UARTG>; 1245 clock-names = "serial"; 1246 resets = <&bpmp TEGRA186_RESET_UARTG>; 1247 reset-names = "serial"; 1248 status = "disabled"; 1249 }; 1250 1251 rtc: rtc@c2a0000 { 1252 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 1253 reg = <0 0x0c2a0000 0 0x10000>; 1254 interrupt-parent = <&pmc>; 1255 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1256 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 1257 clock-names = "rtc"; 1258 status = "disabled"; 1259 }; 1260 1261 gpio_aon: gpio@c2f0000 { 1262 compatible = "nvidia,tegra186-gpio-aon"; 1263 reg-names = "security", "gpio"; 1264 reg = <0x0 0xc2f0000 0x0 0x1000>, 1265 <0x0 0xc2f1000 0x0 0x1000>; 1266 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1267 gpio-controller; 1268 #gpio-cells = <2>; 1269 interrupt-controller; 1270 #interrupt-cells = <2>; 1271 }; 1272 1273 pwm4: pwm@c340000 { 1274 compatible = "nvidia,tegra186-pwm"; 1275 reg = <0x0 0xc340000 0x0 0x10000>; 1276 clocks = <&bpmp TEGRA186_CLK_PWM4>; 1277 clock-names = "pwm"; 1278 resets = <&bpmp TEGRA186_RESET_PWM4>; 1279 reset-names = "pwm"; 1280 status = "disabled"; 1281 #pwm-cells = <2>; 1282 }; 1283 1284 pmc: pmc@c360000 { 1285 compatible = "nvidia,tegra186-pmc"; 1286 reg = <0 0x0c360000 0 0x10000>, 1287 <0 0x0c370000 0 0x10000>, 1288 <0 0x0c380000 0 0x10000>, 1289 <0 0x0c390000 0 0x10000>; 1290 reg-names = "pmc", "wake", "aotag", "scratch"; 1291 1292 #interrupt-cells = <2>; 1293 interrupt-controller; 1294 1295 sdmmc1_3v3: sdmmc1-3v3 { 1296 pins = "sdmmc1-hv"; 1297 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1298 }; 1299 1300 sdmmc1_1v8: sdmmc1-1v8 { 1301 pins = "sdmmc1-hv"; 1302 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1303 }; 1304 1305 sdmmc2_3v3: sdmmc2-3v3 { 1306 pins = "sdmmc2-hv"; 1307 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1308 }; 1309 1310 sdmmc2_1v8: sdmmc2-1v8 { 1311 pins = "sdmmc2-hv"; 1312 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1313 }; 1314 1315 sdmmc3_3v3: sdmmc3-3v3 { 1316 pins = "sdmmc3-hv"; 1317 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1318 }; 1319 1320 sdmmc3_1v8: sdmmc3-1v8 { 1321 pins = "sdmmc3-hv"; 1322 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1323 }; 1324 }; 1325 1326 ccplex@e000000 { 1327 compatible = "nvidia,tegra186-ccplex-cluster"; 1328 reg = <0x0 0x0e000000 0x0 0x400000>; 1329 1330 nvidia,bpmp = <&bpmp>; 1331 }; 1332 1333 pcie@10003000 { 1334 compatible = "nvidia,tegra186-pcie"; 1335 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1336 device_type = "pci"; 1337 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1338 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1339 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1340 reg-names = "pads", "afi", "cs"; 1341 1342 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1343 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1344 interrupt-names = "intr", "msi"; 1345 1346 #interrupt-cells = <1>; 1347 interrupt-map-mask = <0 0 0 0>; 1348 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1349 1350 bus-range = <0x00 0xff>; 1351 #address-cells = <3>; 1352 #size-cells = <2>; 1353 1354 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1355 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1356 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1357 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1358 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1359 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1360 1361 clocks = <&bpmp TEGRA186_CLK_PCIE>, 1362 <&bpmp TEGRA186_CLK_AFI>, 1363 <&bpmp TEGRA186_CLK_PLLE>; 1364 clock-names = "pex", "afi", "pll_e"; 1365 1366 resets = <&bpmp TEGRA186_RESET_PCIE>, 1367 <&bpmp TEGRA186_RESET_AFI>, 1368 <&bpmp TEGRA186_RESET_PCIEXCLK>; 1369 reset-names = "pex", "afi", "pcie_x"; 1370 1371 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1372 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1373 interconnect-names = "dma-mem", "write"; 1374 1375 iommus = <&smmu TEGRA186_SID_AFI>; 1376 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1377 iommu-map-mask = <0x0>; 1378 1379 status = "disabled"; 1380 1381 pci@1,0 { 1382 device_type = "pci"; 1383 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1384 reg = <0x000800 0 0 0 0>; 1385 status = "disabled"; 1386 1387 #address-cells = <3>; 1388 #size-cells = <2>; 1389 ranges; 1390 1391 nvidia,num-lanes = <2>; 1392 }; 1393 1394 pci@2,0 { 1395 device_type = "pci"; 1396 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1397 reg = <0x001000 0 0 0 0>; 1398 status = "disabled"; 1399 1400 #address-cells = <3>; 1401 #size-cells = <2>; 1402 ranges; 1403 1404 nvidia,num-lanes = <1>; 1405 }; 1406 1407 pci@3,0 { 1408 device_type = "pci"; 1409 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1410 reg = <0x001800 0 0 0 0>; 1411 status = "disabled"; 1412 1413 #address-cells = <3>; 1414 #size-cells = <2>; 1415 ranges; 1416 1417 nvidia,num-lanes = <1>; 1418 }; 1419 }; 1420 1421 smmu: iommu@12000000 { 1422 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1423 reg = <0 0x12000000 0 0x800000>; 1424 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1489 stream-match-mask = <0x7f80>; 1490 #global-interrupts = <1>; 1491 #iommu-cells = <1>; 1492 1493 nvidia,memory-controller = <&mc>; 1494 }; 1495 1496 host1x@13e00000 { 1497 compatible = "nvidia,tegra186-host1x"; 1498 reg = <0x0 0x13e00000 0x0 0x10000>, 1499 <0x0 0x13e10000 0x0 0x10000>; 1500 reg-names = "hypervisor", "vm"; 1501 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1503 interrupt-names = "syncpt", "host1x"; 1504 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 1505 clock-names = "host1x"; 1506 resets = <&bpmp TEGRA186_RESET_HOST1X>; 1507 reset-names = "host1x"; 1508 1509 #address-cells = <1>; 1510 #size-cells = <1>; 1511 1512 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1513 1514 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1515 interconnect-names = "dma-mem"; 1516 1517 iommus = <&smmu TEGRA186_SID_HOST1X>; 1518 1519 /* Context isolation domains */ 1520 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>, 1521 <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>, 1522 <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>, 1523 <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>, 1524 <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>, 1525 <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>, 1526 <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>, 1527 <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; 1528 1529 dpaux1: dpaux@15040000 { 1530 compatible = "nvidia,tegra186-dpaux"; 1531 reg = <0x15040000 0x10000>; 1532 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1533 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1534 <&bpmp TEGRA186_CLK_PLLDP>; 1535 clock-names = "dpaux", "parent"; 1536 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1537 reset-names = "dpaux"; 1538 status = "disabled"; 1539 1540 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1541 1542 state_dpaux1_aux: pinmux-aux { 1543 groups = "dpaux-io"; 1544 function = "aux"; 1545 }; 1546 1547 state_dpaux1_i2c: pinmux-i2c { 1548 groups = "dpaux-io"; 1549 function = "i2c"; 1550 }; 1551 1552 state_dpaux1_off: pinmux-off { 1553 groups = "dpaux-io"; 1554 function = "off"; 1555 }; 1556 1557 i2c-bus { 1558 #address-cells = <1>; 1559 #size-cells = <0>; 1560 }; 1561 }; 1562 1563 display-hub@15200000 { 1564 compatible = "nvidia,tegra186-display"; 1565 reg = <0x15200000 0x00040000>; 1566 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1567 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1568 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1569 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1570 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1571 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1572 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1573 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1574 "wgrp3", "wgrp4", "wgrp5"; 1575 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1576 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1577 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1578 clock-names = "disp", "dsc", "hub"; 1579 status = "disabled"; 1580 1581 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1582 1583 #address-cells = <1>; 1584 #size-cells = <1>; 1585 1586 ranges = <0x15200000 0x15200000 0x40000>; 1587 1588 display@15200000 { 1589 compatible = "nvidia,tegra186-dc"; 1590 reg = <0x15200000 0x10000>; 1591 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1592 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1593 clock-names = "dc"; 1594 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1595 reset-names = "dc"; 1596 1597 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1598 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1599 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1600 interconnect-names = "dma-mem", "read-1"; 1601 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1602 1603 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1604 nvidia,head = <0>; 1605 }; 1606 1607 display@15210000 { 1608 compatible = "nvidia,tegra186-dc"; 1609 reg = <0x15210000 0x10000>; 1610 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1611 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1612 clock-names = "dc"; 1613 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1614 reset-names = "dc"; 1615 1616 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1617 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1618 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1619 interconnect-names = "dma-mem", "read-1"; 1620 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1621 1622 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1623 nvidia,head = <1>; 1624 }; 1625 1626 display@15220000 { 1627 compatible = "nvidia,tegra186-dc"; 1628 reg = <0x15220000 0x10000>; 1629 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1630 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1631 clock-names = "dc"; 1632 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1633 reset-names = "dc"; 1634 1635 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1636 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1637 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1638 interconnect-names = "dma-mem", "read-1"; 1639 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1640 1641 nvidia,outputs = <&sor0 &sor1>; 1642 nvidia,head = <2>; 1643 }; 1644 }; 1645 1646 dsia: dsi@15300000 { 1647 compatible = "nvidia,tegra186-dsi"; 1648 reg = <0x15300000 0x10000>; 1649 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1650 clocks = <&bpmp TEGRA186_CLK_DSI>, 1651 <&bpmp TEGRA186_CLK_DSIA_LP>, 1652 <&bpmp TEGRA186_CLK_PLLD>; 1653 clock-names = "dsi", "lp", "parent"; 1654 resets = <&bpmp TEGRA186_RESET_DSI>; 1655 reset-names = "dsi"; 1656 status = "disabled"; 1657 1658 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1659 }; 1660 1661 vic@15340000 { 1662 compatible = "nvidia,tegra186-vic"; 1663 reg = <0x15340000 0x40000>; 1664 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1665 clocks = <&bpmp TEGRA186_CLK_VIC>; 1666 clock-names = "vic"; 1667 resets = <&bpmp TEGRA186_RESET_VIC>; 1668 reset-names = "vic"; 1669 1670 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1671 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1672 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1673 interconnect-names = "dma-mem", "write"; 1674 iommus = <&smmu TEGRA186_SID_VIC>; 1675 }; 1676 1677 nvjpg@15380000 { 1678 compatible = "nvidia,tegra186-nvjpg"; 1679 reg = <0x15380000 0x40000>; 1680 clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1681 clock-names = "nvjpg"; 1682 resets = <&bpmp TEGRA186_RESET_NVJPG>; 1683 reset-names = "nvjpg"; 1684 1685 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1686 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1687 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1688 interconnect-names = "dma-mem", "write"; 1689 iommus = <&smmu TEGRA186_SID_NVJPG>; 1690 }; 1691 1692 dsib: dsi@15400000 { 1693 compatible = "nvidia,tegra186-dsi"; 1694 reg = <0x15400000 0x10000>; 1695 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1696 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1697 <&bpmp TEGRA186_CLK_DSIB_LP>, 1698 <&bpmp TEGRA186_CLK_PLLD>; 1699 clock-names = "dsi", "lp", "parent"; 1700 resets = <&bpmp TEGRA186_RESET_DSIB>; 1701 reset-names = "dsi"; 1702 status = "disabled"; 1703 1704 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1705 }; 1706 1707 nvdec@15480000 { 1708 compatible = "nvidia,tegra186-nvdec"; 1709 reg = <0x15480000 0x40000>; 1710 clocks = <&bpmp TEGRA186_CLK_NVDEC>; 1711 clock-names = "nvdec"; 1712 resets = <&bpmp TEGRA186_RESET_NVDEC>; 1713 reset-names = "nvdec"; 1714 1715 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 1716 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 1717 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 1718 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 1719 interconnect-names = "dma-mem", "read-1", "write"; 1720 iommus = <&smmu TEGRA186_SID_NVDEC>; 1721 }; 1722 1723 nvenc@154c0000 { 1724 compatible = "nvidia,tegra186-nvenc"; 1725 reg = <0x154c0000 0x40000>; 1726 clocks = <&bpmp TEGRA186_CLK_NVENC>; 1727 clock-names = "nvenc"; 1728 resets = <&bpmp TEGRA186_RESET_NVENC>; 1729 reset-names = "nvenc"; 1730 1731 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1732 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1733 <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1734 interconnect-names = "dma-mem", "write"; 1735 iommus = <&smmu TEGRA186_SID_NVENC>; 1736 }; 1737 1738 sor0: sor@15540000 { 1739 compatible = "nvidia,tegra186-sor"; 1740 reg = <0x15540000 0x10000>; 1741 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1742 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1743 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1744 <&bpmp TEGRA186_CLK_PLLD2>, 1745 <&bpmp TEGRA186_CLK_PLLDP>, 1746 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1747 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1748 clock-names = "sor", "out", "parent", "dp", "safe", 1749 "pad"; 1750 resets = <&bpmp TEGRA186_RESET_SOR0>; 1751 reset-names = "sor"; 1752 pinctrl-0 = <&state_dpaux_aux>; 1753 pinctrl-1 = <&state_dpaux_i2c>; 1754 pinctrl-2 = <&state_dpaux_off>; 1755 pinctrl-names = "aux", "i2c", "off"; 1756 status = "disabled"; 1757 1758 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1759 nvidia,interface = <0>; 1760 }; 1761 1762 sor1: sor@15580000 { 1763 compatible = "nvidia,tegra186-sor"; 1764 reg = <0x15580000 0x10000>; 1765 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1766 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1767 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1768 <&bpmp TEGRA186_CLK_PLLD3>, 1769 <&bpmp TEGRA186_CLK_PLLDP>, 1770 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1771 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1772 clock-names = "sor", "out", "parent", "dp", "safe", 1773 "pad"; 1774 resets = <&bpmp TEGRA186_RESET_SOR1>; 1775 reset-names = "sor"; 1776 pinctrl-0 = <&state_dpaux1_aux>; 1777 pinctrl-1 = <&state_dpaux1_i2c>; 1778 pinctrl-2 = <&state_dpaux1_off>; 1779 pinctrl-names = "aux", "i2c", "off"; 1780 status = "disabled"; 1781 1782 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1783 nvidia,interface = <1>; 1784 }; 1785 1786 dpaux: dpaux@155c0000 { 1787 compatible = "nvidia,tegra186-dpaux"; 1788 reg = <0x155c0000 0x10000>; 1789 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1790 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1791 <&bpmp TEGRA186_CLK_PLLDP>; 1792 clock-names = "dpaux", "parent"; 1793 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1794 reset-names = "dpaux"; 1795 status = "disabled"; 1796 1797 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1798 1799 state_dpaux_aux: pinmux-aux { 1800 groups = "dpaux-io"; 1801 function = "aux"; 1802 }; 1803 1804 state_dpaux_i2c: pinmux-i2c { 1805 groups = "dpaux-io"; 1806 function = "i2c"; 1807 }; 1808 1809 state_dpaux_off: pinmux-off { 1810 groups = "dpaux-io"; 1811 function = "off"; 1812 }; 1813 1814 i2c-bus { 1815 #address-cells = <1>; 1816 #size-cells = <0>; 1817 }; 1818 }; 1819 1820 padctl@15880000 { 1821 compatible = "nvidia,tegra186-dsi-padctl"; 1822 reg = <0x15880000 0x10000>; 1823 resets = <&bpmp TEGRA186_RESET_DSI>; 1824 reset-names = "dsi"; 1825 status = "disabled"; 1826 }; 1827 1828 dsic: dsi@15900000 { 1829 compatible = "nvidia,tegra186-dsi"; 1830 reg = <0x15900000 0x10000>; 1831 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1832 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1833 <&bpmp TEGRA186_CLK_DSIC_LP>, 1834 <&bpmp TEGRA186_CLK_PLLD>; 1835 clock-names = "dsi", "lp", "parent"; 1836 resets = <&bpmp TEGRA186_RESET_DSIC>; 1837 reset-names = "dsi"; 1838 status = "disabled"; 1839 1840 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1841 }; 1842 1843 dsid: dsi@15940000 { 1844 compatible = "nvidia,tegra186-dsi"; 1845 reg = <0x15940000 0x10000>; 1846 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1847 clocks = <&bpmp TEGRA186_CLK_DSID>, 1848 <&bpmp TEGRA186_CLK_DSID_LP>, 1849 <&bpmp TEGRA186_CLK_PLLD>; 1850 clock-names = "dsi", "lp", "parent"; 1851 resets = <&bpmp TEGRA186_RESET_DSID>; 1852 reset-names = "dsi"; 1853 status = "disabled"; 1854 1855 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1856 }; 1857 }; 1858 1859 gpu@17000000 { 1860 compatible = "nvidia,gp10b"; 1861 reg = <0x0 0x17000000 0x0 0x1000000>, 1862 <0x0 0x18000000 0x0 0x1000000>; 1863 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1865 interrupt-names = "stall", "nonstall"; 1866 1867 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1868 <&bpmp TEGRA186_CLK_GPU>; 1869 clock-names = "gpu", "pwr"; 1870 resets = <&bpmp TEGRA186_RESET_GPU>; 1871 reset-names = "gpu"; 1872 status = "disabled"; 1873 1874 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1875 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1876 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1877 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1878 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1879 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1880 }; 1881 1882 sram@30000000 { 1883 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1884 reg = <0x0 0x30000000 0x0 0x50000>; 1885 #address-cells = <1>; 1886 #size-cells = <1>; 1887 ranges = <0x0 0x0 0x30000000 0x50000>; 1888 no-memory-wc; 1889 1890 cpu_bpmp_tx: sram@4e000 { 1891 reg = <0x4e000 0x1000>; 1892 label = "cpu-bpmp-tx"; 1893 pool; 1894 }; 1895 1896 cpu_bpmp_rx: sram@4f000 { 1897 reg = <0x4f000 0x1000>; 1898 label = "cpu-bpmp-rx"; 1899 pool; 1900 }; 1901 }; 1902 1903 sata@3507000 { 1904 compatible = "nvidia,tegra186-ahci"; 1905 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 1906 <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 1907 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 1908 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1909 1910 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 1911 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 1912 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 1913 interconnect-names = "dma-mem", "write"; 1914 iommus = <&smmu TEGRA186_SID_SATA>; 1915 1916 clocks = <&bpmp TEGRA186_CLK_SATA>, 1917 <&bpmp TEGRA186_CLK_SATA_OOB>; 1918 clock-names = "sata", "sata-oob"; 1919 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 1920 <&bpmp TEGRA186_CLK_SATA_OOB>; 1921 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 1922 <&bpmp TEGRA186_CLK_PLLP>; 1923 assigned-clock-rates = <102000000>, 1924 <204000000>; 1925 resets = <&bpmp TEGRA186_RESET_SATA>, 1926 <&bpmp TEGRA186_RESET_SATACOLD>; 1927 reset-names = "sata", "sata-cold"; 1928 status = "disabled"; 1929 }; 1930 1931 bpmp: bpmp { 1932 compatible = "nvidia,tegra186-bpmp"; 1933 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1934 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1935 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1936 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1937 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1938 iommus = <&smmu TEGRA186_SID_BPMP>; 1939 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1940 TEGRA_HSP_DB_MASTER_BPMP>; 1941 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1942 #clock-cells = <1>; 1943 #reset-cells = <1>; 1944 #power-domain-cells = <1>; 1945 1946 bpmp_i2c: i2c { 1947 compatible = "nvidia,tegra186-bpmp-i2c"; 1948 nvidia,bpmp-bus-id = <5>; 1949 #address-cells = <1>; 1950 #size-cells = <0>; 1951 status = "disabled"; 1952 }; 1953 1954 bpmp_thermal: thermal { 1955 compatible = "nvidia,tegra186-bpmp-thermal"; 1956 #thermal-sensor-cells = <1>; 1957 }; 1958 }; 1959 1960 cpus { 1961 #address-cells = <1>; 1962 #size-cells = <0>; 1963 1964 denver_0: cpu@0 { 1965 compatible = "nvidia,tegra186-denver"; 1966 device_type = "cpu"; 1967 i-cache-size = <0x20000>; 1968 i-cache-line-size = <64>; 1969 i-cache-sets = <512>; 1970 d-cache-size = <0x10000>; 1971 d-cache-line-size = <64>; 1972 d-cache-sets = <256>; 1973 next-level-cache = <&L2_DENVER>; 1974 reg = <0x000>; 1975 }; 1976 1977 denver_1: cpu@1 { 1978 compatible = "nvidia,tegra186-denver"; 1979 device_type = "cpu"; 1980 i-cache-size = <0x20000>; 1981 i-cache-line-size = <64>; 1982 i-cache-sets = <512>; 1983 d-cache-size = <0x10000>; 1984 d-cache-line-size = <64>; 1985 d-cache-sets = <256>; 1986 next-level-cache = <&L2_DENVER>; 1987 reg = <0x001>; 1988 }; 1989 1990 ca57_0: cpu@2 { 1991 compatible = "arm,cortex-a57"; 1992 device_type = "cpu"; 1993 i-cache-size = <0xC000>; 1994 i-cache-line-size = <64>; 1995 i-cache-sets = <256>; 1996 d-cache-size = <0x8000>; 1997 d-cache-line-size = <64>; 1998 d-cache-sets = <256>; 1999 next-level-cache = <&L2_A57>; 2000 reg = <0x100>; 2001 }; 2002 2003 ca57_1: cpu@3 { 2004 compatible = "arm,cortex-a57"; 2005 device_type = "cpu"; 2006 i-cache-size = <0xC000>; 2007 i-cache-line-size = <64>; 2008 i-cache-sets = <256>; 2009 d-cache-size = <0x8000>; 2010 d-cache-line-size = <64>; 2011 d-cache-sets = <256>; 2012 next-level-cache = <&L2_A57>; 2013 reg = <0x101>; 2014 }; 2015 2016 ca57_2: cpu@4 { 2017 compatible = "arm,cortex-a57"; 2018 device_type = "cpu"; 2019 i-cache-size = <0xC000>; 2020 i-cache-line-size = <64>; 2021 i-cache-sets = <256>; 2022 d-cache-size = <0x8000>; 2023 d-cache-line-size = <64>; 2024 d-cache-sets = <256>; 2025 next-level-cache = <&L2_A57>; 2026 reg = <0x102>; 2027 }; 2028 2029 ca57_3: cpu@5 { 2030 compatible = "arm,cortex-a57"; 2031 device_type = "cpu"; 2032 i-cache-size = <0xC000>; 2033 i-cache-line-size = <64>; 2034 i-cache-sets = <256>; 2035 d-cache-size = <0x8000>; 2036 d-cache-line-size = <64>; 2037 d-cache-sets = <256>; 2038 next-level-cache = <&L2_A57>; 2039 reg = <0x103>; 2040 }; 2041 2042 L2_DENVER: l2-cache0 { 2043 compatible = "cache"; 2044 cache-unified; 2045 cache-level = <2>; 2046 cache-size = <0x200000>; 2047 cache-line-size = <64>; 2048 cache-sets = <2048>; 2049 }; 2050 2051 L2_A57: l2-cache1 { 2052 compatible = "cache"; 2053 cache-unified; 2054 cache-level = <2>; 2055 cache-size = <0x200000>; 2056 cache-line-size = <64>; 2057 cache-sets = <2048>; 2058 }; 2059 }; 2060 2061 pmu_denver { 2062 compatible = "nvidia,denver-pmu"; 2063 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2064 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2065 interrupt-affinity = <&denver_0 &denver_1>; 2066 }; 2067 2068 pmu_a57 { 2069 compatible = "arm,cortex-a57-pmu"; 2070 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2071 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2072 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 2073 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 2074 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 2075 }; 2076 2077 sound { 2078 status = "disabled"; 2079 2080 clocks = <&bpmp TEGRA186_CLK_PLLA>, 2081 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2082 clock-names = "pll_a", "plla_out0"; 2083 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2084 <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2085 <&bpmp TEGRA186_CLK_AUD_MCLK>; 2086 assigned-clock-parents = <0>, 2087 <&bpmp TEGRA186_CLK_PLLA>, 2088 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2089 /* 2090 * PLLA supports dynamic ramp. Below initial rate is chosen 2091 * for this to work and oscillate between base rates required 2092 * for 8x and 11.025x sample rate streams. 2093 */ 2094 assigned-clock-rates = <258000000>; 2095 2096 iommus = <&smmu TEGRA186_SID_APE>; 2097 }; 2098 2099 thermal-zones { 2100 /* Cortex-A57 cluster */ 2101 cpu-thermal { 2102 polling-delay = <0>; 2103 polling-delay-passive = <1000>; 2104 2105 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 2106 2107 trips { 2108 critical { 2109 temperature = <101000>; 2110 hysteresis = <0>; 2111 type = "critical"; 2112 }; 2113 }; 2114 2115 cooling-maps { 2116 }; 2117 }; 2118 2119 /* Denver cluster */ 2120 aux-thermal { 2121 polling-delay = <0>; 2122 polling-delay-passive = <1000>; 2123 2124 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 2125 2126 trips { 2127 critical { 2128 temperature = <101000>; 2129 hysteresis = <0>; 2130 type = "critical"; 2131 }; 2132 }; 2133 2134 cooling-maps { 2135 }; 2136 }; 2137 2138 gpu-thermal { 2139 polling-delay = <0>; 2140 polling-delay-passive = <1000>; 2141 2142 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 2143 2144 trips { 2145 critical { 2146 temperature = <101000>; 2147 hysteresis = <0>; 2148 type = "critical"; 2149 }; 2150 }; 2151 2152 cooling-maps { 2153 }; 2154 }; 2155 2156 pll-thermal { 2157 polling-delay = <0>; 2158 polling-delay-passive = <1000>; 2159 2160 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 2161 2162 trips { 2163 critical { 2164 temperature = <101000>; 2165 hysteresis = <0>; 2166 type = "critical"; 2167 }; 2168 }; 2169 2170 cooling-maps { 2171 }; 2172 }; 2173 2174 ao-thermal { 2175 polling-delay = <0>; 2176 polling-delay-passive = <1000>; 2177 2178 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 2179 2180 trips { 2181 critical { 2182 temperature = <101000>; 2183 hysteresis = <0>; 2184 type = "critical"; 2185 }; 2186 }; 2187 2188 cooling-maps { 2189 }; 2190 }; 2191 }; 2192 2193 timer { 2194 compatible = "arm,armv8-timer"; 2195 interrupts = <GIC_PPI 13 2196 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2197 <GIC_PPI 14 2198 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2199 <GIC_PPI 11 2200 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2201 <GIC_PPI 10 2202 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2203 interrupt-parent = <&gic>; 2204 always-on; 2205 }; 2206}; 2207