1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 gpio-ranges = <&pinmux 0 0 140>; 40 }; 41 42 pinmux: pinmux@2430000 { 43 compatible = "nvidia,tegra186-pinmux"; 44 reg = <0x0 0x2430000 0x0 0x15000>; 45 }; 46 47 ethernet@2490000 { 48 compatible = "nvidia,tegra186-eqos", 49 "snps,dwc-qos-ethernet-4.10"; 50 reg = <0x0 0x02490000 0x0 0x10000>; 51 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 52 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 53 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 54 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 55 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 56 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 57 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 58 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 59 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 60 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 61 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 62 <&bpmp TEGRA186_CLK_EQOS_AXI>, 63 <&bpmp TEGRA186_CLK_EQOS_RX>, 64 <&bpmp TEGRA186_CLK_EQOS_TX>, 65 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 66 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 67 resets = <&bpmp TEGRA186_RESET_EQOS>; 68 reset-names = "eqos"; 69 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 70 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 71 interconnect-names = "dma-mem", "write"; 72 iommus = <&smmu TEGRA186_SID_EQOS>; 73 status = "disabled"; 74 75 snps,write-requests = <1>; 76 snps,read-requests = <3>; 77 snps,burst-map = <0x7>; 78 snps,txpbl = <32>; 79 snps,rxpbl = <8>; 80 }; 81 82 gpcdma: dma-controller@2600000 { 83 compatible = "nvidia,tegra186-gpcdma"; 84 reg = <0x0 0x2600000 0x0 0x210000>; 85 resets = <&bpmp TEGRA186_RESET_GPCDMA>; 86 reset-names = "gpcdma"; 87 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 119 #dma-cells = <1>; 120 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 121 dma-coherent; 122 dma-channel-mask = <0xfffffffe>; 123 }; 124 125 aconnect@2900000 { 126 compatible = "nvidia,tegra186-aconnect", 127 "nvidia,tegra210-aconnect"; 128 clocks = <&bpmp TEGRA186_CLK_APE>, 129 <&bpmp TEGRA186_CLK_APB2APE>; 130 clock-names = "ape", "apb2ape"; 131 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 132 #address-cells = <2>; 133 #size-cells = <2>; 134 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 135 status = "disabled"; 136 137 tegra_ahub: ahub@2900800 { 138 compatible = "nvidia,tegra186-ahub"; 139 reg = <0x0 0x02900800 0x0 0x800>; 140 clocks = <&bpmp TEGRA186_CLK_AHUB>; 141 clock-names = "ahub"; 142 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 143 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 144 assigned-clock-rates = <81600000>; 145 #address-cells = <2>; 146 #size-cells = <2>; 147 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 148 status = "disabled"; 149 150 tegra_i2s1: i2s@2901000 { 151 compatible = "nvidia,tegra186-i2s", 152 "nvidia,tegra210-i2s"; 153 reg = <0x0 0x2901000 0x0 0x100>; 154 clocks = <&bpmp TEGRA186_CLK_I2S1>, 155 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 156 clock-names = "i2s", "sync_input"; 157 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 158 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 159 assigned-clock-rates = <1536000>; 160 sound-name-prefix = "I2S1"; 161 status = "disabled"; 162 }; 163 164 tegra_i2s2: i2s@2901100 { 165 compatible = "nvidia,tegra186-i2s", 166 "nvidia,tegra210-i2s"; 167 reg = <0x0 0x2901100 0x0 0x100>; 168 clocks = <&bpmp TEGRA186_CLK_I2S2>, 169 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 170 clock-names = "i2s", "sync_input"; 171 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 172 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 173 assigned-clock-rates = <1536000>; 174 sound-name-prefix = "I2S2"; 175 status = "disabled"; 176 }; 177 178 tegra_i2s3: i2s@2901200 { 179 compatible = "nvidia,tegra186-i2s", 180 "nvidia,tegra210-i2s"; 181 reg = <0x0 0x2901200 0x0 0x100>; 182 clocks = <&bpmp TEGRA186_CLK_I2S3>, 183 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 184 clock-names = "i2s", "sync_input"; 185 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 186 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 187 assigned-clock-rates = <1536000>; 188 sound-name-prefix = "I2S3"; 189 status = "disabled"; 190 }; 191 192 tegra_i2s4: i2s@2901300 { 193 compatible = "nvidia,tegra186-i2s", 194 "nvidia,tegra210-i2s"; 195 reg = <0x0 0x2901300 0x0 0x100>; 196 clocks = <&bpmp TEGRA186_CLK_I2S4>, 197 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 198 clock-names = "i2s", "sync_input"; 199 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 200 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 201 assigned-clock-rates = <1536000>; 202 sound-name-prefix = "I2S4"; 203 status = "disabled"; 204 }; 205 206 tegra_i2s5: i2s@2901400 { 207 compatible = "nvidia,tegra186-i2s", 208 "nvidia,tegra210-i2s"; 209 reg = <0x0 0x2901400 0x0 0x100>; 210 clocks = <&bpmp TEGRA186_CLK_I2S5>, 211 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 212 clock-names = "i2s", "sync_input"; 213 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 214 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 215 assigned-clock-rates = <1536000>; 216 sound-name-prefix = "I2S5"; 217 status = "disabled"; 218 }; 219 220 tegra_i2s6: i2s@2901500 { 221 compatible = "nvidia,tegra186-i2s", 222 "nvidia,tegra210-i2s"; 223 reg = <0x0 0x2901500 0x0 0x100>; 224 clocks = <&bpmp TEGRA186_CLK_I2S6>, 225 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 226 clock-names = "i2s", "sync_input"; 227 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 228 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 229 assigned-clock-rates = <1536000>; 230 sound-name-prefix = "I2S6"; 231 status = "disabled"; 232 }; 233 234 tegra_sfc1: sfc@2902000 { 235 compatible = "nvidia,tegra186-sfc", 236 "nvidia,tegra210-sfc"; 237 reg = <0x0 0x2902000 0x0 0x200>; 238 sound-name-prefix = "SFC1"; 239 status = "disabled"; 240 }; 241 242 tegra_sfc2: sfc@2902200 { 243 compatible = "nvidia,tegra186-sfc", 244 "nvidia,tegra210-sfc"; 245 reg = <0x0 0x2902200 0x0 0x200>; 246 sound-name-prefix = "SFC2"; 247 status = "disabled"; 248 }; 249 250 tegra_sfc3: sfc@2902400 { 251 compatible = "nvidia,tegra186-sfc", 252 "nvidia,tegra210-sfc"; 253 reg = <0x0 0x2902400 0x0 0x200>; 254 sound-name-prefix = "SFC3"; 255 status = "disabled"; 256 }; 257 258 tegra_sfc4: sfc@2902600 { 259 compatible = "nvidia,tegra186-sfc", 260 "nvidia,tegra210-sfc"; 261 reg = <0x0 0x2902600 0x0 0x200>; 262 sound-name-prefix = "SFC4"; 263 status = "disabled"; 264 }; 265 266 tegra_amx1: amx@2903000 { 267 compatible = "nvidia,tegra186-amx", 268 "nvidia,tegra210-amx"; 269 reg = <0x0 0x2903000 0x0 0x100>; 270 sound-name-prefix = "AMX1"; 271 status = "disabled"; 272 }; 273 274 tegra_amx2: amx@2903100 { 275 compatible = "nvidia,tegra186-amx", 276 "nvidia,tegra210-amx"; 277 reg = <0x0 0x2903100 0x0 0x100>; 278 sound-name-prefix = "AMX2"; 279 status = "disabled"; 280 }; 281 282 tegra_amx3: amx@2903200 { 283 compatible = "nvidia,tegra186-amx", 284 "nvidia,tegra210-amx"; 285 reg = <0x0 0x2903200 0x0 0x100>; 286 sound-name-prefix = "AMX3"; 287 status = "disabled"; 288 }; 289 290 tegra_amx4: amx@2903300 { 291 compatible = "nvidia,tegra186-amx", 292 "nvidia,tegra210-amx"; 293 reg = <0x0 0x2903300 0x0 0x100>; 294 sound-name-prefix = "AMX4"; 295 status = "disabled"; 296 }; 297 298 tegra_adx1: adx@2903800 { 299 compatible = "nvidia,tegra186-adx", 300 "nvidia,tegra210-adx"; 301 reg = <0x0 0x2903800 0x0 0x100>; 302 sound-name-prefix = "ADX1"; 303 status = "disabled"; 304 }; 305 306 tegra_adx2: adx@2903900 { 307 compatible = "nvidia,tegra186-adx", 308 "nvidia,tegra210-adx"; 309 reg = <0x0 0x2903900 0x0 0x100>; 310 sound-name-prefix = "ADX2"; 311 status = "disabled"; 312 }; 313 314 tegra_adx3: adx@2903a00 { 315 compatible = "nvidia,tegra186-adx", 316 "nvidia,tegra210-adx"; 317 reg = <0x0 0x2903a00 0x0 0x100>; 318 sound-name-prefix = "ADX3"; 319 status = "disabled"; 320 }; 321 322 tegra_adx4: adx@2903b00 { 323 compatible = "nvidia,tegra186-adx", 324 "nvidia,tegra210-adx"; 325 reg = <0x0 0x2903b00 0x0 0x100>; 326 sound-name-prefix = "ADX4"; 327 status = "disabled"; 328 }; 329 330 tegra_dmic1: dmic@2904000 { 331 compatible = "nvidia,tegra210-dmic"; 332 reg = <0x0 0x2904000 0x0 0x100>; 333 clocks = <&bpmp TEGRA186_CLK_DMIC1>; 334 clock-names = "dmic"; 335 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 336 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 337 assigned-clock-rates = <3072000>; 338 sound-name-prefix = "DMIC1"; 339 status = "disabled"; 340 }; 341 342 tegra_dmic2: dmic@2904100 { 343 compatible = "nvidia,tegra210-dmic"; 344 reg = <0x0 0x2904100 0x0 0x100>; 345 clocks = <&bpmp TEGRA186_CLK_DMIC2>; 346 clock-names = "dmic"; 347 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 348 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 349 assigned-clock-rates = <3072000>; 350 sound-name-prefix = "DMIC2"; 351 status = "disabled"; 352 }; 353 354 tegra_dmic3: dmic@2904200 { 355 compatible = "nvidia,tegra210-dmic"; 356 reg = <0x0 0x2904200 0x0 0x100>; 357 clocks = <&bpmp TEGRA186_CLK_DMIC3>; 358 clock-names = "dmic"; 359 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 360 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 361 assigned-clock-rates = <3072000>; 362 sound-name-prefix = "DMIC3"; 363 status = "disabled"; 364 }; 365 366 tegra_dmic4: dmic@2904300 { 367 compatible = "nvidia,tegra210-dmic"; 368 reg = <0x0 0x2904300 0x0 0x100>; 369 clocks = <&bpmp TEGRA186_CLK_DMIC4>; 370 clock-names = "dmic"; 371 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 372 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 373 assigned-clock-rates = <3072000>; 374 sound-name-prefix = "DMIC4"; 375 status = "disabled"; 376 }; 377 378 tegra_dspk1: dspk@2905000 { 379 compatible = "nvidia,tegra186-dspk"; 380 reg = <0x0 0x2905000 0x0 0x100>; 381 clocks = <&bpmp TEGRA186_CLK_DSPK1>; 382 clock-names = "dspk"; 383 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 384 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 385 assigned-clock-rates = <12288000>; 386 sound-name-prefix = "DSPK1"; 387 status = "disabled"; 388 }; 389 390 tegra_dspk2: dspk@2905100 { 391 compatible = "nvidia,tegra186-dspk"; 392 reg = <0x0 0x2905100 0x0 0x100>; 393 clocks = <&bpmp TEGRA186_CLK_DSPK2>; 394 clock-names = "dspk"; 395 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 396 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 397 assigned-clock-rates = <12288000>; 398 sound-name-prefix = "DSPK2"; 399 status = "disabled"; 400 }; 401 402 tegra_ope1: processing-engine@2908000 { 403 compatible = "nvidia,tegra186-ope", 404 "nvidia,tegra210-ope"; 405 reg = <0x0 0x2908000 0x0 0x100>; 406 #address-cells = <2>; 407 #size-cells = <2>; 408 ranges; 409 sound-name-prefix = "OPE1"; 410 status = "disabled"; 411 412 equalizer@2908100 { 413 compatible = "nvidia,tegra186-peq", 414 "nvidia,tegra210-peq"; 415 reg = <0x0 0x2908100 0x0 0x100>; 416 }; 417 418 dynamic-range-compressor@2908200 { 419 compatible = "nvidia,tegra186-mbdrc", 420 "nvidia,tegra210-mbdrc"; 421 reg = <0x0 0x2908200 0x0 0x200>; 422 }; 423 }; 424 425 tegra_mvc1: mvc@290a000 { 426 compatible = "nvidia,tegra186-mvc", 427 "nvidia,tegra210-mvc"; 428 reg = <0x0 0x290a000 0x0 0x200>; 429 sound-name-prefix = "MVC1"; 430 status = "disabled"; 431 }; 432 433 tegra_mvc2: mvc@290a200 { 434 compatible = "nvidia,tegra186-mvc", 435 "nvidia,tegra210-mvc"; 436 reg = <0x0 0x290a200 0x0 0x200>; 437 sound-name-prefix = "MVC2"; 438 status = "disabled"; 439 }; 440 441 tegra_amixer: amixer@290bb00 { 442 compatible = "nvidia,tegra186-amixer", 443 "nvidia,tegra210-amixer"; 444 reg = <0x0 0x290bb00 0x0 0x800>; 445 sound-name-prefix = "MIXER1"; 446 status = "disabled"; 447 }; 448 449 tegra_admaif: admaif@290f000 { 450 compatible = "nvidia,tegra186-admaif"; 451 reg = <0x0 0x0290f000 0x0 0x1000>; 452 dmas = <&adma 1>, <&adma 1>, 453 <&adma 2>, <&adma 2>, 454 <&adma 3>, <&adma 3>, 455 <&adma 4>, <&adma 4>, 456 <&adma 5>, <&adma 5>, 457 <&adma 6>, <&adma 6>, 458 <&adma 7>, <&adma 7>, 459 <&adma 8>, <&adma 8>, 460 <&adma 9>, <&adma 9>, 461 <&adma 10>, <&adma 10>, 462 <&adma 11>, <&adma 11>, 463 <&adma 12>, <&adma 12>, 464 <&adma 13>, <&adma 13>, 465 <&adma 14>, <&adma 14>, 466 <&adma 15>, <&adma 15>, 467 <&adma 16>, <&adma 16>, 468 <&adma 17>, <&adma 17>, 469 <&adma 18>, <&adma 18>, 470 <&adma 19>, <&adma 19>, 471 <&adma 20>, <&adma 20>; 472 dma-names = "rx1", "tx1", 473 "rx2", "tx2", 474 "rx3", "tx3", 475 "rx4", "tx4", 476 "rx5", "tx5", 477 "rx6", "tx6", 478 "rx7", "tx7", 479 "rx8", "tx8", 480 "rx9", "tx9", 481 "rx10", "tx10", 482 "rx11", "tx11", 483 "rx12", "tx12", 484 "rx13", "tx13", 485 "rx14", "tx14", 486 "rx15", "tx15", 487 "rx16", "tx16", 488 "rx17", "tx17", 489 "rx18", "tx18", 490 "rx19", "tx19", 491 "rx20", "tx20"; 492 status = "disabled"; 493 }; 494 495 tegra_asrc: asrc@2910000 { 496 compatible = "nvidia,tegra186-asrc"; 497 reg = <0x0 0x2910000 0x0 0x2000>; 498 sound-name-prefix = "ASRC1"; 499 status = "disabled"; 500 }; 501 }; 502 503 adma: dma-controller@2930000 { 504 compatible = "nvidia,tegra186-adma"; 505 reg = <0x0 0x02930000 0x0 0x20000>; 506 interrupt-parent = <&agic>; 507 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 539 #dma-cells = <1>; 540 clocks = <&bpmp TEGRA186_CLK_AHUB>; 541 clock-names = "d_audio"; 542 status = "disabled"; 543 }; 544 545 agic: interrupt-controller@2a40000 { 546 compatible = "nvidia,tegra186-agic", 547 "nvidia,tegra210-agic"; 548 #interrupt-cells = <3>; 549 interrupt-controller; 550 reg = <0x0 0x02a41000 0x0 0x1000>, 551 <0x0 0x02a42000 0x0 0x2000>; 552 interrupts = <GIC_SPI 145 553 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 554 clocks = <&bpmp TEGRA186_CLK_APE>; 555 clock-names = "clk"; 556 status = "disabled"; 557 }; 558 }; 559 560 mc: memory-controller@2c00000 { 561 compatible = "nvidia,tegra186-mc"; 562 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 563 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 564 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 565 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 566 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 567 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 568 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; 569 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 570 status = "disabled"; 571 572 #interconnect-cells = <1>; 573 #address-cells = <2>; 574 #size-cells = <2>; 575 576 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 577 578 /* 579 * Memory clients have access to all 40 bits that the memory 580 * controller can address. 581 */ 582 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 583 584 emc: external-memory-controller@2c60000 { 585 compatible = "nvidia,tegra186-emc"; 586 reg = <0x0 0x02c60000 0x0 0x50000>; 587 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&bpmp TEGRA186_CLK_EMC>; 589 clock-names = "emc"; 590 591 #interconnect-cells = <0>; 592 593 nvidia,bpmp = <&bpmp>; 594 }; 595 }; 596 597 timer@3010000 { 598 compatible = "nvidia,tegra186-timer"; 599 reg = <0x0 0x03010000 0x0 0x000e0000>; 600 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 610 }; 611 612 uarta: serial@3100000 { 613 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 614 reg = <0x0 0x03100000 0x0 0x40>; 615 reg-shift = <2>; 616 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&bpmp TEGRA186_CLK_UARTA>; 618 resets = <&bpmp TEGRA186_RESET_UARTA>; 619 dmas = <&gpcdma 8>, <&gpcdma 8>; 620 dma-names = "rx", "tx"; 621 status = "disabled"; 622 }; 623 624 uartb: serial@3110000 { 625 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 626 reg = <0x0 0x03110000 0x0 0x40>; 627 reg-shift = <2>; 628 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&bpmp TEGRA186_CLK_UARTB>; 630 resets = <&bpmp TEGRA186_RESET_UARTB>; 631 dmas = <&gpcdma 9>, <&gpcdma 9>; 632 dma-names = "rx", "tx"; 633 status = "disabled"; 634 }; 635 636 uartd: serial@3130000 { 637 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 638 reg = <0x0 0x03130000 0x0 0x40>; 639 reg-shift = <2>; 640 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&bpmp TEGRA186_CLK_UARTD>; 642 resets = <&bpmp TEGRA186_RESET_UARTD>; 643 dmas = <&gpcdma 19>, <&gpcdma 19>; 644 dma-names = "rx", "tx"; 645 status = "disabled"; 646 }; 647 648 uarte: serial@3140000 { 649 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 650 reg = <0x0 0x03140000 0x0 0x40>; 651 reg-shift = <2>; 652 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&bpmp TEGRA186_CLK_UARTE>; 654 resets = <&bpmp TEGRA186_RESET_UARTE>; 655 dmas = <&gpcdma 20>, <&gpcdma 20>; 656 dma-names = "rx", "tx"; 657 status = "disabled"; 658 }; 659 660 uartf: serial@3150000 { 661 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 662 reg = <0x0 0x03150000 0x0 0x40>; 663 reg-shift = <2>; 664 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&bpmp TEGRA186_CLK_UARTF>; 666 resets = <&bpmp TEGRA186_RESET_UARTF>; 667 dmas = <&gpcdma 12>, <&gpcdma 12>; 668 dma-names = "rx", "tx"; 669 status = "disabled"; 670 }; 671 672 gen1_i2c: i2c@3160000 { 673 compatible = "nvidia,tegra186-i2c"; 674 reg = <0x0 0x03160000 0x0 0x10000>; 675 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 676 #address-cells = <1>; 677 #size-cells = <0>; 678 clocks = <&bpmp TEGRA186_CLK_I2C1>; 679 clock-names = "div-clk"; 680 resets = <&bpmp TEGRA186_RESET_I2C1>; 681 reset-names = "i2c"; 682 dmas = <&gpcdma 21>, <&gpcdma 21>; 683 dma-names = "rx", "tx"; 684 status = "disabled"; 685 }; 686 687 cam_i2c: i2c@3180000 { 688 compatible = "nvidia,tegra186-i2c"; 689 reg = <0x0 0x03180000 0x0 0x10000>; 690 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 691 #address-cells = <1>; 692 #size-cells = <0>; 693 clocks = <&bpmp TEGRA186_CLK_I2C3>; 694 clock-names = "div-clk"; 695 resets = <&bpmp TEGRA186_RESET_I2C3>; 696 reset-names = "i2c"; 697 dmas = <&gpcdma 23>, <&gpcdma 23>; 698 dma-names = "rx", "tx"; 699 status = "disabled"; 700 }; 701 702 /* shares pads with dpaux1 */ 703 dp_aux_ch1_i2c: i2c@3190000 { 704 compatible = "nvidia,tegra186-i2c"; 705 reg = <0x0 0x03190000 0x0 0x10000>; 706 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 clocks = <&bpmp TEGRA186_CLK_I2C4>; 710 clock-names = "div-clk"; 711 resets = <&bpmp TEGRA186_RESET_I2C4>; 712 reset-names = "i2c"; 713 pinctrl-names = "default", "idle"; 714 pinctrl-0 = <&state_dpaux1_i2c>; 715 pinctrl-1 = <&state_dpaux1_off>; 716 dmas = <&gpcdma 26>, <&gpcdma 26>; 717 dma-names = "rx", "tx"; 718 status = "disabled"; 719 }; 720 721 /* controlled by BPMP, should not be enabled */ 722 pwr_i2c: i2c@31a0000 { 723 compatible = "nvidia,tegra186-i2c"; 724 reg = <0x0 0x031a0000 0x0 0x10000>; 725 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 726 #address-cells = <1>; 727 #size-cells = <0>; 728 clocks = <&bpmp TEGRA186_CLK_I2C5>; 729 clock-names = "div-clk"; 730 resets = <&bpmp TEGRA186_RESET_I2C5>; 731 reset-names = "i2c"; 732 status = "disabled"; 733 }; 734 735 /* shares pads with dpaux0 */ 736 dp_aux_ch0_i2c: i2c@31b0000 { 737 compatible = "nvidia,tegra186-i2c"; 738 reg = <0x0 0x031b0000 0x0 0x10000>; 739 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 clocks = <&bpmp TEGRA186_CLK_I2C6>; 743 clock-names = "div-clk"; 744 resets = <&bpmp TEGRA186_RESET_I2C6>; 745 reset-names = "i2c"; 746 pinctrl-names = "default", "idle"; 747 pinctrl-0 = <&state_dpaux_i2c>; 748 pinctrl-1 = <&state_dpaux_off>; 749 dmas = <&gpcdma 30>, <&gpcdma 30>; 750 dma-names = "rx", "tx"; 751 status = "disabled"; 752 }; 753 754 gen7_i2c: i2c@31c0000 { 755 compatible = "nvidia,tegra186-i2c"; 756 reg = <0x0 0x031c0000 0x0 0x10000>; 757 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 clocks = <&bpmp TEGRA186_CLK_I2C7>; 761 clock-names = "div-clk"; 762 resets = <&bpmp TEGRA186_RESET_I2C7>; 763 reset-names = "i2c"; 764 dmas = <&gpcdma 27>, <&gpcdma 27>; 765 dma-names = "rx", "tx"; 766 status = "disabled"; 767 }; 768 769 gen9_i2c: i2c@31e0000 { 770 compatible = "nvidia,tegra186-i2c"; 771 reg = <0x0 0x031e0000 0x0 0x10000>; 772 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 clocks = <&bpmp TEGRA186_CLK_I2C9>; 776 clock-names = "div-clk"; 777 resets = <&bpmp TEGRA186_RESET_I2C9>; 778 reset-names = "i2c"; 779 dmas = <&gpcdma 31>, <&gpcdma 31>; 780 dma-names = "rx", "tx"; 781 status = "disabled"; 782 }; 783 784 pwm1: pwm@3280000 { 785 compatible = "nvidia,tegra186-pwm"; 786 reg = <0x0 0x3280000 0x0 0x10000>; 787 clocks = <&bpmp TEGRA186_CLK_PWM1>; 788 resets = <&bpmp TEGRA186_RESET_PWM1>; 789 reset-names = "pwm"; 790 status = "disabled"; 791 #pwm-cells = <2>; 792 }; 793 794 pwm2: pwm@3290000 { 795 compatible = "nvidia,tegra186-pwm"; 796 reg = <0x0 0x3290000 0x0 0x10000>; 797 clocks = <&bpmp TEGRA186_CLK_PWM2>; 798 resets = <&bpmp TEGRA186_RESET_PWM2>; 799 reset-names = "pwm"; 800 status = "disabled"; 801 #pwm-cells = <2>; 802 }; 803 804 pwm3: pwm@32a0000 { 805 compatible = "nvidia,tegra186-pwm"; 806 reg = <0x0 0x32a0000 0x0 0x10000>; 807 clocks = <&bpmp TEGRA186_CLK_PWM3>; 808 resets = <&bpmp TEGRA186_RESET_PWM3>; 809 reset-names = "pwm"; 810 status = "disabled"; 811 #pwm-cells = <2>; 812 }; 813 814 pwm5: pwm@32c0000 { 815 compatible = "nvidia,tegra186-pwm"; 816 reg = <0x0 0x32c0000 0x0 0x10000>; 817 clocks = <&bpmp TEGRA186_CLK_PWM5>; 818 resets = <&bpmp TEGRA186_RESET_PWM5>; 819 reset-names = "pwm"; 820 status = "disabled"; 821 #pwm-cells = <2>; 822 }; 823 824 pwm6: pwm@32d0000 { 825 compatible = "nvidia,tegra186-pwm"; 826 reg = <0x0 0x32d0000 0x0 0x10000>; 827 clocks = <&bpmp TEGRA186_CLK_PWM6>; 828 resets = <&bpmp TEGRA186_RESET_PWM6>; 829 reset-names = "pwm"; 830 status = "disabled"; 831 #pwm-cells = <2>; 832 }; 833 834 pwm7: pwm@32e0000 { 835 compatible = "nvidia,tegra186-pwm"; 836 reg = <0x0 0x32e0000 0x0 0x10000>; 837 clocks = <&bpmp TEGRA186_CLK_PWM7>; 838 resets = <&bpmp TEGRA186_RESET_PWM7>; 839 reset-names = "pwm"; 840 status = "disabled"; 841 #pwm-cells = <2>; 842 }; 843 844 pwm8: pwm@32f0000 { 845 compatible = "nvidia,tegra186-pwm"; 846 reg = <0x0 0x32f0000 0x0 0x10000>; 847 clocks = <&bpmp TEGRA186_CLK_PWM8>; 848 resets = <&bpmp TEGRA186_RESET_PWM8>; 849 reset-names = "pwm"; 850 status = "disabled"; 851 #pwm-cells = <2>; 852 }; 853 854 sdmmc1: mmc@3400000 { 855 compatible = "nvidia,tegra186-sdhci"; 856 reg = <0x0 0x03400000 0x0 0x10000>; 857 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 858 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 859 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 860 clock-names = "sdhci", "tmclk"; 861 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 862 reset-names = "sdhci"; 863 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 864 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 865 interconnect-names = "dma-mem", "write"; 866 iommus = <&smmu TEGRA186_SID_SDMMC1>; 867 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 868 pinctrl-0 = <&sdmmc1_3v3>; 869 pinctrl-1 = <&sdmmc1_1v8>; 870 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 871 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 872 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 873 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 874 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 875 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 876 nvidia,default-tap = <0x5>; 877 nvidia,default-trim = <0xb>; 878 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 879 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 880 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 881 status = "disabled"; 882 }; 883 884 sdmmc2: mmc@3420000 { 885 compatible = "nvidia,tegra186-sdhci"; 886 reg = <0x0 0x03420000 0x0 0x10000>; 887 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 889 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 890 clock-names = "sdhci", "tmclk"; 891 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 892 reset-names = "sdhci"; 893 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 894 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 895 interconnect-names = "dma-mem", "write"; 896 iommus = <&smmu TEGRA186_SID_SDMMC2>; 897 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 898 pinctrl-0 = <&sdmmc2_3v3>; 899 pinctrl-1 = <&sdmmc2_1v8>; 900 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 901 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 902 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 903 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 904 nvidia,default-tap = <0x5>; 905 nvidia,default-trim = <0xb>; 906 status = "disabled"; 907 }; 908 909 sdmmc3: mmc@3440000 { 910 compatible = "nvidia,tegra186-sdhci"; 911 reg = <0x0 0x03440000 0x0 0x10000>; 912 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 914 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 915 clock-names = "sdhci", "tmclk"; 916 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 917 reset-names = "sdhci"; 918 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 919 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 920 interconnect-names = "dma-mem", "write"; 921 iommus = <&smmu TEGRA186_SID_SDMMC3>; 922 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 923 pinctrl-0 = <&sdmmc3_3v3>; 924 pinctrl-1 = <&sdmmc3_1v8>; 925 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 926 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 927 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 928 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 929 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 930 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 931 nvidia,default-tap = <0x5>; 932 nvidia,default-trim = <0xb>; 933 status = "disabled"; 934 }; 935 936 sdmmc4: mmc@3460000 { 937 compatible = "nvidia,tegra186-sdhci"; 938 reg = <0x0 0x03460000 0x0 0x10000>; 939 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 941 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 942 clock-names = "sdhci", "tmclk"; 943 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 944 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 945 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 946 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 947 reset-names = "sdhci"; 948 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 949 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 950 interconnect-names = "dma-mem", "write"; 951 iommus = <&smmu TEGRA186_SID_SDMMC4>; 952 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 953 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 954 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 955 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 956 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 957 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 958 nvidia,default-tap = <0x9>; 959 nvidia,default-trim = <0x5>; 960 nvidia,dqs-trim = <63>; 961 mmc-hs400-1_8v; 962 supports-cqe; 963 status = "disabled"; 964 }; 965 966 sata@3507000 { 967 compatible = "nvidia,tegra186-ahci"; 968 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 969 <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 970 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 971 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 972 973 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 974 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 975 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 976 interconnect-names = "dma-mem", "write"; 977 iommus = <&smmu TEGRA186_SID_SATA>; 978 979 clocks = <&bpmp TEGRA186_CLK_SATA>, 980 <&bpmp TEGRA186_CLK_SATA_OOB>; 981 clock-names = "sata", "sata-oob"; 982 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 983 <&bpmp TEGRA186_CLK_SATA_OOB>; 984 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 985 <&bpmp TEGRA186_CLK_PLLP>; 986 assigned-clock-rates = <102000000>, 987 <204000000>; 988 resets = <&bpmp TEGRA186_RESET_SATA>, 989 <&bpmp TEGRA186_RESET_SATACOLD>; 990 reset-names = "sata", "sata-cold"; 991 status = "disabled"; 992 }; 993 994 hda@3510000 { 995 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 996 reg = <0x0 0x03510000 0x0 0x10000>; 997 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&bpmp TEGRA186_CLK_HDA>, 999 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 1000 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 1001 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1002 resets = <&bpmp TEGRA186_RESET_HDA>, 1003 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 1004 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 1005 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1006 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1007 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 1008 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 1009 interconnect-names = "dma-mem", "write"; 1010 iommus = <&smmu TEGRA186_SID_HDA>; 1011 status = "disabled"; 1012 }; 1013 1014 padctl: padctl@3520000 { 1015 compatible = "nvidia,tegra186-xusb-padctl"; 1016 reg = <0x0 0x03520000 0x0 0x1000>, 1017 <0x0 0x03540000 0x0 0x1000>; 1018 reg-names = "padctl", "ao"; 1019 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1020 1021 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 1022 reset-names = "padctl"; 1023 1024 status = "disabled"; 1025 1026 pads { 1027 usb2 { 1028 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 1029 clock-names = "trk"; 1030 status = "disabled"; 1031 1032 lanes { 1033 usb2-0 { 1034 status = "disabled"; 1035 #phy-cells = <0>; 1036 }; 1037 1038 usb2-1 { 1039 status = "disabled"; 1040 #phy-cells = <0>; 1041 }; 1042 1043 usb2-2 { 1044 status = "disabled"; 1045 #phy-cells = <0>; 1046 }; 1047 }; 1048 }; 1049 1050 hsic { 1051 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 1052 clock-names = "trk"; 1053 status = "disabled"; 1054 1055 lanes { 1056 hsic-0 { 1057 status = "disabled"; 1058 #phy-cells = <0>; 1059 }; 1060 }; 1061 }; 1062 1063 usb3 { 1064 status = "disabled"; 1065 1066 lanes { 1067 usb3-0 { 1068 status = "disabled"; 1069 #phy-cells = <0>; 1070 }; 1071 1072 usb3-1 { 1073 status = "disabled"; 1074 #phy-cells = <0>; 1075 }; 1076 1077 usb3-2 { 1078 status = "disabled"; 1079 #phy-cells = <0>; 1080 }; 1081 }; 1082 }; 1083 }; 1084 1085 ports { 1086 usb2-0 { 1087 status = "disabled"; 1088 }; 1089 1090 usb2-1 { 1091 status = "disabled"; 1092 }; 1093 1094 usb2-2 { 1095 status = "disabled"; 1096 }; 1097 1098 hsic-0 { 1099 status = "disabled"; 1100 }; 1101 1102 usb3-0 { 1103 status = "disabled"; 1104 }; 1105 1106 usb3-1 { 1107 status = "disabled"; 1108 }; 1109 1110 usb3-2 { 1111 status = "disabled"; 1112 }; 1113 }; 1114 }; 1115 1116 usb@3530000 { 1117 compatible = "nvidia,tegra186-xusb"; 1118 reg = <0x0 0x03530000 0x0 0x8000>, 1119 <0x0 0x03538000 0x0 0x1000>; 1120 reg-names = "hcd", "fpci"; 1121 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 1124 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 1125 <&bpmp TEGRA186_CLK_XUSB_SS>, 1126 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1127 <&bpmp TEGRA186_CLK_CLK_M>, 1128 <&bpmp TEGRA186_CLK_XUSB_FS>, 1129 <&bpmp TEGRA186_CLK_PLLU>, 1130 <&bpmp TEGRA186_CLK_CLK_M>, 1131 <&bpmp TEGRA186_CLK_PLLE>; 1132 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 1133 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 1134 "pll_u_480m", "clk_m", "pll_e"; 1135 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 1136 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1137 power-domain-names = "xusb_host", "xusb_ss"; 1138 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1139 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1140 interconnect-names = "dma-mem", "write"; 1141 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 status = "disabled"; 1145 1146 nvidia,xusb-padctl = <&padctl>; 1147 }; 1148 1149 usb@3550000 { 1150 compatible = "nvidia,tegra186-xudc"; 1151 reg = <0x0 0x03550000 0x0 0x8000>, 1152 <0x0 0x03558000 0x0 0x1000>; 1153 reg-names = "base", "fpci"; 1154 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1155 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1156 <&bpmp TEGRA186_CLK_XUSB_SS>, 1157 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1158 <&bpmp TEGRA186_CLK_XUSB_FS>; 1159 clock-names = "dev", "ss", "ss_src", "fs_src"; 1160 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1161 <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1162 interconnect-names = "dma-mem", "write"; 1163 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1164 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1165 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1166 power-domain-names = "dev", "ss"; 1167 nvidia,xusb-padctl = <&padctl>; 1168 status = "disabled"; 1169 }; 1170 1171 fuse@3820000 { 1172 compatible = "nvidia,tegra186-efuse"; 1173 reg = <0x0 0x03820000 0x0 0x10000>; 1174 clocks = <&bpmp TEGRA186_CLK_FUSE>; 1175 clock-names = "fuse"; 1176 }; 1177 1178 gic: interrupt-controller@3881000 { 1179 compatible = "arm,gic-400"; 1180 #address-cells = <0>; 1181 #interrupt-cells = <3>; 1182 interrupt-controller; 1183 reg = <0x0 0x03881000 0x0 0x1000>, 1184 <0x0 0x03882000 0x0 0x2000>, 1185 <0x0 0x03884000 0x0 0x2000>, 1186 <0x0 0x03886000 0x0 0x2000>; 1187 interrupts = <GIC_PPI 9 1188 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1189 interrupt-parent = <&gic>; 1190 }; 1191 1192 cec@3960000 { 1193 compatible = "nvidia,tegra186-cec", "nvidia,tegra210-cec"; 1194 reg = <0x0 0x03960000 0x0 0x10000>; 1195 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1196 clocks = <&bpmp TEGRA186_CLK_CEC>; 1197 clock-names = "cec"; 1198 status = "disabled"; 1199 }; 1200 1201 hsp_top0: hsp@3c00000 { 1202 compatible = "nvidia,tegra186-hsp"; 1203 reg = <0x0 0x03c00000 0x0 0xa0000>; 1204 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1205 interrupt-names = "doorbell"; 1206 #mbox-cells = <2>; 1207 status = "disabled"; 1208 }; 1209 1210 gen2_i2c: i2c@c240000 { 1211 compatible = "nvidia,tegra186-i2c"; 1212 reg = <0x0 0x0c240000 0x0 0x10000>; 1213 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 clocks = <&bpmp TEGRA186_CLK_I2C2>; 1217 clock-names = "div-clk"; 1218 resets = <&bpmp TEGRA186_RESET_I2C2>; 1219 reset-names = "i2c"; 1220 dmas = <&gpcdma 22>, <&gpcdma 22>; 1221 dma-names = "rx", "tx"; 1222 status = "disabled"; 1223 }; 1224 1225 gen8_i2c: i2c@c250000 { 1226 compatible = "nvidia,tegra186-i2c"; 1227 reg = <0x0 0x0c250000 0x0 0x10000>; 1228 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 clocks = <&bpmp TEGRA186_CLK_I2C8>; 1232 clock-names = "div-clk"; 1233 resets = <&bpmp TEGRA186_RESET_I2C8>; 1234 reset-names = "i2c"; 1235 dmas = <&gpcdma 0>, <&gpcdma 0>; 1236 dma-names = "rx", "tx"; 1237 status = "disabled"; 1238 }; 1239 1240 uartc: serial@c280000 { 1241 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1242 reg = <0x0 0x0c280000 0x0 0x40>; 1243 reg-shift = <2>; 1244 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1245 clocks = <&bpmp TEGRA186_CLK_UARTC>; 1246 resets = <&bpmp TEGRA186_RESET_UARTC>; 1247 dmas = <&gpcdma 3>, <&gpcdma 3>; 1248 dma-names = "rx", "tx"; 1249 status = "disabled"; 1250 }; 1251 1252 uartg: serial@c290000 { 1253 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1254 reg = <0x0 0x0c290000 0x0 0x40>; 1255 reg-shift = <2>; 1256 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&bpmp TEGRA186_CLK_UARTG>; 1258 resets = <&bpmp TEGRA186_RESET_UARTG>; 1259 dmas = <&gpcdma 2>, <&gpcdma 2>; 1260 dma-names = "rx", "tx"; 1261 status = "disabled"; 1262 }; 1263 1264 rtc: rtc@c2a0000 { 1265 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 1266 reg = <0 0x0c2a0000 0 0x10000>; 1267 interrupt-parent = <&pmc>; 1268 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1269 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 1270 clock-names = "rtc"; 1271 status = "disabled"; 1272 }; 1273 1274 gpio_aon: gpio@c2f0000 { 1275 compatible = "nvidia,tegra186-gpio-aon"; 1276 reg-names = "security", "gpio"; 1277 reg = <0x0 0xc2f0000 0x0 0x1000>, 1278 <0x0 0xc2f1000 0x0 0x1000>; 1279 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1280 gpio-controller; 1281 #gpio-cells = <2>; 1282 gpio-ranges = <&pinmux_aon 0 0 47>; 1283 interrupt-controller; 1284 #interrupt-cells = <2>; 1285 }; 1286 1287 pinmux_aon: pinmux@c300000 { 1288 compatible = "nvidia,tegra186-pinmux-aon"; 1289 reg = <0x0 0xc300000 0x0 0x4000>; 1290 }; 1291 1292 pwm4: pwm@c340000 { 1293 compatible = "nvidia,tegra186-pwm"; 1294 reg = <0x0 0xc340000 0x0 0x10000>; 1295 clocks = <&bpmp TEGRA186_CLK_PWM4>; 1296 resets = <&bpmp TEGRA186_RESET_PWM4>; 1297 reset-names = "pwm"; 1298 status = "disabled"; 1299 #pwm-cells = <2>; 1300 }; 1301 1302 pmc: pmc@c360000 { 1303 compatible = "nvidia,tegra186-pmc"; 1304 reg = <0 0x0c360000 0 0x10000>, 1305 <0 0x0c370000 0 0x10000>, 1306 <0 0x0c380000 0 0x10000>, 1307 <0 0x0c390000 0 0x10000>; 1308 reg-names = "pmc", "wake", "aotag", "scratch"; 1309 1310 #interrupt-cells = <2>; 1311 interrupt-controller; 1312 1313 sdmmc1_1v8: sdmmc1-1v8 { 1314 pins = "sdmmc1-hv"; 1315 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1316 }; 1317 1318 sdmmc1_3v3: sdmmc1-3v3 { 1319 pins = "sdmmc1-hv"; 1320 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1321 }; 1322 1323 sdmmc2_1v8: sdmmc2-1v8 { 1324 pins = "sdmmc2-hv"; 1325 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1326 }; 1327 1328 sdmmc2_3v3: sdmmc2-3v3 { 1329 pins = "sdmmc2-hv"; 1330 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1331 }; 1332 1333 sdmmc3_1v8: sdmmc3-1v8 { 1334 pins = "sdmmc3-hv"; 1335 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1336 }; 1337 1338 sdmmc3_3v3: sdmmc3-3v3 { 1339 pins = "sdmmc3-hv"; 1340 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1341 }; 1342 }; 1343 1344 ccplex@e000000 { 1345 compatible = "nvidia,tegra186-ccplex-cluster"; 1346 reg = <0x0 0x0e000000 0x0 0x400000>; 1347 1348 nvidia,bpmp = <&bpmp>; 1349 }; 1350 1351 pcie@10003000 { 1352 compatible = "nvidia,tegra186-pcie"; 1353 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1354 device_type = "pci"; 1355 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1356 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1357 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1358 reg-names = "pads", "afi", "cs"; 1359 1360 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1361 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1362 interrupt-names = "intr", "msi"; 1363 1364 #interrupt-cells = <1>; 1365 interrupt-map-mask = <0 0 0 0>; 1366 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1367 1368 bus-range = <0x00 0xff>; 1369 #address-cells = <3>; 1370 #size-cells = <2>; 1371 1372 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1373 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1374 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1375 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1376 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1377 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1378 1379 clocks = <&bpmp TEGRA186_CLK_PCIE>, 1380 <&bpmp TEGRA186_CLK_AFI>, 1381 <&bpmp TEGRA186_CLK_PLLE>; 1382 clock-names = "pex", "afi", "pll_e"; 1383 1384 resets = <&bpmp TEGRA186_RESET_PCIE>, 1385 <&bpmp TEGRA186_RESET_AFI>, 1386 <&bpmp TEGRA186_RESET_PCIEXCLK>; 1387 reset-names = "pex", "afi", "pcie_x"; 1388 1389 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1390 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1391 interconnect-names = "dma-mem", "write"; 1392 1393 iommus = <&smmu TEGRA186_SID_AFI>; 1394 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1395 iommu-map-mask = <0x0>; 1396 1397 status = "disabled"; 1398 1399 pci@1,0 { 1400 device_type = "pci"; 1401 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1402 reg = <0x000800 0 0 0 0>; 1403 status = "disabled"; 1404 1405 #address-cells = <3>; 1406 #size-cells = <2>; 1407 ranges; 1408 1409 nvidia,num-lanes = <2>; 1410 }; 1411 1412 pci@2,0 { 1413 device_type = "pci"; 1414 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1415 reg = <0x001000 0 0 0 0>; 1416 status = "disabled"; 1417 1418 #address-cells = <3>; 1419 #size-cells = <2>; 1420 ranges; 1421 1422 nvidia,num-lanes = <1>; 1423 }; 1424 1425 pci@3,0 { 1426 device_type = "pci"; 1427 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1428 reg = <0x001800 0 0 0 0>; 1429 status = "disabled"; 1430 1431 #address-cells = <3>; 1432 #size-cells = <2>; 1433 ranges; 1434 1435 nvidia,num-lanes = <1>; 1436 }; 1437 }; 1438 1439 smmu: iommu@12000000 { 1440 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1441 reg = <0 0x12000000 0 0x800000>; 1442 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1507 stream-match-mask = <0x7f80>; 1508 #global-interrupts = <1>; 1509 #iommu-cells = <1>; 1510 1511 nvidia,memory-controller = <&mc>; 1512 }; 1513 1514 host1x@13e00000 { 1515 compatible = "nvidia,tegra186-host1x"; 1516 reg = <0x0 0x13e00000 0x0 0x10000>, 1517 <0x0 0x13e10000 0x0 0x10000>; 1518 reg-names = "hypervisor", "vm"; 1519 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1521 interrupt-names = "syncpt", "host1x"; 1522 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 1523 clock-names = "host1x"; 1524 resets = <&bpmp TEGRA186_RESET_HOST1X>; 1525 reset-names = "host1x"; 1526 1527 #address-cells = <2>; 1528 #size-cells = <2>; 1529 1530 ranges = <0x0 0x15000000 0x0 0x15000000 0x0 0x01000000>; 1531 1532 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1533 interconnect-names = "dma-mem"; 1534 1535 iommus = <&smmu TEGRA186_SID_HOST1X>; 1536 1537 /* Context isolation domains */ 1538 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>, 1539 <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>, 1540 <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>, 1541 <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>, 1542 <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>, 1543 <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>, 1544 <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>, 1545 <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; 1546 1547 dpaux1: dpaux@15040000 { 1548 compatible = "nvidia,tegra186-dpaux"; 1549 reg = <0x0 0x15040000 0x0 0x10000>; 1550 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1551 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1552 <&bpmp TEGRA186_CLK_PLLDP>; 1553 clock-names = "dpaux", "parent"; 1554 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1555 reset-names = "dpaux"; 1556 status = "disabled"; 1557 1558 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1559 1560 state_dpaux1_aux: pinmux-aux { 1561 groups = "dpaux-io"; 1562 function = "aux"; 1563 }; 1564 1565 state_dpaux1_i2c: pinmux-i2c { 1566 groups = "dpaux-io"; 1567 function = "i2c"; 1568 }; 1569 1570 state_dpaux1_off: pinmux-off { 1571 groups = "dpaux-io"; 1572 function = "off"; 1573 }; 1574 1575 i2c-bus { 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 }; 1579 }; 1580 1581 display-hub@15200000 { 1582 compatible = "nvidia,tegra186-display"; 1583 reg = <0x0 0x15200000 0x0 0x00040000>; 1584 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1585 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1586 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1587 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1588 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1589 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1590 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1591 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1592 "wgrp3", "wgrp4", "wgrp5"; 1593 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1594 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1595 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1596 clock-names = "disp", "dsc", "hub"; 1597 status = "disabled"; 1598 1599 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1600 1601 #address-cells = <2>; 1602 #size-cells = <2>; 1603 1604 ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>; 1605 1606 display@15200000 { 1607 compatible = "nvidia,tegra186-dc"; 1608 reg = <0x0 0x15200000 0x0 0x10000>; 1609 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1610 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1611 clock-names = "dc"; 1612 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1613 reset-names = "dc"; 1614 1615 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1616 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1617 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1618 interconnect-names = "dma-mem", "read-1"; 1619 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1620 1621 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1622 nvidia,head = <0>; 1623 }; 1624 1625 display@15210000 { 1626 compatible = "nvidia,tegra186-dc"; 1627 reg = <0x0 0x15210000 0x0 0x10000>; 1628 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1629 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1630 clock-names = "dc"; 1631 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1632 reset-names = "dc"; 1633 1634 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1635 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1636 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1637 interconnect-names = "dma-mem", "read-1"; 1638 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1639 1640 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1641 nvidia,head = <1>; 1642 }; 1643 1644 display@15220000 { 1645 compatible = "nvidia,tegra186-dc"; 1646 reg = <0x0 0x15220000 0x0 0x10000>; 1647 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1648 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1649 clock-names = "dc"; 1650 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1651 reset-names = "dc"; 1652 1653 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1654 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1655 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1656 interconnect-names = "dma-mem", "read-1"; 1657 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1658 1659 nvidia,outputs = <&sor0 &sor1>; 1660 nvidia,head = <2>; 1661 }; 1662 }; 1663 1664 dsia: dsi@15300000 { 1665 compatible = "nvidia,tegra186-dsi"; 1666 reg = <0x0 0x15300000 0x0 0x10000>; 1667 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1668 clocks = <&bpmp TEGRA186_CLK_DSI>, 1669 <&bpmp TEGRA186_CLK_DSIA_LP>, 1670 <&bpmp TEGRA186_CLK_PLLD>; 1671 clock-names = "dsi", "lp", "parent"; 1672 resets = <&bpmp TEGRA186_RESET_DSI>; 1673 reset-names = "dsi"; 1674 status = "disabled"; 1675 1676 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1677 }; 1678 1679 vic@15340000 { 1680 compatible = "nvidia,tegra186-vic"; 1681 reg = <0x0 0x15340000 0x0 0x40000>; 1682 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1683 clocks = <&bpmp TEGRA186_CLK_VIC>; 1684 clock-names = "vic"; 1685 resets = <&bpmp TEGRA186_RESET_VIC>; 1686 reset-names = "vic"; 1687 1688 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1689 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1690 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1691 interconnect-names = "dma-mem", "write"; 1692 iommus = <&smmu TEGRA186_SID_VIC>; 1693 }; 1694 1695 nvjpg@15380000 { 1696 compatible = "nvidia,tegra186-nvjpg"; 1697 reg = <0x0 0x15380000 0x0 0x40000>; 1698 clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1699 clock-names = "nvjpg"; 1700 resets = <&bpmp TEGRA186_RESET_NVJPG>; 1701 reset-names = "nvjpg"; 1702 1703 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1704 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1705 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1706 interconnect-names = "dma-mem", "write"; 1707 iommus = <&smmu TEGRA186_SID_NVJPG>; 1708 }; 1709 1710 dsib: dsi@15400000 { 1711 compatible = "nvidia,tegra186-dsi"; 1712 reg = <0x0 0x15400000 0x0 0x10000>; 1713 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1714 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1715 <&bpmp TEGRA186_CLK_DSIB_LP>, 1716 <&bpmp TEGRA186_CLK_PLLD>; 1717 clock-names = "dsi", "lp", "parent"; 1718 resets = <&bpmp TEGRA186_RESET_DSIB>; 1719 reset-names = "dsi"; 1720 status = "disabled"; 1721 1722 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1723 }; 1724 1725 nvdec@15480000 { 1726 compatible = "nvidia,tegra186-nvdec"; 1727 reg = <0x0 0x15480000 0x0 0x40000>; 1728 clocks = <&bpmp TEGRA186_CLK_NVDEC>; 1729 clock-names = "nvdec"; 1730 resets = <&bpmp TEGRA186_RESET_NVDEC>; 1731 reset-names = "nvdec"; 1732 1733 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 1734 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 1735 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 1736 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 1737 interconnect-names = "dma-mem", "read-1", "write"; 1738 iommus = <&smmu TEGRA186_SID_NVDEC>; 1739 }; 1740 1741 nvenc@154c0000 { 1742 compatible = "nvidia,tegra186-nvenc"; 1743 reg = <0x0 0x154c0000 0x0 0x40000>; 1744 clocks = <&bpmp TEGRA186_CLK_NVENC>; 1745 clock-names = "nvenc"; 1746 resets = <&bpmp TEGRA186_RESET_NVENC>; 1747 reset-names = "nvenc"; 1748 1749 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1750 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1751 <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1752 interconnect-names = "dma-mem", "write"; 1753 iommus = <&smmu TEGRA186_SID_NVENC>; 1754 }; 1755 1756 sor0: sor@15540000 { 1757 compatible = "nvidia,tegra186-sor"; 1758 reg = <0x0 0x15540000 0x0 0x10000>; 1759 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1760 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1761 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1762 <&bpmp TEGRA186_CLK_PLLD2>, 1763 <&bpmp TEGRA186_CLK_PLLDP>, 1764 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1765 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1766 clock-names = "sor", "out", "parent", "dp", "safe", 1767 "pad"; 1768 resets = <&bpmp TEGRA186_RESET_SOR0>; 1769 reset-names = "sor"; 1770 pinctrl-0 = <&state_dpaux_aux>; 1771 pinctrl-1 = <&state_dpaux_i2c>; 1772 pinctrl-2 = <&state_dpaux_off>; 1773 pinctrl-names = "aux", "i2c", "off"; 1774 status = "disabled"; 1775 1776 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1777 nvidia,interface = <0>; 1778 }; 1779 1780 sor1: sor@15580000 { 1781 compatible = "nvidia,tegra186-sor"; 1782 reg = <0x0 0x15580000 0x0 0x10000>; 1783 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1784 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1785 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1786 <&bpmp TEGRA186_CLK_PLLD3>, 1787 <&bpmp TEGRA186_CLK_PLLDP>, 1788 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1789 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1790 clock-names = "sor", "out", "parent", "dp", "safe", 1791 "pad"; 1792 resets = <&bpmp TEGRA186_RESET_SOR1>; 1793 reset-names = "sor"; 1794 pinctrl-0 = <&state_dpaux1_aux>; 1795 pinctrl-1 = <&state_dpaux1_i2c>; 1796 pinctrl-2 = <&state_dpaux1_off>; 1797 pinctrl-names = "aux", "i2c", "off"; 1798 status = "disabled"; 1799 1800 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1801 nvidia,interface = <1>; 1802 }; 1803 1804 dpaux: dpaux@155c0000 { 1805 compatible = "nvidia,tegra186-dpaux"; 1806 reg = <0x0 0x155c0000 0x0 0x10000>; 1807 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1808 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1809 <&bpmp TEGRA186_CLK_PLLDP>; 1810 clock-names = "dpaux", "parent"; 1811 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1812 reset-names = "dpaux"; 1813 status = "disabled"; 1814 1815 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1816 1817 state_dpaux_aux: pinmux-aux { 1818 groups = "dpaux-io"; 1819 function = "aux"; 1820 }; 1821 1822 state_dpaux_i2c: pinmux-i2c { 1823 groups = "dpaux-io"; 1824 function = "i2c"; 1825 }; 1826 1827 state_dpaux_off: pinmux-off { 1828 groups = "dpaux-io"; 1829 function = "off"; 1830 }; 1831 1832 i2c-bus { 1833 #address-cells = <1>; 1834 #size-cells = <0>; 1835 }; 1836 }; 1837 1838 padctl@15880000 { 1839 compatible = "nvidia,tegra186-dsi-padctl"; 1840 reg = <0x0 0x15880000 0x0 0x10000>; 1841 resets = <&bpmp TEGRA186_RESET_DSI>; 1842 reset-names = "dsi"; 1843 status = "disabled"; 1844 }; 1845 1846 dsic: dsi@15900000 { 1847 compatible = "nvidia,tegra186-dsi"; 1848 reg = <0x0 0x15900000 0x0 0x10000>; 1849 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1850 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1851 <&bpmp TEGRA186_CLK_DSIC_LP>, 1852 <&bpmp TEGRA186_CLK_PLLD>; 1853 clock-names = "dsi", "lp", "parent"; 1854 resets = <&bpmp TEGRA186_RESET_DSIC>; 1855 reset-names = "dsi"; 1856 status = "disabled"; 1857 1858 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1859 }; 1860 1861 dsid: dsi@15940000 { 1862 compatible = "nvidia,tegra186-dsi"; 1863 reg = <0x0 0x15940000 0x0 0x10000>; 1864 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1865 clocks = <&bpmp TEGRA186_CLK_DSID>, 1866 <&bpmp TEGRA186_CLK_DSID_LP>, 1867 <&bpmp TEGRA186_CLK_PLLD>; 1868 clock-names = "dsi", "lp", "parent"; 1869 resets = <&bpmp TEGRA186_RESET_DSID>; 1870 reset-names = "dsi"; 1871 status = "disabled"; 1872 1873 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1874 }; 1875 }; 1876 1877 gpu@17000000 { 1878 compatible = "nvidia,gp10b"; 1879 reg = <0x0 0x17000000 0x0 0x1000000>, 1880 <0x0 0x18000000 0x0 0x1000000>; 1881 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1883 interrupt-names = "stall", "nonstall"; 1884 1885 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1886 <&bpmp TEGRA186_CLK_GPU>; 1887 clock-names = "gpu", "pwr"; 1888 resets = <&bpmp TEGRA186_RESET_GPU>; 1889 reset-names = "gpu"; 1890 status = "disabled"; 1891 1892 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1893 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1894 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1895 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1896 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1897 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1898 }; 1899 1900 sram@30000000 { 1901 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1902 reg = <0x0 0x30000000 0x0 0x50000>; 1903 #address-cells = <1>; 1904 #size-cells = <1>; 1905 ranges = <0x0 0x0 0x30000000 0x50000>; 1906 no-memory-wc; 1907 1908 cpu_bpmp_tx: sram@4e000 { 1909 reg = <0x4e000 0x1000>; 1910 label = "cpu-bpmp-tx"; 1911 pool; 1912 }; 1913 1914 cpu_bpmp_rx: sram@4f000 { 1915 reg = <0x4f000 0x1000>; 1916 label = "cpu-bpmp-rx"; 1917 pool; 1918 }; 1919 }; 1920 1921 bpmp: bpmp { 1922 compatible = "nvidia,tegra186-bpmp"; 1923 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1924 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1925 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1926 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1927 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1928 iommus = <&smmu TEGRA186_SID_BPMP>; 1929 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1930 TEGRA_HSP_DB_MASTER_BPMP>; 1931 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1932 #clock-cells = <1>; 1933 #reset-cells = <1>; 1934 #power-domain-cells = <1>; 1935 1936 bpmp_i2c: i2c { 1937 compatible = "nvidia,tegra186-bpmp-i2c"; 1938 nvidia,bpmp-bus-id = <5>; 1939 #address-cells = <1>; 1940 #size-cells = <0>; 1941 status = "disabled"; 1942 }; 1943 1944 bpmp_thermal: thermal { 1945 compatible = "nvidia,tegra186-bpmp-thermal"; 1946 #thermal-sensor-cells = <1>; 1947 }; 1948 }; 1949 1950 cpus { 1951 #address-cells = <1>; 1952 #size-cells = <0>; 1953 1954 denver_0: cpu@0 { 1955 compatible = "nvidia,tegra186-denver"; 1956 device_type = "cpu"; 1957 i-cache-size = <0x20000>; 1958 i-cache-line-size = <64>; 1959 i-cache-sets = <512>; 1960 d-cache-size = <0x10000>; 1961 d-cache-line-size = <64>; 1962 d-cache-sets = <256>; 1963 next-level-cache = <&L2_DENVER>; 1964 reg = <0x000>; 1965 }; 1966 1967 denver_1: cpu@1 { 1968 compatible = "nvidia,tegra186-denver"; 1969 device_type = "cpu"; 1970 i-cache-size = <0x20000>; 1971 i-cache-line-size = <64>; 1972 i-cache-sets = <512>; 1973 d-cache-size = <0x10000>; 1974 d-cache-line-size = <64>; 1975 d-cache-sets = <256>; 1976 next-level-cache = <&L2_DENVER>; 1977 reg = <0x001>; 1978 }; 1979 1980 ca57_0: cpu@2 { 1981 compatible = "arm,cortex-a57"; 1982 device_type = "cpu"; 1983 i-cache-size = <0xC000>; 1984 i-cache-line-size = <64>; 1985 i-cache-sets = <256>; 1986 d-cache-size = <0x8000>; 1987 d-cache-line-size = <64>; 1988 d-cache-sets = <256>; 1989 next-level-cache = <&L2_A57>; 1990 reg = <0x100>; 1991 }; 1992 1993 ca57_1: cpu@3 { 1994 compatible = "arm,cortex-a57"; 1995 device_type = "cpu"; 1996 i-cache-size = <0xC000>; 1997 i-cache-line-size = <64>; 1998 i-cache-sets = <256>; 1999 d-cache-size = <0x8000>; 2000 d-cache-line-size = <64>; 2001 d-cache-sets = <256>; 2002 next-level-cache = <&L2_A57>; 2003 reg = <0x101>; 2004 }; 2005 2006 ca57_2: cpu@4 { 2007 compatible = "arm,cortex-a57"; 2008 device_type = "cpu"; 2009 i-cache-size = <0xC000>; 2010 i-cache-line-size = <64>; 2011 i-cache-sets = <256>; 2012 d-cache-size = <0x8000>; 2013 d-cache-line-size = <64>; 2014 d-cache-sets = <256>; 2015 next-level-cache = <&L2_A57>; 2016 reg = <0x102>; 2017 }; 2018 2019 ca57_3: cpu@5 { 2020 compatible = "arm,cortex-a57"; 2021 device_type = "cpu"; 2022 i-cache-size = <0xC000>; 2023 i-cache-line-size = <64>; 2024 i-cache-sets = <256>; 2025 d-cache-size = <0x8000>; 2026 d-cache-line-size = <64>; 2027 d-cache-sets = <256>; 2028 next-level-cache = <&L2_A57>; 2029 reg = <0x103>; 2030 }; 2031 2032 L2_DENVER: l2-cache0 { 2033 compatible = "cache"; 2034 cache-unified; 2035 cache-level = <2>; 2036 cache-size = <0x200000>; 2037 cache-line-size = <64>; 2038 cache-sets = <2048>; 2039 }; 2040 2041 L2_A57: l2-cache1 { 2042 compatible = "cache"; 2043 cache-unified; 2044 cache-level = <2>; 2045 cache-size = <0x200000>; 2046 cache-line-size = <64>; 2047 cache-sets = <2048>; 2048 }; 2049 }; 2050 2051 pmu-a57 { 2052 compatible = "arm,cortex-a57-pmu"; 2053 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 2057 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 2058 }; 2059 2060 pmu-denver { 2061 compatible = "nvidia,denver-pmu"; 2062 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2064 interrupt-affinity = <&denver_0 &denver_1>; 2065 }; 2066 2067 sound { 2068 status = "disabled"; 2069 2070 clocks = <&bpmp TEGRA186_CLK_PLLA>, 2071 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2072 clock-names = "pll_a", "plla_out0"; 2073 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2074 <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2075 <&bpmp TEGRA186_CLK_AUD_MCLK>; 2076 assigned-clock-parents = <0>, 2077 <&bpmp TEGRA186_CLK_PLLA>, 2078 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2079 /* 2080 * PLLA supports dynamic ramp. Below initial rate is chosen 2081 * for this to work and oscillate between base rates required 2082 * for 8x and 11.025x sample rate streams. 2083 */ 2084 assigned-clock-rates = <258000000>; 2085 2086 iommus = <&smmu TEGRA186_SID_APE>; 2087 }; 2088 2089 thermal-zones { 2090 /* Cortex-A57 cluster */ 2091 cpu-thermal { 2092 polling-delay = <0>; 2093 polling-delay-passive = <1000>; 2094 2095 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 2096 2097 trips { 2098 critical { 2099 temperature = <101000>; 2100 hysteresis = <0>; 2101 type = "critical"; 2102 }; 2103 }; 2104 2105 cooling-maps { 2106 }; 2107 }; 2108 2109 /* Denver cluster */ 2110 aux-thermal { 2111 polling-delay = <0>; 2112 polling-delay-passive = <1000>; 2113 2114 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 2115 2116 trips { 2117 critical { 2118 temperature = <101000>; 2119 hysteresis = <0>; 2120 type = "critical"; 2121 }; 2122 }; 2123 2124 cooling-maps { 2125 }; 2126 }; 2127 2128 gpu-thermal { 2129 polling-delay = <0>; 2130 polling-delay-passive = <1000>; 2131 2132 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 2133 2134 trips { 2135 critical { 2136 temperature = <101000>; 2137 hysteresis = <0>; 2138 type = "critical"; 2139 }; 2140 }; 2141 2142 cooling-maps { 2143 }; 2144 }; 2145 2146 pll-thermal { 2147 polling-delay = <0>; 2148 polling-delay-passive = <1000>; 2149 2150 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 2151 2152 trips { 2153 critical { 2154 temperature = <101000>; 2155 hysteresis = <0>; 2156 type = "critical"; 2157 }; 2158 }; 2159 2160 cooling-maps { 2161 }; 2162 }; 2163 2164 ao-thermal { 2165 polling-delay = <0>; 2166 polling-delay-passive = <1000>; 2167 2168 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 2169 2170 trips { 2171 critical { 2172 temperature = <101000>; 2173 hysteresis = <0>; 2174 type = "critical"; 2175 }; 2176 }; 2177 2178 cooling-maps { 2179 }; 2180 }; 2181 }; 2182 2183 timer { 2184 compatible = "arm,armv8-timer"; 2185 interrupts = <GIC_PPI 13 2186 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2187 <GIC_PPI 14 2188 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2189 <GIC_PPI 11 2190 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2191 <GIC_PPI 10 2192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2193 interrupt-parent = <&gic>; 2194 always-on; 2195 }; 2196}; 2197