1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 status = "disabled"; 64 65 snps,write-requests = <1>; 66 snps,read-requests = <3>; 67 snps,burst-map = <0x7>; 68 snps,txpbl = <32>; 69 snps,rxpbl = <8>; 70 }; 71 72 memory-controller@2c00000 { 73 compatible = "nvidia,tegra186-mc"; 74 reg = <0x0 0x02c00000 0x0 0xb0000>; 75 status = "disabled"; 76 }; 77 78 uarta: serial@3100000 { 79 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 80 reg = <0x0 0x03100000 0x0 0x40>; 81 reg-shift = <2>; 82 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 83 clocks = <&bpmp TEGRA186_CLK_UARTA>; 84 clock-names = "serial"; 85 resets = <&bpmp TEGRA186_RESET_UARTA>; 86 reset-names = "serial"; 87 status = "disabled"; 88 }; 89 90 uartb: serial@3110000 { 91 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 92 reg = <0x0 0x03110000 0x0 0x40>; 93 reg-shift = <2>; 94 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&bpmp TEGRA186_CLK_UARTB>; 96 clock-names = "serial"; 97 resets = <&bpmp TEGRA186_RESET_UARTB>; 98 reset-names = "serial"; 99 status = "disabled"; 100 }; 101 102 uartd: serial@3130000 { 103 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 104 reg = <0x0 0x03130000 0x0 0x40>; 105 reg-shift = <2>; 106 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&bpmp TEGRA186_CLK_UARTD>; 108 clock-names = "serial"; 109 resets = <&bpmp TEGRA186_RESET_UARTD>; 110 reset-names = "serial"; 111 status = "disabled"; 112 }; 113 114 uarte: serial@3140000 { 115 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 116 reg = <0x0 0x03140000 0x0 0x40>; 117 reg-shift = <2>; 118 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&bpmp TEGRA186_CLK_UARTE>; 120 clock-names = "serial"; 121 resets = <&bpmp TEGRA186_RESET_UARTE>; 122 reset-names = "serial"; 123 status = "disabled"; 124 }; 125 126 uartf: serial@3150000 { 127 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 128 reg = <0x0 0x03150000 0x0 0x40>; 129 reg-shift = <2>; 130 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&bpmp TEGRA186_CLK_UARTF>; 132 clock-names = "serial"; 133 resets = <&bpmp TEGRA186_RESET_UARTF>; 134 reset-names = "serial"; 135 status = "disabled"; 136 }; 137 138 gen1_i2c: i2c@3160000 { 139 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 140 reg = <0x0 0x03160000 0x0 0x10000>; 141 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 clocks = <&bpmp TEGRA186_CLK_I2C1>; 145 clock-names = "div-clk"; 146 resets = <&bpmp TEGRA186_RESET_I2C1>; 147 reset-names = "i2c"; 148 status = "disabled"; 149 }; 150 151 cam_i2c: i2c@3180000 { 152 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 153 reg = <0x0 0x03180000 0x0 0x10000>; 154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 clocks = <&bpmp TEGRA186_CLK_I2C3>; 158 clock-names = "div-clk"; 159 resets = <&bpmp TEGRA186_RESET_I2C3>; 160 reset-names = "i2c"; 161 status = "disabled"; 162 }; 163 164 /* shares pads with dpaux1 */ 165 dp_aux_ch1_i2c: i2c@3190000 { 166 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 167 reg = <0x0 0x03190000 0x0 0x10000>; 168 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 clocks = <&bpmp TEGRA186_CLK_I2C4>; 172 clock-names = "div-clk"; 173 resets = <&bpmp TEGRA186_RESET_I2C4>; 174 reset-names = "i2c"; 175 status = "disabled"; 176 }; 177 178 /* controlled by BPMP, should not be enabled */ 179 pwr_i2c: i2c@31a0000 { 180 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 181 reg = <0x0 0x031a0000 0x0 0x10000>; 182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 clocks = <&bpmp TEGRA186_CLK_I2C5>; 186 clock-names = "div-clk"; 187 resets = <&bpmp TEGRA186_RESET_I2C5>; 188 reset-names = "i2c"; 189 status = "disabled"; 190 }; 191 192 /* shares pads with dpaux0 */ 193 dp_aux_ch0_i2c: i2c@31b0000 { 194 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 195 reg = <0x0 0x031b0000 0x0 0x10000>; 196 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clocks = <&bpmp TEGRA186_CLK_I2C6>; 200 clock-names = "div-clk"; 201 resets = <&bpmp TEGRA186_RESET_I2C6>; 202 reset-names = "i2c"; 203 status = "disabled"; 204 }; 205 206 gen7_i2c: i2c@31c0000 { 207 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 208 reg = <0x0 0x031c0000 0x0 0x10000>; 209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 clocks = <&bpmp TEGRA186_CLK_I2C7>; 213 clock-names = "div-clk"; 214 resets = <&bpmp TEGRA186_RESET_I2C7>; 215 reset-names = "i2c"; 216 status = "disabled"; 217 }; 218 219 gen9_i2c: i2c@31e0000 { 220 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 221 reg = <0x0 0x031e0000 0x0 0x10000>; 222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 clocks = <&bpmp TEGRA186_CLK_I2C9>; 226 clock-names = "div-clk"; 227 resets = <&bpmp TEGRA186_RESET_I2C9>; 228 reset-names = "i2c"; 229 status = "disabled"; 230 }; 231 232 sdmmc1: sdhci@3400000 { 233 compatible = "nvidia,tegra186-sdhci"; 234 reg = <0x0 0x03400000 0x0 0x10000>; 235 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 237 clock-names = "sdhci"; 238 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 239 reset-names = "sdhci"; 240 iommus = <&smmu TEGRA186_SID_SDMMC1>; 241 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 242 pinctrl-0 = <&sdmmc1_3v3>; 243 pinctrl-1 = <&sdmmc1_1v8>; 244 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 245 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 246 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 247 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 248 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 249 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 250 nvidia,default-tap = <0x5>; 251 nvidia,default-trim = <0xb>; 252 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 253 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 254 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 255 status = "disabled"; 256 }; 257 258 sdmmc2: sdhci@3420000 { 259 compatible = "nvidia,tegra186-sdhci"; 260 reg = <0x0 0x03420000 0x0 0x10000>; 261 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 263 clock-names = "sdhci"; 264 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 265 reset-names = "sdhci"; 266 iommus = <&smmu TEGRA186_SID_SDMMC2>; 267 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 268 pinctrl-0 = <&sdmmc2_3v3>; 269 pinctrl-1 = <&sdmmc2_1v8>; 270 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 271 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 272 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 273 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 274 nvidia,default-tap = <0x5>; 275 nvidia,default-trim = <0xb>; 276 status = "disabled"; 277 }; 278 279 sdmmc3: sdhci@3440000 { 280 compatible = "nvidia,tegra186-sdhci"; 281 reg = <0x0 0x03440000 0x0 0x10000>; 282 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 284 clock-names = "sdhci"; 285 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 286 reset-names = "sdhci"; 287 iommus = <&smmu TEGRA186_SID_SDMMC3>; 288 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 289 pinctrl-0 = <&sdmmc3_3v3>; 290 pinctrl-1 = <&sdmmc3_1v8>; 291 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 292 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 293 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 294 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 295 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 296 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 297 nvidia,default-tap = <0x5>; 298 nvidia,default-trim = <0xb>; 299 status = "disabled"; 300 }; 301 302 sdmmc4: sdhci@3460000 { 303 compatible = "nvidia,tegra186-sdhci"; 304 reg = <0x0 0x03460000 0x0 0x10000>; 305 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 307 clock-names = "sdhci"; 308 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 309 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 310 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 311 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 312 reset-names = "sdhci"; 313 iommus = <&smmu TEGRA186_SID_SDMMC4>; 314 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 315 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 316 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 317 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 318 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 319 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 320 nvidia,default-tap = <0x5>; 321 nvidia,default-trim = <0x9>; 322 nvidia,dqs-trim = <63>; 323 mmc-hs400-1_8v; 324 supports-cqe; 325 status = "disabled"; 326 }; 327 328 hda@3510000 { 329 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 330 reg = <0x0 0x03510000 0x0 0x10000>; 331 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&bpmp TEGRA186_CLK_HDA>, 333 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 334 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 335 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 336 resets = <&bpmp TEGRA186_RESET_HDA>, 337 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 338 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 339 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 340 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 341 status = "disabled"; 342 }; 343 344 fuse@3820000 { 345 compatible = "nvidia,tegra186-efuse"; 346 reg = <0x0 0x03820000 0x0 0x10000>; 347 clocks = <&bpmp TEGRA186_CLK_FUSE>; 348 clock-names = "fuse"; 349 }; 350 351 gic: interrupt-controller@3881000 { 352 compatible = "arm,gic-400"; 353 #interrupt-cells = <3>; 354 interrupt-controller; 355 reg = <0x0 0x03881000 0x0 0x1000>, 356 <0x0 0x03882000 0x0 0x2000>; 357 interrupts = <GIC_PPI 9 358 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 359 interrupt-parent = <&gic>; 360 }; 361 362 cec@3960000 { 363 compatible = "nvidia,tegra186-cec"; 364 reg = <0x0 0x03960000 0x0 0x10000>; 365 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&bpmp TEGRA186_CLK_CEC>; 367 clock-names = "cec"; 368 status = "disabled"; 369 }; 370 371 hsp_top0: hsp@3c00000 { 372 compatible = "nvidia,tegra186-hsp"; 373 reg = <0x0 0x03c00000 0x0 0xa0000>; 374 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 375 interrupt-names = "doorbell"; 376 #mbox-cells = <2>; 377 status = "disabled"; 378 }; 379 380 gen2_i2c: i2c@c240000 { 381 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 382 reg = <0x0 0x0c240000 0x0 0x10000>; 383 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 clocks = <&bpmp TEGRA186_CLK_I2C2>; 387 clock-names = "div-clk"; 388 resets = <&bpmp TEGRA186_RESET_I2C2>; 389 reset-names = "i2c"; 390 status = "disabled"; 391 }; 392 393 gen8_i2c: i2c@c250000 { 394 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 395 reg = <0x0 0x0c250000 0x0 0x10000>; 396 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 clocks = <&bpmp TEGRA186_CLK_I2C8>; 400 clock-names = "div-clk"; 401 resets = <&bpmp TEGRA186_RESET_I2C8>; 402 reset-names = "i2c"; 403 status = "disabled"; 404 }; 405 406 uartc: serial@c280000 { 407 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 408 reg = <0x0 0x0c280000 0x0 0x40>; 409 reg-shift = <2>; 410 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&bpmp TEGRA186_CLK_UARTC>; 412 clock-names = "serial"; 413 resets = <&bpmp TEGRA186_RESET_UARTC>; 414 reset-names = "serial"; 415 status = "disabled"; 416 }; 417 418 uartg: serial@c290000 { 419 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 420 reg = <0x0 0x0c290000 0x0 0x40>; 421 reg-shift = <2>; 422 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&bpmp TEGRA186_CLK_UARTG>; 424 clock-names = "serial"; 425 resets = <&bpmp TEGRA186_RESET_UARTG>; 426 reset-names = "serial"; 427 status = "disabled"; 428 }; 429 430 rtc: rtc@c2a0000 { 431 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 432 reg = <0 0x0c2a0000 0 0x10000>; 433 interrupt-parent = <&pmc>; 434 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 436 clock-names = "rtc"; 437 status = "disabled"; 438 }; 439 440 gpio_aon: gpio@c2f0000 { 441 compatible = "nvidia,tegra186-gpio-aon"; 442 reg-names = "security", "gpio"; 443 reg = <0x0 0xc2f0000 0x0 0x1000>, 444 <0x0 0xc2f1000 0x0 0x1000>; 445 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 446 gpio-controller; 447 #gpio-cells = <2>; 448 interrupt-controller; 449 #interrupt-cells = <2>; 450 }; 451 452 pmc: pmc@c360000 { 453 compatible = "nvidia,tegra186-pmc"; 454 reg = <0 0x0c360000 0 0x10000>, 455 <0 0x0c370000 0 0x10000>, 456 <0 0x0c380000 0 0x10000>, 457 <0 0x0c390000 0 0x10000>; 458 reg-names = "pmc", "wake", "aotag", "scratch"; 459 460 #interrupt-cells = <2>; 461 interrupt-controller; 462 463 sdmmc1_3v3: sdmmc1-3v3 { 464 pins = "sdmmc1-hv"; 465 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 466 }; 467 468 sdmmc1_1v8: sdmmc1-1v8 { 469 pins = "sdmmc1-hv"; 470 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 471 }; 472 473 sdmmc2_3v3: sdmmc2-3v3 { 474 pins = "sdmmc2-hv"; 475 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 476 }; 477 478 sdmmc2_1v8: sdmmc2-1v8 { 479 pins = "sdmmc2-hv"; 480 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 481 }; 482 483 sdmmc3_3v3: sdmmc3-3v3 { 484 pins = "sdmmc3-hv"; 485 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 486 }; 487 488 sdmmc3_1v8: sdmmc3-1v8 { 489 pins = "sdmmc3-hv"; 490 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 491 }; 492 }; 493 494 ccplex@e000000 { 495 compatible = "nvidia,tegra186-ccplex-cluster"; 496 reg = <0x0 0x0e000000 0x0 0x3fffff>; 497 498 nvidia,bpmp = <&bpmp>; 499 }; 500 501 pcie@10003000 { 502 compatible = "nvidia,tegra186-pcie"; 503 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 504 device_type = "pci"; 505 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 506 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 507 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 508 reg-names = "pads", "afi", "cs"; 509 510 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 511 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 512 interrupt-names = "intr", "msi"; 513 514 #interrupt-cells = <1>; 515 interrupt-map-mask = <0 0 0 0>; 516 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 517 518 bus-range = <0x00 0xff>; 519 #address-cells = <3>; 520 #size-cells = <2>; 521 522 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 523 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 524 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 525 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 526 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 527 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 528 529 clocks = <&bpmp TEGRA186_CLK_AFI>, 530 <&bpmp TEGRA186_CLK_PCIE>, 531 <&bpmp TEGRA186_CLK_PLLE>; 532 clock-names = "afi", "pex", "pll_e"; 533 534 resets = <&bpmp TEGRA186_RESET_AFI>, 535 <&bpmp TEGRA186_RESET_PCIE>, 536 <&bpmp TEGRA186_RESET_PCIEXCLK>; 537 reset-names = "afi", "pex", "pcie_x"; 538 539 status = "disabled"; 540 541 pci@1,0 { 542 device_type = "pci"; 543 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 544 reg = <0x000800 0 0 0 0>; 545 status = "disabled"; 546 547 #address-cells = <3>; 548 #size-cells = <2>; 549 ranges; 550 551 nvidia,num-lanes = <2>; 552 }; 553 554 pci@2,0 { 555 device_type = "pci"; 556 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 557 reg = <0x001000 0 0 0 0>; 558 status = "disabled"; 559 560 #address-cells = <3>; 561 #size-cells = <2>; 562 ranges; 563 564 nvidia,num-lanes = <1>; 565 }; 566 567 pci@3,0 { 568 device_type = "pci"; 569 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 570 reg = <0x001800 0 0 0 0>; 571 status = "disabled"; 572 573 #address-cells = <3>; 574 #size-cells = <2>; 575 ranges; 576 577 nvidia,num-lanes = <1>; 578 }; 579 }; 580 581 smmu: iommu@12000000 { 582 compatible = "arm,mmu-500"; 583 reg = <0 0x12000000 0 0x800000>; 584 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 649 stream-match-mask = <0x7f80>; 650 #global-interrupts = <1>; 651 #iommu-cells = <1>; 652 }; 653 654 host1x@13e00000 { 655 compatible = "nvidia,tegra186-host1x", "simple-bus"; 656 reg = <0x0 0x13e00000 0x0 0x10000>, 657 <0x0 0x13e10000 0x0 0x10000>; 658 reg-names = "hypervisor", "vm"; 659 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 662 clock-names = "host1x"; 663 resets = <&bpmp TEGRA186_RESET_HOST1X>; 664 reset-names = "host1x"; 665 666 #address-cells = <1>; 667 #size-cells = <1>; 668 669 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 670 iommus = <&smmu TEGRA186_SID_HOST1X>; 671 672 dpaux1: dpaux@15040000 { 673 compatible = "nvidia,tegra186-dpaux"; 674 reg = <0x15040000 0x10000>; 675 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 677 <&bpmp TEGRA186_CLK_PLLDP>; 678 clock-names = "dpaux", "parent"; 679 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 680 reset-names = "dpaux"; 681 status = "disabled"; 682 683 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 684 685 state_dpaux1_aux: pinmux-aux { 686 groups = "dpaux-io"; 687 function = "aux"; 688 }; 689 690 state_dpaux1_i2c: pinmux-i2c { 691 groups = "dpaux-io"; 692 function = "i2c"; 693 }; 694 695 state_dpaux1_off: pinmux-off { 696 groups = "dpaux-io"; 697 function = "off"; 698 }; 699 700 i2c-bus { 701 #address-cells = <1>; 702 #size-cells = <0>; 703 }; 704 }; 705 706 display-hub@15200000 { 707 compatible = "nvidia,tegra186-display", "simple-bus"; 708 reg = <0x15200000 0x00040000>; 709 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 710 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 711 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 712 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 713 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 714 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 715 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 716 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 717 "wgrp3", "wgrp4", "wgrp5"; 718 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 719 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 720 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 721 clock-names = "disp", "dsc", "hub"; 722 status = "disabled"; 723 724 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 725 726 #address-cells = <1>; 727 #size-cells = <1>; 728 729 ranges = <0x15200000 0x15200000 0x40000>; 730 731 display@15200000 { 732 compatible = "nvidia,tegra186-dc"; 733 reg = <0x15200000 0x10000>; 734 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 736 clock-names = "dc"; 737 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 738 reset-names = "dc"; 739 740 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 741 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 742 743 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 744 nvidia,head = <0>; 745 }; 746 747 display@15210000 { 748 compatible = "nvidia,tegra186-dc"; 749 reg = <0x15210000 0x10000>; 750 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 752 clock-names = "dc"; 753 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 754 reset-names = "dc"; 755 756 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 757 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 758 759 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 760 nvidia,head = <1>; 761 }; 762 763 display@15220000 { 764 compatible = "nvidia,tegra186-dc"; 765 reg = <0x15220000 0x10000>; 766 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 768 clock-names = "dc"; 769 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 770 reset-names = "dc"; 771 772 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 773 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 774 775 nvidia,outputs = <&sor0 &sor1>; 776 nvidia,head = <2>; 777 }; 778 }; 779 780 dsia: dsi@15300000 { 781 compatible = "nvidia,tegra186-dsi"; 782 reg = <0x15300000 0x10000>; 783 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 784 clocks = <&bpmp TEGRA186_CLK_DSI>, 785 <&bpmp TEGRA186_CLK_DSIA_LP>, 786 <&bpmp TEGRA186_CLK_PLLD>; 787 clock-names = "dsi", "lp", "parent"; 788 resets = <&bpmp TEGRA186_RESET_DSI>; 789 reset-names = "dsi"; 790 status = "disabled"; 791 792 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 793 }; 794 795 vic@15340000 { 796 compatible = "nvidia,tegra186-vic"; 797 reg = <0x15340000 0x40000>; 798 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 799 clocks = <&bpmp TEGRA186_CLK_VIC>; 800 clock-names = "vic"; 801 resets = <&bpmp TEGRA186_RESET_VIC>; 802 reset-names = "vic"; 803 804 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 805 }; 806 807 dsib: dsi@15400000 { 808 compatible = "nvidia,tegra186-dsi"; 809 reg = <0x15400000 0x10000>; 810 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&bpmp TEGRA186_CLK_DSIB>, 812 <&bpmp TEGRA186_CLK_DSIB_LP>, 813 <&bpmp TEGRA186_CLK_PLLD>; 814 clock-names = "dsi", "lp", "parent"; 815 resets = <&bpmp TEGRA186_RESET_DSIB>; 816 reset-names = "dsi"; 817 status = "disabled"; 818 819 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 820 }; 821 822 sor0: sor@15540000 { 823 compatible = "nvidia,tegra186-sor"; 824 reg = <0x15540000 0x10000>; 825 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&bpmp TEGRA186_CLK_SOR0>, 827 <&bpmp TEGRA186_CLK_SOR0_OUT>, 828 <&bpmp TEGRA186_CLK_PLLD2>, 829 <&bpmp TEGRA186_CLK_PLLDP>, 830 <&bpmp TEGRA186_CLK_SOR_SAFE>, 831 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 832 clock-names = "sor", "out", "parent", "dp", "safe", 833 "pad"; 834 resets = <&bpmp TEGRA186_RESET_SOR0>; 835 reset-names = "sor"; 836 pinctrl-0 = <&state_dpaux_aux>; 837 pinctrl-1 = <&state_dpaux_i2c>; 838 pinctrl-2 = <&state_dpaux_off>; 839 pinctrl-names = "aux", "i2c", "off"; 840 status = "disabled"; 841 842 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 843 nvidia,interface = <0>; 844 }; 845 846 sor1: sor@15580000 { 847 compatible = "nvidia,tegra186-sor1"; 848 reg = <0x15580000 0x10000>; 849 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&bpmp TEGRA186_CLK_SOR1>, 851 <&bpmp TEGRA186_CLK_SOR1_OUT>, 852 <&bpmp TEGRA186_CLK_PLLD3>, 853 <&bpmp TEGRA186_CLK_PLLDP>, 854 <&bpmp TEGRA186_CLK_SOR_SAFE>, 855 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 856 clock-names = "sor", "out", "parent", "dp", "safe", 857 "pad"; 858 resets = <&bpmp TEGRA186_RESET_SOR1>; 859 reset-names = "sor"; 860 pinctrl-0 = <&state_dpaux1_aux>; 861 pinctrl-1 = <&state_dpaux1_i2c>; 862 pinctrl-2 = <&state_dpaux1_off>; 863 pinctrl-names = "aux", "i2c", "off"; 864 status = "disabled"; 865 866 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 867 nvidia,interface = <1>; 868 }; 869 870 dpaux: dpaux@155c0000 { 871 compatible = "nvidia,tegra186-dpaux"; 872 reg = <0x155c0000 0x10000>; 873 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 875 <&bpmp TEGRA186_CLK_PLLDP>; 876 clock-names = "dpaux", "parent"; 877 resets = <&bpmp TEGRA186_RESET_DPAUX>; 878 reset-names = "dpaux"; 879 status = "disabled"; 880 881 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 882 883 state_dpaux_aux: pinmux-aux { 884 groups = "dpaux-io"; 885 function = "aux"; 886 }; 887 888 state_dpaux_i2c: pinmux-i2c { 889 groups = "dpaux-io"; 890 function = "i2c"; 891 }; 892 893 state_dpaux_off: pinmux-off { 894 groups = "dpaux-io"; 895 function = "off"; 896 }; 897 898 i2c-bus { 899 #address-cells = <1>; 900 #size-cells = <0>; 901 }; 902 }; 903 904 padctl@15880000 { 905 compatible = "nvidia,tegra186-dsi-padctl"; 906 reg = <0x15880000 0x10000>; 907 resets = <&bpmp TEGRA186_RESET_DSI>; 908 reset-names = "dsi"; 909 status = "disabled"; 910 }; 911 912 dsic: dsi@15900000 { 913 compatible = "nvidia,tegra186-dsi"; 914 reg = <0x15900000 0x10000>; 915 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&bpmp TEGRA186_CLK_DSIC>, 917 <&bpmp TEGRA186_CLK_DSIC_LP>, 918 <&bpmp TEGRA186_CLK_PLLD>; 919 clock-names = "dsi", "lp", "parent"; 920 resets = <&bpmp TEGRA186_RESET_DSIC>; 921 reset-names = "dsi"; 922 status = "disabled"; 923 924 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 925 }; 926 927 dsid: dsi@15940000 { 928 compatible = "nvidia,tegra186-dsi"; 929 reg = <0x15940000 0x10000>; 930 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&bpmp TEGRA186_CLK_DSID>, 932 <&bpmp TEGRA186_CLK_DSID_LP>, 933 <&bpmp TEGRA186_CLK_PLLD>; 934 clock-names = "dsi", "lp", "parent"; 935 resets = <&bpmp TEGRA186_RESET_DSID>; 936 reset-names = "dsi"; 937 status = "disabled"; 938 939 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 940 }; 941 }; 942 943 gpu@17000000 { 944 compatible = "nvidia,gp10b"; 945 reg = <0x0 0x17000000 0x0 0x1000000>, 946 <0x0 0x18000000 0x0 0x1000000>; 947 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 948 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 949 interrupt-names = "stall", "nonstall"; 950 951 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 952 <&bpmp TEGRA186_CLK_GPU>; 953 clock-names = "gpu", "pwr"; 954 resets = <&bpmp TEGRA186_RESET_GPU>; 955 reset-names = "gpu"; 956 status = "disabled"; 957 958 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 959 }; 960 961 sysram@30000000 { 962 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 963 reg = <0x0 0x30000000 0x0 0x50000>; 964 #address-cells = <2>; 965 #size-cells = <2>; 966 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 967 968 cpu_bpmp_tx: shmem@4e000 { 969 compatible = "nvidia,tegra186-bpmp-shmem"; 970 reg = <0x0 0x4e000 0x0 0x1000>; 971 label = "cpu-bpmp-tx"; 972 pool; 973 }; 974 975 cpu_bpmp_rx: shmem@4f000 { 976 compatible = "nvidia,tegra186-bpmp-shmem"; 977 reg = <0x0 0x4f000 0x0 0x1000>; 978 label = "cpu-bpmp-rx"; 979 pool; 980 }; 981 }; 982 983 cpus { 984 #address-cells = <1>; 985 #size-cells = <0>; 986 987 cpu@0 { 988 compatible = "nvidia,tegra186-denver"; 989 device_type = "cpu"; 990 reg = <0x000>; 991 }; 992 993 cpu@1 { 994 compatible = "nvidia,tegra186-denver"; 995 device_type = "cpu"; 996 reg = <0x001>; 997 }; 998 999 cpu@2 { 1000 compatible = "arm,cortex-a57"; 1001 device_type = "cpu"; 1002 reg = <0x100>; 1003 }; 1004 1005 cpu@3 { 1006 compatible = "arm,cortex-a57"; 1007 device_type = "cpu"; 1008 reg = <0x101>; 1009 }; 1010 1011 cpu@4 { 1012 compatible = "arm,cortex-a57"; 1013 device_type = "cpu"; 1014 reg = <0x102>; 1015 }; 1016 1017 cpu@5 { 1018 compatible = "arm,cortex-a57"; 1019 device_type = "cpu"; 1020 reg = <0x103>; 1021 }; 1022 }; 1023 1024 bpmp: bpmp { 1025 compatible = "nvidia,tegra186-bpmp"; 1026 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1027 TEGRA_HSP_DB_MASTER_BPMP>; 1028 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1029 #clock-cells = <1>; 1030 #reset-cells = <1>; 1031 #power-domain-cells = <1>; 1032 1033 bpmp_i2c: i2c { 1034 compatible = "nvidia,tegra186-bpmp-i2c"; 1035 nvidia,bpmp-bus-id = <5>; 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 status = "disabled"; 1039 }; 1040 1041 bpmp_thermal: thermal { 1042 compatible = "nvidia,tegra186-bpmp-thermal"; 1043 #thermal-sensor-cells = <1>; 1044 }; 1045 }; 1046 1047 thermal-zones { 1048 a57 { 1049 polling-delay = <0>; 1050 polling-delay-passive = <1000>; 1051 1052 thermal-sensors = 1053 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1054 1055 trips { 1056 critical { 1057 temperature = <101000>; 1058 hysteresis = <0>; 1059 type = "critical"; 1060 }; 1061 }; 1062 1063 cooling-maps { 1064 }; 1065 }; 1066 1067 denver { 1068 polling-delay = <0>; 1069 polling-delay-passive = <1000>; 1070 1071 thermal-sensors = 1072 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1073 1074 trips { 1075 critical { 1076 temperature = <101000>; 1077 hysteresis = <0>; 1078 type = "critical"; 1079 }; 1080 }; 1081 1082 cooling-maps { 1083 }; 1084 }; 1085 1086 gpu { 1087 polling-delay = <0>; 1088 polling-delay-passive = <1000>; 1089 1090 thermal-sensors = 1091 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1092 1093 trips { 1094 critical { 1095 temperature = <101000>; 1096 hysteresis = <0>; 1097 type = "critical"; 1098 }; 1099 }; 1100 1101 cooling-maps { 1102 }; 1103 }; 1104 1105 pll { 1106 polling-delay = <0>; 1107 polling-delay-passive = <1000>; 1108 1109 thermal-sensors = 1110 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1111 1112 trips { 1113 critical { 1114 temperature = <101000>; 1115 hysteresis = <0>; 1116 type = "critical"; 1117 }; 1118 }; 1119 1120 cooling-maps { 1121 }; 1122 }; 1123 1124 always_on { 1125 polling-delay = <0>; 1126 polling-delay-passive = <1000>; 1127 1128 thermal-sensors = 1129 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1130 1131 trips { 1132 critical { 1133 temperature = <101000>; 1134 hysteresis = <0>; 1135 type = "critical"; 1136 }; 1137 }; 1138 1139 cooling-maps { 1140 }; 1141 }; 1142 }; 1143 1144 timer { 1145 compatible = "arm,armv8-timer"; 1146 interrupts = <GIC_PPI 13 1147 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1148 <GIC_PPI 14 1149 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1150 <GIC_PPI 11 1151 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1152 <GIC_PPI 10 1153 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1154 interrupt-parent = <&gic>; 1155 }; 1156}; 1157