xref: /linux/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts (revision 6beeaf48db6c548fcfc2ad32739d33af2fef3a5b) 
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/input/linux-event-codes.h>
5#include <dt-bindings/input/gpio-keys.h>
6
7#include "tegra186-p3310.dtsi"
8
9/ {
10	model = "NVIDIA Jetson TX2 Developer Kit";
11	compatible = "nvidia,p2771-0000", "nvidia,tegra186";
12
13	aconnect@2900000 {
14		status = "okay";
15
16		dma-controller@2930000 {
17			status = "okay";
18		};
19
20		interrupt-controller@2a40000 {
21			status = "okay";
22		};
23
24		ahub@2900800 {
25			status = "okay";
26
27			ports {
28				#address-cells = <1>;
29				#size-cells = <0>;
30
31				port@0 {
32					reg = <0x0>;
33
34					xbar_admaif0_ep: endpoint {
35						remote-endpoint = <&admaif0_ep>;
36					};
37				};
38
39				port@1 {
40					reg = <0x1>;
41
42					xbar_admaif1_ep: endpoint {
43						remote-endpoint = <&admaif1_ep>;
44					};
45				};
46
47				port@2 {
48					reg = <0x2>;
49
50					xbar_admaif2_ep: endpoint {
51						remote-endpoint = <&admaif2_ep>;
52					};
53				};
54
55				port@3 {
56					reg = <0x3>;
57
58					xbar_admaif3_ep: endpoint {
59						remote-endpoint = <&admaif3_ep>;
60					};
61				};
62
63				port@4 {
64					reg = <0x4>;
65
66					xbar_admaif4_ep: endpoint {
67						remote-endpoint = <&admaif4_ep>;
68					};
69				};
70
71				port@5 {
72					reg = <0x5>;
73
74					xbar_admaif5_ep: endpoint {
75						remote-endpoint = <&admaif5_ep>;
76					};
77				};
78
79				port@6 {
80					reg = <0x6>;
81
82					xbar_admaif6_ep: endpoint {
83						remote-endpoint = <&admaif6_ep>;
84					};
85				};
86
87				port@7 {
88					reg = <0x7>;
89
90					xbar_admaif7_ep: endpoint {
91						remote-endpoint = <&admaif7_ep>;
92					};
93				};
94
95				port@8 {
96					reg = <0x8>;
97
98					xbar_admaif8_ep: endpoint {
99						remote-endpoint = <&admaif8_ep>;
100					};
101				};
102
103				port@9 {
104					reg = <0x9>;
105
106					xbar_admaif9_ep: endpoint {
107						remote-endpoint = <&admaif9_ep>;
108					};
109				};
110
111				port@a {
112					reg = <0xa>;
113
114					xbar_admaif10_ep: endpoint {
115						remote-endpoint = <&admaif10_ep>;
116					};
117				};
118
119				port@b {
120					reg = <0xb>;
121
122					xbar_admaif11_ep: endpoint {
123						remote-endpoint = <&admaif11_ep>;
124					};
125				};
126
127				port@c {
128					reg = <0xc>;
129
130					xbar_admaif12_ep: endpoint {
131						remote-endpoint = <&admaif12_ep>;
132					};
133				};
134
135				port@d {
136					reg = <0xd>;
137
138					xbar_admaif13_ep: endpoint {
139						remote-endpoint = <&admaif13_ep>;
140					};
141				};
142
143				port@e {
144					reg = <0xe>;
145
146					xbar_admaif14_ep: endpoint {
147						remote-endpoint = <&admaif14_ep>;
148					};
149				};
150
151				port@f {
152					reg = <0xf>;
153
154					xbar_admaif15_ep: endpoint {
155						remote-endpoint = <&admaif15_ep>;
156					};
157				};
158
159				port@10 {
160					reg = <0x10>;
161
162					xbar_admaif16_ep: endpoint {
163						remote-endpoint = <&admaif16_ep>;
164					};
165				};
166
167				port@11 {
168					reg = <0x11>;
169
170					xbar_admaif17_ep: endpoint {
171						remote-endpoint = <&admaif17_ep>;
172					};
173				};
174
175				port@12 {
176					reg = <0x12>;
177
178					xbar_admaif18_ep: endpoint {
179						remote-endpoint = <&admaif18_ep>;
180					};
181				};
182
183				port@13 {
184					reg = <0x13>;
185
186					xbar_admaif19_ep: endpoint {
187						remote-endpoint = <&admaif19_ep>;
188					};
189				};
190
191				xbar_i2s1_port: port@14 {
192					reg = <0x14>;
193
194					xbar_i2s1_ep: endpoint {
195						remote-endpoint = <&i2s1_cif_ep>;
196					};
197				};
198
199				xbar_i2s2_port: port@15 {
200					reg = <0x15>;
201
202					xbar_i2s2_ep: endpoint {
203						remote-endpoint = <&i2s2_cif_ep>;
204					};
205				};
206
207				xbar_i2s3_port: port@16 {
208					reg = <0x16>;
209
210					xbar_i2s3_ep: endpoint {
211						remote-endpoint = <&i2s3_cif_ep>;
212					};
213				};
214
215				xbar_i2s4_port: port@17 {
216					reg = <0x17>;
217
218					xbar_i2s4_ep: endpoint {
219						remote-endpoint = <&i2s4_cif_ep>;
220					};
221				};
222
223				xbar_i2s5_port: port@18 {
224					reg = <0x18>;
225
226					xbar_i2s5_ep: endpoint {
227						remote-endpoint = <&i2s5_cif_ep>;
228					};
229				};
230
231				xbar_i2s6_port: port@19 {
232					reg = <0x19>;
233
234					xbar_i2s6_ep: endpoint {
235						remote-endpoint = <&i2s6_cif_ep>;
236					};
237				};
238
239				xbar_dmic1_port: port@1a {
240					reg = <0x1a>;
241
242					xbar_dmic1_ep: endpoint {
243						remote-endpoint = <&dmic1_cif_ep>;
244					};
245				};
246
247				xbar_dmic2_port: port@1b {
248					reg = <0x1b>;
249
250					xbar_dmic2_ep: endpoint {
251						remote-endpoint = <&dmic2_cif_ep>;
252					};
253				};
254
255				xbar_dmic3_port: port@1c {
256					reg = <0x1c>;
257
258					xbar_dmic3_ep: endpoint {
259						remote-endpoint = <&dmic3_cif_ep>;
260					};
261				};
262
263				xbar_dspk1_port: port@1e {
264					reg = <0x1e>;
265
266					xbar_dspk1_ep: endpoint {
267						remote-endpoint = <&dspk1_cif_ep>;
268					};
269				};
270
271				xbar_dspk2_port: port@1f {
272					reg = <0x1f>;
273
274					xbar_dspk2_ep: endpoint {
275						remote-endpoint = <&dspk2_cif_ep>;
276					};
277				};
278			};
279
280			admaif@290f000 {
281				status = "okay";
282
283				ports {
284					#address-cells = <1>;
285					#size-cells = <0>;
286
287					admaif0_port: port@0 {
288						reg = <0x0>;
289
290						admaif0_ep: endpoint {
291							remote-endpoint = <&xbar_admaif0_ep>;
292						};
293					};
294
295					admaif1_port: port@1 {
296						reg = <0x1>;
297
298						admaif1_ep: endpoint {
299							remote-endpoint = <&xbar_admaif1_ep>;
300						};
301					};
302
303					admaif2_port: port@2 {
304						reg = <0x2>;
305
306						admaif2_ep: endpoint {
307							remote-endpoint = <&xbar_admaif2_ep>;
308						};
309					};
310
311					admaif3_port: port@3 {
312						reg = <0x3>;
313
314						admaif3_ep: endpoint {
315							remote-endpoint = <&xbar_admaif3_ep>;
316						};
317					};
318
319					admaif4_port: port@4 {
320						reg = <0x4>;
321
322						admaif4_ep: endpoint {
323							remote-endpoint = <&xbar_admaif4_ep>;
324						};
325					};
326
327					admaif5_port: port@5 {
328						reg = <0x5>;
329
330						admaif5_ep: endpoint {
331							remote-endpoint = <&xbar_admaif5_ep>;
332						};
333					};
334
335					admaif6_port: port@6 {
336						reg = <0x6>;
337
338						admaif6_ep: endpoint {
339							remote-endpoint = <&xbar_admaif6_ep>;
340						};
341					};
342
343					admaif7_port: port@7 {
344						reg = <0x7>;
345
346						admaif7_ep: endpoint {
347							remote-endpoint = <&xbar_admaif7_ep>;
348						};
349					};
350
351					admaif8_port: port@8 {
352						reg = <0x8>;
353
354						admaif8_ep: endpoint {
355							remote-endpoint = <&xbar_admaif8_ep>;
356						};
357					};
358
359					admaif9_port: port@9 {
360						reg = <0x9>;
361
362						admaif9_ep: endpoint {
363							remote-endpoint = <&xbar_admaif9_ep>;
364						};
365					};
366
367					admaif10_port: port@a {
368						reg = <0xa>;
369
370						admaif10_ep: endpoint {
371							remote-endpoint = <&xbar_admaif10_ep>;
372						};
373					};
374
375					admaif11_port: port@b {
376						reg = <0xb>;
377
378						admaif11_ep: endpoint {
379							remote-endpoint = <&xbar_admaif11_ep>;
380						};
381					};
382
383					admaif12_port: port@c {
384						reg = <0xc>;
385
386						admaif12_ep: endpoint {
387							remote-endpoint = <&xbar_admaif12_ep>;
388						};
389					};
390
391					admaif13_port: port@d {
392						reg = <0xd>;
393
394						admaif13_ep: endpoint {
395							remote-endpoint = <&xbar_admaif13_ep>;
396						};
397					};
398
399					admaif14_port: port@e {
400						reg = <0xe>;
401
402						admaif14_ep: endpoint {
403							remote-endpoint = <&xbar_admaif14_ep>;
404						};
405					};
406
407					admaif15_port: port@f {
408						reg = <0xf>;
409
410						admaif15_ep: endpoint {
411							remote-endpoint = <&xbar_admaif15_ep>;
412						};
413					};
414
415					admaif16_port: port@10 {
416						reg = <0x10>;
417
418						admaif16_ep: endpoint {
419							remote-endpoint = <&xbar_admaif16_ep>;
420						};
421					};
422
423					admaif17_port: port@11 {
424						reg = <0x11>;
425
426						admaif17_ep: endpoint {
427							remote-endpoint = <&xbar_admaif17_ep>;
428						};
429					};
430
431					admaif18_port: port@12 {
432						reg = <0x12>;
433
434						admaif18_ep: endpoint {
435							remote-endpoint = <&xbar_admaif18_ep>;
436						};
437					};
438
439					admaif19_port: port@13 {
440						reg = <0x13>;
441
442						admaif19_ep: endpoint {
443							remote-endpoint = <&xbar_admaif19_ep>;
444						};
445					};
446				};
447			};
448
449			i2s@2901000 {
450				status = "okay";
451
452				ports {
453					#address-cells = <1>;
454					#size-cells = <0>;
455
456					port@0 {
457						reg = <0>;
458
459						i2s1_cif_ep: endpoint {
460							remote-endpoint = <&xbar_i2s1_ep>;
461						};
462					};
463
464					i2s1_port: port@1 {
465						reg = <1>;
466
467						i2s1_dap_ep: endpoint {
468							dai-format = "i2s";
469							/* Placeholder for external Codec */
470						};
471					};
472				};
473			};
474
475			i2s@2901100 {
476				status = "okay";
477
478				ports {
479					#address-cells = <1>;
480					#size-cells = <0>;
481
482					port@0 {
483						reg = <0>;
484
485						i2s2_cif_ep: endpoint {
486							remote-endpoint = <&xbar_i2s2_ep>;
487						};
488					};
489
490					i2s2_port: port@1 {
491						reg = <1>;
492
493						i2s2_dap_ep: endpoint {
494							dai-format = "i2s";
495							/* Placeholder for external Codec */
496						};
497					};
498				};
499			};
500
501			i2s@2901200 {
502				status = "okay";
503
504				ports {
505					#address-cells = <1>;
506					#size-cells = <0>;
507
508					port@0 {
509						reg = <0>;
510
511						i2s3_cif_ep: endpoint {
512							remote-endpoint = <&xbar_i2s3_ep>;
513						};
514					};
515
516					i2s3_port: port@1 {
517						reg = <1>;
518
519						i2s3_dap_ep: endpoint {
520							dai-format = "i2s";
521							/* Placeholder for external Codec */
522						};
523					};
524				};
525			};
526
527			i2s@2901300 {
528				status = "okay";
529
530				ports {
531					#address-cells = <1>;
532					#size-cells = <0>;
533
534					port@0 {
535						reg = <0>;
536
537						i2s4_cif_ep: endpoint {
538							remote-endpoint = <&xbar_i2s4_ep>;
539						};
540					};
541
542					i2s4_port: port@1 {
543						reg = <1>;
544
545						i2s4_dap_ep: endpoint {
546							dai-format = "i2s";
547							/* Placeholder for external Codec */
548						};
549					};
550				};
551			};
552
553			i2s@2901400 {
554				status = "okay";
555
556				ports {
557					#address-cells = <1>;
558					#size-cells = <0>;
559
560					port@0 {
561						reg = <0>;
562
563						i2s5_cif_ep: endpoint {
564							remote-endpoint = <&xbar_i2s5_ep>;
565						};
566					};
567
568					i2s5_port: port@1 {
569						reg = <1>;
570
571						i2s5_dap_ep: endpoint {
572							dai-format = "i2s";
573							/* Placeholder for external Codec */
574						};
575					};
576				};
577			};
578
579			i2s@2901500 {
580				status = "okay";
581
582				ports {
583					#address-cells = <1>;
584					#size-cells = <0>;
585
586					port@0 {
587						reg = <0>;
588
589						i2s6_cif_ep: endpoint {
590							remote-endpoint = <&xbar_i2s6_ep>;
591						};
592					};
593
594					i2s6_port: port@1 {
595						reg = <1>;
596
597						i2s6_dap_ep: endpoint {
598							dai-format = "i2s";
599							/* Placeholder for external Codec */
600						};
601					};
602				};
603			};
604
605			dmic@2904000 {
606				status = "okay";
607
608				ports {
609					#address-cells = <1>;
610					#size-cells = <0>;
611
612					port@0 {
613						reg = <0>;
614
615						dmic1_cif_ep: endpoint {
616							remote-endpoint = <&xbar_dmic1_ep>;
617						};
618					};
619
620					dmic1_port: port@1 {
621						reg = <1>;
622
623						dmic1_dap_ep: endpoint {
624							/* Place holder for external Codec */
625						};
626					};
627				};
628			};
629
630			dmic@2904100 {
631				status = "okay";
632
633				ports {
634					#address-cells = <1>;
635					#size-cells = <0>;
636
637					port@0 {
638						reg = <0>;
639
640						dmic2_cif_ep: endpoint {
641							remote-endpoint = <&xbar_dmic2_ep>;
642						};
643					};
644
645					dmic2_port: port@1 {
646						reg = <1>;
647
648						dmic2_dap_ep: endpoint {
649							/* Place holder for external Codec */
650						};
651					};
652				};
653			};
654
655			dmic@2904200 {
656				status = "okay";
657
658				ports {
659					#address-cells = <1>;
660					#size-cells = <0>;
661
662					port@0 {
663						reg = <0>;
664
665						dmic3_cif_ep: endpoint {
666							remote-endpoint = <&xbar_dmic3_ep>;
667						};
668					};
669
670					dmic3_port: port@1 {
671						reg = <1>;
672
673						dmic3_dap_ep: endpoint {
674							/* Place holder for external Codec */
675						};
676					};
677				};
678			};
679
680			dspk@2905000 {
681				status = "okay";
682
683				ports {
684					#address-cells = <1>;
685					#size-cells = <0>;
686
687					port@0 {
688						reg = <0>;
689
690						dspk1_cif_ep: endpoint {
691							remote-endpoint = <&xbar_dspk1_ep>;
692						};
693					};
694
695					dspk1_port: port@1 {
696						reg = <1>;
697
698						dspk1_dap_ep: endpoint {
699							/* Place holder for external Codec */
700						};
701					};
702				};
703			};
704
705			dspk@2905100 {
706				status = "okay";
707
708				ports {
709					#address-cells = <1>;
710					#size-cells = <0>;
711
712					port@0 {
713						reg = <0>;
714
715						dspk2_cif_ep: endpoint {
716							remote-endpoint = <&xbar_dspk2_ep>;
717						};
718					};
719
720					dspk2_port: port@1 {
721						reg = <1>;
722
723						dspk2_dap_ep: endpoint {
724							/* Place holder for external Codec */
725						};
726					};
727				};
728			};
729		};
730	};
731
732	i2c@3160000 {
733		power-monitor@42 {
734			compatible = "ti,ina3221";
735			reg = <0x42>;
736			#address-cells = <1>;
737			#size-cells = <0>;
738
739			channel@0 {
740				reg = <0x0>;
741				label = "VDD_MUX";
742				shunt-resistor-micro-ohms = <20000>;
743			};
744
745			channel@1 {
746				reg = <0x1>;
747				label = "VDD_5V0_IO_SYS";
748				shunt-resistor-micro-ohms = <5000>;
749			};
750
751			channel@2 {
752				reg = <0x2>;
753				label = "VDD_3V3_SYS";
754				shunt-resistor-micro-ohms = <10000>;
755			};
756		};
757
758		power-monitor@43 {
759			compatible = "ti,ina3221";
760			reg = <0x43>;
761			#address-cells = <1>;
762			#size-cells = <0>;
763
764			channel@0 {
765				reg = <0x0>;
766				label = "VDD_3V3_IO_SLP";
767				shunt-resistor-micro-ohms = <10000>;
768			};
769
770			channel@1 {
771				reg = <0x1>;
772				label = "VDD_1V8_IO";
773				shunt-resistor-micro-ohms = <10000>;
774			};
775
776			channel@2 {
777				reg = <0x2>;
778				label = "VDD_M2_IN";
779				shunt-resistor-micro-ohms = <10000>;
780			};
781		};
782
783		exp1: gpio@74 {
784			compatible = "ti,tca9539";
785			reg = <0x74>;
786
787			interrupt-parent = <&gpio>;
788			interrupts = <TEGRA186_MAIN_GPIO(Y, 0)
789				      GPIO_ACTIVE_LOW>;
790
791			#gpio-cells = <2>;
792			gpio-controller;
793
794			vcc-supply = <&vdd_3v3_sys>;
795		};
796
797		exp2: gpio@77 {
798			compatible = "ti,tca9539";
799			reg = <0x77>;
800
801			interrupt-parent = <&gpio>;
802			interrupts = <TEGRA186_MAIN_GPIO(Y, 6)
803				      GPIO_ACTIVE_LOW>;
804
805			#gpio-cells = <2>;
806			gpio-controller;
807
808			vcc-supply = <&vdd_1v8>;
809		};
810	};
811
812	/* SDMMC1 (SD/MMC) */
813	mmc@3400000 {
814		status = "okay";
815
816		vmmc-supply = <&vdd_sd>;
817	};
818
819	hda@3510000 {
820		nvidia,model = "NVIDIA Jetson TX2 HDA";
821		status = "okay";
822	};
823
824	padctl@3520000 {
825		status = "okay";
826
827		avdd-pll-erefeut-supply = <&vdd_1v8_pll>;
828		avdd-usb-supply = <&vdd_3v3_sys>;
829		vclamp-usb-supply = <&vdd_1v8>;
830		vddio-hsic-supply = <&gnd>;
831
832		pads {
833			usb2 {
834				status = "okay";
835
836				lanes {
837					micro_b: usb2-0 {
838						nvidia,function = "xusb";
839						status = "okay";
840					};
841
842					usb2-1 {
843						nvidia,function = "xusb";
844						status = "okay";
845					};
846
847					usb2-2 {
848						nvidia,function = "xusb";
849						status = "okay";
850					};
851				};
852			};
853
854			usb3 {
855				status = "okay";
856
857				lanes {
858					usb3-0 {
859						nvidia,function = "xusb";
860						status = "okay";
861					};
862
863					usb3-1 {
864						nvidia,function = "xusb";
865						status = "okay";
866					};
867
868					usb3-2 {
869						nvidia,function = "xusb";
870						status = "okay";
871					};
872				};
873			};
874		};
875
876		ports {
877			usb2-0 {
878				status = "okay";
879				mode = "otg";
880				vbus-supply = <&vdd_usb0>;
881				usb-role-switch;
882
883				connector {
884					compatible = "gpio-usb-b-connector",
885						     "usb-b-connector";
886					label = "micro-USB";
887					type = "micro";
888					vbus-gpios = <&gpio
889						      TEGRA186_MAIN_GPIO(X, 7)
890						      GPIO_ACTIVE_LOW>;
891					id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>;
892				};
893			};
894
895			usb2-1 {
896				status = "okay";
897				mode = "host";
898
899				vbus-supply = <&vdd_usb1>;
900			};
901
902			usb3-0 {
903				nvidia,usb2-companion = <1>;
904				vbus-supply = <&vdd_usb1>;
905				status = "okay";
906			};
907		};
908	};
909
910	usb@3530000 {
911		status = "okay";
912
913		phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>,
914		       <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>,
915		       <&{/padctl@3520000/pads/usb3/lanes/usb3-0}>;
916		phy-names = "usb2-0", "usb2-1", "usb3-0";
917	};
918
919	usb@3550000 {
920		status = "okay";
921
922		phys = <&micro_b>;
923		phy-names = "usb2-0";
924	};
925
926	i2c@c250000 {
927		/* carrier board ID EEPROM */
928		eeprom@57 {
929			compatible = "atmel,24c02";
930			reg = <0x57>;
931
932			label = "system";
933			vcc-supply = <&vdd_1v8>;
934			address-width = <8>;
935			pagesize = <8>;
936			size = <256>;
937			read-only;
938		};
939	};
940
941	pcie@10003000 {
942		status = "okay";
943
944		dvdd-pex-supply = <&vdd_pex>;
945		hvdd-pex-pll-supply = <&vdd_1v8>;
946		hvdd-pex-supply = <&vdd_1v8>;
947		vddio-pexctl-aud-supply = <&vdd_1v8>;
948
949		pci@1,0 {
950			nvidia,num-lanes = <4>;
951			status = "okay";
952		};
953
954		pci@2,0 {
955			nvidia,num-lanes = <0>;
956			status = "disabled";
957		};
958
959		pci@3,0 {
960			nvidia,num-lanes = <1>;
961			status = "disabled";
962		};
963	};
964
965	host1x@13e00000 {
966		status = "okay";
967
968		dpaux@15040000 {
969			status = "okay";
970		};
971
972		display-hub@15200000 {
973			status = "okay";
974		};
975
976		dsi@15300000 {
977			status = "disabled";
978		};
979
980		/* DP on E3320 */
981		sor@15540000 {
982			status = "okay";
983
984			avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
985			vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
986
987			nvidia,dpaux = <&dpaux>;
988		};
989
990		sor@15580000 {
991			status = "okay";
992
993			avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
994			vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
995			hdmi-supply = <&vdd_hdmi>;
996
997			nvidia,ddc-i2c-bus = <&ddc>;
998			nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1)
999						 GPIO_ACTIVE_LOW>;
1000		};
1001
1002		dpaux@155c0000 {
1003			status = "okay";
1004		};
1005	};
1006
1007	sata@3507000 {
1008		status = "okay";
1009	};
1010
1011	gpio-keys {
1012		compatible = "gpio-keys";
1013
1014		power {
1015			label = "Power";
1016			gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0)
1017					   GPIO_ACTIVE_LOW>;
1018			linux,input-type = <EV_KEY>;
1019			linux,code = <KEY_POWER>;
1020			debounce-interval = <10>;
1021			wakeup-event-action = <EV_ACT_ASSERTED>;
1022			wakeup-source;
1023		};
1024
1025		volume-up {
1026			label = "Volume Up";
1027			gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1)
1028					   GPIO_ACTIVE_LOW>;
1029			linux,input-type = <EV_KEY>;
1030			linux,code = <KEY_VOLUMEUP>;
1031			debounce-interval = <10>;
1032		};
1033
1034		volume-down {
1035			label = "Volume Down";
1036			gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2)
1037					   GPIO_ACTIVE_LOW>;
1038			linux,input-type = <EV_KEY>;
1039			linux,code = <KEY_VOLUMEDOWN>;
1040			debounce-interval = <10>;
1041		};
1042	};
1043
1044	vdd_sd: regulator@100 {
1045		compatible = "regulator-fixed";
1046		regulator-name = "SD_CARD_SW_PWR";
1047		regulator-min-microvolt = <3300000>;
1048		regulator-max-microvolt = <3300000>;
1049
1050		gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
1051		enable-active-high;
1052
1053		vin-supply = <&vdd_3v3_sys>;
1054	};
1055
1056	vdd_hdmi: regulator@101 {
1057		compatible = "regulator-fixed";
1058		regulator-name = "VDD_HDMI_5V0";
1059		regulator-min-microvolt = <5000000>;
1060		regulator-max-microvolt = <5000000>;
1061
1062		gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
1063		enable-active-high;
1064
1065		vin-supply = <&vdd_5v0_sys>;
1066	};
1067
1068	vdd_usb0: regulator@102 {
1069		compatible = "regulator-fixed";
1070		regulator-name = "VDD_USB0";
1071		regulator-min-microvolt = <5000000>;
1072		regulator-max-microvolt = <5000000>;
1073
1074		gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
1075		enable-active-high;
1076
1077		vin-supply = <&vdd_5v0_sys>;
1078	};
1079
1080	vdd_usb1: regulator@103 {
1081		compatible = "regulator-fixed";
1082		regulator-name = "VDD_USB1";
1083		regulator-min-microvolt = <5000000>;
1084		regulator-max-microvolt = <5000000>;
1085
1086		gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>;
1087		enable-active-high;
1088
1089		vin-supply = <&vdd_5v0_sys>;
1090	};
1091
1092	sound {
1093		compatible = "nvidia,tegra186-audio-graph-card";
1094		status = "okay";
1095
1096		dais = /* FE */
1097		       <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
1098		       <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
1099		       <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
1100		       <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
1101		       <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
1102		       /* Router */
1103		       <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>,
1104		       <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_i2s6_port>,
1105		       <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic3_port>,
1106		       <&xbar_dspk1_port>, <&xbar_dspk2_port>,
1107		       /* I/O */
1108		       <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
1109		       <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,
1110		       <&dmic3_port>, <&dspk1_port>, <&dspk2_port>;
1111
1112		label = "NVIDIA Jetson TX2 APE";
1113	};
1114};
1115