1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/input/linux-event-codes.h> 5#include <dt-bindings/input/gpio-keys.h> 6 7#include "tegra186-p3310.dtsi" 8 9/ { 10 model = "NVIDIA Jetson TX2 Developer Kit"; 11 compatible = "nvidia,p2771-0000", "nvidia,tegra186"; 12 13 aconnect@2900000 { 14 status = "okay"; 15 16 dma-controller@2930000 { 17 status = "okay"; 18 }; 19 20 interrupt-controller@2a40000 { 21 status = "okay"; 22 }; 23 24 ahub@2900800 { 25 status = "okay"; 26 27 ports { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 port@0 { 32 reg = <0x0>; 33 34 xbar_admaif0_ep: endpoint { 35 remote-endpoint = <&admaif0_ep>; 36 }; 37 }; 38 39 port@1 { 40 reg = <0x1>; 41 42 xbar_admaif1_ep: endpoint { 43 remote-endpoint = <&admaif1_ep>; 44 }; 45 }; 46 47 port@2 { 48 reg = <0x2>; 49 50 xbar_admaif2_ep: endpoint { 51 remote-endpoint = <&admaif2_ep>; 52 }; 53 }; 54 55 port@3 { 56 reg = <0x3>; 57 58 xbar_admaif3_ep: endpoint { 59 remote-endpoint = <&admaif3_ep>; 60 }; 61 }; 62 63 port@4 { 64 reg = <0x4>; 65 66 xbar_admaif4_ep: endpoint { 67 remote-endpoint = <&admaif4_ep>; 68 }; 69 }; 70 71 port@5 { 72 reg = <0x5>; 73 74 xbar_admaif5_ep: endpoint { 75 remote-endpoint = <&admaif5_ep>; 76 }; 77 }; 78 79 port@6 { 80 reg = <0x6>; 81 82 xbar_admaif6_ep: endpoint { 83 remote-endpoint = <&admaif6_ep>; 84 }; 85 }; 86 87 port@7 { 88 reg = <0x7>; 89 90 xbar_admaif7_ep: endpoint { 91 remote-endpoint = <&admaif7_ep>; 92 }; 93 }; 94 95 port@8 { 96 reg = <0x8>; 97 98 xbar_admaif8_ep: endpoint { 99 remote-endpoint = <&admaif8_ep>; 100 }; 101 }; 102 103 port@9 { 104 reg = <0x9>; 105 106 xbar_admaif9_ep: endpoint { 107 remote-endpoint = <&admaif9_ep>; 108 }; 109 }; 110 111 port@a { 112 reg = <0xa>; 113 114 xbar_admaif10_ep: endpoint { 115 remote-endpoint = <&admaif10_ep>; 116 }; 117 }; 118 119 port@b { 120 reg = <0xb>; 121 122 xbar_admaif11_ep: endpoint { 123 remote-endpoint = <&admaif11_ep>; 124 }; 125 }; 126 127 port@c { 128 reg = <0xc>; 129 130 xbar_admaif12_ep: endpoint { 131 remote-endpoint = <&admaif12_ep>; 132 }; 133 }; 134 135 port@d { 136 reg = <0xd>; 137 138 xbar_admaif13_ep: endpoint { 139 remote-endpoint = <&admaif13_ep>; 140 }; 141 }; 142 143 port@e { 144 reg = <0xe>; 145 146 xbar_admaif14_ep: endpoint { 147 remote-endpoint = <&admaif14_ep>; 148 }; 149 }; 150 151 port@f { 152 reg = <0xf>; 153 154 xbar_admaif15_ep: endpoint { 155 remote-endpoint = <&admaif15_ep>; 156 }; 157 }; 158 159 port@10 { 160 reg = <0x10>; 161 162 xbar_admaif16_ep: endpoint { 163 remote-endpoint = <&admaif16_ep>; 164 }; 165 }; 166 167 port@11 { 168 reg = <0x11>; 169 170 xbar_admaif17_ep: endpoint { 171 remote-endpoint = <&admaif17_ep>; 172 }; 173 }; 174 175 port@12 { 176 reg = <0x12>; 177 178 xbar_admaif18_ep: endpoint { 179 remote-endpoint = <&admaif18_ep>; 180 }; 181 }; 182 183 port@13 { 184 reg = <0x13>; 185 186 xbar_admaif19_ep: endpoint { 187 remote-endpoint = <&admaif19_ep>; 188 }; 189 }; 190 191 xbar_i2s1_port: port@14 { 192 reg = <0x14>; 193 194 xbar_i2s1_ep: endpoint { 195 remote-endpoint = <&i2s1_cif_ep>; 196 }; 197 }; 198 199 xbar_i2s2_port: port@15 { 200 reg = <0x15>; 201 202 xbar_i2s2_ep: endpoint { 203 remote-endpoint = <&i2s2_cif_ep>; 204 }; 205 }; 206 207 xbar_i2s3_port: port@16 { 208 reg = <0x16>; 209 210 xbar_i2s3_ep: endpoint { 211 remote-endpoint = <&i2s3_cif_ep>; 212 }; 213 }; 214 215 xbar_i2s4_port: port@17 { 216 reg = <0x17>; 217 218 xbar_i2s4_ep: endpoint { 219 remote-endpoint = <&i2s4_cif_ep>; 220 }; 221 }; 222 223 xbar_i2s5_port: port@18 { 224 reg = <0x18>; 225 226 xbar_i2s5_ep: endpoint { 227 remote-endpoint = <&i2s5_cif_ep>; 228 }; 229 }; 230 231 xbar_i2s6_port: port@19 { 232 reg = <0x19>; 233 234 xbar_i2s6_ep: endpoint { 235 remote-endpoint = <&i2s6_cif_ep>; 236 }; 237 }; 238 239 xbar_dmic1_port: port@1a { 240 reg = <0x1a>; 241 242 xbar_dmic1_ep: endpoint { 243 remote-endpoint = <&dmic1_cif_ep>; 244 }; 245 }; 246 247 xbar_dmic2_port: port@1b { 248 reg = <0x1b>; 249 250 xbar_dmic2_ep: endpoint { 251 remote-endpoint = <&dmic2_cif_ep>; 252 }; 253 }; 254 255 xbar_dmic3_port: port@1c { 256 reg = <0x1c>; 257 258 xbar_dmic3_ep: endpoint { 259 remote-endpoint = <&dmic3_cif_ep>; 260 }; 261 }; 262 263 xbar_dspk1_port: port@1e { 264 reg = <0x1e>; 265 266 xbar_dspk1_ep: endpoint { 267 remote-endpoint = <&dspk1_cif_ep>; 268 }; 269 }; 270 271 xbar_dspk2_port: port@1f { 272 reg = <0x1f>; 273 274 xbar_dspk2_ep: endpoint { 275 remote-endpoint = <&dspk2_cif_ep>; 276 }; 277 }; 278 279 xbar_sfc1_in_port: port@20 { 280 reg = <0x20>; 281 282 xbar_sfc1_in_ep: endpoint { 283 remote-endpoint = <&sfc1_cif_in_ep>; 284 }; 285 }; 286 287 port@21 { 288 reg = <0x21>; 289 290 xbar_sfc1_out_ep: endpoint { 291 remote-endpoint = <&sfc1_cif_out_ep>; 292 }; 293 }; 294 295 xbar_sfc2_in_port: port@22 { 296 reg = <0x22>; 297 298 xbar_sfc2_in_ep: endpoint { 299 remote-endpoint = <&sfc2_cif_in_ep>; 300 }; 301 }; 302 303 port@23 { 304 reg = <0x23>; 305 306 xbar_sfc2_out_ep: endpoint { 307 remote-endpoint = <&sfc2_cif_out_ep>; 308 }; 309 }; 310 311 xbar_sfc3_in_port: port@24 { 312 reg = <0x24>; 313 314 xbar_sfc3_in_ep: endpoint { 315 remote-endpoint = <&sfc3_cif_in_ep>; 316 }; 317 }; 318 319 port@25 { 320 reg = <0x25>; 321 322 xbar_sfc3_out_ep: endpoint { 323 remote-endpoint = <&sfc3_cif_out_ep>; 324 }; 325 }; 326 327 xbar_sfc4_in_port: port@26 { 328 reg = <0x26>; 329 330 xbar_sfc4_in_ep: endpoint { 331 remote-endpoint = <&sfc4_cif_in_ep>; 332 }; 333 }; 334 335 port@27 { 336 reg = <0x27>; 337 338 xbar_sfc4_out_ep: endpoint { 339 remote-endpoint = <&sfc4_cif_out_ep>; 340 }; 341 }; 342 343 xbar_mvc1_in_port: port@28 { 344 reg = <0x28>; 345 346 xbar_mvc1_in_ep: endpoint { 347 remote-endpoint = <&mvc1_cif_in_ep>; 348 }; 349 }; 350 351 port@29 { 352 reg = <0x29>; 353 354 xbar_mvc1_out_ep: endpoint { 355 remote-endpoint = <&mvc1_cif_out_ep>; 356 }; 357 }; 358 359 xbar_mvc2_in_port: port@2a { 360 reg = <0x2a>; 361 362 xbar_mvc2_in_ep: endpoint { 363 remote-endpoint = <&mvc2_cif_in_ep>; 364 }; 365 }; 366 367 port@2b { 368 reg = <0x2b>; 369 370 xbar_mvc2_out_ep: endpoint { 371 remote-endpoint = <&mvc2_cif_out_ep>; 372 }; 373 }; 374 375 xbar_amx1_in1_port: port@2c { 376 reg = <0x2c>; 377 378 xbar_amx1_in1_ep: endpoint { 379 remote-endpoint = <&amx1_in1_ep>; 380 }; 381 }; 382 383 xbar_amx1_in2_port: port@2d { 384 reg = <0x2d>; 385 386 xbar_amx1_in2_ep: endpoint { 387 remote-endpoint = <&amx1_in2_ep>; 388 }; 389 }; 390 391 xbar_amx1_in3_port: port@2e { 392 reg = <0x2e>; 393 394 xbar_amx1_in3_ep: endpoint { 395 remote-endpoint = <&amx1_in3_ep>; 396 }; 397 }; 398 399 xbar_amx1_in4_port: port@2f { 400 reg = <0x2f>; 401 402 xbar_amx1_in4_ep: endpoint { 403 remote-endpoint = <&amx1_in4_ep>; 404 }; 405 }; 406 407 port@30 { 408 reg = <0x30>; 409 410 xbar_amx1_out_ep: endpoint { 411 remote-endpoint = <&amx1_out_ep>; 412 }; 413 }; 414 415 xbar_amx2_in1_port: port@31 { 416 reg = <0x31>; 417 418 xbar_amx2_in1_ep: endpoint { 419 remote-endpoint = <&amx2_in1_ep>; 420 }; 421 }; 422 423 xbar_amx2_in2_port: port@32 { 424 reg = <0x32>; 425 426 xbar_amx2_in2_ep: endpoint { 427 remote-endpoint = <&amx2_in2_ep>; 428 }; 429 }; 430 431 xbar_amx2_in3_port: port@33 { 432 reg = <0x33>; 433 434 xbar_amx2_in3_ep: endpoint { 435 remote-endpoint = <&amx2_in3_ep>; 436 }; 437 }; 438 439 xbar_amx2_in4_port: port@34 { 440 reg = <0x34>; 441 442 xbar_amx2_in4_ep: endpoint { 443 remote-endpoint = <&amx2_in4_ep>; 444 }; 445 }; 446 447 port@35 { 448 reg = <0x35>; 449 450 xbar_amx2_out_ep: endpoint { 451 remote-endpoint = <&amx2_out_ep>; 452 }; 453 }; 454 455 xbar_amx3_in1_port: port@36 { 456 reg = <0x36>; 457 458 xbar_amx3_in1_ep: endpoint { 459 remote-endpoint = <&amx3_in1_ep>; 460 }; 461 }; 462 463 xbar_amx3_in2_port: port@37 { 464 reg = <0x37>; 465 466 xbar_amx3_in2_ep: endpoint { 467 remote-endpoint = <&amx3_in2_ep>; 468 }; 469 }; 470 471 xbar_amx3_in3_port: port@38 { 472 reg = <0x38>; 473 474 xbar_amx3_in3_ep: endpoint { 475 remote-endpoint = <&amx3_in3_ep>; 476 }; 477 }; 478 479 xbar_amx3_in4_port: port@39 { 480 reg = <0x39>; 481 482 xbar_amx3_in4_ep: endpoint { 483 remote-endpoint = <&amx3_in4_ep>; 484 }; 485 }; 486 487 port@3a { 488 reg = <0x3a>; 489 490 xbar_amx3_out_ep: endpoint { 491 remote-endpoint = <&amx3_out_ep>; 492 }; 493 }; 494 495 xbar_amx4_in1_port: port@3b { 496 reg = <0x3b>; 497 498 xbar_amx4_in1_ep: endpoint { 499 remote-endpoint = <&amx4_in1_ep>; 500 }; 501 }; 502 503 xbar_amx4_in2_port: port@3c { 504 reg = <0x3c>; 505 506 xbar_amx4_in2_ep: endpoint { 507 remote-endpoint = <&amx4_in2_ep>; 508 }; 509 }; 510 511 xbar_amx4_in3_port: port@3d { 512 reg = <0x3d>; 513 514 xbar_amx4_in3_ep: endpoint { 515 remote-endpoint = <&amx4_in3_ep>; 516 }; 517 }; 518 519 xbar_amx4_in4_port: port@3e { 520 reg = <0x3e>; 521 522 xbar_amx4_in4_ep: endpoint { 523 remote-endpoint = <&amx4_in4_ep>; 524 }; 525 }; 526 527 port@3f { 528 reg = <0x3f>; 529 530 xbar_amx4_out_ep: endpoint { 531 remote-endpoint = <&amx4_out_ep>; 532 }; 533 }; 534 535 xbar_adx1_in_port: port@40 { 536 reg = <0x40>; 537 538 xbar_adx1_in_ep: endpoint { 539 remote-endpoint = <&adx1_in_ep>; 540 }; 541 }; 542 543 port@41 { 544 reg = <0x41>; 545 546 xbar_adx1_out1_ep: endpoint { 547 remote-endpoint = <&adx1_out1_ep>; 548 }; 549 }; 550 551 port@42 { 552 reg = <0x42>; 553 554 xbar_adx1_out2_ep: endpoint { 555 remote-endpoint = <&adx1_out2_ep>; 556 }; 557 }; 558 559 port@43 { 560 reg = <0x43>; 561 562 xbar_adx1_out3_ep: endpoint { 563 remote-endpoint = <&adx1_out3_ep>; 564 }; 565 }; 566 567 port@44 { 568 reg = <0x44>; 569 570 xbar_adx1_out4_ep: endpoint { 571 remote-endpoint = <&adx1_out4_ep>; 572 }; 573 }; 574 575 xbar_adx2_in_port: port@45 { 576 reg = <0x45>; 577 578 xbar_adx2_in_ep: endpoint { 579 remote-endpoint = <&adx2_in_ep>; 580 }; 581 }; 582 583 port@46 { 584 reg = <0x46>; 585 586 xbar_adx2_out1_ep: endpoint { 587 remote-endpoint = <&adx2_out1_ep>; 588 }; 589 }; 590 591 port@47 { 592 reg = <0x47>; 593 594 xbar_adx2_out2_ep: endpoint { 595 remote-endpoint = <&adx2_out2_ep>; 596 }; 597 }; 598 599 port@48 { 600 reg = <0x48>; 601 602 xbar_adx2_out3_ep: endpoint { 603 remote-endpoint = <&adx2_out3_ep>; 604 }; 605 }; 606 607 port@49 { 608 reg = <0x49>; 609 610 xbar_adx2_out4_ep: endpoint { 611 remote-endpoint = <&adx2_out4_ep>; 612 }; 613 }; 614 615 xbar_adx3_in_port: port@4a { 616 reg = <0x4a>; 617 618 xbar_adx3_in_ep: endpoint { 619 remote-endpoint = <&adx3_in_ep>; 620 }; 621 }; 622 623 port@4b { 624 reg = <0x4b>; 625 626 xbar_adx3_out1_ep: endpoint { 627 remote-endpoint = <&adx3_out1_ep>; 628 }; 629 }; 630 631 port@4c { 632 reg = <0x4c>; 633 634 xbar_adx3_out2_ep: endpoint { 635 remote-endpoint = <&adx3_out2_ep>; 636 }; 637 }; 638 639 port@4d { 640 reg = <0x4d>; 641 642 xbar_adx3_out3_ep: endpoint { 643 remote-endpoint = <&adx3_out3_ep>; 644 }; 645 }; 646 647 port@4e { 648 reg = <0x4e>; 649 650 xbar_adx3_out4_ep: endpoint { 651 remote-endpoint = <&adx3_out4_ep>; 652 }; 653 }; 654 655 xbar_adx4_in_port: port@4f { 656 reg = <0x4f>; 657 658 xbar_adx4_in_ep: endpoint { 659 remote-endpoint = <&adx4_in_ep>; 660 }; 661 }; 662 663 port@50 { 664 reg = <0x50>; 665 666 xbar_adx4_out1_ep: endpoint { 667 remote-endpoint = <&adx4_out1_ep>; 668 }; 669 }; 670 671 port@51 { 672 reg = <0x51>; 673 674 xbar_adx4_out2_ep: endpoint { 675 remote-endpoint = <&adx4_out2_ep>; 676 }; 677 }; 678 679 port@52 { 680 reg = <0x52>; 681 682 xbar_adx4_out3_ep: endpoint { 683 remote-endpoint = <&adx4_out3_ep>; 684 }; 685 }; 686 687 port@53 { 688 reg = <0x53>; 689 690 xbar_adx4_out4_ep: endpoint { 691 remote-endpoint = <&adx4_out4_ep>; 692 }; 693 }; 694 695 xbar_mixer_in1_port: port@54 { 696 reg = <0x54>; 697 698 xbar_mixer_in1_ep: endpoint { 699 remote-endpoint = <&mixer_in1_ep>; 700 }; 701 }; 702 703 xbar_mixer_in2_port: port@55 { 704 reg = <0x55>; 705 706 xbar_mixer_in2_ep: endpoint { 707 remote-endpoint = <&mixer_in2_ep>; 708 }; 709 }; 710 711 xbar_mixer_in3_port: port@56 { 712 reg = <0x56>; 713 714 xbar_mixer_in3_ep: endpoint { 715 remote-endpoint = <&mixer_in3_ep>; 716 }; 717 }; 718 719 xbar_mixer_in4_port: port@57 { 720 reg = <0x57>; 721 722 xbar_mixer_in4_ep: endpoint { 723 remote-endpoint = <&mixer_in4_ep>; 724 }; 725 }; 726 727 xbar_mixer_in5_port: port@58 { 728 reg = <0x58>; 729 730 xbar_mixer_in5_ep: endpoint { 731 remote-endpoint = <&mixer_in5_ep>; 732 }; 733 }; 734 735 xbar_mixer_in6_port: port@59 { 736 reg = <0x59>; 737 738 xbar_mixer_in6_ep: endpoint { 739 remote-endpoint = <&mixer_in6_ep>; 740 }; 741 }; 742 743 xbar_mixer_in7_port: port@5a { 744 reg = <0x5a>; 745 746 xbar_mixer_in7_ep: endpoint { 747 remote-endpoint = <&mixer_in7_ep>; 748 }; 749 }; 750 751 xbar_mixer_in8_port: port@5b { 752 reg = <0x5b>; 753 754 xbar_mixer_in8_ep: endpoint { 755 remote-endpoint = <&mixer_in8_ep>; 756 }; 757 }; 758 759 xbar_mixer_in9_port: port@5c { 760 reg = <0x5c>; 761 762 xbar_mixer_in9_ep: endpoint { 763 remote-endpoint = <&mixer_in9_ep>; 764 }; 765 }; 766 767 xbar_mixer_in10_port: port@5d { 768 reg = <0x5d>; 769 770 xbar_mixer_in10_ep: endpoint { 771 remote-endpoint = <&mixer_in10_ep>; 772 }; 773 }; 774 775 port@5e { 776 reg = <0x5e>; 777 778 xbar_mixer_out1_ep: endpoint { 779 remote-endpoint = <&mixer_out1_ep>; 780 }; 781 }; 782 783 port@5f { 784 reg = <0x5f>; 785 786 xbar_mixer_out2_ep: endpoint { 787 remote-endpoint = <&mixer_out2_ep>; 788 }; 789 }; 790 791 port@60 { 792 reg = <0x60>; 793 794 xbar_mixer_out3_ep: endpoint { 795 remote-endpoint = <&mixer_out3_ep>; 796 }; 797 }; 798 799 port@61 { 800 reg = <0x61>; 801 802 xbar_mixer_out4_ep: endpoint { 803 remote-endpoint = <&mixer_out4_ep>; 804 }; 805 }; 806 807 port@62 { 808 reg = <0x62>; 809 810 xbar_mixer_out5_ep: endpoint { 811 remote-endpoint = <&mixer_out5_ep>; 812 }; 813 }; 814 815 xbar_asrc_in1_port: port@63 { 816 reg = <0x63>; 817 818 xbar_asrc_in1_ep: endpoint { 819 remote-endpoint = <&asrc_in1_ep>; 820 }; 821 }; 822 823 port@64 { 824 reg = <0x64>; 825 826 xbar_asrc_out1_ep: endpoint { 827 remote-endpoint = <&asrc_out1_ep>; 828 }; 829 }; 830 831 xbar_asrc_in2_port: port@65 { 832 reg = <0x65>; 833 834 xbar_asrc_in2_ep: endpoint { 835 remote-endpoint = <&asrc_in2_ep>; 836 }; 837 }; 838 839 port@66 { 840 reg = <0x66>; 841 842 xbar_asrc_out2_ep: endpoint { 843 remote-endpoint = <&asrc_out2_ep>; 844 }; 845 }; 846 847 xbar_asrc_in3_port: port@67 { 848 reg = <0x67>; 849 850 xbar_asrc_in3_ep: endpoint { 851 remote-endpoint = <&asrc_in3_ep>; 852 }; 853 }; 854 855 port@68 { 856 reg = <0x68>; 857 858 xbar_asrc_out3_ep: endpoint { 859 remote-endpoint = <&asrc_out3_ep>; 860 }; 861 }; 862 863 xbar_asrc_in4_port: port@69 { 864 reg = <0x69>; 865 866 xbar_asrc_in4_ep: endpoint { 867 remote-endpoint = <&asrc_in4_ep>; 868 }; 869 }; 870 871 port@6a { 872 reg = <0x6a>; 873 874 xbar_asrc_out4_ep: endpoint { 875 remote-endpoint = <&asrc_out4_ep>; 876 }; 877 }; 878 879 xbar_asrc_in5_port: port@6b { 880 reg = <0x6b>; 881 882 xbar_asrc_in5_ep: endpoint { 883 remote-endpoint = <&asrc_in5_ep>; 884 }; 885 }; 886 887 port@6c { 888 reg = <0x6c>; 889 890 xbar_asrc_out5_ep: endpoint { 891 remote-endpoint = <&asrc_out5_ep>; 892 }; 893 }; 894 895 xbar_asrc_in6_port: port@6d { 896 reg = <0x6d>; 897 898 xbar_asrc_in6_ep: endpoint { 899 remote-endpoint = <&asrc_in6_ep>; 900 }; 901 }; 902 903 port@6e { 904 reg = <0x6e>; 905 906 xbar_asrc_out6_ep: endpoint { 907 remote-endpoint = <&asrc_out6_ep>; 908 }; 909 }; 910 911 xbar_asrc_in7_port: port@6f { 912 reg = <0x6f>; 913 914 xbar_asrc_in7_ep: endpoint { 915 remote-endpoint = <&asrc_in7_ep>; 916 }; 917 }; 918 919 xbar_ope1_in_port: port@70 { 920 reg = <0x70>; 921 922 xbar_ope1_in_ep: endpoint { 923 remote-endpoint = <&ope1_cif_in_ep>; 924 }; 925 }; 926 927 port@71 { 928 reg = <0x71>; 929 930 xbar_ope1_out_ep: endpoint { 931 remote-endpoint = <&ope1_cif_out_ep>; 932 }; 933 }; 934 }; 935 936 admaif@290f000 { 937 status = "okay"; 938 939 ports { 940 #address-cells = <1>; 941 #size-cells = <0>; 942 943 admaif0_port: port@0 { 944 reg = <0x0>; 945 946 admaif0_ep: endpoint { 947 remote-endpoint = <&xbar_admaif0_ep>; 948 }; 949 }; 950 951 admaif1_port: port@1 { 952 reg = <0x1>; 953 954 admaif1_ep: endpoint { 955 remote-endpoint = <&xbar_admaif1_ep>; 956 }; 957 }; 958 959 admaif2_port: port@2 { 960 reg = <0x2>; 961 962 admaif2_ep: endpoint { 963 remote-endpoint = <&xbar_admaif2_ep>; 964 }; 965 }; 966 967 admaif3_port: port@3 { 968 reg = <0x3>; 969 970 admaif3_ep: endpoint { 971 remote-endpoint = <&xbar_admaif3_ep>; 972 }; 973 }; 974 975 admaif4_port: port@4 { 976 reg = <0x4>; 977 978 admaif4_ep: endpoint { 979 remote-endpoint = <&xbar_admaif4_ep>; 980 }; 981 }; 982 983 admaif5_port: port@5 { 984 reg = <0x5>; 985 986 admaif5_ep: endpoint { 987 remote-endpoint = <&xbar_admaif5_ep>; 988 }; 989 }; 990 991 admaif6_port: port@6 { 992 reg = <0x6>; 993 994 admaif6_ep: endpoint { 995 remote-endpoint = <&xbar_admaif6_ep>; 996 }; 997 }; 998 999 admaif7_port: port@7 { 1000 reg = <0x7>; 1001 1002 admaif7_ep: endpoint { 1003 remote-endpoint = <&xbar_admaif7_ep>; 1004 }; 1005 }; 1006 1007 admaif8_port: port@8 { 1008 reg = <0x8>; 1009 1010 admaif8_ep: endpoint { 1011 remote-endpoint = <&xbar_admaif8_ep>; 1012 }; 1013 }; 1014 1015 admaif9_port: port@9 { 1016 reg = <0x9>; 1017 1018 admaif9_ep: endpoint { 1019 remote-endpoint = <&xbar_admaif9_ep>; 1020 }; 1021 }; 1022 1023 admaif10_port: port@a { 1024 reg = <0xa>; 1025 1026 admaif10_ep: endpoint { 1027 remote-endpoint = <&xbar_admaif10_ep>; 1028 }; 1029 }; 1030 1031 admaif11_port: port@b { 1032 reg = <0xb>; 1033 1034 admaif11_ep: endpoint { 1035 remote-endpoint = <&xbar_admaif11_ep>; 1036 }; 1037 }; 1038 1039 admaif12_port: port@c { 1040 reg = <0xc>; 1041 1042 admaif12_ep: endpoint { 1043 remote-endpoint = <&xbar_admaif12_ep>; 1044 }; 1045 }; 1046 1047 admaif13_port: port@d { 1048 reg = <0xd>; 1049 1050 admaif13_ep: endpoint { 1051 remote-endpoint = <&xbar_admaif13_ep>; 1052 }; 1053 }; 1054 1055 admaif14_port: port@e { 1056 reg = <0xe>; 1057 1058 admaif14_ep: endpoint { 1059 remote-endpoint = <&xbar_admaif14_ep>; 1060 }; 1061 }; 1062 1063 admaif15_port: port@f { 1064 reg = <0xf>; 1065 1066 admaif15_ep: endpoint { 1067 remote-endpoint = <&xbar_admaif15_ep>; 1068 }; 1069 }; 1070 1071 admaif16_port: port@10 { 1072 reg = <0x10>; 1073 1074 admaif16_ep: endpoint { 1075 remote-endpoint = <&xbar_admaif16_ep>; 1076 }; 1077 }; 1078 1079 admaif17_port: port@11 { 1080 reg = <0x11>; 1081 1082 admaif17_ep: endpoint { 1083 remote-endpoint = <&xbar_admaif17_ep>; 1084 }; 1085 }; 1086 1087 admaif18_port: port@12 { 1088 reg = <0x12>; 1089 1090 admaif18_ep: endpoint { 1091 remote-endpoint = <&xbar_admaif18_ep>; 1092 }; 1093 }; 1094 1095 admaif19_port: port@13 { 1096 reg = <0x13>; 1097 1098 admaif19_ep: endpoint { 1099 remote-endpoint = <&xbar_admaif19_ep>; 1100 }; 1101 }; 1102 }; 1103 }; 1104 1105 i2s@2901000 { 1106 status = "okay"; 1107 1108 ports { 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 1112 port@0 { 1113 reg = <0>; 1114 1115 i2s1_cif_ep: endpoint { 1116 remote-endpoint = <&xbar_i2s1_ep>; 1117 }; 1118 }; 1119 1120 i2s1_port: port@1 { 1121 reg = <1>; 1122 1123 i2s1_dap_ep: endpoint { 1124 dai-format = "i2s"; 1125 /* Placeholder for external Codec */ 1126 }; 1127 }; 1128 }; 1129 }; 1130 1131 i2s@2901100 { 1132 status = "okay"; 1133 1134 ports { 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 1138 port@0 { 1139 reg = <0>; 1140 1141 i2s2_cif_ep: endpoint { 1142 remote-endpoint = <&xbar_i2s2_ep>; 1143 }; 1144 }; 1145 1146 i2s2_port: port@1 { 1147 reg = <1>; 1148 1149 i2s2_dap_ep: endpoint { 1150 dai-format = "i2s"; 1151 /* Placeholder for external Codec */ 1152 }; 1153 }; 1154 }; 1155 }; 1156 1157 i2s@2901200 { 1158 status = "okay"; 1159 1160 ports { 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 1164 port@0 { 1165 reg = <0>; 1166 1167 i2s3_cif_ep: endpoint { 1168 remote-endpoint = <&xbar_i2s3_ep>; 1169 }; 1170 }; 1171 1172 i2s3_port: port@1 { 1173 reg = <1>; 1174 1175 i2s3_dap_ep: endpoint { 1176 dai-format = "i2s"; 1177 /* Placeholder for external Codec */ 1178 }; 1179 }; 1180 }; 1181 }; 1182 1183 i2s@2901300 { 1184 status = "okay"; 1185 1186 ports { 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 1190 port@0 { 1191 reg = <0>; 1192 1193 i2s4_cif_ep: endpoint { 1194 remote-endpoint = <&xbar_i2s4_ep>; 1195 }; 1196 }; 1197 1198 i2s4_port: port@1 { 1199 reg = <1>; 1200 1201 i2s4_dap_ep: endpoint { 1202 dai-format = "i2s"; 1203 /* Placeholder for external Codec */ 1204 }; 1205 }; 1206 }; 1207 }; 1208 1209 i2s@2901400 { 1210 status = "okay"; 1211 1212 ports { 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 1216 port@0 { 1217 reg = <0>; 1218 1219 i2s5_cif_ep: endpoint { 1220 remote-endpoint = <&xbar_i2s5_ep>; 1221 }; 1222 }; 1223 1224 i2s5_port: port@1 { 1225 reg = <1>; 1226 1227 i2s5_dap_ep: endpoint { 1228 dai-format = "i2s"; 1229 /* Placeholder for external Codec */ 1230 }; 1231 }; 1232 }; 1233 }; 1234 1235 i2s@2901500 { 1236 status = "okay"; 1237 1238 ports { 1239 #address-cells = <1>; 1240 #size-cells = <0>; 1241 1242 port@0 { 1243 reg = <0>; 1244 1245 i2s6_cif_ep: endpoint { 1246 remote-endpoint = <&xbar_i2s6_ep>; 1247 }; 1248 }; 1249 1250 i2s6_port: port@1 { 1251 reg = <1>; 1252 1253 i2s6_dap_ep: endpoint { 1254 dai-format = "i2s"; 1255 /* Placeholder for external Codec */ 1256 }; 1257 }; 1258 }; 1259 }; 1260 1261 dmic@2904000 { 1262 status = "okay"; 1263 1264 ports { 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 1268 port@0 { 1269 reg = <0>; 1270 1271 dmic1_cif_ep: endpoint { 1272 remote-endpoint = <&xbar_dmic1_ep>; 1273 }; 1274 }; 1275 1276 dmic1_port: port@1 { 1277 reg = <1>; 1278 1279 dmic1_dap_ep: endpoint { 1280 /* Place holder for external Codec */ 1281 }; 1282 }; 1283 }; 1284 }; 1285 1286 dmic@2904100 { 1287 status = "okay"; 1288 1289 ports { 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 1293 port@0 { 1294 reg = <0>; 1295 1296 dmic2_cif_ep: endpoint { 1297 remote-endpoint = <&xbar_dmic2_ep>; 1298 }; 1299 }; 1300 1301 dmic2_port: port@1 { 1302 reg = <1>; 1303 1304 dmic2_dap_ep: endpoint { 1305 /* Place holder for external Codec */ 1306 }; 1307 }; 1308 }; 1309 }; 1310 1311 dmic@2904200 { 1312 status = "okay"; 1313 1314 ports { 1315 #address-cells = <1>; 1316 #size-cells = <0>; 1317 1318 port@0 { 1319 reg = <0>; 1320 1321 dmic3_cif_ep: endpoint { 1322 remote-endpoint = <&xbar_dmic3_ep>; 1323 }; 1324 }; 1325 1326 dmic3_port: port@1 { 1327 reg = <1>; 1328 1329 dmic3_dap_ep: endpoint { 1330 /* Place holder for external Codec */ 1331 }; 1332 }; 1333 }; 1334 }; 1335 1336 dspk@2905000 { 1337 status = "okay"; 1338 1339 ports { 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 1343 port@0 { 1344 reg = <0>; 1345 1346 dspk1_cif_ep: endpoint { 1347 remote-endpoint = <&xbar_dspk1_ep>; 1348 }; 1349 }; 1350 1351 dspk1_port: port@1 { 1352 reg = <1>; 1353 1354 dspk1_dap_ep: endpoint { 1355 /* Place holder for external Codec */ 1356 }; 1357 }; 1358 }; 1359 }; 1360 1361 dspk@2905100 { 1362 status = "okay"; 1363 1364 ports { 1365 #address-cells = <1>; 1366 #size-cells = <0>; 1367 1368 port@0 { 1369 reg = <0>; 1370 1371 dspk2_cif_ep: endpoint { 1372 remote-endpoint = <&xbar_dspk2_ep>; 1373 }; 1374 }; 1375 1376 dspk2_port: port@1 { 1377 reg = <1>; 1378 1379 dspk2_dap_ep: endpoint { 1380 /* Place holder for external Codec */ 1381 }; 1382 }; 1383 }; 1384 }; 1385 1386 sfc@2902000 { 1387 status = "okay"; 1388 1389 ports { 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 1393 port@0 { 1394 reg = <0>; 1395 1396 sfc1_cif_in_ep: endpoint { 1397 remote-endpoint = <&xbar_sfc1_in_ep>; 1398 convert-rate = <44100>; 1399 }; 1400 }; 1401 1402 sfc1_out_port: port@1 { 1403 reg = <1>; 1404 1405 sfc1_cif_out_ep: endpoint { 1406 remote-endpoint = <&xbar_sfc1_out_ep>; 1407 convert-rate = <48000>; 1408 }; 1409 }; 1410 }; 1411 }; 1412 1413 sfc@2902200 { 1414 status = "okay"; 1415 1416 ports { 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 1420 port@0 { 1421 reg = <0>; 1422 1423 sfc2_cif_in_ep: endpoint { 1424 remote-endpoint = <&xbar_sfc2_in_ep>; 1425 }; 1426 }; 1427 1428 sfc2_out_port: port@1 { 1429 reg = <1>; 1430 1431 sfc2_cif_out_ep: endpoint { 1432 remote-endpoint = <&xbar_sfc2_out_ep>; 1433 }; 1434 }; 1435 }; 1436 }; 1437 1438 sfc@2902400 { 1439 status = "okay"; 1440 1441 ports { 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 1445 port@0 { 1446 reg = <0>; 1447 1448 sfc3_cif_in_ep: endpoint { 1449 remote-endpoint = <&xbar_sfc3_in_ep>; 1450 }; 1451 }; 1452 1453 sfc3_out_port: port@1 { 1454 reg = <1>; 1455 1456 sfc3_cif_out_ep: endpoint { 1457 remote-endpoint = <&xbar_sfc3_out_ep>; 1458 }; 1459 }; 1460 }; 1461 }; 1462 1463 sfc@2902600 { 1464 status = "okay"; 1465 1466 ports { 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 1470 port@0 { 1471 reg = <0>; 1472 1473 sfc4_cif_in_ep: endpoint { 1474 remote-endpoint = <&xbar_sfc4_in_ep>; 1475 }; 1476 }; 1477 1478 sfc4_out_port: port@1 { 1479 reg = <1>; 1480 1481 sfc4_cif_out_ep: endpoint { 1482 remote-endpoint = <&xbar_sfc4_out_ep>; 1483 }; 1484 }; 1485 }; 1486 }; 1487 1488 mvc@290a000 { 1489 status = "okay"; 1490 1491 ports { 1492 #address-cells = <1>; 1493 #size-cells = <0>; 1494 1495 port@0 { 1496 reg = <0>; 1497 1498 mvc1_cif_in_ep: endpoint { 1499 remote-endpoint = <&xbar_mvc1_in_ep>; 1500 }; 1501 }; 1502 1503 mvc1_out_port: port@1 { 1504 reg = <1>; 1505 1506 mvc1_cif_out_ep: endpoint { 1507 remote-endpoint = <&xbar_mvc1_out_ep>; 1508 }; 1509 }; 1510 }; 1511 }; 1512 1513 mvc@290a200 { 1514 status = "okay"; 1515 1516 ports { 1517 #address-cells = <1>; 1518 #size-cells = <0>; 1519 1520 port@0 { 1521 reg = <0>; 1522 1523 mvc2_cif_in_ep: endpoint { 1524 remote-endpoint = <&xbar_mvc2_in_ep>; 1525 }; 1526 }; 1527 1528 mvc2_out_port: port@1 { 1529 reg = <1>; 1530 1531 mvc2_cif_out_ep: endpoint { 1532 remote-endpoint = <&xbar_mvc2_out_ep>; 1533 }; 1534 }; 1535 }; 1536 }; 1537 1538 amx@2903000 { 1539 status = "okay"; 1540 1541 ports { 1542 #address-cells = <1>; 1543 #size-cells = <0>; 1544 1545 port@0 { 1546 reg = <0>; 1547 1548 amx1_in1_ep: endpoint { 1549 remote-endpoint = <&xbar_amx1_in1_ep>; 1550 }; 1551 }; 1552 1553 port@1 { 1554 reg = <1>; 1555 1556 amx1_in2_ep: endpoint { 1557 remote-endpoint = <&xbar_amx1_in2_ep>; 1558 }; 1559 }; 1560 1561 port@2 { 1562 reg = <2>; 1563 1564 amx1_in3_ep: endpoint { 1565 remote-endpoint = <&xbar_amx1_in3_ep>; 1566 }; 1567 }; 1568 1569 port@3 { 1570 reg = <3>; 1571 1572 amx1_in4_ep: endpoint { 1573 remote-endpoint = <&xbar_amx1_in4_ep>; 1574 }; 1575 }; 1576 1577 amx1_out_port: port@4 { 1578 reg = <4>; 1579 1580 amx1_out_ep: endpoint { 1581 remote-endpoint = <&xbar_amx1_out_ep>; 1582 }; 1583 }; 1584 }; 1585 }; 1586 1587 amx@2903100 { 1588 status = "okay"; 1589 1590 ports { 1591 #address-cells = <1>; 1592 #size-cells = <0>; 1593 1594 port@0 { 1595 reg = <0>; 1596 1597 amx2_in1_ep: endpoint { 1598 remote-endpoint = <&xbar_amx2_in1_ep>; 1599 }; 1600 }; 1601 1602 port@1 { 1603 reg = <1>; 1604 1605 amx2_in2_ep: endpoint { 1606 remote-endpoint = <&xbar_amx2_in2_ep>; 1607 }; 1608 }; 1609 1610 amx2_in3_port: port@2 { 1611 reg = <2>; 1612 1613 amx2_in3_ep: endpoint { 1614 remote-endpoint = <&xbar_amx2_in3_ep>; 1615 }; 1616 }; 1617 1618 amx2_in4_port: port@3 { 1619 reg = <3>; 1620 1621 amx2_in4_ep: endpoint { 1622 remote-endpoint = <&xbar_amx2_in4_ep>; 1623 }; 1624 }; 1625 1626 amx2_out_port: port@4 { 1627 reg = <4>; 1628 1629 amx2_out_ep: endpoint { 1630 remote-endpoint = <&xbar_amx2_out_ep>; 1631 }; 1632 }; 1633 }; 1634 }; 1635 1636 amx@2903200 { 1637 status = "okay"; 1638 1639 ports { 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 1643 port@0 { 1644 reg = <0>; 1645 1646 amx3_in1_ep: endpoint { 1647 remote-endpoint = <&xbar_amx3_in1_ep>; 1648 }; 1649 }; 1650 1651 port@1 { 1652 reg = <1>; 1653 1654 amx3_in2_ep: endpoint { 1655 remote-endpoint = <&xbar_amx3_in2_ep>; 1656 }; 1657 }; 1658 1659 port@2 { 1660 reg = <2>; 1661 1662 amx3_in3_ep: endpoint { 1663 remote-endpoint = <&xbar_amx3_in3_ep>; 1664 }; 1665 }; 1666 1667 port@3 { 1668 reg = <3>; 1669 1670 amx3_in4_ep: endpoint { 1671 remote-endpoint = <&xbar_amx3_in4_ep>; 1672 }; 1673 }; 1674 1675 amx3_out_port: port@4 { 1676 reg = <4>; 1677 1678 amx3_out_ep: endpoint { 1679 remote-endpoint = <&xbar_amx3_out_ep>; 1680 }; 1681 }; 1682 }; 1683 }; 1684 1685 amx@2903300 { 1686 status = "okay"; 1687 1688 ports { 1689 #address-cells = <1>; 1690 #size-cells = <0>; 1691 1692 port@0 { 1693 reg = <0>; 1694 1695 amx4_in1_ep: endpoint { 1696 remote-endpoint = <&xbar_amx4_in1_ep>; 1697 }; 1698 }; 1699 1700 port@1 { 1701 reg = <1>; 1702 1703 amx4_in2_ep: endpoint { 1704 remote-endpoint = <&xbar_amx4_in2_ep>; 1705 }; 1706 }; 1707 1708 port@2 { 1709 reg = <2>; 1710 1711 amx4_in3_ep: endpoint { 1712 remote-endpoint = <&xbar_amx4_in3_ep>; 1713 }; 1714 }; 1715 1716 port@3 { 1717 reg = <3>; 1718 1719 amx4_in4_ep: endpoint { 1720 remote-endpoint = <&xbar_amx4_in4_ep>; 1721 }; 1722 }; 1723 1724 amx4_out_port: port@4 { 1725 reg = <4>; 1726 1727 amx4_out_ep: endpoint { 1728 remote-endpoint = <&xbar_amx4_out_ep>; 1729 }; 1730 }; 1731 }; 1732 }; 1733 1734 adx@2903800 { 1735 status = "okay"; 1736 1737 ports { 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 1741 port@0 { 1742 reg = <0>; 1743 1744 adx1_in_ep: endpoint { 1745 remote-endpoint = <&xbar_adx1_in_ep>; 1746 }; 1747 }; 1748 1749 adx1_out1_port: port@1 { 1750 reg = <1>; 1751 1752 adx1_out1_ep: endpoint { 1753 remote-endpoint = <&xbar_adx1_out1_ep>; 1754 }; 1755 }; 1756 1757 adx1_out2_port: port@2 { 1758 reg = <2>; 1759 1760 adx1_out2_ep: endpoint { 1761 remote-endpoint = <&xbar_adx1_out2_ep>; 1762 }; 1763 }; 1764 1765 adx1_out3_port: port@3 { 1766 reg = <3>; 1767 1768 adx1_out3_ep: endpoint { 1769 remote-endpoint = <&xbar_adx1_out3_ep>; 1770 }; 1771 }; 1772 1773 adx1_out4_port: port@4 { 1774 reg = <4>; 1775 1776 adx1_out4_ep: endpoint { 1777 remote-endpoint = <&xbar_adx1_out4_ep>; 1778 }; 1779 }; 1780 }; 1781 }; 1782 1783 adx@2903900 { 1784 status = "okay"; 1785 1786 ports { 1787 #address-cells = <1>; 1788 #size-cells = <0>; 1789 1790 port@0 { 1791 reg = <0>; 1792 1793 adx2_in_ep: endpoint { 1794 remote-endpoint = <&xbar_adx2_in_ep>; 1795 }; 1796 }; 1797 1798 adx2_out1_port: port@1 { 1799 reg = <1>; 1800 1801 adx2_out1_ep: endpoint { 1802 remote-endpoint = <&xbar_adx2_out1_ep>; 1803 }; 1804 }; 1805 1806 adx2_out2_port: port@2 { 1807 reg = <2>; 1808 1809 adx2_out2_ep: endpoint { 1810 remote-endpoint = <&xbar_adx2_out2_ep>; 1811 }; 1812 }; 1813 1814 adx2_out3_port: port@3 { 1815 reg = <3>; 1816 1817 adx2_out3_ep: endpoint { 1818 remote-endpoint = <&xbar_adx2_out3_ep>; 1819 }; 1820 }; 1821 1822 adx2_out4_port: port@4 { 1823 reg = <4>; 1824 1825 adx2_out4_ep: endpoint { 1826 remote-endpoint = <&xbar_adx2_out4_ep>; 1827 }; 1828 }; 1829 }; 1830 }; 1831 1832 adx@2903a00 { 1833 status = "okay"; 1834 1835 ports { 1836 #address-cells = <1>; 1837 #size-cells = <0>; 1838 1839 port@0 { 1840 reg = <0>; 1841 1842 adx3_in_ep: endpoint { 1843 remote-endpoint = <&xbar_adx3_in_ep>; 1844 }; 1845 }; 1846 1847 adx3_out1_port: port@1 { 1848 reg = <1>; 1849 1850 adx3_out1_ep: endpoint { 1851 remote-endpoint = <&xbar_adx3_out1_ep>; 1852 }; 1853 }; 1854 1855 adx3_out2_port: port@2 { 1856 reg = <2>; 1857 1858 adx3_out2_ep: endpoint { 1859 remote-endpoint = <&xbar_adx3_out2_ep>; 1860 }; 1861 }; 1862 1863 adx3_out3_port: port@3 { 1864 reg = <3>; 1865 1866 adx3_out3_ep: endpoint { 1867 remote-endpoint = <&xbar_adx3_out3_ep>; 1868 }; 1869 }; 1870 1871 adx3_out4_port: port@4 { 1872 reg = <4>; 1873 1874 adx3_out4_ep: endpoint { 1875 remote-endpoint = <&xbar_adx3_out4_ep>; 1876 }; 1877 }; 1878 }; 1879 }; 1880 1881 adx@2903b00 { 1882 status = "okay"; 1883 1884 ports { 1885 #address-cells = <1>; 1886 #size-cells = <0>; 1887 1888 port@0 { 1889 reg = <0>; 1890 1891 adx4_in_ep: endpoint { 1892 remote-endpoint = <&xbar_adx4_in_ep>; 1893 }; 1894 }; 1895 1896 adx4_out1_port: port@1 { 1897 reg = <1>; 1898 1899 adx4_out1_ep: endpoint { 1900 remote-endpoint = <&xbar_adx4_out1_ep>; 1901 }; 1902 }; 1903 1904 adx4_out2_port: port@2 { 1905 reg = <2>; 1906 1907 adx4_out2_ep: endpoint { 1908 remote-endpoint = <&xbar_adx4_out2_ep>; 1909 }; 1910 }; 1911 1912 adx4_out3_port: port@3 { 1913 reg = <3>; 1914 1915 adx4_out3_ep: endpoint { 1916 remote-endpoint = <&xbar_adx4_out3_ep>; 1917 }; 1918 }; 1919 1920 adx4_out4_port: port@4 { 1921 reg = <4>; 1922 1923 adx4_out4_ep: endpoint { 1924 remote-endpoint = <&xbar_adx4_out4_ep>; 1925 }; 1926 }; 1927 }; 1928 }; 1929 1930 processing-engine@2908000 { 1931 status = "okay"; 1932 1933 ports { 1934 #address-cells = <1>; 1935 #size-cells = <0>; 1936 1937 port@0 { 1938 reg = <0x0>; 1939 1940 ope1_cif_in_ep: endpoint { 1941 remote-endpoint = <&xbar_ope1_in_ep>; 1942 }; 1943 }; 1944 1945 ope1_out_port: port@1 { 1946 reg = <0x1>; 1947 1948 ope1_cif_out_ep: endpoint { 1949 remote-endpoint = <&xbar_ope1_out_ep>; 1950 }; 1951 }; 1952 }; 1953 }; 1954 1955 amixer@290bb00 { 1956 status = "okay"; 1957 1958 ports { 1959 #address-cells = <1>; 1960 #size-cells = <0>; 1961 1962 port@0 { 1963 reg = <0x0>; 1964 1965 mixer_in1_ep: endpoint { 1966 remote-endpoint = <&xbar_mixer_in1_ep>; 1967 }; 1968 }; 1969 1970 port@1 { 1971 reg = <0x1>; 1972 1973 mixer_in2_ep: endpoint { 1974 remote-endpoint = <&xbar_mixer_in2_ep>; 1975 }; 1976 }; 1977 1978 port@2 { 1979 reg = <0x2>; 1980 1981 mixer_in3_ep: endpoint { 1982 remote-endpoint = <&xbar_mixer_in3_ep>; 1983 }; 1984 }; 1985 1986 port@3 { 1987 reg = <0x3>; 1988 1989 mixer_in4_ep: endpoint { 1990 remote-endpoint = <&xbar_mixer_in4_ep>; 1991 }; 1992 }; 1993 1994 port@4 { 1995 reg = <0x4>; 1996 1997 mixer_in5_ep: endpoint { 1998 remote-endpoint = <&xbar_mixer_in5_ep>; 1999 }; 2000 }; 2001 2002 port@5 { 2003 reg = <0x5>; 2004 2005 mixer_in6_ep: endpoint { 2006 remote-endpoint = <&xbar_mixer_in6_ep>; 2007 }; 2008 }; 2009 2010 port@6 { 2011 reg = <0x6>; 2012 2013 mixer_in7_ep: endpoint { 2014 remote-endpoint = <&xbar_mixer_in7_ep>; 2015 }; 2016 }; 2017 2018 port@7 { 2019 reg = <0x7>; 2020 2021 mixer_in8_ep: endpoint { 2022 remote-endpoint = <&xbar_mixer_in8_ep>; 2023 }; 2024 }; 2025 2026 port@8 { 2027 reg = <0x8>; 2028 2029 mixer_in9_ep: endpoint { 2030 remote-endpoint = <&xbar_mixer_in9_ep>; 2031 }; 2032 }; 2033 2034 port@9 { 2035 reg = <0x9>; 2036 2037 mixer_in10_ep: endpoint { 2038 remote-endpoint = <&xbar_mixer_in10_ep>; 2039 }; 2040 }; 2041 2042 mixer_out1_port: port@a { 2043 reg = <0xa>; 2044 2045 mixer_out1_ep: endpoint { 2046 remote-endpoint = <&xbar_mixer_out1_ep>; 2047 }; 2048 }; 2049 2050 mixer_out2_port: port@b { 2051 reg = <0xb>; 2052 2053 mixer_out2_ep: endpoint { 2054 remote-endpoint = <&xbar_mixer_out2_ep>; 2055 }; 2056 }; 2057 2058 mixer_out3_port: port@c { 2059 reg = <0xc>; 2060 2061 mixer_out3_ep: endpoint { 2062 remote-endpoint = <&xbar_mixer_out3_ep>; 2063 }; 2064 }; 2065 2066 mixer_out4_port: port@d { 2067 reg = <0xd>; 2068 2069 mixer_out4_ep: endpoint { 2070 remote-endpoint = <&xbar_mixer_out4_ep>; 2071 }; 2072 }; 2073 2074 mixer_out5_port: port@e { 2075 reg = <0xe>; 2076 2077 mixer_out5_ep: endpoint { 2078 remote-endpoint = <&xbar_mixer_out5_ep>; 2079 }; 2080 }; 2081 }; 2082 }; 2083 2084 asrc@2910000 { 2085 status = "okay"; 2086 2087 ports { 2088 #address-cells = <1>; 2089 #size-cells = <0>; 2090 2091 port@0 { 2092 reg = <0x0>; 2093 2094 asrc_in1_ep: endpoint { 2095 remote-endpoint = <&xbar_asrc_in1_ep>; 2096 }; 2097 }; 2098 2099 port@1 { 2100 reg = <0x1>; 2101 2102 asrc_in2_ep: endpoint { 2103 remote-endpoint = <&xbar_asrc_in2_ep>; 2104 }; 2105 }; 2106 2107 port@2 { 2108 reg = <0x2>; 2109 2110 asrc_in3_ep: endpoint { 2111 remote-endpoint = <&xbar_asrc_in3_ep>; 2112 }; 2113 }; 2114 2115 port@3 { 2116 reg = <0x3>; 2117 2118 asrc_in4_ep: endpoint { 2119 remote-endpoint = <&xbar_asrc_in4_ep>; 2120 }; 2121 }; 2122 2123 port@4 { 2124 reg = <0x4>; 2125 2126 asrc_in5_ep: endpoint { 2127 remote-endpoint = <&xbar_asrc_in5_ep>; 2128 }; 2129 }; 2130 2131 port@5 { 2132 reg = <0x5>; 2133 2134 asrc_in6_ep: endpoint { 2135 remote-endpoint = <&xbar_asrc_in6_ep>; 2136 }; 2137 }; 2138 2139 port@6 { 2140 reg = <0x6>; 2141 2142 asrc_in7_ep: endpoint { 2143 remote-endpoint = <&xbar_asrc_in7_ep>; 2144 }; 2145 }; 2146 2147 asrc_out1_port: port@7 { 2148 reg = <0x7>; 2149 2150 asrc_out1_ep: endpoint { 2151 remote-endpoint = <&xbar_asrc_out1_ep>; 2152 }; 2153 }; 2154 2155 asrc_out2_port: port@8 { 2156 reg = <0x8>; 2157 2158 asrc_out2_ep: endpoint { 2159 remote-endpoint = <&xbar_asrc_out2_ep>; 2160 }; 2161 }; 2162 2163 asrc_out3_port: port@9 { 2164 reg = <0x9>; 2165 2166 asrc_out3_ep: endpoint { 2167 remote-endpoint = <&xbar_asrc_out3_ep>; 2168 }; 2169 }; 2170 2171 asrc_out4_port: port@a { 2172 reg = <0xa>; 2173 2174 asrc_out4_ep: endpoint { 2175 remote-endpoint = <&xbar_asrc_out4_ep>; 2176 }; 2177 }; 2178 2179 asrc_out5_port: port@b { 2180 reg = <0xb>; 2181 2182 asrc_out5_ep: endpoint { 2183 remote-endpoint = <&xbar_asrc_out5_ep>; 2184 }; 2185 }; 2186 2187 asrc_out6_port: port@c { 2188 reg = <0xc>; 2189 2190 asrc_out6_ep: endpoint { 2191 remote-endpoint = <&xbar_asrc_out6_ep>; 2192 }; 2193 }; 2194 }; 2195 }; 2196 }; 2197 }; 2198 2199 i2c@3160000 { 2200 power-monitor@42 { 2201 compatible = "ti,ina3221"; 2202 reg = <0x42>; 2203 #address-cells = <1>; 2204 #size-cells = <0>; 2205 2206 input@0 { 2207 reg = <0x0>; 2208 label = "VDD_MUX"; 2209 shunt-resistor-micro-ohms = <20000>; 2210 }; 2211 2212 input@1 { 2213 reg = <0x1>; 2214 label = "VDD_5V0_IO_SYS"; 2215 shunt-resistor-micro-ohms = <5000>; 2216 }; 2217 2218 input@2 { 2219 reg = <0x2>; 2220 label = "VDD_3V3_SYS"; 2221 shunt-resistor-micro-ohms = <10000>; 2222 }; 2223 }; 2224 2225 power-monitor@43 { 2226 compatible = "ti,ina3221"; 2227 reg = <0x43>; 2228 #address-cells = <1>; 2229 #size-cells = <0>; 2230 2231 input@0 { 2232 reg = <0x0>; 2233 label = "VDD_3V3_IO_SLP"; 2234 shunt-resistor-micro-ohms = <10000>; 2235 }; 2236 2237 input@1 { 2238 reg = <0x1>; 2239 label = "VDD_1V8_IO"; 2240 shunt-resistor-micro-ohms = <10000>; 2241 }; 2242 2243 input@2 { 2244 reg = <0x2>; 2245 label = "VDD_M2_IN"; 2246 shunt-resistor-micro-ohms = <10000>; 2247 }; 2248 }; 2249 2250 exp1: gpio@74 { 2251 compatible = "ti,tca9539"; 2252 reg = <0x74>; 2253 2254 interrupt-parent = <&gpio>; 2255 interrupts = <TEGRA186_MAIN_GPIO(Y, 0) 2256 GPIO_ACTIVE_LOW>; 2257 2258 #gpio-cells = <2>; 2259 gpio-controller; 2260 2261 vcc-supply = <&vdd_3v3_sys>; 2262 }; 2263 2264 exp2: gpio@77 { 2265 compatible = "ti,tca9539"; 2266 reg = <0x77>; 2267 2268 interrupt-parent = <&gpio>; 2269 interrupts = <TEGRA186_MAIN_GPIO(Y, 6) 2270 GPIO_ACTIVE_LOW>; 2271 2272 #gpio-cells = <2>; 2273 gpio-controller; 2274 2275 vcc-supply = <&vdd_1v8>; 2276 }; 2277 }; 2278 2279 /* SDMMC1 (SD/MMC) */ 2280 mmc@3400000 { 2281 status = "okay"; 2282 2283 vmmc-supply = <&vdd_sd>; 2284 }; 2285 2286 hda@3510000 { 2287 nvidia,model = "NVIDIA Jetson TX2 HDA"; 2288 status = "okay"; 2289 }; 2290 2291 padctl@3520000 { 2292 status = "okay"; 2293 2294 avdd-pll-erefeut-supply = <&vdd_1v8_pll>; 2295 avdd-usb-supply = <&vdd_3v3_sys>; 2296 vclamp-usb-supply = <&vdd_1v8>; 2297 vddio-hsic-supply = <&gnd>; 2298 2299 pads { 2300 usb2 { 2301 status = "okay"; 2302 2303 lanes { 2304 micro_b: usb2-0 { 2305 nvidia,function = "xusb"; 2306 status = "okay"; 2307 }; 2308 2309 usb2-1 { 2310 nvidia,function = "xusb"; 2311 status = "okay"; 2312 }; 2313 2314 usb2-2 { 2315 nvidia,function = "xusb"; 2316 status = "okay"; 2317 }; 2318 }; 2319 }; 2320 2321 usb3 { 2322 status = "okay"; 2323 2324 lanes { 2325 usb3-0 { 2326 nvidia,function = "xusb"; 2327 status = "okay"; 2328 }; 2329 2330 usb3-1 { 2331 nvidia,function = "xusb"; 2332 status = "okay"; 2333 }; 2334 2335 usb3-2 { 2336 nvidia,function = "xusb"; 2337 status = "okay"; 2338 }; 2339 }; 2340 }; 2341 }; 2342 2343 ports { 2344 usb2-0 { 2345 status = "okay"; 2346 mode = "otg"; 2347 vbus-supply = <&vdd_usb0>; 2348 usb-role-switch; 2349 2350 connector { 2351 compatible = "gpio-usb-b-connector", 2352 "usb-b-connector"; 2353 label = "micro-USB"; 2354 type = "micro"; 2355 vbus-gpios = <&gpio 2356 TEGRA186_MAIN_GPIO(X, 7) 2357 GPIO_ACTIVE_LOW>; 2358 id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>; 2359 }; 2360 }; 2361 2362 usb2-1 { 2363 status = "okay"; 2364 mode = "host"; 2365 2366 vbus-supply = <&vdd_usb1>; 2367 }; 2368 2369 usb3-0 { 2370 nvidia,usb2-companion = <1>; 2371 vbus-supply = <&vdd_usb1>; 2372 status = "okay"; 2373 }; 2374 }; 2375 }; 2376 2377 usb@3530000 { 2378 status = "okay"; 2379 2380 phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>, 2381 <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>, 2382 <&{/padctl@3520000/pads/usb3/lanes/usb3-0}>; 2383 phy-names = "usb2-0", "usb2-1", "usb3-0"; 2384 }; 2385 2386 usb@3550000 { 2387 status = "okay"; 2388 2389 phys = <µ_b>; 2390 phy-names = "usb2-0"; 2391 }; 2392 2393 i2c@c250000 { 2394 /* carrier board ID EEPROM */ 2395 eeprom@57 { 2396 compatible = "atmel,24c02"; 2397 reg = <0x57>; 2398 2399 label = "system"; 2400 vcc-supply = <&vdd_1v8>; 2401 address-width = <8>; 2402 pagesize = <8>; 2403 size = <256>; 2404 read-only; 2405 }; 2406 }; 2407 2408 pcie@10003000 { 2409 status = "okay"; 2410 2411 dvdd-pex-supply = <&vdd_pex>; 2412 hvdd-pex-pll-supply = <&vdd_1v8>; 2413 hvdd-pex-supply = <&vdd_1v8>; 2414 vddio-pexctl-aud-supply = <&vdd_1v8>; 2415 2416 pci@1,0 { 2417 nvidia,num-lanes = <4>; 2418 status = "okay"; 2419 }; 2420 2421 pci@2,0 { 2422 nvidia,num-lanes = <0>; 2423 status = "disabled"; 2424 }; 2425 2426 pci@3,0 { 2427 nvidia,num-lanes = <1>; 2428 status = "disabled"; 2429 }; 2430 }; 2431 2432 host1x@13e00000 { 2433 status = "okay"; 2434 2435 dpaux@15040000 { 2436 status = "okay"; 2437 }; 2438 2439 display-hub@15200000 { 2440 status = "okay"; 2441 }; 2442 2443 dsi@15300000 { 2444 status = "disabled"; 2445 }; 2446 2447 /* DP on E3320 */ 2448 sor@15540000 { 2449 status = "okay"; 2450 2451 avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; 2452 vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>; 2453 2454 nvidia,dpaux = <&dpaux>; 2455 }; 2456 2457 sor@15580000 { 2458 status = "okay"; 2459 2460 avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; 2461 vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>; 2462 hdmi-supply = <&vdd_hdmi>; 2463 2464 nvidia,ddc-i2c-bus = <&ddc>; 2465 nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1) 2466 GPIO_ACTIVE_LOW>; 2467 }; 2468 2469 dpaux@155c0000 { 2470 status = "okay"; 2471 }; 2472 }; 2473 2474 sata@3507000 { 2475 status = "okay"; 2476 }; 2477 2478 gpio-keys { 2479 compatible = "gpio-keys"; 2480 2481 key-power { 2482 label = "Power"; 2483 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0) 2484 GPIO_ACTIVE_LOW>; 2485 linux,input-type = <EV_KEY>; 2486 linux,code = <KEY_POWER>; 2487 debounce-interval = <10>; 2488 wakeup-event-action = <EV_ACT_ASSERTED>; 2489 wakeup-source; 2490 }; 2491 2492 key-volume-up { 2493 label = "Volume Up"; 2494 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) 2495 GPIO_ACTIVE_LOW>; 2496 linux,input-type = <EV_KEY>; 2497 linux,code = <KEY_VOLUMEUP>; 2498 debounce-interval = <10>; 2499 }; 2500 2501 key-volume-down { 2502 label = "Volume Down"; 2503 gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) 2504 GPIO_ACTIVE_LOW>; 2505 linux,input-type = <EV_KEY>; 2506 linux,code = <KEY_VOLUMEDOWN>; 2507 debounce-interval = <10>; 2508 }; 2509 }; 2510 2511 vdd_sd: regulator-vdd-sd { 2512 compatible = "regulator-fixed"; 2513 regulator-name = "SD_CARD_SW_PWR"; 2514 regulator-min-microvolt = <3300000>; 2515 regulator-max-microvolt = <3300000>; 2516 2517 gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>; 2518 enable-active-high; 2519 2520 vin-supply = <&vdd_3v3_sys>; 2521 }; 2522 2523 vdd_hdmi: regulator-vdd-hdmi { 2524 compatible = "regulator-fixed"; 2525 regulator-name = "VDD_HDMI_5V0"; 2526 regulator-min-microvolt = <5000000>; 2527 regulator-max-microvolt = <5000000>; 2528 2529 gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; 2530 enable-active-high; 2531 2532 vin-supply = <&vdd_5v0_sys>; 2533 }; 2534 2535 vdd_usb0: regulator-vdd-usb0 { 2536 compatible = "regulator-fixed"; 2537 regulator-name = "VDD_USB0"; 2538 regulator-min-microvolt = <5000000>; 2539 regulator-max-microvolt = <5000000>; 2540 2541 gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>; 2542 enable-active-high; 2543 2544 vin-supply = <&vdd_5v0_sys>; 2545 }; 2546 2547 vdd_usb1: regulator-vdd-usb1 { 2548 compatible = "regulator-fixed"; 2549 regulator-name = "VDD_USB1"; 2550 regulator-min-microvolt = <5000000>; 2551 regulator-max-microvolt = <5000000>; 2552 2553 gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>; 2554 enable-active-high; 2555 2556 vin-supply = <&vdd_5v0_sys>; 2557 }; 2558 2559 sound { 2560 compatible = "nvidia,tegra186-audio-graph-card"; 2561 status = "okay"; 2562 2563 dais = /* FE */ 2564 <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, 2565 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, 2566 <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, 2567 <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, 2568 <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, 2569 /* Router */ 2570 <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>, 2571 <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_i2s6_port>, 2572 <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic3_port>, 2573 <&xbar_dspk1_port>, <&xbar_dspk2_port>, 2574 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, 2575 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, 2576 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, 2577 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, 2578 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, 2579 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, 2580 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, 2581 <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>, 2582 <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>, 2583 <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>, 2584 <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>, 2585 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, 2586 <&xbar_adx3_in_port>, <&xbar_adx4_in_port>, 2587 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>, 2588 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>, 2589 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, 2590 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, 2591 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, 2592 <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>, 2593 <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, 2594 <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, 2595 <&xbar_asrc_in7_port>, 2596 <&xbar_ope1_in_port>, 2597 /* HW accelerators */ 2598 <&sfc1_out_port>, <&sfc2_out_port>, 2599 <&sfc3_out_port>, <&sfc4_out_port>, 2600 <&mvc1_out_port>, <&mvc2_out_port>, 2601 <&amx1_out_port>, <&amx2_out_port>, 2602 <&amx3_out_port>, <&amx4_out_port>, 2603 <&adx1_out1_port>, <&adx1_out2_port>, 2604 <&adx1_out3_port>, <&adx1_out4_port>, 2605 <&adx2_out1_port>, <&adx2_out2_port>, 2606 <&adx2_out3_port>, <&adx2_out4_port>, 2607 <&adx3_out1_port>, <&adx3_out2_port>, 2608 <&adx3_out3_port>, <&adx3_out4_port>, 2609 <&adx4_out1_port>, <&adx4_out2_port>, 2610 <&adx4_out3_port>, <&adx4_out4_port>, 2611 <&mixer_out1_port>, <&mixer_out2_port>, 2612 <&mixer_out3_port>, <&mixer_out4_port>, 2613 <&mixer_out5_port>, 2614 <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, 2615 <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, 2616 <&ope1_out_port>, 2617 /* I/O */ 2618 <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>, 2619 <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>, 2620 <&dmic3_port>, <&dspk1_port>, <&dspk2_port>; 2621 2622 label = "NVIDIA Jetson TX2 APE"; 2623 }; 2624}; 2625