1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra124-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra124-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9#include <dt-bindings/soc/tegra-pmc.h> 10 11#include "tegra132-peripherals-opp.dtsi" 12 13/ { 14 compatible = "nvidia,tegra132", "nvidia,tegra124"; 15 interrupt-parent = <&lic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 pcie@1003000 { 20 compatible = "nvidia,tegra124-pcie"; 21 device_type = "pci"; 22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 25 reg-names = "pads", "afi", "cs"; 26 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 27 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 28 interrupt-names = "intr", "msi"; 29 30 #interrupt-cells = <1>; 31 interrupt-map-mask = <0 0 0 0>; 32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 33 34 bus-range = <0x00 0xff>; 35 #address-cells = <3>; 36 #size-cells = <2>; 37 38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 42 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 43 44 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 45 <&tegra_car TEGRA124_CLK_AFI>, 46 <&tegra_car TEGRA124_CLK_PLL_E>, 47 <&tegra_car TEGRA124_CLK_CML0>; 48 clock-names = "pex", "afi", "pll_e", "cml"; 49 resets = <&tegra_car 70>, 50 <&tegra_car 72>, 51 <&tegra_car 74>; 52 reset-names = "pex", "afi", "pcie_x"; 53 status = "disabled"; 54 55 pci@1,0 { 56 device_type = "pci"; 57 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 58 reg = <0x000800 0 0 0 0>; 59 bus-range = <0x00 0xff>; 60 status = "disabled"; 61 62 #address-cells = <3>; 63 #size-cells = <2>; 64 ranges; 65 66 nvidia,num-lanes = <2>; 67 }; 68 69 pci@2,0 { 70 device_type = "pci"; 71 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 72 reg = <0x001000 0 0 0 0>; 73 bus-range = <0x00 0xff>; 74 status = "disabled"; 75 76 #address-cells = <3>; 77 #size-cells = <2>; 78 ranges; 79 80 nvidia,num-lanes = <1>; 81 }; 82 }; 83 84 host1x@50000000 { 85 compatible = "nvidia,tegra132-host1x", 86 "nvidia,tegra124-host1x"; 87 reg = <0x0 0x50000000 0x0 0x00034000>; 88 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 89 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 90 interrupt-names = "syncpt", "host1x"; 91 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 92 clock-names = "host1x"; 93 resets = <&tegra_car 28>; 94 reset-names = "host1x"; 95 96 #address-cells = <2>; 97 #size-cells = <2>; 98 99 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 100 101 dc@54200000 { 102 compatible = "nvidia,tegra124-dc"; 103 reg = <0x0 0x54200000 0x0 0x00040000>; 104 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 105 clocks = <&tegra_car TEGRA124_CLK_DISP1>; 106 clock-names = "dc"; 107 resets = <&tegra_car 27>; 108 reset-names = "dc"; 109 110 iommus = <&mc TEGRA_SWGROUP_DC>; 111 112 nvidia,head = <0>; 113 }; 114 115 dc@54240000 { 116 compatible = "nvidia,tegra124-dc"; 117 reg = <0x0 0x54240000 0x0 0x00040000>; 118 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&tegra_car TEGRA124_CLK_DISP2>; 120 clock-names = "dc"; 121 resets = <&tegra_car 26>; 122 reset-names = "dc"; 123 124 iommus = <&mc TEGRA_SWGROUP_DCB>; 125 126 nvidia,head = <1>; 127 }; 128 129 hdmi@54280000 { 130 compatible = "nvidia,tegra124-hdmi"; 131 reg = <0x0 0x54280000 0x0 0x00040000>; 132 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 133 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 134 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 135 clock-names = "hdmi", "parent"; 136 resets = <&tegra_car 51>; 137 reset-names = "hdmi"; 138 status = "disabled"; 139 }; 140 141 sor@54540000 { 142 compatible = "nvidia,tegra124-sor"; 143 reg = <0x0 0x54540000 0x0 0x00040000>; 144 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 146 <&tegra_car TEGRA124_CLK_SOR0_OUT>, 147 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 148 <&tegra_car TEGRA124_CLK_PLL_DP>, 149 <&tegra_car TEGRA124_CLK_CLK_M>; 150 clock-names = "sor", "out", "parent", "dp", "safe"; 151 resets = <&tegra_car 182>; 152 reset-names = "sor"; 153 status = "disabled"; 154 }; 155 156 dpaux: dpaux@545c0000 { 157 compatible = "nvidia,tegra124-dpaux"; 158 reg = <0x0 0x545c0000 0x0 0x00040000>; 159 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 161 <&tegra_car TEGRA124_CLK_PLL_DP>; 162 clock-names = "dpaux", "parent"; 163 resets = <&tegra_car 181>; 164 reset-names = "dpaux"; 165 status = "disabled"; 166 167 i2c-bus { 168 #address-cells = <1>; 169 #size-cells = <0>; 170 }; 171 }; 172 }; 173 174 gic: interrupt-controller@50041000 { 175 compatible = "arm,cortex-a15-gic"; 176 #interrupt-cells = <3>; 177 interrupt-controller; 178 reg = <0x0 0x50041000 0x0 0x1000>, 179 <0x0 0x50042000 0x0 0x2000>, 180 <0x0 0x50044000 0x0 0x2000>, 181 <0x0 0x50046000 0x0 0x2000>; 182 interrupts = <GIC_PPI 9 183 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 184 interrupt-parent = <&gic>; 185 }; 186 187 gpu@57000000 { 188 compatible = "nvidia,gk20a"; 189 reg = <0x0 0x57000000 0x0 0x01000000>, 190 <0x0 0x58000000 0x0 0x01000000>; 191 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 193 interrupt-names = "stall", "nonstall"; 194 clocks = <&tegra_car TEGRA124_CLK_GPU>, 195 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 196 clock-names = "gpu", "pwr"; 197 resets = <&tegra_car 184>; 198 reset-names = "gpu"; 199 status = "disabled"; 200 }; 201 202 lic: interrupt-controller@60004000 { 203 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 204 reg = <0x0 0x60004000 0x0 0x100>, 205 <0x0 0x60004100 0x0 0x100>, 206 <0x0 0x60004200 0x0 0x100>, 207 <0x0 0x60004300 0x0 0x100>, 208 <0x0 0x60004400 0x0 0x100>; 209 interrupt-controller; 210 #interrupt-cells = <3>; 211 interrupt-parent = <&gic>; 212 }; 213 214 timer@60005000 { 215 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer"; 216 reg = <0x0 0x60005000 0x0 0x400>; 217 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 224 clock-names = "timer"; 225 }; 226 227 tegra_car: clock@60006000 { 228 compatible = "nvidia,tegra132-car"; 229 reg = <0x0 0x60006000 0x0 0x1000>; 230 #clock-cells = <1>; 231 #reset-cells = <1>; 232 nvidia,external-memory-controller = <&emc>; 233 }; 234 235 flow-controller@60007000 { 236 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; 237 reg = <0x0 0x60007000 0x0 0x1000>; 238 }; 239 240 actmon@6000c800 { 241 compatible = "nvidia,tegra124-actmon"; 242 reg = <0x0 0x6000c800 0x0 0x400>; 243 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 245 <&tegra_car TEGRA124_CLK_EMC>; 246 clock-names = "actmon", "emc"; 247 resets = <&tegra_car 119>; 248 reset-names = "actmon"; 249 operating-points-v2 = <&emc_bw_dfs_opp_table>; 250 interconnects = <&mc TEGRA124_MC_MPCORER &emc>; 251 interconnect-names = "cpu-read"; 252 #cooling-cells = <2>; 253 }; 254 255 gpio: gpio@6000d000 { 256 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 257 reg = <0x0 0x6000d000 0x0 0x1000>; 258 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 266 #gpio-cells = <2>; 267 gpio-controller; 268 #interrupt-cells = <2>; 269 interrupt-controller; 270 }; 271 272 apbdma: dma@60020000 { 273 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 274 reg = <0x0 0x60020000 0x0 0x1400>; 275 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 308 clock-names = "dma"; 309 resets = <&tegra_car 34>; 310 reset-names = "dma"; 311 #dma-cells = <1>; 312 }; 313 314 apbmisc@70000800 { 315 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 316 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 317 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 318 }; 319 320 pinmux: pinmux@70000868 { 321 compatible = "nvidia,tegra124-pinmux"; 322 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 323 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 324 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 325 }; 326 327 /* 328 * There are two serial driver i.e. 8250 based simple serial 329 * driver and APB DMA based serial driver for higher baudrate 330 * and performance. To enable the 8250 based driver, the compatible 331 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 332 * the APB DMA based serial driver, the compatible is 333 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 334 */ 335 uarta: serial@70006000 { 336 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 337 reg = <0x0 0x70006000 0x0 0x40>; 338 reg-shift = <2>; 339 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 341 clock-names = "serial"; 342 resets = <&tegra_car 6>; 343 reset-names = "serial"; 344 dmas = <&apbdma 8>, <&apbdma 8>; 345 dma-names = "rx", "tx"; 346 status = "disabled"; 347 }; 348 349 uartb: serial@70006040 { 350 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 351 reg = <0x0 0x70006040 0x0 0x40>; 352 reg-shift = <2>; 353 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 355 clock-names = "serial"; 356 resets = <&tegra_car 7>; 357 reset-names = "serial"; 358 dmas = <&apbdma 9>, <&apbdma 9>; 359 dma-names = "rx", "tx"; 360 status = "disabled"; 361 }; 362 363 uartc: serial@70006200 { 364 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 365 reg = <0x0 0x70006200 0x0 0x40>; 366 reg-shift = <2>; 367 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 369 clock-names = "serial"; 370 resets = <&tegra_car 55>; 371 reset-names = "serial"; 372 dmas = <&apbdma 10>, <&apbdma 10>; 373 dma-names = "rx", "tx"; 374 status = "disabled"; 375 }; 376 377 uartd: serial@70006300 { 378 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 379 reg = <0x0 0x70006300 0x0 0x40>; 380 reg-shift = <2>; 381 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 383 clock-names = "serial"; 384 resets = <&tegra_car 65>; 385 reset-names = "serial"; 386 dmas = <&apbdma 19>, <&apbdma 19>; 387 dma-names = "rx", "tx"; 388 status = "disabled"; 389 }; 390 391 pwm: pwm@7000a000 { 392 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 393 reg = <0x0 0x7000a000 0x0 0x100>; 394 #pwm-cells = <2>; 395 clocks = <&tegra_car TEGRA124_CLK_PWM>; 396 resets = <&tegra_car 17>; 397 reset-names = "pwm"; 398 status = "disabled"; 399 }; 400 401 i2c@7000c000 { 402 compatible = "nvidia,tegra124-i2c"; 403 reg = <0x0 0x7000c000 0x0 0x100>; 404 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 408 clock-names = "div-clk"; 409 resets = <&tegra_car 12>; 410 reset-names = "i2c"; 411 dmas = <&apbdma 21>, <&apbdma 21>; 412 dma-names = "rx", "tx"; 413 status = "disabled"; 414 }; 415 416 i2c@7000c400 { 417 compatible = "nvidia,tegra124-i2c"; 418 reg = <0x0 0x7000c400 0x0 0x100>; 419 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 423 clock-names = "div-clk"; 424 resets = <&tegra_car 54>; 425 reset-names = "i2c"; 426 dmas = <&apbdma 22>, <&apbdma 22>; 427 dma-names = "rx", "tx"; 428 status = "disabled"; 429 }; 430 431 i2c@7000c500 { 432 compatible = "nvidia,tegra124-i2c"; 433 reg = <0x0 0x7000c500 0x0 0x100>; 434 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 438 clock-names = "div-clk"; 439 resets = <&tegra_car 67>; 440 reset-names = "i2c"; 441 dmas = <&apbdma 23>, <&apbdma 23>; 442 dma-names = "rx", "tx"; 443 status = "disabled"; 444 }; 445 446 i2c@7000c700 { 447 compatible = "nvidia,tegra124-i2c"; 448 reg = <0x0 0x7000c700 0x0 0x100>; 449 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 453 clock-names = "div-clk"; 454 resets = <&tegra_car 103>; 455 reset-names = "i2c"; 456 dmas = <&apbdma 26>, <&apbdma 26>; 457 dma-names = "rx", "tx"; 458 status = "disabled"; 459 }; 460 461 i2c@7000d000 { 462 compatible = "nvidia,tegra124-i2c"; 463 reg = <0x0 0x7000d000 0x0 0x100>; 464 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 468 clock-names = "div-clk"; 469 resets = <&tegra_car 47>; 470 reset-names = "i2c"; 471 dmas = <&apbdma 24>, <&apbdma 24>; 472 dma-names = "rx", "tx"; 473 status = "disabled"; 474 }; 475 476 i2c@7000d100 { 477 compatible = "nvidia,tegra124-i2c"; 478 reg = <0x0 0x7000d100 0x0 0x100>; 479 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 483 clock-names = "div-clk"; 484 resets = <&tegra_car 166>; 485 reset-names = "i2c"; 486 dmas = <&apbdma 30>, <&apbdma 30>; 487 dma-names = "rx", "tx"; 488 status = "disabled"; 489 }; 490 491 spi@7000d400 { 492 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 493 reg = <0x0 0x7000d400 0x0 0x200>; 494 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 498 clock-names = "spi"; 499 resets = <&tegra_car 41>; 500 reset-names = "spi"; 501 dmas = <&apbdma 15>, <&apbdma 15>; 502 dma-names = "rx", "tx"; 503 status = "disabled"; 504 }; 505 506 spi@7000d600 { 507 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 508 reg = <0x0 0x7000d600 0x0 0x200>; 509 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 513 clock-names = "spi"; 514 resets = <&tegra_car 44>; 515 reset-names = "spi"; 516 dmas = <&apbdma 16>, <&apbdma 16>; 517 dma-names = "rx", "tx"; 518 status = "disabled"; 519 }; 520 521 spi@7000d800 { 522 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 523 reg = <0x0 0x7000d800 0x0 0x200>; 524 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 528 clock-names = "spi"; 529 resets = <&tegra_car 46>; 530 reset-names = "spi"; 531 dmas = <&apbdma 17>, <&apbdma 17>; 532 dma-names = "rx", "tx"; 533 status = "disabled"; 534 }; 535 536 spi@7000da00 { 537 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 538 reg = <0x0 0x7000da00 0x0 0x200>; 539 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 543 clock-names = "spi"; 544 resets = <&tegra_car 68>; 545 reset-names = "spi"; 546 dmas = <&apbdma 18>, <&apbdma 18>; 547 dma-names = "rx", "tx"; 548 status = "disabled"; 549 }; 550 551 spi@7000dc00 { 552 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 553 reg = <0x0 0x7000dc00 0x0 0x200>; 554 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 558 clock-names = "spi"; 559 resets = <&tegra_car 104>; 560 reset-names = "spi"; 561 dmas = <&apbdma 27>, <&apbdma 27>; 562 dma-names = "rx", "tx"; 563 status = "disabled"; 564 }; 565 566 spi@7000de00 { 567 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 568 reg = <0x0 0x7000de00 0x0 0x200>; 569 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 573 clock-names = "spi"; 574 resets = <&tegra_car 105>; 575 reset-names = "spi"; 576 dmas = <&apbdma 28>, <&apbdma 28>; 577 dma-names = "rx", "tx"; 578 status = "disabled"; 579 }; 580 581 rtc@7000e000 { 582 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 583 reg = <0x0 0x7000e000 0x0 0x100>; 584 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&tegra_car TEGRA124_CLK_RTC>; 586 clock-names = "rtc"; 587 }; 588 589 tegra_pmc: pmc@7000e400 { 590 compatible = "nvidia,tegra124-pmc"; 591 reg = <0x0 0x7000e400 0x0 0x400>; 592 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 593 clock-names = "pclk", "clk32k_in"; 594 #clock-cells = <1>; 595 }; 596 597 fuse@7000f800 { 598 compatible = "nvidia,tegra124-efuse"; 599 reg = <0x0 0x7000f800 0x0 0x400>; 600 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 601 clock-names = "fuse"; 602 resets = <&tegra_car 39>; 603 reset-names = "fuse"; 604 }; 605 606 mc: memory-controller@70019000 { 607 compatible = "nvidia,tegra132-mc"; 608 reg = <0x0 0x70019000 0x0 0x1000>; 609 clocks = <&tegra_car TEGRA124_CLK_MC>; 610 clock-names = "mc"; 611 612 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 613 614 #iommu-cells = <1>; 615 #reset-cells = <1>; 616 #interconnect-cells = <1>; 617 }; 618 619 emc: external-memory-controller@7001b000 { 620 compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; 621 reg = <0x0 0x7001b000 0x0 0x1000>; 622 clocks = <&tegra_car TEGRA124_CLK_EMC>; 623 clock-names = "emc"; 624 625 nvidia,memory-controller = <&mc>; 626 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 627 628 #interconnect-cells = <0>; 629 }; 630 631 sata@70020000 { 632 compatible = "nvidia,tegra124-ahci"; 633 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 634 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 635 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&tegra_car TEGRA124_CLK_SATA>, 637 <&tegra_car TEGRA124_CLK_SATA_OOB>; 638 clock-names = "sata", "sata-oob"; 639 resets = <&tegra_car 124>, 640 <&tegra_car 129>, 641 <&tegra_car 123>; 642 reset-names = "sata", "sata-cold", "sata-oob"; 643 status = "disabled"; 644 }; 645 646 hda@70030000 { 647 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", 648 "nvidia,tegra30-hda"; 649 reg = <0x0 0x70030000 0x0 0x10000>; 650 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&tegra_car TEGRA124_CLK_HDA>, 652 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 653 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 654 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 655 resets = <&tegra_car 125>, /* hda */ 656 <&tegra_car 128>, /* hda2hdmi */ 657 <&tegra_car 111>; /* hda2codec_2x */ 658 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 659 status = "disabled"; 660 }; 661 662 usb@70090000 { 663 compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"; 664 reg = <0x0 0x70090000 0x0 0x8000>, 665 <0x0 0x70098000 0x0 0x1000>, 666 <0x0 0x70099000 0x0 0x1000>; 667 reg-names = "hcd", "fpci", "ipfs"; 668 669 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 671 672 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, 673 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, 674 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, 675 <&tegra_car TEGRA124_CLK_XUSB_SS>, 676 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, 677 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, 678 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, 679 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, 680 <&tegra_car TEGRA124_CLK_PLL_U_480M>, 681 <&tegra_car TEGRA124_CLK_CLK_M>, 682 <&tegra_car TEGRA124_CLK_PLL_E>; 683 clock-names = "xusb_host", "xusb_host_src", 684 "xusb_falcon_src", "xusb_ss", 685 "xusb_ss_div2", "xusb_ss_src", 686 "xusb_hs_src", "xusb_fs_src", 687 "pll_u_480m", "clk_m", "pll_e"; 688 resets = <&tegra_car 89>, <&tegra_car 156>, 689 <&tegra_car 143>; 690 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 691 692 nvidia,xusb-padctl = <&padctl>; 693 694 status = "disabled"; 695 }; 696 697 padctl: padctl@7009f000 { 698 compatible = "nvidia,tegra132-xusb-padctl", 699 "nvidia,tegra124-xusb-padctl"; 700 reg = <0x0 0x7009f000 0x0 0x1000>; 701 resets = <&tegra_car 142>; 702 reset-names = "padctl"; 703 704 pads { 705 usb2 { 706 status = "disabled"; 707 708 lanes { 709 usb2-0 { 710 status = "disabled"; 711 #phy-cells = <0>; 712 }; 713 714 usb2-1 { 715 status = "disabled"; 716 #phy-cells = <0>; 717 }; 718 719 usb2-2 { 720 status = "disabled"; 721 #phy-cells = <0>; 722 }; 723 }; 724 }; 725 726 ulpi { 727 status = "disabled"; 728 729 lanes { 730 ulpi-0 { 731 status = "disabled"; 732 #phy-cells = <0>; 733 }; 734 }; 735 }; 736 737 hsic { 738 status = "disabled"; 739 740 lanes { 741 hsic-0 { 742 status = "disabled"; 743 #phy-cells = <0>; 744 }; 745 746 hsic-1 { 747 status = "disabled"; 748 #phy-cells = <0>; 749 }; 750 }; 751 }; 752 753 pcie { 754 status = "disabled"; 755 756 lanes { 757 pcie-0 { 758 status = "disabled"; 759 #phy-cells = <0>; 760 }; 761 762 pcie-1 { 763 status = "disabled"; 764 #phy-cells = <0>; 765 }; 766 767 pcie-2 { 768 status = "disabled"; 769 #phy-cells = <0>; 770 }; 771 772 pcie-3 { 773 status = "disabled"; 774 #phy-cells = <0>; 775 }; 776 777 pcie-4 { 778 status = "disabled"; 779 #phy-cells = <0>; 780 }; 781 }; 782 }; 783 784 sata { 785 status = "disabled"; 786 787 lanes { 788 sata-0 { 789 status = "disabled"; 790 #phy-cells = <0>; 791 }; 792 }; 793 }; 794 }; 795 796 ports { 797 usb2-0 { 798 status = "disabled"; 799 }; 800 801 usb2-1 { 802 status = "disabled"; 803 }; 804 805 usb2-2 { 806 status = "disabled"; 807 }; 808 809 hsic-0 { 810 status = "disabled"; 811 }; 812 813 hsic-1 { 814 status = "disabled"; 815 }; 816 817 usb3-0 { 818 status = "disabled"; 819 }; 820 821 usb3-1 { 822 status = "disabled"; 823 }; 824 }; 825 }; 826 827 mmc@700b0000 { 828 compatible = "nvidia,tegra124-sdhci"; 829 reg = <0x0 0x700b0000 0x0 0x200>; 830 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 832 clock-names = "sdhci"; 833 resets = <&tegra_car 14>; 834 reset-names = "sdhci"; 835 status = "disabled"; 836 }; 837 838 mmc@700b0200 { 839 compatible = "nvidia,tegra124-sdhci"; 840 reg = <0x0 0x700b0200 0x0 0x200>; 841 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 843 clock-names = "sdhci"; 844 resets = <&tegra_car 9>; 845 reset-names = "sdhci"; 846 status = "disabled"; 847 }; 848 849 mmc@700b0400 { 850 compatible = "nvidia,tegra124-sdhci"; 851 reg = <0x0 0x700b0400 0x0 0x200>; 852 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 854 clock-names = "sdhci"; 855 resets = <&tegra_car 69>; 856 reset-names = "sdhci"; 857 status = "disabled"; 858 }; 859 860 mmc@700b0600 { 861 compatible = "nvidia,tegra124-sdhci"; 862 reg = <0x0 0x700b0600 0x0 0x200>; 863 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 865 clock-names = "sdhci"; 866 resets = <&tegra_car 15>; 867 reset-names = "sdhci"; 868 status = "disabled"; 869 }; 870 871 soctherm: thermal-sensor@700e2000 { 872 compatible = "nvidia,tegra132-soctherm"; 873 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */ 874 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ 875 reg-names = "soctherm-reg", "ccroc-reg"; 876 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 878 interrupt-names = "thermal", "edp"; 879 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 880 <&tegra_car TEGRA124_CLK_SOC_THERM>; 881 clock-names = "tsensor", "soctherm"; 882 resets = <&tegra_car 78>; 883 reset-names = "soctherm"; 884 #thermal-sensor-cells = <1>; 885 886 throttle-cfgs { 887 throttle_heavy: heavy { 888 nvidia,priority = <100>; 889 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 890 891 #cooling-cells = <2>; 892 }; 893 }; 894 }; 895 896 ahub@70300000 { 897 compatible = "nvidia,tegra124-ahub"; 898 reg = <0x0 0x70300000 0x0 0x200>, 899 <0x0 0x70300800 0x0 0x800>, 900 <0x0 0x70300200 0x0 0x600>; 901 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 903 <&tegra_car TEGRA124_CLK_APBIF>; 904 clock-names = "d_audio", "apbif"; 905 resets = <&tegra_car 106>, /* d_audio */ 906 <&tegra_car 107>, /* apbif */ 907 <&tegra_car 30>, /* i2s0 */ 908 <&tegra_car 11>, /* i2s1 */ 909 <&tegra_car 18>, /* i2s2 */ 910 <&tegra_car 101>, /* i2s3 */ 911 <&tegra_car 102>, /* i2s4 */ 912 <&tegra_car 108>, /* dam0 */ 913 <&tegra_car 109>, /* dam1 */ 914 <&tegra_car 110>, /* dam2 */ 915 <&tegra_car 10>, /* spdif */ 916 <&tegra_car 153>, /* amx */ 917 <&tegra_car 185>, /* amx1 */ 918 <&tegra_car 154>, /* adx */ 919 <&tegra_car 180>, /* adx1 */ 920 <&tegra_car 186>, /* afc0 */ 921 <&tegra_car 187>, /* afc1 */ 922 <&tegra_car 188>, /* afc2 */ 923 <&tegra_car 189>, /* afc3 */ 924 <&tegra_car 190>, /* afc4 */ 925 <&tegra_car 191>; /* afc5 */ 926 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 927 "i2s3", "i2s4", "dam0", "dam1", "dam2", 928 "spdif", "amx", "amx1", "adx", "adx1", 929 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 930 dmas = <&apbdma 1>, <&apbdma 1>, 931 <&apbdma 2>, <&apbdma 2>, 932 <&apbdma 3>, <&apbdma 3>, 933 <&apbdma 4>, <&apbdma 4>, 934 <&apbdma 6>, <&apbdma 6>, 935 <&apbdma 7>, <&apbdma 7>, 936 <&apbdma 12>, <&apbdma 12>, 937 <&apbdma 13>, <&apbdma 13>, 938 <&apbdma 14>, <&apbdma 14>, 939 <&apbdma 29>, <&apbdma 29>; 940 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 941 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 942 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 943 "rx9", "tx9"; 944 ranges; 945 #address-cells = <2>; 946 #size-cells = <2>; 947 948 tegra_i2s0: i2s@70301000 { 949 compatible = "nvidia,tegra124-i2s"; 950 reg = <0x0 0x70301000 0x0 0x100>; 951 nvidia,ahub-cif-ids = <4 4>; 952 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 953 clock-names = "i2s"; 954 resets = <&tegra_car 30>; 955 reset-names = "i2s"; 956 status = "disabled"; 957 }; 958 959 tegra_i2s1: i2s@70301100 { 960 compatible = "nvidia,tegra124-i2s"; 961 reg = <0x0 0x70301100 0x0 0x100>; 962 nvidia,ahub-cif-ids = <5 5>; 963 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 964 clock-names = "i2s"; 965 resets = <&tegra_car 11>; 966 reset-names = "i2s"; 967 status = "disabled"; 968 }; 969 970 tegra_i2s2: i2s@70301200 { 971 compatible = "nvidia,tegra124-i2s"; 972 reg = <0x0 0x70301200 0x0 0x100>; 973 nvidia,ahub-cif-ids = <6 6>; 974 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 975 clock-names = "i2s"; 976 resets = <&tegra_car 18>; 977 reset-names = "i2s"; 978 status = "disabled"; 979 }; 980 981 tegra_i2s3: i2s@70301300 { 982 compatible = "nvidia,tegra124-i2s"; 983 reg = <0x0 0x70301300 0x0 0x100>; 984 nvidia,ahub-cif-ids = <7 7>; 985 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 986 clock-names = "i2s"; 987 resets = <&tegra_car 101>; 988 reset-names = "i2s"; 989 status = "disabled"; 990 }; 991 992 tegra_i2s4: i2s@70301400 { 993 compatible = "nvidia,tegra124-i2s"; 994 reg = <0x0 0x70301400 0x0 0x100>; 995 nvidia,ahub-cif-ids = <8 8>; 996 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 997 clock-names = "i2s"; 998 resets = <&tegra_car 102>; 999 reset-names = "i2s"; 1000 status = "disabled"; 1001 }; 1002 }; 1003 1004 usb@7d000000 { 1005 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1006 reg = <0x0 0x7d000000 0x0 0x4000>; 1007 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1008 phy_type = "utmi"; 1009 clocks = <&tegra_car TEGRA124_CLK_USBD>; 1010 clock-names = "usb"; 1011 resets = <&tegra_car 22>; 1012 reset-names = "usb"; 1013 nvidia,phy = <&phy1>; 1014 status = "disabled"; 1015 }; 1016 1017 phy1: usb-phy@7d000000 { 1018 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1019 reg = <0x0 0x7d000000 0x0 0x4000>, 1020 <0x0 0x7d000000 0x0 0x4000>; 1021 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1022 phy_type = "utmi"; 1023 clocks = <&tegra_car TEGRA124_CLK_USBD>, 1024 <&tegra_car TEGRA124_CLK_PLL_U>, 1025 <&tegra_car TEGRA124_CLK_USBD>; 1026 clock-names = "reg", "pll_u", "utmi-pads"; 1027 resets = <&tegra_car 22>, <&tegra_car 22>; 1028 reset-names = "usb", "utmi-pads"; 1029 #phy-cells = <0>; 1030 nvidia,hssync-start-delay = <0>; 1031 nvidia,idle-wait-delay = <17>; 1032 nvidia,elastic-limit = <16>; 1033 nvidia,term-range-adj = <6>; 1034 nvidia,xcvr-setup = <9>; 1035 nvidia,xcvr-lsfslew = <0>; 1036 nvidia,xcvr-lsrslew = <3>; 1037 nvidia,hssquelch-level = <2>; 1038 nvidia,hsdiscon-level = <5>; 1039 nvidia,xcvr-hsslew = <12>; 1040 nvidia,has-utmi-pad-registers; 1041 nvidia,pmc = <&tegra_pmc 0>; 1042 status = "disabled"; 1043 }; 1044 1045 usb@7d004000 { 1046 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1047 reg = <0x0 0x7d004000 0x0 0x4000>; 1048 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1049 phy_type = "utmi"; 1050 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1051 clock-names = "usb"; 1052 resets = <&tegra_car 58>; 1053 reset-names = "usb"; 1054 nvidia,phy = <&phy2>; 1055 status = "disabled"; 1056 }; 1057 1058 phy2: usb-phy@7d004000 { 1059 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1060 reg = <0x0 0x7d004000 0x0 0x4000>, 1061 <0x0 0x7d000000 0x0 0x4000>; 1062 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1063 phy_type = "utmi"; 1064 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1065 <&tegra_car TEGRA124_CLK_PLL_U>, 1066 <&tegra_car TEGRA124_CLK_USBD>; 1067 clock-names = "reg", "pll_u", "utmi-pads"; 1068 resets = <&tegra_car 58>, <&tegra_car 22>; 1069 reset-names = "usb", "utmi-pads"; 1070 #phy-cells = <0>; 1071 nvidia,hssync-start-delay = <0>; 1072 nvidia,idle-wait-delay = <17>; 1073 nvidia,elastic-limit = <16>; 1074 nvidia,term-range-adj = <6>; 1075 nvidia,xcvr-setup = <9>; 1076 nvidia,xcvr-lsfslew = <0>; 1077 nvidia,xcvr-lsrslew = <3>; 1078 nvidia,hssquelch-level = <2>; 1079 nvidia,hsdiscon-level = <5>; 1080 nvidia,xcvr-hsslew = <12>; 1081 nvidia,pmc = <&tegra_pmc 1>; 1082 status = "disabled"; 1083 }; 1084 1085 usb@7d008000 { 1086 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1087 reg = <0x0 0x7d008000 0x0 0x4000>; 1088 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1089 phy_type = "utmi"; 1090 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1091 clock-names = "usb"; 1092 resets = <&tegra_car 59>; 1093 reset-names = "usb"; 1094 nvidia,phy = <&phy3>; 1095 status = "disabled"; 1096 }; 1097 1098 phy3: usb-phy@7d008000 { 1099 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1100 reg = <0x0 0x7d008000 0x0 0x4000>, 1101 <0x0 0x7d000000 0x0 0x4000>; 1102 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1103 phy_type = "utmi"; 1104 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1105 <&tegra_car TEGRA124_CLK_PLL_U>, 1106 <&tegra_car TEGRA124_CLK_USBD>; 1107 clock-names = "reg", "pll_u", "utmi-pads"; 1108 resets = <&tegra_car 59>, <&tegra_car 22>; 1109 reset-names = "usb", "utmi-pads"; 1110 #phy-cells = <0>; 1111 nvidia,hssync-start-delay = <0>; 1112 nvidia,idle-wait-delay = <17>; 1113 nvidia,elastic-limit = <16>; 1114 nvidia,term-range-adj = <6>; 1115 nvidia,xcvr-setup = <9>; 1116 nvidia,xcvr-lsfslew = <0>; 1117 nvidia,xcvr-lsrslew = <3>; 1118 nvidia,hssquelch-level = <2>; 1119 nvidia,hsdiscon-level = <5>; 1120 nvidia,xcvr-hsslew = <12>; 1121 nvidia,pmc = <&tegra_pmc 2>; 1122 status = "disabled"; 1123 }; 1124 1125 cpus { 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 1129 cpu@0 { 1130 device_type = "cpu"; 1131 compatible = "nvidia,tegra132-denver"; 1132 reg = <0>; 1133 }; 1134 1135 cpu@1 { 1136 device_type = "cpu"; 1137 compatible = "nvidia,tegra132-denver"; 1138 reg = <1>; 1139 }; 1140 }; 1141 1142 thermal-zones { 1143 cpu-thermal { 1144 polling-delay-passive = <1000>; 1145 polling-delay = <0>; 1146 1147 thermal-sensors = 1148 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1149 1150 trips { 1151 cpu_shutdown_trip { 1152 temperature = <105000>; 1153 hysteresis = <1000>; 1154 type = "critical"; 1155 }; 1156 1157 cpu_throttle_trip: throttle-trip { 1158 temperature = <102000>; 1159 hysteresis = <1000>; 1160 type = "hot"; 1161 }; 1162 }; 1163 1164 cooling-maps { 1165 map0 { 1166 trip = <&cpu_throttle_trip>; 1167 cooling-device = <&throttle_heavy 1 1>; 1168 }; 1169 }; 1170 }; 1171 1172 mem-thermal { 1173 polling-delay-passive = <0>; 1174 polling-delay = <0>; 1175 1176 thermal-sensors = 1177 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1178 1179 trips { 1180 mem_shutdown_trip { 1181 temperature = <101000>; 1182 hysteresis = <1000>; 1183 type = "critical"; 1184 }; 1185 mem_throttle_trip { 1186 temperature = <99000>; 1187 hysteresis = <1000>; 1188 type = "hot"; 1189 }; 1190 }; 1191 1192 cooling-maps { 1193 /* 1194 * There are currently no cooling maps, 1195 * because there are no cooling devices. 1196 */ 1197 }; 1198 }; 1199 1200 gpu-thermal { 1201 polling-delay-passive = <1000>; 1202 polling-delay = <0>; 1203 1204 thermal-sensors = 1205 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1206 1207 trips { 1208 gpu_shutdown_trip { 1209 temperature = <101000>; 1210 hysteresis = <1000>; 1211 type = "critical"; 1212 }; 1213 1214 gpu_throttle_trip: throttle-trip { 1215 temperature = <99000>; 1216 hysteresis = <1000>; 1217 type = "hot"; 1218 }; 1219 }; 1220 1221 cooling-maps { 1222 map0 { 1223 trip = <&gpu_throttle_trip>; 1224 cooling-device = <&throttle_heavy 1 1>; 1225 }; 1226 }; 1227 }; 1228 1229 pllx-thermal { 1230 polling-delay-passive = <0>; 1231 polling-delay = <0>; 1232 1233 thermal-sensors = 1234 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1235 1236 trips { 1237 pllx_shutdown_trip { 1238 temperature = <105000>; 1239 hysteresis = <1000>; 1240 type = "critical"; 1241 }; 1242 pllx_throttle_trip { 1243 temperature = <99000>; 1244 hysteresis = <1000>; 1245 type = "hot"; 1246 }; 1247 }; 1248 1249 cooling-maps { 1250 /* 1251 * There are currently no cooling maps, 1252 * because there are no cooling devices. 1253 */ 1254 }; 1255 }; 1256 }; 1257 1258 timer { 1259 compatible = "arm,armv7-timer"; 1260 interrupts = <GIC_PPI 13 1261 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1262 <GIC_PPI 14 1263 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1264 <GIC_PPI 11 1265 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1266 <GIC_PPI 10 1267 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1268 interrupt-parent = <&gic>; 1269 }; 1270}; 1271