1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 4 */ 5 6/dts-v1/; 7#include "sparx5_pcb_common.dtsi" 8 9/{ 10 gpio-restart { 11 compatible = "gpio-restart"; 12 gpios = <&gpio 37 GPIO_ACTIVE_LOW>; 13 priority = <200>; 14 }; 15 16 i2c0_imux: i2c-mux { 17 compatible = "i2c-mux-pinctrl"; 18 #address-cells = <1>; 19 #size-cells = <0>; 20 i2c-parent = <&i2c0>; 21 }; 22 23 leds { 24 compatible = "gpio-leds"; 25 led-0 { 26 label = "eth60:yellow"; 27 gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_LOW>; 28 default-state = "off"; 29 }; 30 led-1 { 31 label = "eth60:green"; 32 gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_LOW>; 33 default-state = "off"; 34 }; 35 led-2 { 36 label = "eth61:yellow"; 37 gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_LOW>; 38 default-state = "off"; 39 }; 40 led-3 { 41 label = "eth61:green"; 42 gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_LOW>; 43 default-state = "off"; 44 }; 45 led-4 { 46 label = "eth62:yellow"; 47 gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_LOW>; 48 default-state = "off"; 49 }; 50 led-5 { 51 label = "eth62:green"; 52 gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_LOW>; 53 default-state = "off"; 54 }; 55 led-6 { 56 label = "eth63:yellow"; 57 gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_LOW>; 58 default-state = "off"; 59 }; 60 led-7 { 61 label = "eth63:green"; 62 gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_LOW>; 63 default-state = "off"; 64 }; 65 }; 66 67 sfp_eth60: sfp-eth60 { 68 compatible = "sff,sfp"; 69 i2c-bus = <&i2c_sfp1>; 70 tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>; 71 rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>; 72 los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; 73 mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>; 74 tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>; 75 }; 76 77 sfp_eth61: sfp-eth61 { 78 compatible = "sff,sfp"; 79 i2c-bus = <&i2c_sfp2>; 80 tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>; 81 rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>; 82 los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; 83 mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>; 84 tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>; 85 }; 86 87 sfp_eth62: sfp-eth62 { 88 compatible = "sff,sfp"; 89 i2c-bus = <&i2c_sfp3>; 90 tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>; 91 rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>; 92 los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; 93 mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>; 94 tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>; 95 }; 96 97 sfp_eth63: sfp-eth63 { 98 compatible = "sff,sfp"; 99 i2c-bus = <&i2c_sfp4>; 100 tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>; 101 rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>; 102 los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; 103 mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>; 104 tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>; 105 }; 106}; 107 108&gpio { 109 i2cmux_pins_i: i2cmux-pins { 110 pins = "GPIO_35", "GPIO_36", 111 "GPIO_50", "GPIO_51"; 112 function = "twi_scl_m"; 113 output-low; 114 }; 115 i2cmux_s29: i2cmux-0-pins { 116 pins = "GPIO_35"; 117 function = "twi_scl_m"; 118 output-high; 119 }; 120 i2cmux_s30: i2cmux-1-pins { 121 pins = "GPIO_36"; 122 function = "twi_scl_m"; 123 output-high; 124 }; 125 i2cmux_s31: i2cmux-2-pins { 126 pins = "GPIO_50"; 127 function = "twi_scl_m"; 128 output-high; 129 }; 130 i2cmux_s32: i2cmux-3-pins { 131 pins = "GPIO_51"; 132 function = "twi_scl_m"; 133 output-high; 134 }; 135}; 136 137&spi0 { 138 status = "okay"; 139 spi@0 { 140 compatible = "spi-mux"; 141 mux-controls = <&mux>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 reg = <0>; /* CS0 */ 145 flash@9 { 146 compatible = "jedec,spi-nor"; 147 spi-max-frequency = <8000000>; 148 reg = <0x9>; /* SPI */ 149 }; 150 }; 151}; 152 153&sgpio1 { 154 status = "okay"; 155 microchip,sgpio-port-ranges = <24 31>; 156 gpio@0 { 157 ngpios = <64>; 158 }; 159 gpio@1 { 160 ngpios = <64>; 161 }; 162}; 163 164&sgpio2 { 165 status = "okay"; 166 microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>; 167}; 168 169&i2c0_imux { 170 pinctrl-names = 171 "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4", 172 "idle"; 173 pinctrl-0 = <&i2cmux_s29>; 174 pinctrl-1 = <&i2cmux_s30>; 175 pinctrl-2 = <&i2cmux_s31>; 176 pinctrl-3 = <&i2cmux_s32>; 177 pinctrl-4 = <&i2cmux_pins_i>; 178 i2c_sfp1: i2c@0 { 179 reg = <0x0>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 }; 183 i2c_sfp2: i2c@1 { 184 reg = <0x1>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 }; 188 i2c_sfp3: i2c@2 { 189 reg = <0x2>; 190 #address-cells = <1>; 191 #size-cells = <0>; 192 }; 193 i2c_sfp4: i2c@3 { 194 reg = <0x3>; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 }; 198}; 199 200&mdio0 { 201 status = "okay"; 202 phy0: ethernet-phy@0 { 203 reg = <0>; 204 }; 205 phy1: ethernet-phy@1 { 206 reg = <1>; 207 }; 208 phy2: ethernet-phy@2 { 209 reg = <2>; 210 }; 211 phy3: ethernet-phy@3 { 212 reg = <3>; 213 }; 214 phy4: ethernet-phy@4 { 215 reg = <4>; 216 }; 217 phy5: ethernet-phy@5 { 218 reg = <5>; 219 }; 220 phy6: ethernet-phy@6 { 221 reg = <6>; 222 }; 223 phy7: ethernet-phy@7 { 224 reg = <7>; 225 }; 226 phy8: ethernet-phy@8 { 227 reg = <8>; 228 }; 229 phy9: ethernet-phy@9 { 230 reg = <9>; 231 }; 232 phy10: ethernet-phy@10 { 233 reg = <10>; 234 }; 235 phy11: ethernet-phy@11 { 236 reg = <11>; 237 }; 238 phy12: ethernet-phy@12 { 239 reg = <12>; 240 }; 241 phy13: ethernet-phy@13 { 242 reg = <13>; 243 }; 244 phy14: ethernet-phy@14 { 245 reg = <14>; 246 }; 247 phy15: ethernet-phy@15 { 248 reg = <15>; 249 }; 250 phy16: ethernet-phy@16 { 251 reg = <16>; 252 }; 253 phy17: ethernet-phy@17 { 254 reg = <17>; 255 }; 256 phy18: ethernet-phy@18 { 257 reg = <18>; 258 }; 259 phy19: ethernet-phy@19 { 260 reg = <19>; 261 }; 262 phy20: ethernet-phy@20 { 263 reg = <20>; 264 }; 265 phy21: ethernet-phy@21 { 266 reg = <21>; 267 }; 268 phy22: ethernet-phy@22 { 269 reg = <22>; 270 }; 271 phy23: ethernet-phy@23 { 272 reg = <23>; 273 }; 274}; 275 276&mdio1 { 277 status = "okay"; 278 phy24: ethernet-phy@24 { 279 reg = <0>; 280 }; 281 phy25: ethernet-phy@25 { 282 reg = <1>; 283 }; 284 phy26: ethernet-phy@26 { 285 reg = <2>; 286 }; 287 phy27: ethernet-phy@27 { 288 reg = <3>; 289 }; 290 phy28: ethernet-phy@28 { 291 reg = <4>; 292 }; 293 phy29: ethernet-phy@29 { 294 reg = <5>; 295 }; 296 phy30: ethernet-phy@30 { 297 reg = <6>; 298 }; 299 phy31: ethernet-phy@31 { 300 reg = <7>; 301 }; 302 phy32: ethernet-phy@32 { 303 reg = <8>; 304 }; 305 phy33: ethernet-phy@33 { 306 reg = <9>; 307 }; 308 phy34: ethernet-phy@34 { 309 reg = <10>; 310 }; 311 phy35: ethernet-phy@35 { 312 reg = <11>; 313 }; 314 phy36: ethernet-phy@36 { 315 reg = <12>; 316 }; 317 phy37: ethernet-phy@37 { 318 reg = <13>; 319 }; 320 phy38: ethernet-phy@38 { 321 reg = <14>; 322 }; 323 phy39: ethernet-phy@39 { 324 reg = <15>; 325 }; 326 phy40: ethernet-phy@40 { 327 reg = <16>; 328 }; 329 phy41: ethernet-phy@41 { 330 reg = <17>; 331 }; 332 phy42: ethernet-phy@42 { 333 reg = <18>; 334 }; 335 phy43: ethernet-phy@43 { 336 reg = <19>; 337 }; 338 phy44: ethernet-phy@44 { 339 reg = <20>; 340 }; 341 phy45: ethernet-phy@45 { 342 reg = <21>; 343 }; 344 phy46: ethernet-phy@46 { 345 reg = <22>; 346 }; 347 phy47: ethernet-phy@47 { 348 reg = <23>; 349 }; 350}; 351 352&mdio3 { 353 status = "okay"; 354 phy64: ethernet-phy@64 { 355 reg = <28>; 356 }; 357}; 358 359&switch { 360 ethernet-ports { 361 #address-cells = <1>; 362 #size-cells = <0>; 363 364 port0: port@0 { 365 reg = <0>; 366 microchip,bandwidth = <1000>; 367 phys = <&serdes 13>; 368 phy-handle = <&phy0>; 369 phy-mode = "qsgmii"; 370 }; 371 port1: port@1 { 372 reg = <1>; 373 microchip,bandwidth = <1000>; 374 phys = <&serdes 13>; 375 phy-handle = <&phy1>; 376 phy-mode = "qsgmii"; 377 }; 378 port2: port@2 { 379 reg = <2>; 380 microchip,bandwidth = <1000>; 381 phys = <&serdes 13>; 382 phy-handle = <&phy2>; 383 phy-mode = "qsgmii"; 384 }; 385 port3: port@3 { 386 reg = <3>; 387 microchip,bandwidth = <1000>; 388 phys = <&serdes 13>; 389 phy-handle = <&phy3>; 390 phy-mode = "qsgmii"; 391 }; 392 port4: port@4 { 393 reg = <4>; 394 microchip,bandwidth = <1000>; 395 phys = <&serdes 14>; 396 phy-handle = <&phy4>; 397 phy-mode = "qsgmii"; 398 }; 399 port5: port@5 { 400 reg = <5>; 401 microchip,bandwidth = <1000>; 402 phys = <&serdes 14>; 403 phy-handle = <&phy5>; 404 phy-mode = "qsgmii"; 405 }; 406 port6: port@6 { 407 reg = <6>; 408 microchip,bandwidth = <1000>; 409 phys = <&serdes 14>; 410 phy-handle = <&phy6>; 411 phy-mode = "qsgmii"; 412 }; 413 port7: port@7 { 414 reg = <7>; 415 microchip,bandwidth = <1000>; 416 phys = <&serdes 14>; 417 phy-handle = <&phy7>; 418 phy-mode = "qsgmii"; 419 }; 420 port8: port@8 { 421 reg = <8>; 422 microchip,bandwidth = <1000>; 423 phys = <&serdes 15>; 424 phy-handle = <&phy8>; 425 phy-mode = "qsgmii"; 426 }; 427 port9: port@9 { 428 reg = <9>; 429 microchip,bandwidth = <1000>; 430 phys = <&serdes 15>; 431 phy-handle = <&phy9>; 432 phy-mode = "qsgmii"; 433 }; 434 port10: port@10 { 435 reg = <10>; 436 microchip,bandwidth = <1000>; 437 phys = <&serdes 15>; 438 phy-handle = <&phy10>; 439 phy-mode = "qsgmii"; 440 }; 441 port11: port@11 { 442 reg = <11>; 443 microchip,bandwidth = <1000>; 444 phys = <&serdes 15>; 445 phy-handle = <&phy11>; 446 phy-mode = "qsgmii"; 447 }; 448 port12: port@12 { 449 reg = <12>; 450 microchip,bandwidth = <1000>; 451 phys = <&serdes 16>; 452 phy-handle = <&phy12>; 453 phy-mode = "qsgmii"; 454 }; 455 port13: port@13 { 456 reg = <13>; 457 microchip,bandwidth = <1000>; 458 phys = <&serdes 16>; 459 phy-handle = <&phy13>; 460 phy-mode = "qsgmii"; 461 }; 462 port14: port@14 { 463 reg = <14>; 464 microchip,bandwidth = <1000>; 465 phys = <&serdes 16>; 466 phy-handle = <&phy14>; 467 phy-mode = "qsgmii"; 468 }; 469 port15: port@15 { 470 reg = <15>; 471 microchip,bandwidth = <1000>; 472 phys = <&serdes 16>; 473 phy-handle = <&phy15>; 474 phy-mode = "qsgmii"; 475 }; 476 port16: port@16 { 477 reg = <16>; 478 microchip,bandwidth = <1000>; 479 phys = <&serdes 17>; 480 phy-handle = <&phy16>; 481 phy-mode = "qsgmii"; 482 }; 483 port17: port@17 { 484 reg = <17>; 485 microchip,bandwidth = <1000>; 486 phys = <&serdes 17>; 487 phy-handle = <&phy17>; 488 phy-mode = "qsgmii"; 489 }; 490 port18: port@18 { 491 reg = <18>; 492 microchip,bandwidth = <1000>; 493 phys = <&serdes 17>; 494 phy-handle = <&phy18>; 495 phy-mode = "qsgmii"; 496 }; 497 port19: port@19 { 498 reg = <19>; 499 microchip,bandwidth = <1000>; 500 phys = <&serdes 17>; 501 phy-handle = <&phy19>; 502 phy-mode = "qsgmii"; 503 }; 504 port20: port@20 { 505 reg = <20>; 506 microchip,bandwidth = <1000>; 507 phys = <&serdes 18>; 508 phy-handle = <&phy20>; 509 phy-mode = "qsgmii"; 510 }; 511 port21: port@21 { 512 reg = <21>; 513 microchip,bandwidth = <1000>; 514 phys = <&serdes 18>; 515 phy-handle = <&phy21>; 516 phy-mode = "qsgmii"; 517 }; 518 port22: port@22 { 519 reg = <22>; 520 microchip,bandwidth = <1000>; 521 phys = <&serdes 18>; 522 phy-handle = <&phy22>; 523 phy-mode = "qsgmii"; 524 }; 525 port23: port@23 { 526 reg = <23>; 527 microchip,bandwidth = <1000>; 528 phys = <&serdes 18>; 529 phy-handle = <&phy23>; 530 phy-mode = "qsgmii"; 531 }; 532 port24: port@24 { 533 reg = <24>; 534 microchip,bandwidth = <1000>; 535 phys = <&serdes 19>; 536 phy-handle = <&phy24>; 537 phy-mode = "qsgmii"; 538 }; 539 port25: port@25 { 540 reg = <25>; 541 microchip,bandwidth = <1000>; 542 phys = <&serdes 19>; 543 phy-handle = <&phy25>; 544 phy-mode = "qsgmii"; 545 }; 546 port26: port@26 { 547 reg = <26>; 548 microchip,bandwidth = <1000>; 549 phys = <&serdes 19>; 550 phy-handle = <&phy26>; 551 phy-mode = "qsgmii"; 552 }; 553 port27: port@27 { 554 reg = <27>; 555 microchip,bandwidth = <1000>; 556 phys = <&serdes 19>; 557 phy-handle = <&phy27>; 558 phy-mode = "qsgmii"; 559 }; 560 port28: port@28 { 561 reg = <28>; 562 microchip,bandwidth = <1000>; 563 phys = <&serdes 20>; 564 phy-handle = <&phy28>; 565 phy-mode = "qsgmii"; 566 }; 567 port29: port@29 { 568 reg = <29>; 569 microchip,bandwidth = <1000>; 570 phys = <&serdes 20>; 571 phy-handle = <&phy29>; 572 phy-mode = "qsgmii"; 573 }; 574 port30: port@30 { 575 reg = <30>; 576 microchip,bandwidth = <1000>; 577 phys = <&serdes 20>; 578 phy-handle = <&phy30>; 579 phy-mode = "qsgmii"; 580 }; 581 port31: port@31 { 582 reg = <31>; 583 microchip,bandwidth = <1000>; 584 phys = <&serdes 20>; 585 phy-handle = <&phy31>; 586 phy-mode = "qsgmii"; 587 }; 588 port32: port@32 { 589 reg = <32>; 590 microchip,bandwidth = <1000>; 591 phys = <&serdes 21>; 592 phy-handle = <&phy32>; 593 phy-mode = "qsgmii"; 594 }; 595 port33: port@33 { 596 reg = <33>; 597 microchip,bandwidth = <1000>; 598 phys = <&serdes 21>; 599 phy-handle = <&phy33>; 600 phy-mode = "qsgmii"; 601 }; 602 port34: port@34 { 603 reg = <34>; 604 microchip,bandwidth = <1000>; 605 phys = <&serdes 21>; 606 phy-handle = <&phy34>; 607 phy-mode = "qsgmii"; 608 }; 609 port35: port@35 { 610 reg = <35>; 611 microchip,bandwidth = <1000>; 612 phys = <&serdes 21>; 613 phy-handle = <&phy35>; 614 phy-mode = "qsgmii"; 615 }; 616 port36: port@36 { 617 reg = <36>; 618 microchip,bandwidth = <1000>; 619 phys = <&serdes 22>; 620 phy-handle = <&phy36>; 621 phy-mode = "qsgmii"; 622 }; 623 port37: port@37 { 624 reg = <37>; 625 microchip,bandwidth = <1000>; 626 phys = <&serdes 22>; 627 phy-handle = <&phy37>; 628 phy-mode = "qsgmii"; 629 }; 630 port38: port@38 { 631 reg = <38>; 632 microchip,bandwidth = <1000>; 633 phys = <&serdes 22>; 634 phy-handle = <&phy38>; 635 phy-mode = "qsgmii"; 636 }; 637 port39: port@39 { 638 reg = <39>; 639 microchip,bandwidth = <1000>; 640 phys = <&serdes 22>; 641 phy-handle = <&phy39>; 642 phy-mode = "qsgmii"; 643 }; 644 port40: port@40 { 645 reg = <40>; 646 microchip,bandwidth = <1000>; 647 phys = <&serdes 23>; 648 phy-handle = <&phy40>; 649 phy-mode = "qsgmii"; 650 }; 651 port41: port@41 { 652 reg = <41>; 653 microchip,bandwidth = <1000>; 654 phys = <&serdes 23>; 655 phy-handle = <&phy41>; 656 phy-mode = "qsgmii"; 657 }; 658 port42: port@42 { 659 reg = <42>; 660 microchip,bandwidth = <1000>; 661 phys = <&serdes 23>; 662 phy-handle = <&phy42>; 663 phy-mode = "qsgmii"; 664 }; 665 port43: port@43 { 666 reg = <43>; 667 microchip,bandwidth = <1000>; 668 phys = <&serdes 23>; 669 phy-handle = <&phy43>; 670 phy-mode = "qsgmii"; 671 }; 672 port44: port@44 { 673 reg = <44>; 674 microchip,bandwidth = <1000>; 675 phys = <&serdes 24>; 676 phy-handle = <&phy44>; 677 phy-mode = "qsgmii"; 678 }; 679 port45: port@45 { 680 reg = <45>; 681 microchip,bandwidth = <1000>; 682 phys = <&serdes 24>; 683 phy-handle = <&phy45>; 684 phy-mode = "qsgmii"; 685 }; 686 port46: port@46 { 687 reg = <46>; 688 microchip,bandwidth = <1000>; 689 phys = <&serdes 24>; 690 phy-handle = <&phy46>; 691 phy-mode = "qsgmii"; 692 }; 693 port47: port@47 { 694 reg = <47>; 695 microchip,bandwidth = <1000>; 696 phys = <&serdes 24>; 697 phy-handle = <&phy47>; 698 phy-mode = "qsgmii"; 699 }; 700 /* Then the 25G interfaces */ 701 port60: port@60 { 702 reg = <60>; 703 microchip,bandwidth = <25000>; 704 phys = <&serdes 29>; 705 phy-mode = "10gbase-r"; 706 sfp = <&sfp_eth60>; 707 managed = "in-band-status"; 708 }; 709 port61: port@61 { 710 reg = <61>; 711 microchip,bandwidth = <25000>; 712 phys = <&serdes 30>; 713 phy-mode = "10gbase-r"; 714 sfp = <&sfp_eth61>; 715 managed = "in-band-status"; 716 }; 717 port62: port@62 { 718 reg = <62>; 719 microchip,bandwidth = <25000>; 720 phys = <&serdes 31>; 721 phy-mode = "10gbase-r"; 722 sfp = <&sfp_eth62>; 723 managed = "in-band-status"; 724 }; 725 port63: port@63 { 726 reg = <63>; 727 microchip,bandwidth = <25000>; 728 phys = <&serdes 32>; 729 phy-mode = "10gbase-r"; 730 sfp = <&sfp_eth63>; 731 managed = "in-band-status"; 732 }; 733 /* Finally the Management interface */ 734 port64: port@64 { 735 reg = <64>; 736 microchip,bandwidth = <1000>; 737 phys = <&serdes 0>; 738 phy-handle = <&phy64>; 739 phy-mode = "sgmii"; 740 }; 741 }; 742}; 743