1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 4 */ 5 6/dts-v1/; 7#include "sparx5_pcb_common.dtsi" 8 9/{ 10 gpio-restart { 11 compatible = "gpio-restart"; 12 gpios = <&gpio 37 GPIO_ACTIVE_LOW>; 13 priority = <200>; 14 }; 15 16 leds { 17 compatible = "gpio-leds"; 18 led-0 { 19 label = "twr0:green"; 20 gpios = <&sgpio_out0 8 0 GPIO_ACTIVE_LOW>; 21 }; 22 led-1 { 23 label = "twr0:yellow"; 24 gpios = <&sgpio_out0 8 1 GPIO_ACTIVE_LOW>; 25 }; 26 led-2 { 27 label = "twr1:green"; 28 gpios = <&sgpio_out0 9 0 GPIO_ACTIVE_LOW>; 29 }; 30 led-3 { 31 label = "twr1:yellow"; 32 gpios = <&sgpio_out0 9 1 GPIO_ACTIVE_LOW>; 33 }; 34 led-4 { 35 label = "twr2:green"; 36 gpios = <&sgpio_out0 10 0 GPIO_ACTIVE_LOW>; 37 }; 38 led-5 { 39 label = "twr2:yellow"; 40 gpios = <&sgpio_out0 10 1 GPIO_ACTIVE_LOW>; 41 }; 42 led-6 { 43 label = "twr3:green"; 44 gpios = <&sgpio_out0 11 0 GPIO_ACTIVE_LOW>; 45 }; 46 led-7 { 47 label = "twr3:yellow"; 48 gpios = <&sgpio_out0 11 1 GPIO_ACTIVE_LOW>; 49 }; 50 led-8 { 51 label = "eth12:green"; 52 gpios = <&sgpio_out0 12 0 GPIO_ACTIVE_HIGH>; 53 default-state = "off"; 54 }; 55 led-9 { 56 label = "eth12:yellow"; 57 gpios = <&sgpio_out0 12 1 GPIO_ACTIVE_HIGH>; 58 default-state = "off"; 59 }; 60 led-10 { 61 label = "eth13:green"; 62 gpios = <&sgpio_out0 13 0 GPIO_ACTIVE_HIGH>; 63 default-state = "off"; 64 }; 65 led-11 { 66 label = "eth13:yellow"; 67 gpios = <&sgpio_out0 13 1 GPIO_ACTIVE_HIGH>; 68 default-state = "off"; 69 }; 70 led-12 { 71 label = "eth14:green"; 72 gpios = <&sgpio_out0 14 0 GPIO_ACTIVE_HIGH>; 73 default-state = "off"; 74 }; 75 led-13 { 76 label = "eth14:yellow"; 77 gpios = <&sgpio_out0 14 1 GPIO_ACTIVE_HIGH>; 78 default-state = "off"; 79 }; 80 led-14 { 81 label = "eth15:green"; 82 gpios = <&sgpio_out0 15 0 GPIO_ACTIVE_HIGH>; 83 default-state = "off"; 84 }; 85 led-15 { 86 label = "eth15:yellow"; 87 gpios = <&sgpio_out0 15 1 GPIO_ACTIVE_HIGH>; 88 default-state = "off"; 89 }; 90 led-16 { 91 label = "eth48:green"; 92 gpios = <&sgpio_out1 16 0 GPIO_ACTIVE_HIGH>; 93 default-state = "off"; 94 }; 95 led-17 { 96 label = "eth48:yellow"; 97 gpios = <&sgpio_out1 16 1 GPIO_ACTIVE_HIGH>; 98 default-state = "off"; 99 }; 100 led-18 { 101 label = "eth49:green"; 102 gpios = <&sgpio_out1 17 0 GPIO_ACTIVE_HIGH>; 103 default-state = "off"; 104 }; 105 led-19 { 106 label = "eth49:yellow"; 107 gpios = <&sgpio_out1 17 1 GPIO_ACTIVE_HIGH>; 108 default-state = "off"; 109 }; 110 led-20 { 111 label = "eth50:green"; 112 gpios = <&sgpio_out1 18 0 GPIO_ACTIVE_HIGH>; 113 default-state = "off"; 114 }; 115 led-21 { 116 label = "eth50:yellow"; 117 gpios = <&sgpio_out1 18 1 GPIO_ACTIVE_HIGH>; 118 default-state = "off"; 119 }; 120 led-22 { 121 label = "eth51:green"; 122 gpios = <&sgpio_out1 19 0 GPIO_ACTIVE_HIGH>; 123 default-state = "off"; 124 }; 125 led-23 { 126 label = "eth51:yellow"; 127 gpios = <&sgpio_out1 19 1 GPIO_ACTIVE_HIGH>; 128 default-state = "off"; 129 }; 130 led-24 { 131 label = "eth52:green"; 132 gpios = <&sgpio_out1 20 0 GPIO_ACTIVE_HIGH>; 133 default-state = "off"; 134 }; 135 led-25 { 136 label = "eth52:yellow"; 137 gpios = <&sgpio_out1 20 1 GPIO_ACTIVE_HIGH>; 138 default-state = "off"; 139 }; 140 led-26 { 141 label = "eth53:green"; 142 gpios = <&sgpio_out1 21 0 GPIO_ACTIVE_HIGH>; 143 default-state = "off"; 144 }; 145 led-27 { 146 label = "eth53:yellow"; 147 gpios = <&sgpio_out1 21 1 GPIO_ACTIVE_HIGH>; 148 default-state = "off"; 149 }; 150 led-28 { 151 label = "eth54:green"; 152 gpios = <&sgpio_out1 22 0 GPIO_ACTIVE_HIGH>; 153 default-state = "off"; 154 }; 155 led-29 { 156 label = "eth54:yellow"; 157 gpios = <&sgpio_out1 22 1 GPIO_ACTIVE_HIGH>; 158 default-state = "off"; 159 }; 160 led-30 { 161 label = "eth55:green"; 162 gpios = <&sgpio_out1 23 0 GPIO_ACTIVE_HIGH>; 163 default-state = "off"; 164 }; 165 led-31 { 166 label = "eth55:yellow"; 167 gpios = <&sgpio_out1 23 1 GPIO_ACTIVE_HIGH>; 168 default-state = "off"; 169 }; 170 led-32 { 171 label = "eth56:green"; 172 gpios = <&sgpio_out1 24 0 GPIO_ACTIVE_HIGH>; 173 default-state = "off"; 174 }; 175 led-33 { 176 label = "eth56:yellow"; 177 gpios = <&sgpio_out1 24 1 GPIO_ACTIVE_HIGH>; 178 default-state = "off"; 179 }; 180 led-34 { 181 label = "eth57:green"; 182 gpios = <&sgpio_out1 25 0 GPIO_ACTIVE_HIGH>; 183 default-state = "off"; 184 }; 185 led-35 { 186 label = "eth57:yellow"; 187 gpios = <&sgpio_out1 25 1 GPIO_ACTIVE_HIGH>; 188 default-state = "off"; 189 }; 190 led-36 { 191 label = "eth58:green"; 192 gpios = <&sgpio_out1 26 0 GPIO_ACTIVE_HIGH>; 193 default-state = "off"; 194 }; 195 led-37 { 196 label = "eth58:yellow"; 197 gpios = <&sgpio_out1 26 1 GPIO_ACTIVE_HIGH>; 198 default-state = "off"; 199 }; 200 led-38 { 201 label = "eth59:green"; 202 gpios = <&sgpio_out1 27 0 GPIO_ACTIVE_HIGH>; 203 default-state = "off"; 204 }; 205 led-39 { 206 label = "eth59:yellow"; 207 gpios = <&sgpio_out1 27 1 GPIO_ACTIVE_HIGH>; 208 default-state = "off"; 209 }; 210 led-40 { 211 label = "eth60:green"; 212 gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_HIGH>; 213 default-state = "off"; 214 }; 215 led-41 { 216 label = "eth60:yellow"; 217 gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_HIGH>; 218 default-state = "off"; 219 }; 220 led-42 { 221 label = "eth61:green"; 222 gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_HIGH>; 223 default-state = "off"; 224 }; 225 led-43 { 226 label = "eth61:yellow"; 227 gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_HIGH>; 228 default-state = "off"; 229 }; 230 led-44 { 231 label = "eth62:green"; 232 gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_HIGH>; 233 default-state = "off"; 234 }; 235 led-45 { 236 label = "eth62:yellow"; 237 gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_HIGH>; 238 default-state = "off"; 239 }; 240 led-46 { 241 label = "eth63:green"; 242 gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_HIGH>; 243 default-state = "off"; 244 }; 245 led-47 { 246 label = "eth63:yellow"; 247 gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_HIGH>; 248 default-state = "off"; 249 }; 250 }; 251}; 252 253&sgpio0 { 254 status = "okay"; 255 microchip,sgpio-port-ranges = <8 15>; 256 gpio@0 { 257 ngpios = <64>; 258 }; 259 gpio@1 { 260 ngpios = <64>; 261 }; 262}; 263 264&sgpio1 { 265 status = "okay"; 266 microchip,sgpio-port-ranges = <24 31>; 267 gpio@0 { 268 ngpios = <64>; 269 }; 270 gpio@1 { 271 ngpios = <64>; 272 }; 273}; 274 275&spi0 { 276 status = "okay"; 277 spi@0 { 278 compatible = "spi-mux"; 279 mux-controls = <&mux>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 reg = <0>; /* CS0 */ 283 flash@9 { 284 compatible = "jedec,spi-nor"; 285 spi-max-frequency = <8000000>; 286 reg = <0x9>; /* SPI */ 287 }; 288 }; 289}; 290 291&sgpio0 { 292 status = "okay"; 293 microchip,sgpio-port-ranges = <8 15>; 294 gpio@0 { 295 ngpios = <64>; 296 }; 297 gpio@1 { 298 ngpios = <64>; 299 }; 300}; 301 302&sgpio1 { 303 status = "okay"; 304 microchip,sgpio-port-ranges = <24 31>; 305 gpio@0 { 306 ngpios = <64>; 307 }; 308 gpio@1 { 309 ngpios = <64>; 310 }; 311}; 312 313&sgpio2 { 314 status = "okay"; 315 microchip,sgpio-port-ranges = <0 0>, <11 31>; 316}; 317 318&gpio { 319 i2cmux_pins_i: i2cmux-pins { 320 pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", 321 "GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35", 322 "GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57"; 323 function = "twi_scl_m"; 324 output-low; 325 }; 326 i2cmux_0: i2cmux-0-pins { 327 pins = "GPIO_16"; 328 function = "twi_scl_m"; 329 output-high; 330 }; 331 i2cmux_1: i2cmux-1-pins { 332 pins = "GPIO_17"; 333 function = "twi_scl_m"; 334 output-high; 335 }; 336 i2cmux_2: i2cmux-2-pins { 337 pins = "GPIO_18"; 338 function = "twi_scl_m"; 339 output-high; 340 }; 341 i2cmux_3: i2cmux-3-pins { 342 pins = "GPIO_19"; 343 function = "twi_scl_m"; 344 output-high; 345 }; 346 i2cmux_4: i2cmux-4-pins { 347 pins = "GPIO_20"; 348 function = "twi_scl_m"; 349 output-high; 350 }; 351 i2cmux_5: i2cmux-5-pins { 352 pins = "GPIO_22"; 353 function = "twi_scl_m"; 354 output-high; 355 }; 356 i2cmux_6: i2cmux-6-pins { 357 pins = "GPIO_36"; 358 function = "twi_scl_m"; 359 output-high; 360 }; 361 i2cmux_7: i2cmux-7-pins { 362 pins = "GPIO_35"; 363 function = "twi_scl_m"; 364 output-high; 365 }; 366 i2cmux_8: i2cmux-8-pins { 367 pins = "GPIO_50"; 368 function = "twi_scl_m"; 369 output-high; 370 }; 371 i2cmux_9: i2cmux-9-pins { 372 pins = "GPIO_51"; 373 function = "twi_scl_m"; 374 output-high; 375 }; 376 i2cmux_10: i2cmux-10-pins { 377 pins = "GPIO_56"; 378 function = "twi_scl_m"; 379 output-high; 380 }; 381 i2cmux_11: i2cmux-11-pins { 382 pins = "GPIO_57"; 383 function = "twi_scl_m"; 384 output-high; 385 }; 386}; 387 388&axi { 389 i2c0_imux: i2c-mux-0 { 390 compatible = "i2c-mux-pinctrl"; 391 #address-cells = <1>; 392 #size-cells = <0>; 393 i2c-parent = <&i2c0>; 394 }; 395 i2c0_emux: i2c-mux-1 { 396 compatible = "i2c-mux-gpio"; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 i2c-parent = <&i2c0>; 400 }; 401}; 402 403&i2c0_imux { 404 pinctrl-names = 405 "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4", 406 "i2c_sfp5", "i2c_sfp6", "i2c_sfp7", "i2c_sfp8", 407 "i2c_sfp9", "i2c_sfp10", "i2c_sfp11", "i2c_sfp12", "idle"; 408 pinctrl-0 = <&i2cmux_0>; 409 pinctrl-1 = <&i2cmux_1>; 410 pinctrl-2 = <&i2cmux_2>; 411 pinctrl-3 = <&i2cmux_3>; 412 pinctrl-4 = <&i2cmux_4>; 413 pinctrl-5 = <&i2cmux_5>; 414 pinctrl-6 = <&i2cmux_6>; 415 pinctrl-7 = <&i2cmux_7>; 416 pinctrl-8 = <&i2cmux_8>; 417 pinctrl-9 = <&i2cmux_9>; 418 pinctrl-10 = <&i2cmux_10>; 419 pinctrl-11 = <&i2cmux_11>; 420 pinctrl-12 = <&i2cmux_pins_i>; 421 i2c_sfp1: i2c@0 { 422 reg = <0x0>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 }; 426 i2c_sfp2: i2c@1 { 427 reg = <0x1>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 }; 431 i2c_sfp3: i2c@2 { 432 reg = <0x2>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 }; 436 i2c_sfp4: i2c@3 { 437 reg = <0x3>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 }; 441 i2c_sfp5: i2c@4 { 442 reg = <0x4>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 }; 446 i2c_sfp6: i2c@5 { 447 reg = <0x5>; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 }; 451 i2c_sfp7: i2c@6 { 452 reg = <0x6>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 }; 456 i2c_sfp8: i2c@7 { 457 reg = <0x7>; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 }; 461 i2c_sfp9: i2c@8 { 462 reg = <0x8>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 }; 466 i2c_sfp10: i2c@9 { 467 reg = <0x9>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 }; 471 i2c_sfp11: i2c@a { 472 reg = <0xa>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 }; 476 i2c_sfp12: i2c@b { 477 reg = <0xb>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 }; 481}; 482 483&i2c0_emux { 484 mux-gpios = <&gpio 55 GPIO_ACTIVE_HIGH 485 &gpio 60 GPIO_ACTIVE_HIGH 486 &gpio 61 GPIO_ACTIVE_HIGH 487 &gpio 54 GPIO_ACTIVE_HIGH>; 488 idle-state = <0x8>; 489 i2c_sfp13: i2c@0 { 490 reg = <0x0>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 }; 494 i2c_sfp14: i2c@1 { 495 reg = <0x1>; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 }; 499 i2c_sfp15: i2c@2 { 500 reg = <0x2>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 }; 504 i2c_sfp16: i2c@3 { 505 reg = <0x3>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 }; 509 i2c_sfp17: i2c@4 { 510 reg = <0x4>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 }; 514 i2c_sfp18: i2c@5 { 515 reg = <0x5>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 }; 519 i2c_sfp19: i2c@6 { 520 reg = <0x6>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 }; 524 i2c_sfp20: i2c@7 { 525 reg = <0x7>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 }; 529}; 530 531&mdio3 { 532 status = "okay"; 533 phy64: ethernet-phy@64 { 534 reg = <28>; 535 }; 536}; 537 538&axi { 539 sfp_eth12: sfp-eth12 { 540 compatible = "sff,sfp"; 541 i2c-bus = <&i2c_sfp1>; 542 tx-disable-gpios = <&sgpio_out2 11 1 GPIO_ACTIVE_LOW>; 543 los-gpios = <&sgpio_in2 11 1 GPIO_ACTIVE_HIGH>; 544 mod-def0-gpios = <&sgpio_in2 11 2 GPIO_ACTIVE_LOW>; 545 tx-fault-gpios = <&sgpio_in2 12 0 GPIO_ACTIVE_HIGH>; 546 }; 547 sfp_eth13: sfp-eth13 { 548 compatible = "sff,sfp"; 549 i2c-bus = <&i2c_sfp2>; 550 tx-disable-gpios = <&sgpio_out2 12 1 GPIO_ACTIVE_LOW>; 551 los-gpios = <&sgpio_in2 12 1 GPIO_ACTIVE_HIGH>; 552 mod-def0-gpios = <&sgpio_in2 12 2 GPIO_ACTIVE_LOW>; 553 tx-fault-gpios = <&sgpio_in2 13 0 GPIO_ACTIVE_HIGH>; 554 }; 555 sfp_eth14: sfp-eth14 { 556 compatible = "sff,sfp"; 557 i2c-bus = <&i2c_sfp3>; 558 tx-disable-gpios = <&sgpio_out2 13 1 GPIO_ACTIVE_LOW>; 559 los-gpios = <&sgpio_in2 13 1 GPIO_ACTIVE_HIGH>; 560 mod-def0-gpios = <&sgpio_in2 13 2 GPIO_ACTIVE_LOW>; 561 tx-fault-gpios = <&sgpio_in2 14 0 GPIO_ACTIVE_HIGH>; 562 }; 563 sfp_eth15: sfp-eth15 { 564 compatible = "sff,sfp"; 565 i2c-bus = <&i2c_sfp4>; 566 tx-disable-gpios = <&sgpio_out2 14 1 GPIO_ACTIVE_LOW>; 567 los-gpios = <&sgpio_in2 14 1 GPIO_ACTIVE_HIGH>; 568 mod-def0-gpios = <&sgpio_in2 14 2 GPIO_ACTIVE_LOW>; 569 tx-fault-gpios = <&sgpio_in2 15 0 GPIO_ACTIVE_HIGH>; 570 }; 571 sfp_eth48: sfp-eth48 { 572 compatible = "sff,sfp"; 573 i2c-bus = <&i2c_sfp5>; 574 tx-disable-gpios = <&sgpio_out2 15 1 GPIO_ACTIVE_LOW>; 575 los-gpios = <&sgpio_in2 15 1 GPIO_ACTIVE_HIGH>; 576 mod-def0-gpios = <&sgpio_in2 15 2 GPIO_ACTIVE_LOW>; 577 tx-fault-gpios = <&sgpio_in2 16 0 GPIO_ACTIVE_HIGH>; 578 }; 579 sfp_eth49: sfp-eth49 { 580 compatible = "sff,sfp"; 581 i2c-bus = <&i2c_sfp6>; 582 tx-disable-gpios = <&sgpio_out2 16 1 GPIO_ACTIVE_LOW>; 583 los-gpios = <&sgpio_in2 16 1 GPIO_ACTIVE_HIGH>; 584 mod-def0-gpios = <&sgpio_in2 16 2 GPIO_ACTIVE_LOW>; 585 tx-fault-gpios = <&sgpio_in2 17 0 GPIO_ACTIVE_HIGH>; 586 }; 587 sfp_eth50: sfp-eth50 { 588 compatible = "sff,sfp"; 589 i2c-bus = <&i2c_sfp7>; 590 tx-disable-gpios = <&sgpio_out2 17 1 GPIO_ACTIVE_LOW>; 591 los-gpios = <&sgpio_in2 17 1 GPIO_ACTIVE_HIGH>; 592 mod-def0-gpios = <&sgpio_in2 17 2 GPIO_ACTIVE_LOW>; 593 tx-fault-gpios = <&sgpio_in2 18 0 GPIO_ACTIVE_HIGH>; 594 }; 595 sfp_eth51: sfp-eth51 { 596 compatible = "sff,sfp"; 597 i2c-bus = <&i2c_sfp8>; 598 tx-disable-gpios = <&sgpio_out2 18 1 GPIO_ACTIVE_LOW>; 599 los-gpios = <&sgpio_in2 18 1 GPIO_ACTIVE_HIGH>; 600 mod-def0-gpios = <&sgpio_in2 18 2 GPIO_ACTIVE_LOW>; 601 tx-fault-gpios = <&sgpio_in2 19 0 GPIO_ACTIVE_HIGH>; 602 }; 603 sfp_eth52: sfp-eth52 { 604 compatible = "sff,sfp"; 605 i2c-bus = <&i2c_sfp9>; 606 tx-disable-gpios = <&sgpio_out2 19 1 GPIO_ACTIVE_LOW>; 607 los-gpios = <&sgpio_in2 19 1 GPIO_ACTIVE_HIGH>; 608 mod-def0-gpios = <&sgpio_in2 19 2 GPIO_ACTIVE_LOW>; 609 tx-fault-gpios = <&sgpio_in2 20 0 GPIO_ACTIVE_HIGH>; 610 }; 611 sfp_eth53: sfp-eth53 { 612 compatible = "sff,sfp"; 613 i2c-bus = <&i2c_sfp10>; 614 tx-disable-gpios = <&sgpio_out2 20 1 GPIO_ACTIVE_LOW>; 615 los-gpios = <&sgpio_in2 20 1 GPIO_ACTIVE_HIGH>; 616 mod-def0-gpios = <&sgpio_in2 20 2 GPIO_ACTIVE_LOW>; 617 tx-fault-gpios = <&sgpio_in2 21 0 GPIO_ACTIVE_HIGH>; 618 }; 619 sfp_eth54: sfp-eth54 { 620 compatible = "sff,sfp"; 621 i2c-bus = <&i2c_sfp11>; 622 tx-disable-gpios = <&sgpio_out2 21 1 GPIO_ACTIVE_LOW>; 623 los-gpios = <&sgpio_in2 21 1 GPIO_ACTIVE_HIGH>; 624 mod-def0-gpios = <&sgpio_in2 21 2 GPIO_ACTIVE_LOW>; 625 tx-fault-gpios = <&sgpio_in2 22 0 GPIO_ACTIVE_HIGH>; 626 }; 627 sfp_eth55: sfp-eth55 { 628 compatible = "sff,sfp"; 629 i2c-bus = <&i2c_sfp12>; 630 tx-disable-gpios = <&sgpio_out2 22 1 GPIO_ACTIVE_LOW>; 631 los-gpios = <&sgpio_in2 22 1 GPIO_ACTIVE_HIGH>; 632 mod-def0-gpios = <&sgpio_in2 22 2 GPIO_ACTIVE_LOW>; 633 tx-fault-gpios = <&sgpio_in2 23 0 GPIO_ACTIVE_HIGH>; 634 }; 635 sfp_eth56: sfp-eth56 { 636 compatible = "sff,sfp"; 637 i2c-bus = <&i2c_sfp13>; 638 tx-disable-gpios = <&sgpio_out2 23 1 GPIO_ACTIVE_LOW>; 639 los-gpios = <&sgpio_in2 23 1 GPIO_ACTIVE_HIGH>; 640 mod-def0-gpios = <&sgpio_in2 23 2 GPIO_ACTIVE_LOW>; 641 tx-fault-gpios = <&sgpio_in2 24 0 GPIO_ACTIVE_HIGH>; 642 }; 643 sfp_eth57: sfp-eth57 { 644 compatible = "sff,sfp"; 645 i2c-bus = <&i2c_sfp14>; 646 tx-disable-gpios = <&sgpio_out2 24 1 GPIO_ACTIVE_LOW>; 647 los-gpios = <&sgpio_in2 24 1 GPIO_ACTIVE_HIGH>; 648 mod-def0-gpios = <&sgpio_in2 24 2 GPIO_ACTIVE_LOW>; 649 tx-fault-gpios = <&sgpio_in2 25 0 GPIO_ACTIVE_HIGH>; 650 }; 651 sfp_eth58: sfp-eth58 { 652 compatible = "sff,sfp"; 653 i2c-bus = <&i2c_sfp15>; 654 tx-disable-gpios = <&sgpio_out2 25 1 GPIO_ACTIVE_LOW>; 655 los-gpios = <&sgpio_in2 25 1 GPIO_ACTIVE_HIGH>; 656 mod-def0-gpios = <&sgpio_in2 25 2 GPIO_ACTIVE_LOW>; 657 tx-fault-gpios = <&sgpio_in2 26 0 GPIO_ACTIVE_HIGH>; 658 }; 659 sfp_eth59: sfp-eth59 { 660 compatible = "sff,sfp"; 661 i2c-bus = <&i2c_sfp16>; 662 tx-disable-gpios = <&sgpio_out2 26 1 GPIO_ACTIVE_LOW>; 663 los-gpios = <&sgpio_in2 26 1 GPIO_ACTIVE_HIGH>; 664 mod-def0-gpios = <&sgpio_in2 26 2 GPIO_ACTIVE_LOW>; 665 tx-fault-gpios = <&sgpio_in2 27 0 GPIO_ACTIVE_HIGH>; 666 }; 667 sfp_eth60: sfp-eth60 { 668 compatible = "sff,sfp"; 669 i2c-bus = <&i2c_sfp17>; 670 tx-disable-gpios = <&sgpio_out2 27 1 GPIO_ACTIVE_LOW>; 671 los-gpios = <&sgpio_in2 27 1 GPIO_ACTIVE_HIGH>; 672 mod-def0-gpios = <&sgpio_in2 27 2 GPIO_ACTIVE_LOW>; 673 tx-fault-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; 674 }; 675 sfp_eth61: sfp-eth61 { 676 compatible = "sff,sfp"; 677 i2c-bus = <&i2c_sfp18>; 678 tx-disable-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_LOW>; 679 los-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_HIGH>; 680 mod-def0-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_LOW>; 681 tx-fault-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; 682 }; 683 sfp_eth62: sfp-eth62 { 684 compatible = "sff,sfp"; 685 i2c-bus = <&i2c_sfp19>; 686 tx-disable-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_LOW>; 687 los-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_HIGH>; 688 mod-def0-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_LOW>; 689 tx-fault-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; 690 }; 691 sfp_eth63: sfp-eth63 { 692 compatible = "sff,sfp"; 693 i2c-bus = <&i2c_sfp20>; 694 tx-disable-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_LOW>; 695 los-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_HIGH>; 696 mod-def0-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_LOW>; 697 tx-fault-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; 698 }; 699}; 700 701&switch { 702 ethernet-ports { 703 #address-cells = <1>; 704 #size-cells = <0>; 705 706 /* 10G SFPs */ 707 port12: port@12 { 708 reg = <12>; 709 microchip,bandwidth = <10000>; 710 phys = <&serdes 13>; 711 phy-mode = "10gbase-r"; 712 sfp = <&sfp_eth12>; 713 microchip,sd-sgpio = <301>; 714 managed = "in-band-status"; 715 }; 716 port13: port@13 { 717 reg = <13>; 718 /* Example: CU SFP, 1G speed */ 719 microchip,bandwidth = <10000>; 720 phys = <&serdes 14>; 721 phy-mode = "10gbase-r"; 722 sfp = <&sfp_eth13>; 723 microchip,sd-sgpio = <305>; 724 managed = "in-band-status"; 725 }; 726 port14: port@14 { 727 reg = <14>; 728 microchip,bandwidth = <10000>; 729 phys = <&serdes 15>; 730 phy-mode = "10gbase-r"; 731 sfp = <&sfp_eth14>; 732 microchip,sd-sgpio = <309>; 733 managed = "in-band-status"; 734 }; 735 port15: port@15 { 736 reg = <15>; 737 microchip,bandwidth = <10000>; 738 phys = <&serdes 16>; 739 phy-mode = "10gbase-r"; 740 sfp = <&sfp_eth15>; 741 microchip,sd-sgpio = <313>; 742 managed = "in-band-status"; 743 }; 744 port48: port@48 { 745 reg = <48>; 746 microchip,bandwidth = <10000>; 747 phys = <&serdes 17>; 748 phy-mode = "10gbase-r"; 749 sfp = <&sfp_eth48>; 750 microchip,sd-sgpio = <317>; 751 managed = "in-band-status"; 752 }; 753 port49: port@49 { 754 reg = <49>; 755 microchip,bandwidth = <10000>; 756 phys = <&serdes 18>; 757 phy-mode = "10gbase-r"; 758 sfp = <&sfp_eth49>; 759 microchip,sd-sgpio = <321>; 760 managed = "in-band-status"; 761 }; 762 port50: port@50 { 763 reg = <50>; 764 microchip,bandwidth = <10000>; 765 phys = <&serdes 19>; 766 phy-mode = "10gbase-r"; 767 sfp = <&sfp_eth50>; 768 microchip,sd-sgpio = <325>; 769 managed = "in-band-status"; 770 }; 771 port51: port@51 { 772 reg = <51>; 773 microchip,bandwidth = <10000>; 774 phys = <&serdes 20>; 775 phy-mode = "10gbase-r"; 776 sfp = <&sfp_eth51>; 777 microchip,sd-sgpio = <329>; 778 managed = "in-band-status"; 779 }; 780 port52: port@52 { 781 reg = <52>; 782 microchip,bandwidth = <10000>; 783 phys = <&serdes 21>; 784 phy-mode = "10gbase-r"; 785 sfp = <&sfp_eth52>; 786 microchip,sd-sgpio = <333>; 787 managed = "in-band-status"; 788 }; 789 port53: port@53 { 790 reg = <53>; 791 microchip,bandwidth = <10000>; 792 phys = <&serdes 22>; 793 phy-mode = "10gbase-r"; 794 sfp = <&sfp_eth53>; 795 microchip,sd-sgpio = <337>; 796 managed = "in-band-status"; 797 }; 798 port54: port@54 { 799 reg = <54>; 800 microchip,bandwidth = <10000>; 801 phys = <&serdes 23>; 802 phy-mode = "10gbase-r"; 803 sfp = <&sfp_eth54>; 804 microchip,sd-sgpio = <341>; 805 managed = "in-band-status"; 806 }; 807 port55: port@55 { 808 reg = <55>; 809 microchip,bandwidth = <10000>; 810 phys = <&serdes 24>; 811 phy-mode = "10gbase-r"; 812 sfp = <&sfp_eth55>; 813 microchip,sd-sgpio = <345>; 814 managed = "in-band-status"; 815 }; 816 /* 25G SFPs */ 817 port56: port@56 { 818 reg = <56>; 819 microchip,bandwidth = <10000>; 820 phys = <&serdes 25>; 821 phy-mode = "10gbase-r"; 822 sfp = <&sfp_eth56>; 823 microchip,sd-sgpio = <349>; 824 managed = "in-band-status"; 825 }; 826 port57: port@57 { 827 reg = <57>; 828 microchip,bandwidth = <10000>; 829 phys = <&serdes 26>; 830 phy-mode = "10gbase-r"; 831 sfp = <&sfp_eth57>; 832 microchip,sd-sgpio = <353>; 833 managed = "in-band-status"; 834 }; 835 port58: port@58 { 836 reg = <58>; 837 microchip,bandwidth = <10000>; 838 phys = <&serdes 27>; 839 phy-mode = "10gbase-r"; 840 sfp = <&sfp_eth58>; 841 microchip,sd-sgpio = <357>; 842 managed = "in-band-status"; 843 }; 844 port59: port@59 { 845 reg = <59>; 846 microchip,bandwidth = <10000>; 847 phys = <&serdes 28>; 848 phy-mode = "10gbase-r"; 849 sfp = <&sfp_eth59>; 850 microchip,sd-sgpio = <361>; 851 managed = "in-band-status"; 852 }; 853 port60: port@60 { 854 reg = <60>; 855 microchip,bandwidth = <10000>; 856 phys = <&serdes 29>; 857 phy-mode = "10gbase-r"; 858 sfp = <&sfp_eth60>; 859 microchip,sd-sgpio = <365>; 860 managed = "in-band-status"; 861 }; 862 port61: port@61 { 863 reg = <61>; 864 microchip,bandwidth = <10000>; 865 phys = <&serdes 30>; 866 phy-mode = "10gbase-r"; 867 sfp = <&sfp_eth61>; 868 microchip,sd-sgpio = <369>; 869 managed = "in-band-status"; 870 }; 871 port62: port@62 { 872 reg = <62>; 873 microchip,bandwidth = <10000>; 874 phys = <&serdes 31>; 875 phy-mode = "10gbase-r"; 876 sfp = <&sfp_eth62>; 877 microchip,sd-sgpio = <373>; 878 managed = "in-band-status"; 879 }; 880 port63: port@63 { 881 reg = <63>; 882 microchip,bandwidth = <10000>; 883 phys = <&serdes 32>; 884 phy-mode = "10gbase-r"; 885 sfp = <&sfp_eth63>; 886 microchip,sd-sgpio = <377>; 887 managed = "in-band-status"; 888 }; 889 /* Finally the Management interface */ 890 port64: port@64 { 891 reg = <64>; 892 microchip,bandwidth = <1000>; 893 phys = <&serdes 0>; 894 phy-handle = <&phy64>; 895 phy-mode = "sgmii"; 896 }; 897 }; 898}; 899