xref: /linux/arch/arm64/boot/dts/microchip/sparx5.dtsi (revision 6694aee00a4b478d2dd82837f39b5dc9cbedfbcf)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/ {
10	compatible = "microchip,sparx5";
11	interrupt-parent = <&gic>;
12	#address-cells = <2>;
13	#size-cells = <1>;
14
15	aliases {
16		serial0 = &uart0;
17		serial1 = &uart1;
18	};
19
20	chosen {
21		stdout-path = "serial0:115200n8";
22	};
23
24	cpus {
25		#address-cells = <2>;
26		#size-cells = <0>;
27		cpu-map {
28			cluster0 {
29				core0 {
30					cpu = <&cpu0>;
31				};
32				core1 {
33					cpu = <&cpu1>;
34				};
35			};
36		};
37		cpu0: cpu@0 {
38			compatible = "arm,cortex-a53";
39			device_type = "cpu";
40			reg = <0x0 0x0>;
41			enable-method = "psci";
42			next-level-cache = <&L2_0>;
43		};
44		cpu1: cpu@1 {
45			compatible = "arm,cortex-a53";
46			device_type = "cpu";
47			reg = <0x0 0x1>;
48			enable-method = "psci";
49			next-level-cache = <&L2_0>;
50		};
51		L2_0: l2-cache0 {
52			compatible = "cache";
53		};
54	};
55
56	arm-pmu {
57		compatible = "arm,cortex-a53-pmu";
58		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
59		interrupt-affinity = <&cpu0>, <&cpu1>;
60	};
61
62	psci {
63		compatible = "arm,psci-0.2";
64		method = "smc";
65	};
66
67	timer {
68		compatible = "arm,armv8-timer";
69		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
70			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
71			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
72			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
73	};
74
75	clocks: clocks {
76		#address-cells = <2>;
77		#size-cells = <1>;
78		ranges;
79		ahb_clk: ahb-clk {
80			compatible = "fixed-clock";
81			#clock-cells = <0>;
82			clock-frequency = <250000000>;
83		};
84		sys_clk: sys-clk {
85			compatible = "fixed-clock";
86			#clock-cells = <0>;
87			clock-frequency = <625000000>;
88		};
89	};
90
91	axi: axi@600000000 {
92		compatible = "simple-bus";
93		#address-cells = <2>;
94		#size-cells = <1>;
95		ranges;
96
97		gic: interrupt-controller@600300000 {
98			compatible = "arm,gic-v3";
99			#interrupt-cells = <3>;
100			#address-cells = <2>;
101			#size-cells = <2>;
102			interrupt-controller;
103			reg = <0x6 0x00300000 0x10000>,	/* GIC Dist */
104			      <0x6 0x00340000 0xc0000>,	/* GICR */
105			      <0x6 0x00200000 0x2000>,	/* GICC */
106			      <0x6 0x00210000 0x2000>,  /* GICV */
107			      <0x6 0x00220000 0x2000>;  /* GICH */
108			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
109		};
110
111		uart0: serial@600100000 {
112			compatible = "ns16550a";
113			reg = <0x6 0x00100000 0x20>;
114			clocks = <&ahb_clk>;
115			reg-io-width = <4>;
116			reg-shift = <2>;
117			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
118
119			status = "disabled";
120		};
121
122		uart1: serial@600102000 {
123			compatible = "ns16550a";
124			reg = <0x6 0x00102000 0x20>;
125			clocks = <&ahb_clk>;
126			reg-io-width = <4>;
127			reg-shift = <2>;
128			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
129
130			status = "disabled";
131		};
132
133		timer1: timer@600105000 {
134			compatible = "snps,dw-apb-timer";
135			reg = <0x6 0x00105000 0x1000>;
136			clocks = <&ahb_clk>;
137			clock-names = "timer";
138			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
139		};
140
141	};
142};
143