1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. 4 */ 5 6#include <dt-bindings/dma/at91.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/mfd/at91-usart.h> 9#include <dt-bindings/mfd/atmel-flexcom.h> 10 11#include "clk-lan9691.h" 12 13/ { 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 model = "Microchip LAN969x"; 18 compatible = "microchip,lan9691"; 19 interrupt-parent = <&gic>; 20 21 clocks { 22 fx100_clk: fx100-clk { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <320000000>; 26 }; 27 28 cpu_clk: cpu-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <1000000000>; 32 }; 33 34 ddr_clk: ddr-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <600000000>; 38 }; 39 40 fabric_clk: fabric-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <250000000>; 44 }; 45 }; 46 47 cpus { 48 #address-cells = <2>; 49 #size-cells = <0>; 50 51 cpu0: cpu@0 { 52 compatible = "arm,cortex-a53"; 53 device_type = "cpu"; 54 reg = <0x0 0x0>; 55 next-level-cache = <&l2_0>; 56 }; 57 58 l2_0: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 cache-unified; 62 }; 63 }; 64 65 psci { 66 compatible = "arm,psci-1.0"; 67 method = "smc"; 68 }; 69 70 pmu { 71 compatible = "arm,cortex-a53-pmu"; 72 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 73 }; 74 75 timer { 76 compatible = "arm,armv8-timer"; 77 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Secure Phys IRQ */ 78 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Non-secure Phys IRQ */ 79 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virt IRQ */ 80 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hyp IRQ */ 81 }; 82 83 axi: axi { 84 compatible = "simple-bus"; 85 #address-cells = <1>; 86 #size-cells = <1>; 87 ranges; 88 89 usb: usb@300000 { 90 compatible = "microchip,lan9691-dwc3", "snps,dwc3"; 91 reg = <0x300000 0x80000>; 92 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 93 clocks = <&clks GCK_GATE_USB_DRD>, 94 <&clks GCK_ID_USB_REFCLK>; 95 clock-names = "bus_early", "ref"; 96 assigned-clocks = <&clks GCK_ID_USB_REFCLK>; 97 assigned-clock-rates = <60000000>; 98 maximum-speed = "high-speed"; 99 dr_mode = "host"; 100 status = "disabled"; 101 }; 102 103 otp: otp@e0021000 { 104 compatible = "microchip,lan9691-otpc"; 105 reg = <0xe0021000 0x1000>; 106 }; 107 108 flx0: flexcom@e0040000 { 109 compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; 110 reg = <0xe0040000 0x100>; 111 ranges = <0x0 0xe0040000 0x800>; 112 clocks = <&clks GCK_ID_FLEXCOM0>; 113 #address-cells = <1>; 114 #size-cells = <1>; 115 status = "disabled"; 116 117 usart0: serial@200 { 118 compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart"; 119 reg = <0x200 0x200>; 120 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 121 dmas = <&dma AT91_XDMAC_DT_PERID(3)>, 122 <&dma AT91_XDMAC_DT_PERID(2)>; 123 dma-names = "tx", "rx"; 124 clocks = <&fabric_clk>; 125 clock-names = "usart"; 126 atmel,fifo-size = <32>; 127 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 128 status = "disabled"; 129 }; 130 131 spi0: spi@400 { 132 compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi"; 133 reg = <0x400 0x200>; 134 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 135 dmas = <&dma AT91_XDMAC_DT_PERID(3)>, 136 <&dma AT91_XDMAC_DT_PERID(2)>; 137 dma-names = "tx", "rx"; 138 clocks = <&fabric_clk>; 139 clock-names = "spi_clk"; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 atmel,fifo-size = <32>; 143 status = "disabled"; 144 }; 145 146 i2c0: i2c@600 { 147 compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; 148 reg = <0x600 0x200>; 149 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 150 dmas = <&dma AT91_XDMAC_DT_PERID(3)>, 151 <&dma AT91_XDMAC_DT_PERID(2)>; 152 dma-names = "tx", "rx"; 153 clocks = <&fabric_clk>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 status = "disabled"; 157 }; 158 }; 159 160 flx1: flexcom@e0044000 { 161 compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; 162 reg = <0xe0044000 0x100>; 163 ranges = <0x0 0xe0044000 0x800>; 164 clocks = <&clks GCK_ID_FLEXCOM1>; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 status = "disabled"; 168 169 usart1: serial@200 { 170 compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart"; 171 reg = <0x200 0x200>; 172 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 173 dmas = <&dma AT91_XDMAC_DT_PERID(3)>, 174 <&dma AT91_XDMAC_DT_PERID(2)>; 175 dma-names = "tx", "rx"; 176 clocks = <&fabric_clk>; 177 clock-names = "usart"; 178 atmel,fifo-size = <32>; 179 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 180 status = "disabled"; 181 }; 182 183 spi1: spi@400 { 184 compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi"; 185 reg = <0x400 0x200>; 186 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 187 dmas = <&dma AT91_XDMAC_DT_PERID(3)>, 188 <&dma AT91_XDMAC_DT_PERID(2)>; 189 dma-names = "tx", "rx"; 190 clocks = <&fabric_clk>; 191 clock-names = "spi_clk"; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 atmel,fifo-size = <32>; 195 status = "disabled"; 196 }; 197 198 i2c1: i2c@600 { 199 compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; 200 reg = <0x600 0x200>; 201 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 202 dmas = <&dma AT91_XDMAC_DT_PERID(3)>, 203 <&dma AT91_XDMAC_DT_PERID(2)>; 204 dma-names = "tx", "rx"; 205 clocks = <&fabric_clk>; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 status = "disabled"; 209 }; 210 }; 211 212 trng: rng@e0048000 { 213 compatible = "microchip,lan9691-trng", "atmel,at91sam9g45-trng"; 214 reg = <0xe0048000 0x100>; 215 clocks = <&fabric_clk>; 216 status = "disabled"; 217 }; 218 219 aes: crypto@e004c000 { 220 compatible = "microchip,lan9691-aes", "atmel,at91sam9g46-aes"; 221 reg = <0xe004c000 0x100>; 222 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 223 dmas = <&dma AT91_XDMAC_DT_PERID(12)>, 224 <&dma AT91_XDMAC_DT_PERID(13)>; 225 dma-names = "tx", "rx"; 226 clocks = <&fabric_clk>; 227 clock-names = "aes_clk"; 228 status = "disabled"; 229 }; 230 231 flx2: flexcom@e0060000 { 232 compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; 233 reg = <0xe0060000 0x100>; 234 ranges = <0x0 0xe0060000 0x800>; 235 clocks = <&clks GCK_ID_FLEXCOM2>; 236 #address-cells = <1>; 237 #size-cells = <1>; 238 status = "disabled"; 239 240 usart2: serial@200 { 241 compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart"; 242 reg = <0x200 0x200>; 243 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 244 dmas = <&dma AT91_XDMAC_DT_PERID(7)>, 245 <&dma AT91_XDMAC_DT_PERID(6)>; 246 dma-names = "tx", "rx"; 247 clocks = <&fabric_clk>; 248 clock-names = "usart"; 249 atmel,fifo-size = <32>; 250 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 251 status = "disabled"; 252 }; 253 254 spi2: spi@400 { 255 compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi"; 256 reg = <0x400 0x200>; 257 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 258 dmas = <&dma AT91_XDMAC_DT_PERID(7)>, 259 <&dma AT91_XDMAC_DT_PERID(6)>; 260 dma-names = "tx", "rx"; 261 clocks = <&fabric_clk>; 262 clock-names = "spi_clk"; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 atmel,fifo-size = <32>; 266 status = "disabled"; 267 }; 268 269 i2c2: i2c@600 { 270 compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; 271 reg = <0x600 0x200>; 272 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 273 dmas = <&dma AT91_XDMAC_DT_PERID(7)>, 274 <&dma AT91_XDMAC_DT_PERID(6)>; 275 dma-names = "tx", "rx"; 276 clocks = <&fabric_clk>; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 status = "disabled"; 280 }; 281 }; 282 283 flx3: flexcom@e0064000 { 284 compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; 285 reg = <0xe0064000 0x100>; 286 ranges = <0x0 0xe0064000 0x800>; 287 clocks = <&clks GCK_ID_FLEXCOM3>; 288 #address-cells = <1>; 289 #size-cells = <1>; 290 status = "disabled"; 291 292 usart3: serial@200 { 293 compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart"; 294 reg = <0x200 0x200>; 295 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 296 dmas = <&dma AT91_XDMAC_DT_PERID(9)>, 297 <&dma AT91_XDMAC_DT_PERID(8)>; 298 dma-names = "tx", "rx"; 299 clocks = <&fabric_clk>; 300 clock-names = "usart"; 301 atmel,fifo-size = <32>; 302 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 303 status = "disabled"; 304 }; 305 306 spi3: spi@400 { 307 compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi"; 308 reg = <0x400 0x200>; 309 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 310 dmas = <&dma AT91_XDMAC_DT_PERID(9)>, 311 <&dma AT91_XDMAC_DT_PERID(8)>; 312 dma-names = "tx", "rx"; 313 clocks = <&fabric_clk>; 314 clock-names = "spi_clk"; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 atmel,fifo-size = <32>; 318 status = "disabled"; 319 }; 320 321 i2c3: i2c@600 { 322 compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; 323 reg = <0x600 0x200>; 324 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 325 dmas = <&dma AT91_XDMAC_DT_PERID(9)>, 326 <&dma AT91_XDMAC_DT_PERID(8)>; 327 dma-names = "tx", "rx"; 328 clocks = <&fabric_clk>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 status = "disabled"; 332 }; 333 }; 334 335 dma: dma-controller@e0068000 { 336 compatible = "microchip,lan9691-dma", "microchip,sama7g5-dma"; 337 reg = <0xe0068000 0x1000>; 338 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 339 dma-channels = <16>; 340 #dma-cells = <1>; 341 clocks = <&fabric_clk>; 342 clock-names = "dma_clk"; 343 }; 344 345 sha: crypto@e006c000 { 346 compatible = "microchip,lan9691-sha", "atmel,at91sam9g46-sha"; 347 reg = <0xe006c000 0xec>; 348 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 349 dmas = <&dma AT91_XDMAC_DT_PERID(14)>; 350 dma-names = "tx"; 351 clocks = <&fabric_clk>; 352 clock-names = "sha_clk"; 353 status = "disabled"; 354 }; 355 356 timer: timer@e008c000 { 357 compatible = "snps,dw-apb-timer"; 358 reg = <0xe008c000 0x400>; 359 clocks = <&fabric_clk>; 360 clock-names = "timer"; 361 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 362 status = "disabled"; 363 }; 364 365 watchdog: watchdog@e0090000 { 366 compatible = "snps,dw-wdt"; 367 reg = <0xe0090000 0x1000>; 368 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&fabric_clk>; 370 }; 371 372 cpu_ctrl: syscon@e00c0000 { 373 compatible = "microchip,lan966x-cpu-syscon", "syscon"; 374 reg = <0xe00c0000 0x350>; 375 }; 376 377 switch: switch@e00c0000 { 378 compatible = "microchip,lan9691-switch"; 379 reg = <0xe00c0000 0x0010000>, 380 <0xe2010000 0x1410000>; 381 reg-names = "cpu", "devices"; 382 interrupt-names = "xtr", "fdma", "ptp"; 383 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 386 resets = <&reset 0>; 387 reset-names = "switch"; 388 status = "disabled"; 389 }; 390 391 clks: clock-controller@e00c00b4 { 392 compatible = "microchip,lan9691-gck"; 393 reg = <0xe00c00b4 0x30>, <0xe00c0308 0x4>; 394 #clock-cells = <1>; 395 clocks = <&cpu_clk>, <&ddr_clk>, <&fx100_clk>; 396 clock-names = "cpu", "ddr", "sys"; 397 }; 398 399 qspi0: spi@e0804000 { 400 compatible = "microchip,lan9691-qspi"; 401 reg = <0xe0804000 0x00000100>, 402 <0x20000000 0x08000000>; 403 reg-names = "qspi_base", "qspi_mmap"; 404 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&fabric_clk>, <&clks GCK_ID_QSPI0>; 406 clock-names = "pclk", "gclk"; 407 assigned-clocks = <&clks GCK_ID_QSPI0>; 408 assigned-clock-rates = <100000000>; 409 dmas = <&dma AT91_XDMAC_DT_PERID(1)>, 410 <&dma AT91_XDMAC_DT_PERID(0)>; 411 dma-names = "tx", "rx"; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 status = "disabled"; 415 }; 416 417 qspi2: spi@e0834000 { 418 compatible = "microchip,lan9691-qspi"; 419 reg = <0xe0834000 0x00000100>, 420 <0x30000000 0x04000000>; 421 reg-names = "qspi_base", "qspi_mmap"; 422 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&fabric_clk>, <&clks GCK_ID_QSPI2>; 424 clock-names = "pclk", "gclk"; 425 assigned-clocks = <&clks GCK_ID_QSPI2>; 426 assigned-clock-rates = <100000000>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 status = "disabled"; 430 }; 431 432 reset: reset-controller@e201000c { 433 compatible = "microchip,lan9691-switch-reset", 434 "microchip,lan966x-switch-reset"; 435 reg = <0xe201000c 0x4>; 436 reg-names = "gcb"; 437 #reset-cells = <1>; 438 cpu-syscon = <&cpu_ctrl>; 439 }; 440 441 gpio: pinctrl@e20100d4 { 442 compatible = "microchip,lan9691-pinctrl"; 443 reg = <0xe20100d4 0xd4>, 444 <0xe2010370 0xa8>; 445 gpio-controller; 446 #gpio-cells = <2>; 447 gpio-ranges = <&gpio 0 0 66>; 448 interrupt-controller; 449 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 450 #interrupt-cells = <2>; 451 }; 452 453 mdio0: mdio@e20101a8 { 454 compatible = "microchip,lan9691-miim", "mscc,ocelot-miim"; 455 reg = <0xe20101a8 0x24>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 clocks = <&fx100_clk>; 459 status = "disabled"; 460 }; 461 462 mdio1: mdio@e20101cc { 463 compatible = "microchip,lan9691-miim", "mscc,ocelot-miim"; 464 reg = <0xe20101cc 0x24>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 clocks = <&fx100_clk>; 468 status = "disabled"; 469 }; 470 471 sgpio: gpio@e2010230 { 472 compatible = "microchip,lan9691-sgpio", "microchip,sparx5-sgpio"; 473 reg = <0xe2010230 0x118>; 474 clocks = <&fx100_clk>; 475 resets = <&reset 0>; 476 reset-names = "switch"; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 status = "disabled"; 480 481 sgpio_in: gpio@0 { 482 compatible = "microchip,lan9691-sgpio-bank", 483 "microchip,sparx5-sgpio-bank"; 484 reg = <0>; 485 gpio-controller; 486 #gpio-cells = <3>; 487 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 488 interrupt-controller; 489 #interrupt-cells = <3>; 490 }; 491 492 sgpio_out: gpio@1 { 493 compatible = "microchip,lan9691-sgpio-bank", 494 "microchip,sparx5-sgpio-bank"; 495 reg = <1>; 496 gpio-controller; 497 #gpio-cells = <3>; 498 }; 499 }; 500 501 tmon: hwmon@e2020100 { 502 compatible = "microchip,lan9691-temp", "microchip,sparx5-temp"; 503 reg = <0xe2020100 0xc>; 504 clocks = <&fx100_clk>; 505 #thermal-sensor-cells = <0>; 506 }; 507 508 serdes: serdes@e3410000 { 509 compatible = "microchip,lan9691-serdes"; 510 reg = <0xe3410000 0x150000>; 511 #phy-cells = <1>; 512 clocks = <&fabric_clk>; 513 }; 514 515 gic: interrupt-controller@e8c11000 { 516 compatible = "arm,gic-400"; 517 reg = <0xe8c11000 0x1000>, /* Distributor GICD_ */ 518 <0xe8c12000 0x2000>, /* CPU interface GICC_ */ 519 <0xe8c14000 0x2000>, /* Virt interface control */ 520 <0xe8c16000 0x2000>; /* Virt CPU interface */ 521 #interrupt-cells = <3>; 522 interrupt-controller; 523 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 524 }; 525 }; 526}; 527