1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Copyright (c) 2019 BayLibre, SAS. 5 * Author: Fabien Parent <fparent@baylibre.com> 6 */ 7 8#include <dt-bindings/clock/mt8516-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/phy/phy.h> 12 13#include "mt8516-pinfunc.h" 14 15/ { 16 compatible = "mediatek,mt8516"; 17 interrupt-parent = <&sysirq>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cluster0_opp: opp-table-0 { 22 compatible = "operating-points-v2"; 23 opp-shared; 24 opp-598000000 { 25 opp-hz = /bits/ 64 <598000000>; 26 opp-microvolt = <1150000>; 27 }; 28 opp-747500000 { 29 opp-hz = /bits/ 64 <747500000>; 30 opp-microvolt = <1150000>; 31 }; 32 opp-1040000000 { 33 opp-hz = /bits/ 64 <1040000000>; 34 opp-microvolt = <1200000>; 35 }; 36 opp-1196000000 { 37 opp-hz = /bits/ 64 <1196000000>; 38 opp-microvolt = <1250000>; 39 }; 40 opp-1300000000 { 41 opp-hz = /bits/ 64 <1300000000>; 42 opp-microvolt = <1300000>; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a35"; 53 reg = <0x0>; 54 enable-method = "psci"; 55 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, 56 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; 57 clocks = <&infracfg CLK_IFR_MUX1_SEL>, 58 <&topckgen CLK_TOP_MAINPLL_D2>; 59 clock-names = "cpu", "intermediate"; 60 operating-points-v2 = <&cluster0_opp>; 61 }; 62 63 cpu1: cpu@1 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a35"; 66 reg = <0x1>; 67 enable-method = "psci"; 68 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, 69 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; 70 clocks = <&infracfg CLK_IFR_MUX1_SEL>, 71 <&topckgen CLK_TOP_MAINPLL_D2>; 72 clock-names = "cpu", "intermediate"; 73 operating-points-v2 = <&cluster0_opp>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a35"; 79 reg = <0x2>; 80 enable-method = "psci"; 81 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, 82 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; 83 clocks = <&infracfg CLK_IFR_MUX1_SEL>, 84 <&topckgen CLK_TOP_MAINPLL_D2>; 85 clock-names = "cpu", "intermediate"; 86 operating-points-v2 = <&cluster0_opp>; 87 }; 88 89 cpu3: cpu@3 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a35"; 92 reg = <0x3>; 93 enable-method = "psci"; 94 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, 95 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; 96 clocks = <&infracfg CLK_IFR_MUX1_SEL>, 97 <&topckgen CLK_TOP_MAINPLL_D2>; 98 clock-names = "cpu", "intermediate", "armpll"; 99 operating-points-v2 = <&cluster0_opp>; 100 }; 101 102 idle-states { 103 entry-method = "psci"; 104 105 CPU_SLEEP_0_0: cpu-sleep-0-0 { 106 compatible = "arm,idle-state"; 107 entry-latency-us = <600>; 108 exit-latency-us = <600>; 109 min-residency-us = <1200>; 110 arm,psci-suspend-param = <0x0010000>; 111 }; 112 113 CLUSTER_SLEEP_0: cluster-sleep-0 { 114 compatible = "arm,idle-state"; 115 entry-latency-us = <800>; 116 exit-latency-us = <1000>; 117 min-residency-us = <2000>; 118 arm,psci-suspend-param = <0x2010000>; 119 }; 120 }; 121 }; 122 123 psci { 124 compatible = "arm,psci-1.0"; 125 method = "smc"; 126 }; 127 128 clk26m: clk26m { 129 compatible = "fixed-clock"; 130 #clock-cells = <0>; 131 clock-frequency = <26000000>; 132 clock-output-names = "clk26m"; 133 }; 134 135 clk32k: clk32k { 136 compatible = "fixed-clock"; 137 #clock-cells = <0>; 138 clock-frequency = <32000>; 139 clock-output-names = "clk32k"; 140 }; 141 142 reserved-memory { 143 #address-cells = <2>; 144 #size-cells = <2>; 145 ranges; 146 147 /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ 148 bl31_secmon_reserved: secmon@43000000 { 149 no-map; 150 reg = <0 0x43000000 0 0x20000>; 151 }; 152 }; 153 154 timer { 155 compatible = "arm,armv8-timer"; 156 interrupt-parent = <&gic>; 157 interrupts = <GIC_PPI 13 158 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 159 <GIC_PPI 14 160 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 161 <GIC_PPI 11 162 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 163 <GIC_PPI 10 164 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 165 }; 166 167 pmu { 168 compatible = "arm,armv8-pmuv3"; 169 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>, 170 <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>, 171 <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>, 172 <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>; 173 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 174 }; 175 176 soc { 177 #address-cells = <2>; 178 #size-cells = <2>; 179 compatible = "simple-bus"; 180 ranges; 181 182 topckgen: topckgen@10000000 { 183 compatible = "mediatek,mt8516-topckgen", "syscon"; 184 reg = <0 0x10000000 0 0x1000>; 185 #clock-cells = <1>; 186 }; 187 188 infracfg: infracfg@10001000 { 189 compatible = "mediatek,mt8516-infracfg", "syscon"; 190 reg = <0 0x10001000 0 0x1000>; 191 #clock-cells = <1>; 192 }; 193 194 pericfg: pericfg@10003050 { 195 compatible = "mediatek,mt8516-pericfg", "syscon"; 196 reg = <0 0x10003050 0 0x1000>; 197 }; 198 199 apmixedsys: apmixedsys@10018000 { 200 compatible = "mediatek,mt8516-apmixedsys", "syscon"; 201 reg = <0 0x10018000 0 0x710>; 202 #clock-cells = <1>; 203 }; 204 205 toprgu: toprgu@10007000 { 206 compatible = "mediatek,mt8516-wdt", 207 "mediatek,mt6589-wdt"; 208 reg = <0 0x10007000 0 0x1000>; 209 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>; 210 #reset-cells = <1>; 211 }; 212 213 timer: timer@10008000 { 214 compatible = "mediatek,mt8516-timer", 215 "mediatek,mt6577-timer"; 216 reg = <0 0x10008000 0 0x1000>; 217 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 218 clocks = <&topckgen CLK_TOP_CLK26M_D2>, 219 <&topckgen CLK_TOP_APXGPT>; 220 clock-names = "clk13m", "bus"; 221 }; 222 223 syscfg_pctl: syscfg-pctl@10005000 { 224 compatible = "syscon"; 225 reg = <0 0x10005000 0 0x1000>; 226 }; 227 228 pio: pinctrl@1000b000 { 229 compatible = "mediatek,mt8516-pinctrl"; 230 reg = <0 0x1000b000 0 0x1000>; 231 mediatek,pctl-regmap = <&syscfg_pctl>; 232 pins-are-numbered; 233 gpio-controller; 234 #gpio-cells = <2>; 235 interrupt-controller; 236 #interrupt-cells = <2>; 237 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 238 }; 239 240 pwrap: pwrap@1000f000 { 241 compatible = "mediatek,mt8516-pwrap"; 242 reg = <0 0x1000f000 0 0x1000>; 243 reg-names = "pwrap"; 244 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 245 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>, 246 <&topckgen CLK_TOP_PMICWRAP_AP>; 247 clock-names = "spi", "wrap"; 248 }; 249 250 sysirq: interrupt-controller@10200620 { 251 compatible = "mediatek,mt8516-sysirq", 252 "mediatek,mt6577-sysirq"; 253 interrupt-controller; 254 #interrupt-cells = <3>; 255 interrupt-parent = <&gic>; 256 reg = <0 0x10200620 0 0x20>; 257 }; 258 259 gic: interrupt-controller@10310000 { 260 compatible = "arm,gic-400"; 261 #interrupt-cells = <3>; 262 interrupt-parent = <&gic>; 263 interrupt-controller; 264 reg = <0 0x10310000 0 0x1000>, 265 <0 0x10320000 0 0x1000>, 266 <0 0x10340000 0 0x2000>, 267 <0 0x10360000 0 0x2000>; 268 interrupts = <GIC_PPI 9 269 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 270 }; 271 272 uart0: serial@11005000 { 273 compatible = "mediatek,mt8516-uart", 274 "mediatek,mt6577-uart"; 275 reg = <0 0x11005000 0 0x1000>; 276 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 277 clocks = <&topckgen CLK_TOP_UART0_SEL>, 278 <&topckgen CLK_TOP_UART0>; 279 clock-names = "baud", "bus"; 280 status = "disabled"; 281 }; 282 283 uart1: serial@11006000 { 284 compatible = "mediatek,mt8516-uart", 285 "mediatek,mt6577-uart"; 286 reg = <0 0x11006000 0 0x1000>; 287 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 288 clocks = <&topckgen CLK_TOP_UART1_SEL>, 289 <&topckgen CLK_TOP_UART1>; 290 clock-names = "baud", "bus"; 291 status = "disabled"; 292 }; 293 294 uart2: serial@11007000 { 295 compatible = "mediatek,mt8516-uart", 296 "mediatek,mt6577-uart"; 297 reg = <0 0x11007000 0 0x1000>; 298 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>; 299 clocks = <&topckgen CLK_TOP_UART2_SEL>, 300 <&topckgen CLK_TOP_UART2>; 301 clock-names = "baud", "bus"; 302 status = "disabled"; 303 }; 304 305 i2c0: i2c@11009000 { 306 compatible = "mediatek,mt8516-i2c", 307 "mediatek,mt2712-i2c"; 308 reg = <0 0x11009000 0 0x90>, 309 <0 0x11000180 0 0x80>; 310 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 311 clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, 312 <&infracfg CLK_IFR_I2C0_SEL>, 313 <&topckgen CLK_TOP_I2C0>, 314 <&topckgen CLK_TOP_APDMA>; 315 clock-names = "main-source", 316 "main-sel", 317 "main", 318 "dma"; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 status = "disabled"; 322 }; 323 324 i2c1: i2c@1100a000 { 325 compatible = "mediatek,mt8516-i2c", 326 "mediatek,mt2712-i2c"; 327 reg = <0 0x1100a000 0 0x90>, 328 <0 0x11000200 0 0x80>; 329 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 330 clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, 331 <&infracfg CLK_IFR_I2C1_SEL>, 332 <&topckgen CLK_TOP_I2C1>, 333 <&topckgen CLK_TOP_APDMA>; 334 clock-names = "main-source", 335 "main-sel", 336 "main", 337 "dma"; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 status = "disabled"; 341 }; 342 343 i2c2: i2c@1100b000 { 344 compatible = "mediatek,mt8516-i2c", 345 "mediatek,mt2712-i2c"; 346 reg = <0 0x1100b000 0 0x90>, 347 <0 0x11000280 0 0x80>; 348 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 349 clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, 350 <&infracfg CLK_IFR_I2C2_SEL>, 351 <&topckgen CLK_TOP_I2C2>, 352 <&topckgen CLK_TOP_APDMA>; 353 clock-names = "main-source", 354 "main-sel", 355 "main", 356 "dma"; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 status = "disabled"; 360 }; 361 362 spi: spi@1100c000 { 363 compatible = "mediatek,mt8516-spi", 364 "mediatek,mt2712-spi"; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 reg = <0 0x1100c000 0 0x1000>; 368 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>; 369 clocks = <&topckgen CLK_TOP_UNIVPLL_D12>, 370 <&topckgen CLK_TOP_SPI_SEL>, 371 <&topckgen CLK_TOP_SPI>; 372 clock-names = "parent-clk", "sel-clk", "spi-clk"; 373 status = "disabled"; 374 }; 375 376 mmc0: mmc@11120000 { 377 compatible = "mediatek,mt8516-mmc"; 378 reg = <0 0x11120000 0 0x1000>; 379 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 380 clocks = <&topckgen CLK_TOP_MSDC0>, 381 <&topckgen CLK_TOP_AHB_INFRA_SEL>, 382 <&topckgen CLK_TOP_MSDC0_INFRA>; 383 clock-names = "source", "hclk", "source_cg"; 384 status = "disabled"; 385 }; 386 387 mmc1: mmc@11130000 { 388 compatible = "mediatek,mt8516-mmc"; 389 reg = <0 0x11130000 0 0x1000>; 390 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 391 clocks = <&topckgen CLK_TOP_MSDC1>, 392 <&topckgen CLK_TOP_AHB_INFRA_SEL>, 393 <&topckgen CLK_TOP_MSDC1_INFRA>; 394 clock-names = "source", "hclk", "source_cg"; 395 status = "disabled"; 396 }; 397 398 mmc2: mmc@11170000 { 399 compatible = "mediatek,mt8516-mmc"; 400 reg = <0 0x11170000 0 0x1000>; 401 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>; 402 clocks = <&topckgen CLK_TOP_MSDC2>, 403 <&topckgen CLK_TOP_RG_MSDC2>, 404 <&topckgen CLK_TOP_MSDC2_INFRA>; 405 clock-names = "source", "hclk", "source_cg"; 406 status = "disabled"; 407 }; 408 409 ethernet: ethernet@11180000 { 410 compatible = "mediatek,mt8516-eth"; 411 reg = <0 0x11180000 0 0x1000>; 412 mediatek,pericfg = <&pericfg>; 413 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>; 414 clocks = <&topckgen CLK_TOP_RG_ETH>, 415 <&topckgen CLK_TOP_66M_ETH>, 416 <&topckgen CLK_TOP_133M_ETH>; 417 clock-names = "core", "reg", "trans"; 418 status = "disabled"; 419 }; 420 421 rng: rng@1020c000 { 422 compatible = "mediatek,mt8516-rng", 423 "mediatek,mt7623-rng"; 424 reg = <0 0x1020c000 0 0x100>; 425 clocks = <&topckgen CLK_TOP_TRNG>; 426 clock-names = "rng"; 427 }; 428 429 pwm: pwm@11008000 { 430 compatible = "mediatek,mt8516-pwm"; 431 reg = <0 0x11008000 0 0x1000>; 432 #pwm-cells = <2>; 433 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 434 clocks = <&topckgen CLK_TOP_PWM>, 435 <&topckgen CLK_TOP_PWM_B>, 436 <&topckgen CLK_TOP_PWM1_FB>, 437 <&topckgen CLK_TOP_PWM2_FB>, 438 <&topckgen CLK_TOP_PWM3_FB>, 439 <&topckgen CLK_TOP_PWM4_FB>, 440 <&topckgen CLK_TOP_PWM5_FB>; 441 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 442 "pwm4", "pwm5"; 443 }; 444 445 usb0: usb@11100000 { 446 compatible = "mediatek,mtk-musb"; 447 reg = <0 0x11100000 0 0x1000>; 448 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 449 interrupt-names = "mc"; 450 phys = <&usb0_port PHY_TYPE_USB2>; 451 clocks = <&topckgen CLK_TOP_USB>, 452 <&topckgen CLK_TOP_USBIF>, 453 <&topckgen CLK_TOP_USB_1P>; 454 clock-names = "main","mcu","univpll"; 455 status = "disabled"; 456 }; 457 458 usb0_phy: usb@11110000 { 459 compatible = "mediatek,generic-tphy-v1"; 460 reg = <0 0x11110000 0 0x800>; 461 #address-cells = <2>; 462 #size-cells = <2>; 463 ranges; 464 status = "disabled"; 465 466 usb0_port: usb-phy@11110800 { 467 reg = <0 0x11110800 0 0x100>; 468 clocks = <&topckgen CLK_TOP_USB_PHY48M>; 469 clock-names = "ref"; 470 #phy-cells = <1>; 471 }; 472 }; 473 }; 474}; 475