1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2023 MediaTek Inc. 4 * Author: Ben Lok <ben.lok@mediatek.com> 5 * Macpaul Lin <macpaul.lin@mediatek.com> 6 */ 7/dts-v1/; 8 9#include "mt8195.dtsi" 10#include "mt6359.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/regulator/mediatek,mt6360-regulator.h> 16#include <dt-bindings/spmi/spmi.h> 17#include <dt-bindings/usb/pd.h> 18 19/ { 20 model = "MediaTek Genio 1200 EVK-P1V2-EMMC"; 21 compatible = "mediatek,mt8395-evk", "mediatek,mt8395", 22 "mediatek,mt8195"; 23 24 aliases { 25 serial0 = &uart0; 26 ethernet0 = ð 27 }; 28 29 chosen { 30 stdout-path = "serial0:921600n8"; 31 }; 32 33 firmware { 34 optee { 35 compatible = "linaro,optee-tz"; 36 method = "smc"; 37 }; 38 }; 39 40 memory@40000000 { 41 device_type = "memory"; 42 reg = <0 0x40000000 0x2 0x00000000>; 43 }; 44 45 reserved-memory { 46 #address-cells = <2>; 47 #size-cells = <2>; 48 ranges; 49 50 /* 51 * 12 MiB reserved for OP-TEE (BL32) 52 * +-----------------------+ 0x43e0_0000 53 * | SHMEM 2MiB | 54 * +-----------------------+ 0x43c0_0000 55 * | | TA_RAM 8MiB | 56 * + TZDRAM +--------------+ 0x4340_0000 57 * | | TEE_RAM 2MiB | 58 * +-----------------------+ 0x4320_0000 59 */ 60 optee_reserved: optee@43200000 { 61 no-map; 62 reg = <0 0x43200000 0 0x00c00000>; 63 }; 64 65 scp_mem: memory@50000000 { 66 compatible = "shared-dma-pool"; 67 reg = <0 0x50000000 0 0x2900000>; 68 no-map; 69 }; 70 71 vpu_mem: memory@53000000 { 72 compatible = "shared-dma-pool"; 73 reg = <0 0x53000000 0 0x1400000>; /* 20 MB */ 74 }; 75 76 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ 77 bl31_secmon_mem: memory@54600000 { 78 no-map; 79 reg = <0 0x54600000 0x0 0x200000>; 80 }; 81 82 snd_dma_mem: memory@60000000 { 83 compatible = "shared-dma-pool"; 84 reg = <0 0x60000000 0 0x1100000>; 85 no-map; 86 }; 87 88 apu_mem: memory@62000000 { 89 compatible = "shared-dma-pool"; 90 reg = <0 0x62000000 0 0x1400000>; /* 20 MB */ 91 }; 92 }; 93 94 backlight_lcd0: backlight-lcd0 { 95 compatible = "pwm-backlight"; 96 pwms = <&disp_pwm0 0 500000>; 97 enable-gpios = <&pio 47 GPIO_ACTIVE_HIGH>; 98 brightness-levels = <0 1023>; 99 num-interpolated-steps = <1023>; 100 default-brightness-level = <576>; 101 }; 102 103 backlight_lcd1: backlight-lcd1 { 104 compatible = "pwm-backlight"; 105 pwms = <&disp_pwm1 0 500000>; 106 enable-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; 107 brightness-levels = <0 1023>; 108 num-interpolated-steps = <1023>; 109 default-brightness-level = <576>; 110 }; 111 112 can_clk: can-clk { 113 compatible = "fixed-clock"; 114 #clock-cells = <0>; 115 clock-frequency = <20000000>; 116 clock-output-names = "can-clk"; 117 }; 118 119 edp_panel_fixed_3v3: regulator-0 { 120 compatible = "regulator-fixed"; 121 regulator-name = "edp_panel_3v3"; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 enable-active-high; 125 gpio = <&pio 6 GPIO_ACTIVE_HIGH>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&edp_panel_3v3_en_pins>; 128 }; 129 130 edp_panel_fixed_12v: regulator-1 { 131 compatible = "regulator-fixed"; 132 regulator-name = "edp_backlight_12v"; 133 regulator-min-microvolt = <12000000>; 134 regulator-max-microvolt = <12000000>; 135 enable-active-high; 136 gpio = <&pio 96 GPIO_ACTIVE_HIGH>; 137 pinctrl-names = "default"; 138 pinctrl-0 = <&edp_panel_12v_en_pins>; 139 }; 140 141 keys: gpio-keys { 142 compatible = "gpio-keys"; 143 144 button-volume-up { 145 wakeup-source; 146 debounce-interval = <100>; 147 gpios = <&pio 106 GPIO_ACTIVE_LOW>; 148 label = "volume_up"; 149 linux,code = <KEY_VOLUMEUP>; 150 }; 151 }; 152 153 wifi_fixed_3v3: regulator-2 { 154 compatible = "regulator-fixed"; 155 regulator-name = "wifi_3v3"; 156 regulator-min-microvolt = <3300000>; 157 regulator-max-microvolt = <3300000>; 158 gpio = <&pio 135 GPIO_ACTIVE_HIGH>; 159 enable-active-high; 160 regulator-always-on; 161 }; 162}; 163 164&disp_pwm0 { 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pwm0_default_pins>; 167 status = "okay"; 168}; 169 170&dmic_codec { 171 wakeup-delay-ms = <200>; 172}; 173 174ð { 175 phy-mode ="rgmii-rxid"; 176 phy-handle = <ð_phy0>; 177 snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; 178 snps,reset-delays-us = <0 10000 10000>; 179 mediatek,tx-delay-ps = <2030>; 180 mediatek,mac-wol; 181 pinctrl-names = "default", "sleep"; 182 pinctrl-0 = <ð_default_pins>; 183 pinctrl-1 = <ð_sleep_pins>; 184 status = "okay"; 185 186 mdio { 187 compatible = "snps,dwmac-mdio"; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 eth_phy0: ethernet-phy@1 { 191 compatible = "ethernet-phy-id001c.c916"; 192 reg = <0x1>; 193 }; 194 }; 195}; 196 197&gpu { 198 mali-supply = <&mt6315_7_vbuck1>; 199 status = "okay"; 200}; 201 202&i2c0 { 203 clock-frequency = <400000>; 204 pinctrl-0 = <&i2c0_pins>; 205 pinctrl-names = "default"; 206 status = "okay"; 207}; 208 209&i2c1 { 210 clock-frequency = <400000>; 211 pinctrl-0 = <&i2c1_pins>; 212 pinctrl-names = "default"; 213 status = "okay"; 214 215 touchscreen@5d { 216 compatible = "goodix,gt9271"; 217 reg = <0x5d>; 218 interrupts-extended = <&pio 132 IRQ_TYPE_EDGE_RISING>; 219 irq-gpios = <&pio 132 GPIO_ACTIVE_HIGH>; 220 reset-gpios = <&pio 133 GPIO_ACTIVE_HIGH>; 221 AVDD28-supply = <&mt6360_ldo1>; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&touch_pins>; 224 }; 225}; 226 227&i2c2 { 228 clock-frequency = <400000>; 229 pinctrl-0 = <&i2c2_pins>; 230 pinctrl-names = "default"; 231 status = "okay"; 232}; 233 234&i2c6 { 235 clock-frequency = <400000>; 236 pinctrl-0 = <&i2c6_pins>; 237 pinctrl-names = "default"; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 status = "okay"; 241 242 mt6360: pmic@34 { 243 compatible = "mediatek,mt6360"; 244 reg = <0x34>; 245 interrupt-parent = <&pio>; 246 interrupts = <128 IRQ_TYPE_EDGE_FALLING>; 247 interrupt-names = "IRQB"; 248 interrupt-controller; 249 #interrupt-cells = <1>; 250 pinctrl-0 = <&mt6360_pins>; 251 252 charger { 253 compatible = "mediatek,mt6360-chg"; 254 richtek,vinovp-microvolt = <14500000>; 255 256 otg_vbus_regulator: usb-otg-vbus-regulator { 257 regulator-name = "usb-otg-vbus"; 258 regulator-min-microvolt = <4425000>; 259 regulator-max-microvolt = <5825000>; 260 }; 261 }; 262 263 regulator { 264 compatible = "mediatek,mt6360-regulator"; 265 LDO_VIN3-supply = <&mt6360_buck2>; 266 267 mt6360_buck1: buck1 { 268 regulator-name = "emi_vdd2"; 269 regulator-min-microvolt = <300000>; 270 regulator-max-microvolt = <1300000>; 271 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 272 MT6360_OPMODE_LP 273 MT6360_OPMODE_ULP>; 274 regulator-always-on; 275 }; 276 277 mt6360_buck2: buck2 { 278 regulator-name = "emi_vddq"; 279 regulator-min-microvolt = <300000>; 280 regulator-max-microvolt = <1300000>; 281 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 282 MT6360_OPMODE_LP 283 MT6360_OPMODE_ULP>; 284 regulator-always-on; 285 }; 286 287 mt6360_ldo1: ldo1 { 288 regulator-name = "tp1_p3v0"; 289 regulator-min-microvolt = <3300000>; 290 regulator-max-microvolt = <3300000>; 291 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 292 MT6360_OPMODE_LP>; 293 regulator-always-on; 294 }; 295 296 mt6360_ldo2: ldo2 { 297 regulator-name = "panel1_p1v8"; 298 regulator-min-microvolt = <1800000>; 299 regulator-max-microvolt = <1800000>; 300 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 301 MT6360_OPMODE_LP>; 302 }; 303 304 mt6360_ldo3: ldo3 { 305 regulator-name = "vmc_pmu"; 306 regulator-min-microvolt = <1200000>; 307 regulator-max-microvolt = <3600000>; 308 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 309 MT6360_OPMODE_LP>; 310 }; 311 312 mt6360_ldo5: ldo5 { 313 regulator-name = "vmch_pmu"; 314 regulator-min-microvolt = <2700000>; 315 regulator-max-microvolt = <3600000>; 316 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 317 MT6360_OPMODE_LP>; 318 }; 319 320 /* This is a measure point, which name is mt6360_ldo1 on schematic */ 321 mt6360_ldo6: ldo6 { 322 regulator-name = "mt6360_ldo1"; 323 regulator-min-microvolt = <500000>; 324 regulator-max-microvolt = <2100000>; 325 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 326 MT6360_OPMODE_LP>; 327 }; 328 329 mt6360_ldo7: ldo7 { 330 regulator-name = "emi_vmddr_en"; 331 regulator-min-microvolt = <500000>; 332 regulator-max-microvolt = <2100000>; 333 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 334 MT6360_OPMODE_LP>; 335 regulator-always-on; 336 }; 337 }; 338 }; 339}; 340 341&mfg0 { 342 domain-supply = <&mt6315_7_vbuck1>; 343}; 344 345&mfg1 { 346 domain-supply = <&mt6359_vsram_others_ldo_reg>; 347}; 348 349&mmc0 { 350 status = "okay"; 351 pinctrl-names = "default", "state_uhs"; 352 pinctrl-0 = <&mmc0_default_pins>; 353 pinctrl-1 = <&mmc0_uhs_pins>; 354 bus-width = <8>; 355 max-frequency = <200000000>; 356 cap-mmc-highspeed; 357 mmc-hs200-1_8v; 358 mmc-hs400-1_8v; 359 cap-mmc-hw-reset; 360 no-sdio; 361 no-sd; 362 hs400-ds-delay = <0x14c11>; 363 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 364 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 365 non-removable; 366}; 367 368&mmc1 { 369 pinctrl-names = "default", "state_uhs"; 370 pinctrl-0 = <&mmc1_default_pins>; 371 pinctrl-1 = <&mmc1_uhs_pins>; 372 bus-width = <4>; 373 max-frequency = <200000000>; 374 cap-sd-highspeed; 375 sd-uhs-sdr50; 376 sd-uhs-sdr104; 377 no-mmc; 378 no-sdio; 379 vmmc-supply = <&mt6360_ldo5>; 380 vqmmc-supply = <&mt6360_ldo3>; 381 status = "okay"; 382 non-removable; 383}; 384 385&mt6359_vaud18_ldo_reg { 386 regulator-always-on; 387}; 388 389&mt6359_vbbck_ldo_reg { 390 regulator-always-on; 391}; 392 393/* For USB Hub */ 394&mt6359_vcamio_ldo_reg { 395 regulator-always-on; 396}; 397 398&mt6359_vcn33_2_bt_ldo_reg { 399 regulator-min-microvolt = <3300000>; 400 regulator-max-microvolt = <3300000>; 401}; 402 403&mt6359_vcore_buck_reg { 404 regulator-always-on; 405}; 406 407&mt6359_vgpu11_buck_reg { 408 regulator-always-on; 409}; 410 411&mt6359_vpu_buck_reg { 412 regulator-always-on; 413}; 414 415&mt6359_vrf12_ldo_reg { 416 regulator-always-on; 417}; 418 419/* for GPU SRAM */ 420&mt6359_vsram_others_ldo_reg { 421 regulator-min-microvolt = <750000>; 422 regulator-max-microvolt = <750000>; 423}; 424 425&mt6359codec { 426 mediatek,mic-type-0 = <1>; /* ACC */ 427 mediatek,mic-type-1 = <3>; /* DCC */ 428 mediatek,mic-type-2 = <1>; /* ACC */ 429}; 430 431&pcie0 { 432 pinctrl-names = "default", "idle"; 433 pinctrl-0 = <&pcie0_default_pins>; 434 pinctrl-1 = <&pcie0_idle_pins>; 435 status = "okay"; 436}; 437 438&pcie1 { 439 pinctrl-names = "default"; 440 pinctrl-0 = <&pcie1_default_pins>; 441 status = "disabled"; 442}; 443 444&pciephy { 445 status = "okay"; 446}; 447 448&pio { 449 audio_default_pins: audio-default-pins { 450 pins-cmd-dat { 451 pinmux = <PINMUX_GPIO61__FUNC_DMIC1_CLK>, 452 <PINMUX_GPIO62__FUNC_DMIC1_DAT>, 453 <PINMUX_GPIO65__FUNC_PCM_DO>, 454 <PINMUX_GPIO66__FUNC_PCM_CLK>, 455 <PINMUX_GPIO67__FUNC_PCM_DI>, 456 <PINMUX_GPIO68__FUNC_PCM_SYNC>, 457 <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>, 458 <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>, 459 <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>, 460 <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>, 461 <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>, 462 <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>, 463 <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>; 464 }; 465 }; 466 467 disp_pwm1_default_pins: disp-pwm1-default-pins { 468 pins1 { 469 pinmux = <PINMUX_GPIO104__FUNC_DISP_PWM1>; 470 }; 471 }; 472 473 edp_panel_12v_en_pins: edp-panel-12v-en-pins { 474 pins1 { 475 pinmux = <PINMUX_GPIO96__FUNC_GPIO96>; 476 output-high; 477 }; 478 }; 479 480 edp_panel_3v3_en_pins: edp-panel-3v3-en-pins { 481 pins1 { 482 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 483 output-high; 484 }; 485 }; 486 487 eth_default_pins: eth-default-pins { 488 pins-cc { 489 pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>, 490 <PINMUX_GPIO86__FUNC_GBE_RXC>, 491 <PINMUX_GPIO87__FUNC_GBE_RXDV>, 492 <PINMUX_GPIO88__FUNC_GBE_TXEN>; 493 drive-strength = <8>; 494 }; 495 496 pins-mdio { 497 pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>, 498 <PINMUX_GPIO90__FUNC_GBE_MDIO>; 499 input-enable; 500 }; 501 502 pins-power { 503 pinmux = <PINMUX_GPIO91__FUNC_GPIO91>, 504 <PINMUX_GPIO92__FUNC_GPIO92>; 505 output-high; 506 }; 507 508 pins-rxd { 509 pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>, 510 <PINMUX_GPIO82__FUNC_GBE_RXD2>, 511 <PINMUX_GPIO83__FUNC_GBE_RXD1>, 512 <PINMUX_GPIO84__FUNC_GBE_RXD0>; 513 }; 514 515 pins-txd { 516 pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>, 517 <PINMUX_GPIO78__FUNC_GBE_TXD2>, 518 <PINMUX_GPIO79__FUNC_GBE_TXD1>, 519 <PINMUX_GPIO80__FUNC_GBE_TXD0>; 520 drive-strength = <8>; 521 }; 522 }; 523 524 eth_sleep_pins: eth-sleep-pins { 525 pins-cc { 526 pinmux = <PINMUX_GPIO85__FUNC_GPIO85>, 527 <PINMUX_GPIO86__FUNC_GPIO86>, 528 <PINMUX_GPIO87__FUNC_GPIO87>, 529 <PINMUX_GPIO88__FUNC_GPIO88>; 530 }; 531 532 pins-mdio { 533 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>, 534 <PINMUX_GPIO90__FUNC_GPIO90>; 535 input-disable; 536 bias-disable; 537 }; 538 539 pins-rxd { 540 pinmux = <PINMUX_GPIO81__FUNC_GPIO81>, 541 <PINMUX_GPIO82__FUNC_GPIO82>, 542 <PINMUX_GPIO83__FUNC_GPIO83>, 543 <PINMUX_GPIO84__FUNC_GPIO84>; 544 }; 545 546 pins-txd { 547 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 548 <PINMUX_GPIO78__FUNC_GPIO78>, 549 <PINMUX_GPIO79__FUNC_GPIO79>, 550 <PINMUX_GPIO80__FUNC_GPIO80>; 551 }; 552 }; 553 554 gpio_key_pins: gpio-keys-pins { 555 pins { 556 pinmux = <PINMUX_GPIO106__FUNC_GPIO106>; 557 bias-pull-up; 558 input-enable; 559 }; 560 }; 561 562 i2c0_pins: i2c0-pins { 563 pins { 564 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 565 <PINMUX_GPIO9__FUNC_SCL0>; 566 bias-pull-up = <MTK_PULL_SET_RSEL_111>; 567 drive-strength-microamp = <1000>; 568 }; 569 }; 570 571 i2c1_pins: i2c1-pins { 572 pins { 573 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 574 <PINMUX_GPIO11__FUNC_SCL1>; 575 bias-pull-up = <MTK_PULL_SET_RSEL_111>; 576 drive-strength-microamp = <1000>; 577 }; 578 }; 579 580 i2c2_pins: i2c2-pins { 581 pins { 582 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 583 <PINMUX_GPIO13__FUNC_SCL2>; 584 bias-pull-up = <MTK_PULL_SET_RSEL_111>; 585 drive-strength = <6>; 586 }; 587 }; 588 589 i2c6_pins: i2c6-pins { 590 pins { 591 pinmux = <PINMUX_GPIO25__FUNC_SDA6>, 592 <PINMUX_GPIO26__FUNC_SCL6>; 593 bias-pull-up; 594 }; 595 }; 596 597 mmc0_default_pins: mmc0-default-pins { 598 pins-clk { 599 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 600 drive-strength = <6>; 601 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 602 }; 603 604 pins-cmd-dat { 605 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 606 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 607 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 608 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 609 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 610 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 611 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 612 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 613 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 614 input-enable; 615 drive-strength = <6>; 616 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 617 }; 618 619 pins-rst { 620 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 621 drive-strength = <6>; 622 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 623 }; 624 }; 625 626 mmc0_uhs_pins: mmc0-uhs-pins { 627 pins-clk { 628 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 629 drive-strength = <8>; 630 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 631 }; 632 633 pins-cmd-dat { 634 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 635 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 636 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 637 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 638 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 639 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 640 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 641 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 642 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 643 input-enable; 644 drive-strength = <8>; 645 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 646 }; 647 648 pins-ds { 649 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 650 drive-strength = <8>; 651 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 652 }; 653 654 pins-rst { 655 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 656 drive-strength = <8>; 657 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 658 }; 659 }; 660 661 mmc1_default_pins: mmc1-default-pins { 662 pins-clk { 663 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 664 drive-strength = <8>; 665 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 666 }; 667 668 pins-cmd-dat { 669 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 670 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 671 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 672 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 673 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 674 input-enable; 675 drive-strength = <8>; 676 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 677 }; 678 }; 679 680 mmc1_uhs_pins: mmc1-uhs-pins { 681 pins-clk { 682 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 683 drive-strength = <8>; 684 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 685 }; 686 687 pins-cmd-dat { 688 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 689 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 690 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 691 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 692 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 693 input-enable; 694 drive-strength = <8>; 695 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 696 }; 697 }; 698 699 mt6360_pins: mt6360-pins { 700 pins { 701 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>, 702 <PINMUX_GPIO128__FUNC_GPIO128>; 703 input-enable; 704 bias-pull-up; 705 }; 706 }; 707 708 pcie0_default_pins: pcie0-default-pins { 709 pins { 710 pinmux = <PINMUX_GPIO19__FUNC_WAKEN>, 711 <PINMUX_GPIO20__FUNC_PERSTN>, 712 <PINMUX_GPIO21__FUNC_CLKREQN>; 713 bias-pull-up; 714 }; 715 }; 716 717 pcie0_idle_pins: pcie0-idle-pins { 718 pins { 719 pinmux = <PINMUX_GPIO20__FUNC_GPIO20>; 720 bias-disable; 721 output-low; 722 }; 723 }; 724 725 pcie1_default_pins: pcie1-default-pins { 726 pins { 727 pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>, 728 <PINMUX_GPIO23__FUNC_CLKREQN_1>, 729 <PINMUX_GPIO24__FUNC_WAKEN_1>; 730 bias-pull-up; 731 }; 732 }; 733 734 pwm0_default_pins: pwm0-default-pins { 735 pins-cmd-dat { 736 pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM0>; 737 }; 738 }; 739 740 spi1_pins: spi1-pins { 741 pins { 742 pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>, 743 <PINMUX_GPIO137__FUNC_SPIM1_CLK>, 744 <PINMUX_GPIO138__FUNC_SPIM1_MO>, 745 <PINMUX_GPIO139__FUNC_SPIM1_MI>; 746 bias-disable; 747 }; 748 }; 749 750 spi2_pins: spi-pins { 751 pins { 752 pinmux = <PINMUX_GPIO140__FUNC_SPIM2_CSB>, 753 <PINMUX_GPIO141__FUNC_SPIM2_CLK>, 754 <PINMUX_GPIO142__FUNC_SPIM2_MO>, 755 <PINMUX_GPIO143__FUNC_SPIM2_MI>; 756 bias-disable; 757 }; 758 }; 759 760 touch_pins: touch-pins { 761 pins-irq { 762 pinmux = <PINMUX_GPIO132__FUNC_GPIO132>; 763 input-enable; 764 bias-disable; 765 }; 766 767 pins-reset { 768 pinmux = <PINMUX_GPIO133__FUNC_GPIO133>; 769 output-high; 770 }; 771 }; 772 773 uart0_pins: uart0-pins { 774 pins { 775 pinmux = <PINMUX_GPIO98__FUNC_UTXD0>, 776 <PINMUX_GPIO99__FUNC_URXD0>; 777 }; 778 }; 779 780 uart1_pins: uart1-pins { 781 pins { 782 pinmux = <PINMUX_GPIO100__FUNC_URTS1>, 783 <PINMUX_GPIO101__FUNC_UCTS1>, 784 <PINMUX_GPIO102__FUNC_UTXD1>, 785 <PINMUX_GPIO103__FUNC_URXD1>; 786 }; 787 }; 788}; 789 790&pmic { 791 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 792}; 793 794&scp { 795 memory-region = <&scp_mem>; 796 status = "okay"; 797}; 798 799&spi1 { 800 pinctrl-0 = <&spi1_pins>; 801 pinctrl-names = "default"; 802 mediatek,pad-select = <0>; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 status = "okay"; 806 cs-gpios = <&pio 64 GPIO_ACTIVE_LOW>; 807 808 can0: can@0 { 809 compatible = "microchip,mcp2518fd"; 810 reg = <0>; 811 clocks = <&can_clk>; 812 spi-max-frequency = <20000000>; 813 interrupts-extended = <&pio 16 IRQ_TYPE_LEVEL_LOW>; 814 vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>; 815 xceiver-supply = <&mt6359_vcn33_2_bt_ldo_reg>; 816 }; 817}; 818 819&spi2 { 820 pinctrl-0 = <&spi2_pins>; 821 pinctrl-names = "default"; 822 mediatek,pad-select = <0>; 823 #address-cells = <1>; 824 #size-cells = <0>; 825 status = "okay"; 826}; 827 828&spmi { 829 #address-cells = <2>; 830 #size-cells = <0>; 831 832 mt6315_6: pmic@6 { 833 compatible = "mediatek,mt6315-regulator"; 834 reg = <0x6 SPMI_USID>; 835 836 regulators { 837 mt6315_6_vbuck1: vbuck1 { 838 regulator-compatible = "vbuck1"; 839 regulator-name = "Vbcpu"; 840 regulator-min-microvolt = <300000>; 841 regulator-max-microvolt = <1193750>; 842 regulator-enable-ramp-delay = <256>; 843 regulator-allowed-modes = <0 1 2>; 844 regulator-always-on; 845 }; 846 }; 847 }; 848 849 mt6315_7: pmic@7 { 850 compatible = "mediatek,mt6315-regulator"; 851 reg = <0x7 SPMI_USID>; 852 853 regulators { 854 mt6315_7_vbuck1: vbuck1 { 855 regulator-compatible = "vbuck1"; 856 regulator-name = "Vgpu"; 857 regulator-min-microvolt = <546000>; 858 regulator-max-microvolt = <787000>; 859 regulator-enable-ramp-delay = <256>; 860 regulator-allowed-modes = <0 1 2>; 861 }; 862 }; 863 }; 864}; 865 866&u3phy0 { 867 status = "okay"; 868}; 869 870&u3phy1 { 871 status = "okay"; 872 873 u3port1: usb-phy@700 { 874 mediatek,force-mode; 875 }; 876}; 877 878&u3phy2 { 879 status = "okay"; 880}; 881 882&u3phy3 { 883 status = "okay"; 884}; 885 886&uart0 { 887 pinctrl-0 = <&uart0_pins>; 888 pinctrl-names = "default"; 889 status = "okay"; 890}; 891 892&uart1 { 893 pinctrl-0 = <&uart1_pins>; 894 pinctrl-names = "default"; 895 status = "okay"; 896}; 897 898&ufsphy { 899 status = "disabled"; 900}; 901 902&ssusb0 { 903 vusb33-supply = <&mt6359_vusb_ldo_reg>; 904 status = "okay"; 905}; 906 907&ssusb2 { 908 vusb33-supply = <&mt6359_vusb_ldo_reg>; 909 status = "okay"; 910}; 911 912&ssusb3 { 913 vusb33-supply = <&mt6359_vusb_ldo_reg>; 914 status = "okay"; 915}; 916 917&xhci0 { 918 status = "okay"; 919}; 920 921&xhci1 { 922 vusb33-supply = <&mt6359_vusb_ldo_reg>; 923 status = "okay"; 924}; 925 926&xhci2 { 927 status = "okay"; 928}; 929 930&xhci3 { 931 status = "okay"; 932}; 933