1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2023 MediaTek Inc. 4 * Author: Ben Lok <ben.lok@mediatek.com> 5 * Macpaul Lin <macpaul.lin@mediatek.com> 6 */ 7/dts-v1/; 8 9#include "mt8195.dtsi" 10#include "mt6359.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/regulator/mediatek,mt6360-regulator.h> 16#include <dt-bindings/spmi/spmi.h> 17#include <dt-bindings/usb/pd.h> 18 19/ { 20 model = "MediaTek Genio 1200 EVK-P1V2-EMMC"; 21 compatible = "mediatek,mt8395-evk", "mediatek,mt8395", 22 "mediatek,mt8195"; 23 24 aliases { 25 serial0 = &uart0; 26 ethernet0 = ð 27 }; 28 29 chosen { 30 stdout-path = "serial0:921600n8"; 31 }; 32 33 firmware { 34 optee { 35 compatible = "linaro,optee-tz"; 36 method = "smc"; 37 }; 38 }; 39 40 memory@40000000 { 41 device_type = "memory"; 42 reg = <0 0x40000000 0x2 0x00000000>; 43 }; 44 45 reserved-memory { 46 #address-cells = <2>; 47 #size-cells = <2>; 48 ranges; 49 50 /* 51 * 12 MiB reserved for OP-TEE (BL32) 52 * +-----------------------+ 0x43e0_0000 53 * | SHMEM 2MiB | 54 * +-----------------------+ 0x43c0_0000 55 * | | TA_RAM 8MiB | 56 * + TZDRAM +--------------+ 0x4340_0000 57 * | | TEE_RAM 2MiB | 58 * +-----------------------+ 0x4320_0000 59 */ 60 optee_reserved: optee@43200000 { 61 no-map; 62 reg = <0 0x43200000 0 0x00c00000>; 63 }; 64 65 scp_mem: memory@50000000 { 66 compatible = "shared-dma-pool"; 67 reg = <0 0x50000000 0 0x2900000>; 68 no-map; 69 }; 70 71 vpu_mem: memory@53000000 { 72 compatible = "shared-dma-pool"; 73 reg = <0 0x53000000 0 0x1400000>; /* 20 MB */ 74 }; 75 76 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ 77 bl31_secmon_mem: memory@54600000 { 78 no-map; 79 reg = <0 0x54600000 0x0 0x200000>; 80 }; 81 82 snd_dma_mem: memory@60000000 { 83 compatible = "shared-dma-pool"; 84 reg = <0 0x60000000 0 0x1100000>; 85 no-map; 86 }; 87 88 apu_mem: memory@62000000 { 89 compatible = "shared-dma-pool"; 90 reg = <0 0x62000000 0 0x1400000>; /* 20 MB */ 91 }; 92 }; 93 94 backlight_lcd0: backlight-lcd0 { 95 compatible = "pwm-backlight"; 96 pwms = <&disp_pwm0 0 500000>; 97 enable-gpios = <&pio 47 GPIO_ACTIVE_HIGH>; 98 brightness-levels = <0 1023>; 99 num-interpolated-steps = <1023>; 100 default-brightness-level = <576>; 101 }; 102 103 backlight_lcd1: backlight-lcd1 { 104 compatible = "pwm-backlight"; 105 pwms = <&disp_pwm1 0 500000>; 106 enable-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; 107 brightness-levels = <0 1023>; 108 num-interpolated-steps = <1023>; 109 default-brightness-level = <576>; 110 }; 111 112 can_clk: can-clk { 113 compatible = "fixed-clock"; 114 #clock-cells = <0>; 115 clock-frequency = <20000000>; 116 clock-output-names = "can-clk"; 117 }; 118 119 edp_panel_fixed_3v3: regulator-0 { 120 compatible = "regulator-fixed"; 121 regulator-name = "edp_panel_3v3"; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 enable-active-high; 125 gpio = <&pio 6 GPIO_ACTIVE_HIGH>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&edp_panel_3v3_en_pins>; 128 }; 129 130 edp_panel_fixed_12v: regulator-1 { 131 compatible = "regulator-fixed"; 132 regulator-name = "edp_backlight_12v"; 133 regulator-min-microvolt = <12000000>; 134 regulator-max-microvolt = <12000000>; 135 enable-active-high; 136 gpio = <&pio 96 GPIO_ACTIVE_HIGH>; 137 pinctrl-names = "default"; 138 pinctrl-0 = <&edp_panel_12v_en_pins>; 139 }; 140 141 keys: gpio-keys { 142 compatible = "gpio-keys"; 143 144 button-volume-up { 145 wakeup-source; 146 debounce-interval = <100>; 147 gpios = <&pio 106 GPIO_ACTIVE_LOW>; 148 label = "volume_up"; 149 linux,code = <KEY_VOLUMEUP>; 150 }; 151 }; 152 153 wifi_fixed_3v3: regulator-2 { 154 compatible = "regulator-fixed"; 155 regulator-name = "wifi_3v3"; 156 regulator-min-microvolt = <3300000>; 157 regulator-max-microvolt = <3300000>; 158 gpio = <&pio 135 GPIO_ACTIVE_HIGH>; 159 enable-active-high; 160 regulator-always-on; 161 }; 162}; 163 164&disp_pwm0 { 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pwm0_default_pins>; 167 status = "okay"; 168}; 169 170&dmic_codec { 171 wakeup-delay-ms = <200>; 172}; 173 174ð { 175 phy-mode ="rgmii-rxid"; 176 phy-handle = <ð_phy0>; 177 snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; 178 snps,reset-delays-us = <0 10000 10000>; 179 mediatek,tx-delay-ps = <2030>; 180 mediatek,mac-wol; 181 pinctrl-names = "default", "sleep"; 182 pinctrl-0 = <ð_default_pins>; 183 pinctrl-1 = <ð_sleep_pins>; 184 status = "okay"; 185 186 mdio { 187 compatible = "snps,dwmac-mdio"; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 eth_phy0: eth-phy0@1 { 191 compatible = "ethernet-phy-id001c.c916"; 192 reg = <0x1>; 193 }; 194 }; 195}; 196 197&i2c0 { 198 clock-frequency = <400000>; 199 pinctrl-0 = <&i2c0_pins>; 200 pinctrl-names = "default"; 201 status = "okay"; 202}; 203 204&i2c1 { 205 clock-frequency = <400000>; 206 pinctrl-0 = <&i2c1_pins>; 207 pinctrl-names = "default"; 208 status = "okay"; 209 210 touchscreen@5d { 211 compatible = "goodix,gt9271"; 212 reg = <0x5d>; 213 interrupt-parent = <&pio>; 214 interrupts = <132 IRQ_TYPE_EDGE_RISING>; 215 irq-gpios = <&pio 132 GPIO_ACTIVE_HIGH>; 216 reset-gpios = <&pio 133 GPIO_ACTIVE_HIGH>; 217 AVDD28-supply = <&mt6360_ldo1>; 218 pinctrl-names = "default"; 219 pinctrl-0 = <&touch_pins>; 220 }; 221}; 222 223&i2c2 { 224 clock-frequency = <400000>; 225 pinctrl-0 = <&i2c2_pins>; 226 pinctrl-names = "default"; 227 status = "okay"; 228}; 229 230&i2c6 { 231 clock-frequency = <400000>; 232 pinctrl-0 = <&i2c6_pins>; 233 pinctrl-names = "default"; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 status = "okay"; 237 238 mt6360: pmic@34 { 239 compatible = "mediatek,mt6360"; 240 reg = <0x34>; 241 interrupt-parent = <&pio>; 242 interrupts = <128 IRQ_TYPE_EDGE_FALLING>; 243 interrupt-names = "IRQB"; 244 interrupt-controller; 245 #interrupt-cells = <1>; 246 pinctrl-0 = <&mt6360_pins>; 247 248 charger { 249 compatible = "mediatek,mt6360-chg"; 250 richtek,vinovp-microvolt = <14500000>; 251 252 otg_vbus_regulator: usb-otg-vbus-regulator { 253 regulator-name = "usb-otg-vbus"; 254 regulator-min-microvolt = <4425000>; 255 regulator-max-microvolt = <5825000>; 256 }; 257 }; 258 259 regulator { 260 compatible = "mediatek,mt6360-regulator"; 261 LDO_VIN3-supply = <&mt6360_buck2>; 262 263 mt6360_buck1: buck1 { 264 regulator-name = "emi_vdd2"; 265 regulator-min-microvolt = <300000>; 266 regulator-max-microvolt = <1300000>; 267 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 268 MT6360_OPMODE_LP 269 MT6360_OPMODE_ULP>; 270 regulator-always-on; 271 }; 272 273 mt6360_buck2: buck2 { 274 regulator-name = "emi_vddq"; 275 regulator-min-microvolt = <300000>; 276 regulator-max-microvolt = <1300000>; 277 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 278 MT6360_OPMODE_LP 279 MT6360_OPMODE_ULP>; 280 regulator-always-on; 281 }; 282 283 mt6360_ldo1: ldo1 { 284 regulator-name = "tp1_p3v0"; 285 regulator-min-microvolt = <3300000>; 286 regulator-max-microvolt = <3300000>; 287 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 288 MT6360_OPMODE_LP>; 289 regulator-always-on; 290 }; 291 292 mt6360_ldo2: ldo2 { 293 regulator-name = "panel1_p1v8"; 294 regulator-min-microvolt = <1800000>; 295 regulator-max-microvolt = <1800000>; 296 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 297 MT6360_OPMODE_LP>; 298 }; 299 300 mt6360_ldo3: ldo3 { 301 regulator-name = "vmc_pmu"; 302 regulator-min-microvolt = <1200000>; 303 regulator-max-microvolt = <3600000>; 304 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 305 MT6360_OPMODE_LP>; 306 }; 307 308 mt6360_ldo5: ldo5 { 309 regulator-name = "vmch_pmu"; 310 regulator-min-microvolt = <2700000>; 311 regulator-max-microvolt = <3600000>; 312 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 313 MT6360_OPMODE_LP>; 314 }; 315 316 /* This is a measure point, which name is mt6360_ldo1 on schematic */ 317 mt6360_ldo6: ldo6 { 318 regulator-name = "mt6360_ldo1"; 319 regulator-min-microvolt = <500000>; 320 regulator-max-microvolt = <2100000>; 321 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 322 MT6360_OPMODE_LP>; 323 }; 324 325 mt6360_ldo7: ldo7 { 326 regulator-name = "emi_vmddr_en"; 327 regulator-min-microvolt = <500000>; 328 regulator-max-microvolt = <2100000>; 329 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 330 MT6360_OPMODE_LP>; 331 regulator-always-on; 332 }; 333 }; 334 }; 335}; 336 337&mfg0 { 338 domain-supply = <&mt6315_7_vbuck1>; 339}; 340 341&mmc0 { 342 status = "okay"; 343 pinctrl-names = "default", "state_uhs"; 344 pinctrl-0 = <&mmc0_default_pins>; 345 pinctrl-1 = <&mmc0_uhs_pins>; 346 bus-width = <8>; 347 max-frequency = <200000000>; 348 cap-mmc-highspeed; 349 mmc-hs200-1_8v; 350 mmc-hs400-1_8v; 351 cap-mmc-hw-reset; 352 no-sdio; 353 no-sd; 354 hs400-ds-delay = <0x14c11>; 355 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 356 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 357 non-removable; 358}; 359 360&mmc1 { 361 pinctrl-names = "default", "state_uhs"; 362 pinctrl-0 = <&mmc1_default_pins>; 363 pinctrl-1 = <&mmc1_uhs_pins>; 364 bus-width = <4>; 365 max-frequency = <200000000>; 366 cap-sd-highspeed; 367 sd-uhs-sdr50; 368 sd-uhs-sdr104; 369 no-mmc; 370 no-sdio; 371 vmmc-supply = <&mt6360_ldo5>; 372 vqmmc-supply = <&mt6360_ldo3>; 373 status = "okay"; 374 non-removable; 375}; 376 377&mt6359_vaud18_ldo_reg { 378 regulator-always-on; 379}; 380 381&mt6359_vbbck_ldo_reg { 382 regulator-always-on; 383}; 384 385/* For USB Hub */ 386&mt6359_vcamio_ldo_reg { 387 regulator-always-on; 388}; 389 390&mt6359_vcn33_2_bt_ldo_reg { 391 regulator-min-microvolt = <3300000>; 392 regulator-max-microvolt = <3300000>; 393}; 394 395&mt6359_vcore_buck_reg { 396 regulator-always-on; 397}; 398 399&mt6359_vgpu11_buck_reg { 400 regulator-always-on; 401}; 402 403&mt6359_vpu_buck_reg { 404 regulator-always-on; 405}; 406 407&mt6359_vrf12_ldo_reg { 408 regulator-always-on; 409}; 410 411&mt6359codec { 412 mediatek,mic-type-0 = <1>; /* ACC */ 413 mediatek,mic-type-1 = <3>; /* DCC */ 414 mediatek,mic-type-2 = <1>; /* ACC */ 415}; 416 417&pcie0 { 418 pinctrl-names = "default", "idle"; 419 pinctrl-0 = <&pcie0_default_pins>; 420 pinctrl-1 = <&pcie0_idle_pins>; 421 status = "okay"; 422}; 423 424&pcie1 { 425 pinctrl-names = "default"; 426 pinctrl-0 = <&pcie1_default_pins>; 427 status = "disabled"; 428}; 429 430&pciephy { 431 status = "okay"; 432}; 433 434&pio { 435 audio_default_pins: audio-default-pins { 436 pins-cmd-dat { 437 pinmux = <PINMUX_GPIO61__FUNC_DMIC1_CLK>, 438 <PINMUX_GPIO62__FUNC_DMIC1_DAT>, 439 <PINMUX_GPIO65__FUNC_PCM_DO>, 440 <PINMUX_GPIO66__FUNC_PCM_CLK>, 441 <PINMUX_GPIO67__FUNC_PCM_DI>, 442 <PINMUX_GPIO68__FUNC_PCM_SYNC>, 443 <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>, 444 <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>, 445 <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>, 446 <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>, 447 <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>, 448 <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>, 449 <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>; 450 }; 451 }; 452 453 disp_pwm1_default_pins: disp-pwm1-default-pins { 454 pins1 { 455 pinmux = <PINMUX_GPIO104__FUNC_DISP_PWM1>; 456 }; 457 }; 458 459 edp_panel_12v_en_pins: edp-panel-12v-en-pins { 460 pins1 { 461 pinmux = <PINMUX_GPIO96__FUNC_GPIO96>; 462 output-high; 463 }; 464 }; 465 466 edp_panel_3v3_en_pins: edp-panel-3v3-en-pins { 467 pins1 { 468 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 469 output-high; 470 }; 471 }; 472 473 eth_default_pins: eth-default-pins { 474 pins-cc { 475 pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>, 476 <PINMUX_GPIO86__FUNC_GBE_RXC>, 477 <PINMUX_GPIO87__FUNC_GBE_RXDV>, 478 <PINMUX_GPIO88__FUNC_GBE_TXEN>; 479 drive-strength = <MTK_DRIVE_8mA>; 480 }; 481 482 pins-mdio { 483 pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>, 484 <PINMUX_GPIO90__FUNC_GBE_MDIO>; 485 input-enable; 486 }; 487 488 pins-power { 489 pinmux = <PINMUX_GPIO91__FUNC_GPIO91>, 490 <PINMUX_GPIO92__FUNC_GPIO92>; 491 output-high; 492 }; 493 494 pins-rxd { 495 pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>, 496 <PINMUX_GPIO82__FUNC_GBE_RXD2>, 497 <PINMUX_GPIO83__FUNC_GBE_RXD1>, 498 <PINMUX_GPIO84__FUNC_GBE_RXD0>; 499 }; 500 501 pins-txd { 502 pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>, 503 <PINMUX_GPIO78__FUNC_GBE_TXD2>, 504 <PINMUX_GPIO79__FUNC_GBE_TXD1>, 505 <PINMUX_GPIO80__FUNC_GBE_TXD0>; 506 drive-strength = <MTK_DRIVE_8mA>; 507 }; 508 }; 509 510 eth_sleep_pins: eth-sleep-pins { 511 pins-cc { 512 pinmux = <PINMUX_GPIO85__FUNC_GPIO85>, 513 <PINMUX_GPIO86__FUNC_GPIO86>, 514 <PINMUX_GPIO87__FUNC_GPIO87>, 515 <PINMUX_GPIO88__FUNC_GPIO88>; 516 }; 517 518 pins-mdio { 519 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>, 520 <PINMUX_GPIO90__FUNC_GPIO90>; 521 input-disable; 522 bias-disable; 523 }; 524 525 pins-rxd { 526 pinmux = <PINMUX_GPIO81__FUNC_GPIO81>, 527 <PINMUX_GPIO82__FUNC_GPIO82>, 528 <PINMUX_GPIO83__FUNC_GPIO83>, 529 <PINMUX_GPIO84__FUNC_GPIO84>; 530 }; 531 532 pins-txd { 533 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 534 <PINMUX_GPIO78__FUNC_GPIO78>, 535 <PINMUX_GPIO79__FUNC_GPIO79>, 536 <PINMUX_GPIO80__FUNC_GPIO80>; 537 }; 538 }; 539 540 gpio_key_pins: gpio-keys-pins { 541 pins { 542 pinmux = <PINMUX_GPIO106__FUNC_GPIO106>; 543 bias-pull-up; 544 input-enable; 545 }; 546 }; 547 548 i2c0_pins: i2c0-pins { 549 pins { 550 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 551 <PINMUX_GPIO9__FUNC_SCL0>; 552 bias-pull-up = <MTK_PULL_SET_RSEL_111>; 553 drive-strength-microamp = <1000>; 554 }; 555 }; 556 557 i2c1_pins: i2c1-pins { 558 pins { 559 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 560 <PINMUX_GPIO11__FUNC_SCL1>; 561 bias-pull-up = <MTK_PULL_SET_RSEL_111>; 562 drive-strength-microamp = <1000>; 563 }; 564 }; 565 566 i2c2_pins: i2c2-pins { 567 pins { 568 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 569 <PINMUX_GPIO13__FUNC_SCL2>; 570 bias-pull-up = <MTK_PULL_SET_RSEL_111>; 571 drive-strength = <MTK_DRIVE_6mA>; 572 }; 573 }; 574 575 i2c6_pins: i2c6-pins { 576 pins { 577 pinmux = <PINMUX_GPIO25__FUNC_SDA6>, 578 <PINMUX_GPIO26__FUNC_SCL6>; 579 bias-pull-up; 580 }; 581 }; 582 583 mmc0_default_pins: mmc0-default-pins { 584 pins-clk { 585 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 586 drive-strength = <MTK_DRIVE_6mA>; 587 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 588 }; 589 590 pins-cmd-dat { 591 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 592 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 593 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 594 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 595 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 596 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 597 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 598 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 599 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 600 input-enable; 601 drive-strength = <MTK_DRIVE_6mA>; 602 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 603 }; 604 605 pins-rst { 606 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 607 drive-strength = <MTK_DRIVE_6mA>; 608 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 609 }; 610 }; 611 612 mmc0_uhs_pins: mmc0-uhs-pins { 613 pins-clk { 614 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 615 drive-strength = <MTK_DRIVE_8mA>; 616 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 617 }; 618 619 pins-cmd-dat { 620 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 621 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 622 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 623 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 624 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 625 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 626 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 627 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 628 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 629 input-enable; 630 drive-strength = <MTK_DRIVE_8mA>; 631 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 632 }; 633 634 pins-ds { 635 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 636 drive-strength = <MTK_DRIVE_8mA>; 637 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 638 }; 639 640 pins-rst { 641 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 642 drive-strength = <MTK_DRIVE_8mA>; 643 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 644 }; 645 }; 646 647 mmc1_default_pins: mmc1-default-pins { 648 pins-clk { 649 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 650 drive-strength = <MTK_DRIVE_8mA>; 651 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 652 }; 653 654 pins-cmd-dat { 655 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 656 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 657 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 658 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 659 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 660 input-enable; 661 drive-strength = <MTK_DRIVE_8mA>; 662 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 663 }; 664 }; 665 666 mmc1_uhs_pins: mmc1-uhs-pins { 667 pins-clk { 668 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 669 drive-strength = <MTK_DRIVE_8mA>; 670 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 671 }; 672 673 pins-cmd-dat { 674 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 675 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 676 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 677 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 678 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 679 input-enable; 680 drive-strength = <MTK_DRIVE_8mA>; 681 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 682 }; 683 }; 684 685 mt6360_pins: mt6360-pins { 686 pins { 687 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>, 688 <PINMUX_GPIO128__FUNC_GPIO128>; 689 input-enable; 690 bias-pull-up; 691 }; 692 }; 693 694 pcie0_default_pins: pcie0-default-pins { 695 pins { 696 pinmux = <PINMUX_GPIO19__FUNC_WAKEN>, 697 <PINMUX_GPIO20__FUNC_PERSTN>, 698 <PINMUX_GPIO21__FUNC_CLKREQN>; 699 bias-pull-up; 700 }; 701 }; 702 703 pcie0_idle_pins: pcie0-idle-pins { 704 pins { 705 pinmux = <PINMUX_GPIO20__FUNC_GPIO20>; 706 bias-disable; 707 output-low; 708 }; 709 }; 710 711 pcie1_default_pins: pcie1-default-pins { 712 pins { 713 pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>, 714 <PINMUX_GPIO23__FUNC_CLKREQN_1>, 715 <PINMUX_GPIO24__FUNC_WAKEN_1>; 716 bias-pull-up; 717 }; 718 }; 719 720 pwm0_default_pins: pwm0-default-pins { 721 pins-cmd-dat { 722 pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM0>; 723 }; 724 }; 725 726 spi1_pins: spi1-pins { 727 pins { 728 pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>, 729 <PINMUX_GPIO137__FUNC_SPIM1_CLK>, 730 <PINMUX_GPIO138__FUNC_SPIM1_MO>, 731 <PINMUX_GPIO139__FUNC_SPIM1_MI>; 732 bias-disable; 733 }; 734 }; 735 736 spi2_pins: spi-pins { 737 pins { 738 pinmux = <PINMUX_GPIO140__FUNC_SPIM2_CSB>, 739 <PINMUX_GPIO141__FUNC_SPIM2_CLK>, 740 <PINMUX_GPIO142__FUNC_SPIM2_MO>, 741 <PINMUX_GPIO143__FUNC_SPIM2_MI>; 742 bias-disable; 743 }; 744 }; 745 746 touch_pins: touch-pins { 747 pins-irq { 748 pinmux = <PINMUX_GPIO132__FUNC_GPIO132>; 749 input-enable; 750 bias-disable; 751 }; 752 753 pins-reset { 754 pinmux = <PINMUX_GPIO133__FUNC_GPIO133>; 755 output-high; 756 }; 757 }; 758 759 uart0_pins: uart0-pins { 760 pins { 761 pinmux = <PINMUX_GPIO98__FUNC_UTXD0>, 762 <PINMUX_GPIO99__FUNC_URXD0>; 763 }; 764 }; 765 766 uart1_pins: uart1-pins { 767 pins { 768 pinmux = <PINMUX_GPIO100__FUNC_URTS1>, 769 <PINMUX_GPIO101__FUNC_UCTS1>, 770 <PINMUX_GPIO102__FUNC_UTXD1>, 771 <PINMUX_GPIO103__FUNC_URXD1>; 772 }; 773 }; 774}; 775 776&pmic { 777 interrupt-parent = <&pio>; 778 interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; 779}; 780 781&scp { 782 memory-region = <&scp_mem>; 783 status = "okay"; 784}; 785 786&spi1 { 787 pinctrl-0 = <&spi1_pins>; 788 pinctrl-names = "default"; 789 mediatek,pad-select = <0>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 status = "okay"; 793 cs-gpios = <&pio 64 GPIO_ACTIVE_LOW>; 794 795 can0: can@0 { 796 compatible = "microchip,mcp2518fd"; 797 reg = <0>; 798 clocks = <&can_clk>; 799 spi-max-frequency = <20000000>; 800 interrupts-extended = <&pio 16 IRQ_TYPE_LEVEL_LOW>; 801 vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>; 802 xceiver-supply = <&mt6359_vcn33_2_bt_ldo_reg>; 803 }; 804}; 805 806&spi2 { 807 pinctrl-0 = <&spi2_pins>; 808 pinctrl-names = "default"; 809 mediatek,pad-select = <0>; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 status = "okay"; 813}; 814 815&spmi { 816 #address-cells = <2>; 817 #size-cells = <0>; 818 819 mt6315_6: pmic@6 { 820 compatible = "mediatek,mt6315-regulator"; 821 reg = <0x6 SPMI_USID>; 822 823 regulators { 824 mt6315_6_vbuck1: vbuck1 { 825 regulator-compatible = "vbuck1"; 826 regulator-name = "Vbcpu"; 827 regulator-min-microvolt = <300000>; 828 regulator-max-microvolt = <1193750>; 829 regulator-enable-ramp-delay = <256>; 830 regulator-allowed-modes = <0 1 2>; 831 regulator-always-on; 832 }; 833 }; 834 }; 835 836 mt6315_7: pmic@7 { 837 compatible = "mediatek,mt6315-regulator"; 838 reg = <0x7 SPMI_USID>; 839 840 regulators { 841 mt6315_7_vbuck1: vbuck1 { 842 regulator-compatible = "vbuck1"; 843 regulator-name = "Vgpu"; 844 regulator-min-microvolt = <300000>; 845 regulator-max-microvolt = <1193750>; 846 regulator-enable-ramp-delay = <256>; 847 regulator-allowed-modes = <0 1 2>; 848 }; 849 }; 850 }; 851}; 852 853&u3phy0 { 854 status = "okay"; 855}; 856 857&u3phy1 { 858 status = "okay"; 859}; 860 861&u3phy2 { 862 status = "okay"; 863}; 864 865&u3phy3 { 866 status = "okay"; 867}; 868 869&uart0 { 870 pinctrl-0 = <&uart0_pins>; 871 pinctrl-names = "default"; 872 status = "okay"; 873}; 874 875&uart1 { 876 pinctrl-0 = <&uart1_pins>; 877 pinctrl-names = "default"; 878 status = "okay"; 879}; 880 881&ufsphy { 882 status = "disabled"; 883}; 884 885&xhci0 { 886 status = "okay"; 887}; 888 889&xhci1 { 890 vusb33-supply = <&mt6359_vusb_ldo_reg>; 891 status = "okay"; 892}; 893 894&xhci2 { 895 vusb33-supply = <&mt6359_vusb_ldo_reg>; 896 status = "okay"; 897}; 898 899&xhci3 { 900 vusb33-supply = <&mt6359_vusb_ldo_reg>; 901 status = "okay"; 902}; 903