xref: /linux/arch/arm64/boot/dts/mediatek/mt8365-evk.dts (revision fc2d791a43d3880496d1c729b8bd74d2c19cb4e7) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021-2022 BayLibre, SAS.
4 * Authors:
5 * Fabien Parent <fparent@baylibre.com>
6 * Bernhard Rosenkränzer <bero@baylibre.com>
7 * Alexandre Mergnat <amergnat@baylibre.com>
8 */
9
10/dts-v1/;
11
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
15#include "mt8365.dtsi"
16#include "mt6357.dtsi"
17
18/ {
19	model = "MediaTek MT8365 Open Platform EVK";
20	compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
21
22	aliases {
23		ethernet = &ethernet;
24		mmc0 = &mmc0;
25		mmc1 = &mmc1;
26		serial0 = &uart0;
27	};
28
29	chosen {
30		stdout-path = "serial0:921600n8";
31	};
32
33	connector {
34		compatible = "hdmi-connector";
35		label = "hdmi";
36		type = "d";
37
38		port {
39			#address-cells = <1>;
40			#size-cells = <0>;
41			hdmi_connector_in: endpoint@0 {
42				reg = <0>;
43				remote-endpoint = <&hdmi_connector_out>;
44			};
45		};
46	};
47
48	firmware {
49		optee {
50			compatible = "linaro,optee-tz";
51			method = "smc";
52		};
53	};
54
55	gpio-keys {
56		compatible = "gpio-keys";
57		pinctrl-names = "default";
58		pinctrl-0 = <&gpio_keys>;
59
60		key-volume-up {
61			gpios = <&pio 24 GPIO_ACTIVE_LOW>;
62			label = "volume_up";
63			linux,code = <KEY_VOLUMEUP>;
64			wakeup-source;
65			debounce-interval = <15>;
66		};
67	};
68
69	memory@40000000 {
70		device_type = "memory";
71		reg = <0 0x40000000 0 0xc0000000>;
72	};
73
74	usb_otg_vbus: regulator-0 {
75		compatible = "regulator-fixed";
76		regulator-name = "otg_vbus";
77		regulator-min-microvolt = <5000000>;
78		regulator-max-microvolt = <5000000>;
79		gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
80		enable-active-high;
81	};
82
83	reg_vsys: regulator-vsys {
84		compatible = "regulator-fixed";
85		regulator-name = "vsys";
86		regulator-always-on;
87		regulator-boot-on;
88	};
89
90	touch0_fixed_3v3: regulator-vio33tp {
91		compatible = "regulator-fixed";
92		regulator-name = "vio33_tp";
93		regulator-min-microvolt = <3300000>;
94		regulator-max-microvolt = <3300000>;
95		vin-supply = <&reg_vsys>;
96	};
97
98	reserved-memory {
99		#address-cells = <2>;
100		#size-cells = <2>;
101		ranges;
102
103		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
104		bl31_secmon_reserved: secmon@43000000 {
105			no-map;
106			reg = <0 0x43000000 0 0x30000>;
107		};
108
109		/* 12 MiB reserved for OP-TEE (BL32)
110		 * +-----------------------+ 0x43e0_0000
111		 * |      SHMEM 2MiB       |
112		 * +-----------------------+ 0x43c0_0000
113		 * |        | TA_RAM  8MiB |
114		 * + TZDRAM +--------------+ 0x4340_0000
115		 * |        | TEE_RAM 2MiB |
116		 * +-----------------------+ 0x4320_0000
117		 */
118		optee_reserved: optee@43200000 {
119			no-map;
120			reg = <0 0x43200000 0 0x00c00000>;
121		};
122	};
123
124	sound: sound {
125		compatible = "mediatek,mt8365-mt6357";
126		pinctrl-names = "default",
127				"dmic",
128				"miso_off",
129				"miso_on",
130				"mosi_off",
131				"mosi_on";
132		pinctrl-0 = <&aud_default_pins>;
133		pinctrl-1 = <&aud_dmic_pins>;
134		pinctrl-2 = <&aud_miso_off_pins>;
135		pinctrl-3 = <&aud_miso_on_pins>;
136		pinctrl-4 = <&aud_mosi_off_pins>;
137		pinctrl-5 = <&aud_mosi_on_pins>;
138		mediatek,platform = <&afe>;
139	};
140
141	vsys_lcm_reg: regulator-vsys-lcm {
142		compatible = "regulator-fixed";
143		enable-active-high;
144		gpio = <&pio 129 GPIO_ACTIVE_HIGH>;
145		regulator-max-microvolt = <5000000>;
146		regulator-min-microvolt = <5000000>;
147		regulator-name = "vsys_lcm";
148	};
149
150};
151
152&afe {
153	mediatek,dmic-mode = <1>;
154	status = "okay";
155};
156
157&cpu0 {
158	proc-supply = <&mt6357_vproc_reg>;
159	sram-supply = <&mt6357_vsram_proc_reg>;
160};
161
162&cpu1 {
163	proc-supply = <&mt6357_vproc_reg>;
164	sram-supply = <&mt6357_vsram_proc_reg>;
165};
166
167&cpu2 {
168	proc-supply = <&mt6357_vproc_reg>;
169	sram-supply = <&mt6357_vsram_proc_reg>;
170};
171
172&cpu3 {
173	proc-supply = <&mt6357_vproc_reg>;
174	sram-supply = <&mt6357_vsram_proc_reg>;
175};
176
177&dither0_out {
178	remote-endpoint = <&dsi0_in>;
179};
180
181&dpi0 {
182	pinctrl-0 = <&dpi_default_pins>;
183	pinctrl-1 = <&dpi_idle_pins>;
184	pinctrl-names = "default", "sleep";
185	/*
186	 * Ethernet and HDMI (DPI0) are sharing pins.
187	 * Only one can be enabled at a time and require the physical switch
188	 * SW2101 to be set on LAN position
189	 */
190	status = "disabled";
191
192	ports {
193		#address-cells = <1>;
194		#size-cells = <0>;
195
196		port@0 {
197			#address-cells = <1>;
198			#size-cells = <0>;
199			reg = <0>;
200			dpi0_in: endpoint@1 {
201				reg = <1>;
202				remote-endpoint = <&rdma1_out>;
203			};
204		};
205
206		port@1 {
207			#address-cells = <1>;
208			#size-cells = <0>;
209			reg = <1>;
210			dpi0_out: endpoint@1 {
211				reg = <1>;
212				remote-endpoint = <&it66121_in>;
213			};
214		};
215	};
216};
217
218&dsi0 {
219	#address-cells = <1>;
220	#size-cells = <0>;
221	status = "okay";
222
223	panel@0 {
224		compatible = "startek,kd070fhfid015";
225		reg = <0>;
226		enable-gpios = <&pio 67 GPIO_ACTIVE_HIGH>;
227		reset-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
228		iovcc-supply = <&mt6357_vsim1_reg>;
229		power-supply = <&vsys_lcm_reg>;
230
231		port {
232			#address-cells = <1>;
233			#size-cells = <0>;
234			panel_in: endpoint@0 {
235				reg = <0>;
236				remote-endpoint = <&dsi0_out>;
237			};
238		};
239	};
240	ports {
241		#address-cells = <1>;
242		#size-cells = <0>;
243
244		port@0 {
245			#address-cells = <1>;
246			#size-cells = <0>;
247			reg = <0>;
248			dsi0_in: endpoint@0 {
249				reg = <0>;
250				remote-endpoint = <&dither0_out>;
251			};
252		};
253
254		port@1 {
255			#address-cells = <1>;
256			#size-cells = <0>;
257			reg = <1>;
258			dsi0_out: endpoint@0 {
259				reg = <0>;
260				remote-endpoint = <&panel_in>;
261			};
262		};
263	};
264};
265
266&ethernet {
267	pinctrl-0 = <&ethernet_pins>;
268	pinctrl-names = "default";
269	phy-handle = <&eth_phy>;
270	phy-mode = "rmii";
271	/*
272	 * Ethernet and HDMI (DPI0) are sharing pins.
273	 * Only one can be enabled at a time and require the physical switch
274	 * SW2101 to be set on LAN position
275	 * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet
276	 */
277	status = "disabled";
278
279	mdio {
280		#address-cells = <1>;
281		#size-cells = <0>;
282
283		eth_phy: ethernet-phy@0 {
284			reg = <0>;
285		};
286	};
287};
288
289&gpu {
290	mali-supply = <&mt6357_vcore_reg>;
291	status = "okay";
292};
293
294&i2c0 {
295	clock-frequency = <100000>;
296	pinctrl-0 = <&i2c0_pins>;
297	pinctrl-names = "default";
298	status = "okay";
299};
300
301&i2c1 {
302	#address-cells = <1>;
303	#size-cells = <0>;
304	clock-div = <2>;
305	clock-frequency = <100000>;
306	pinctrl-0 = <&i2c1_pins>;
307	pinctrl-names = "default";
308	status = "okay";
309
310	it66121_hdmi: hdmi@4c {
311		compatible = "ite,it66121";
312		reg = <0x4c>;
313		#sound-dai-cells = <0>;
314		interrupt-parent = <&pio>;
315		interrupts = <68 IRQ_TYPE_LEVEL_LOW>;
316		pinctrl-0 = <&ite_pins>;
317		pinctrl-names = "default";
318		reset-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
319		vcn18-supply = <&mt6357_vsim2_reg>;
320		vcn33-supply = <&mt6357_vibr_reg>;
321		vrf12-supply = <&mt6357_vrf12_reg>;
322
323		ports {
324			#address-cells = <1>;
325			#size-cells = <0>;
326
327			port@0 {
328				#address-cells = <1>;
329				#size-cells = <0>;
330				reg = <0>;
331				it66121_in: endpoint@0 {
332					reg = <0>;
333					bus-width = <12>;
334					remote-endpoint = <&dpi0_out>;
335				};
336			};
337
338			port@1 {
339				#address-cells = <1>;
340				#size-cells = <0>;
341				reg = <1>;
342				hdmi_connector_out: endpoint@0 {
343					reg = <0>;
344					remote-endpoint = <&hdmi_connector_in>;
345				};
346			};
347		};
348	};
349
350	touchscreen@5d {
351		compatible = "goodix,gt9271";
352		reg = <0x5d>;
353		interrupts-extended = <&pio 78 IRQ_TYPE_EDGE_FALLING>;
354		pinctrl-names = "default";
355		pinctrl-0 = <&touch_pins>;
356		irq-gpios = <&pio 78 GPIO_ACTIVE_HIGH>;
357		reset-gpios = <&pio 79 GPIO_ACTIVE_LOW>;
358		AVDD28-supply = <&touch0_fixed_3v3>;
359		VDDIO-supply = <&mt6357_vrf12_reg>;
360	};
361};
362
363&mfg {
364	domain-supply = <&mt6357_vsram_others_reg>;
365};
366
367&mmc0 {
368	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
369	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
370	bus-width = <8>;
371	cap-mmc-highspeed;
372	cap-mmc-hw-reset;
373	hs400-ds-delay = <0x12012>;
374	max-frequency = <200000000>;
375	mmc-hs200-1_8v;
376	mmc-hs400-1_8v;
377	no-sd;
378	no-sdio;
379	non-removable;
380	pinctrl-0 = <&mmc0_default_pins>;
381	pinctrl-1 = <&mmc0_uhs_pins>;
382	pinctrl-names = "default", "state_uhs";
383	vmmc-supply = <&mt6357_vemc_reg>;
384	vqmmc-supply = <&mt6357_vio18_reg>;
385	status = "okay";
386};
387
388&mmc1 {
389	bus-width = <4>;
390	cap-sd-highspeed;
391	cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
392	max-frequency = <200000000>;
393	pinctrl-0 = <&mmc1_default_pins>;
394	pinctrl-1 = <&mmc1_uhs_pins>;
395	pinctrl-names = "default", "state_uhs";
396	sd-uhs-sdr104;
397	sd-uhs-sdr50;
398	vmmc-supply = <&mt6357_vmch_reg>;
399	vqmmc-supply = <&mt6357_vmc_reg>;
400	status = "okay";
401};
402
403&mt6357_pmic {
404	interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
405	interrupt-controller;
406	#interrupt-cells = <2>;
407	mediatek,micbias0-microvolt = <1900000>;
408	mediatek,micbias1-microvolt = <1700000>;
409};
410
411&mt6357_vsim1_reg {
412	regulator-min-microvolt = <1800000>;
413	regulator-max-microvolt = <1800000>;
414};
415
416&pio {
417	aud_default_pins: audiodefault-pins {
418		clk-dat-pins {
419			pinmux = <MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK>,
420				 <MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK>,
421				 <MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK>,
422				 <MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO>;
423		};
424	};
425
426	aud_dmic_pins: audiodmic-pins {
427		clk-dat-pins {
428			pinmux = <MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK>,
429				 <MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0>,
430				 <MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1>;
431		};
432	};
433
434	aud_miso_off_pins: misooff-pins {
435		clk-dat-pins {
436			pinmux = <MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53>,
437				 <MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54>,
438				 <MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55>,
439				 <MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56>;
440			input-enable;
441			bias-pull-down;
442			drive-strength = <2>;
443		};
444	};
445
446	aud_miso_on_pins: misoon-pins {
447		clk-dat-pins {
448			pinmux = <MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO>,
449				 <MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO>,
450				 <MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0>,
451				 <MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1>;
452			drive-strength = <6>;
453		};
454	};
455
456	aud_mosi_off_pins: mosioff-pins {
457		clk-dat-pins {
458			pinmux = <MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49>,
459				 <MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50>,
460				 <MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51>,
461				 <MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52>;
462			input-enable;
463			bias-pull-down;
464			drive-strength = <2>;
465		};
466	};
467
468	aud_mosi_on_pins: mosion-pins {
469		clk-dat-pins {
470			pinmux = <MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI>,
471				 <MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI>,
472				 <MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0>,
473				 <MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1>;
474			drive-strength = <6>;
475		};
476	};
477
478	dpi_default_pins: dpi-default-pins {
479		pins {
480			pinmux = <MT8365_PIN_0_GPIO0__FUNC_DPI_D0>,
481				 <MT8365_PIN_1_GPIO1__FUNC_DPI_D1>,
482				 <MT8365_PIN_2_GPIO2__FUNC_DPI_D2>,
483				 <MT8365_PIN_3_GPIO3__FUNC_DPI_D3>,
484				 <MT8365_PIN_4_GPIO4__FUNC_DPI_D4>,
485				 <MT8365_PIN_5_GPIO5__FUNC_DPI_D5>,
486				 <MT8365_PIN_6_GPIO6__FUNC_DPI_D6>,
487				 <MT8365_PIN_7_GPIO7__FUNC_DPI_D7>,
488				 <MT8365_PIN_8_GPIO8__FUNC_DPI_D8>,
489				 <MT8365_PIN_9_GPIO9__FUNC_DPI_D9>,
490				 <MT8365_PIN_10_GPIO10__FUNC_DPI_D10>,
491				 <MT8365_PIN_11_GPIO11__FUNC_DPI_D11>,
492				 <MT8365_PIN_12_GPIO12__FUNC_DPI_DE>,
493				 <MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC>,
494				 <MT8365_PIN_14_GPIO14__FUNC_DPI_CK>,
495				 <MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC>;
496			drive-strength = <4>;
497		};
498	};
499
500	dpi_idle_pins: dpi-idle-pins {
501		pins {
502			pinmux = <MT8365_PIN_0_GPIO0__FUNC_GPIO0>,
503				 <MT8365_PIN_1_GPIO1__FUNC_GPIO1>,
504				 <MT8365_PIN_2_GPIO2__FUNC_GPIO2>,
505				 <MT8365_PIN_3_GPIO3__FUNC_GPIO3>,
506				 <MT8365_PIN_4_GPIO4__FUNC_GPIO4>,
507				 <MT8365_PIN_5_GPIO5__FUNC_GPIO5>,
508				 <MT8365_PIN_6_GPIO6__FUNC_GPIO6>,
509				 <MT8365_PIN_7_GPIO7__FUNC_GPIO7>,
510				 <MT8365_PIN_8_GPIO8__FUNC_GPIO8>,
511				 <MT8365_PIN_9_GPIO9__FUNC_GPIO9>,
512				 <MT8365_PIN_10_GPIO10__FUNC_GPIO10>,
513				 <MT8365_PIN_11_GPIO11__FUNC_GPIO11>,
514				 <MT8365_PIN_12_GPIO12__FUNC_GPIO12>,
515				 <MT8365_PIN_13_GPIO13__FUNC_GPIO13>,
516				 <MT8365_PIN_14_GPIO14__FUNC_GPIO14>,
517				 <MT8365_PIN_15_GPIO15__FUNC_GPIO15>;
518		};
519	};
520
521	ethernet_pins: ethernet-pins {
522		phy_reset_pins {
523			pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
524		};
525
526		rmii_pins {
527			pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
528				 <MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
529				 <MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
530				 <MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
531				 <MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
532				 <MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
533				 <MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
534				 <MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
535				 <MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
536				 <MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
537				 <MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
538				 <MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
539				 <MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
540				 <MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
541				 <MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
542				 <MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
543		};
544	};
545
546	gpio_keys: gpio-keys-pins {
547		pins {
548			pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
549			bias-pull-up;
550			input-enable;
551		};
552	};
553
554	i2c0_pins: i2c0-pins {
555		pins {
556			pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
557				 <MT8365_PIN_58_SCL0__FUNC_SCL0_0>;
558			bias-pull-up;
559		};
560	};
561
562	i2c1_pins: i2c1-pins {
563		pins {
564			pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>,
565				 <MT8365_PIN_60_SCL1__FUNC_SCL1_0>;
566			bias-pull-up;
567		};
568	};
569
570	ite_pins: ite-pins {
571		irq_ite_pins {
572			pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>;
573			input-enable;
574			bias-pull-up;
575		};
576
577		pwr_pins {
578			pinmux = <MT8365_PIN_70_CMDAT2__FUNC_GPIO70>,
579				 <MT8365_PIN_71_CMDAT3__FUNC_GPIO71>;
580			output-high;
581		};
582
583		rst_ite_pins {
584			pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>;
585			output-high;
586		};
587	};
588
589	mmc0_default_pins: mmc0-default-pins {
590		clk-pins {
591			pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
592			bias-pull-down;
593		};
594
595		cmd-dat-pins {
596			pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
597				 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
598				 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
599				 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
600				 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
601				 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
602				 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
603				 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
604				 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
605			input-enable;
606			bias-pull-up;
607		};
608
609		rst-pins {
610			pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
611			bias-pull-up;
612		};
613	};
614
615	mmc0_uhs_pins: mmc0-uhs-pins {
616		clk-pins {
617			pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
618			drive-strength = <MTK_DRIVE_10mA>;
619			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
620		};
621
622		cmd-dat-pins {
623			pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
624				 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
625				 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
626				 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
627				 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
628				 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
629				 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
630				 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
631				 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
632			input-enable;
633			drive-strength = <MTK_DRIVE_10mA>;
634			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
635		};
636
637		ds-pins {
638			pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
639			drive-strength = <MTK_DRIVE_10mA>;
640			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
641		};
642
643		rst-pins {
644			pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
645			drive-strength = <MTK_DRIVE_10mA>;
646			bias-pull-up;
647		};
648	};
649
650	mmc1_default_pins: mmc1-default-pins {
651		cd-pins {
652			pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
653			bias-pull-up;
654		};
655
656		clk-pins {
657			pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
658			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
659		};
660
661		cmd-dat-pins {
662			pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
663				 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
664				 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
665				 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
666				 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
667			input-enable;
668			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
669		};
670	};
671
672	mmc1_uhs_pins: mmc1-uhs-pins {
673		clk-pins {
674			pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
675			drive-strength = <8>;
676			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
677		};
678
679		cmd-dat-pins {
680			pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
681				 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
682				 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
683				 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
684				 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
685			input-enable;
686			drive-strength = <6>;
687			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
688		};
689	};
690
691	touch_pins: touch-pins {
692		ctp-int1-pins {
693			pinmux = <MT8365_PIN_78_CMHSYNC__FUNC_GPIO78>;
694			input-enable;
695			bias-disable;
696		};
697
698		rst-pins {
699			pinmux = <MT8365_PIN_79_CMVSYNC__FUNC_GPIO79>;
700			output-low;
701		};
702	};
703
704	uart0_pins: uart0-pins {
705		pins {
706			pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
707				 <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
708		};
709	};
710
711	uart1_pins: uart1-pins {
712		pins {
713			pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
714				 <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
715		};
716	};
717
718	uart2_pins: uart2-pins {
719		pins {
720			pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
721				 <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
722		};
723	};
724
725	usb_pins: usb-pins {
726		id-pins {
727			pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
728			input-enable;
729			bias-pull-up;
730		};
731
732		usb0-vbus-pins {
733			pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
734			output-high;
735		};
736
737		usb1-vbus-pins {
738			pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
739			output-high;
740		};
741	};
742
743	pwm_pins: pwm-pins {
744		pins {
745			pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
746				 <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
747		};
748	};
749};
750
751&pwm {
752	pinctrl-0 = <&pwm_pins>;
753	pinctrl-names = "default";
754	status = "okay";
755};
756
757&rdma1_out {
758	remote-endpoint = <&dpi0_in>;
759};
760
761&ssusb {
762	dr_mode = "otg";
763	maximum-speed = "high-speed";
764	pinctrl-0 = <&usb_pins>;
765	pinctrl-names = "default";
766	usb-role-switch;
767	vusb33-supply = <&mt6357_vusb33_reg>;
768	status = "okay";
769
770	connector {
771		compatible = "gpio-usb-b-connector", "usb-b-connector";
772		id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
773		type = "micro";
774		vbus-supply = <&usb_otg_vbus>;
775	};
776};
777
778&usb_host {
779	vusb33-supply = <&mt6357_vusb33_reg>;
780	status = "okay";
781};
782
783&uart0 {
784	pinctrl-0 = <&uart0_pins>;
785	pinctrl-names = "default";
786	status = "okay";
787};
788
789&uart1 {
790	pinctrl-0 = <&uart1_pins>;
791	pinctrl-names = "default";
792	status = "okay";
793};
794
795&uart2 {
796	pinctrl-0 = <&uart2_pins>;
797	pinctrl-names = "default";
798	status = "okay";
799};
800