xref: /linux/arch/arm64/boot/dts/mediatek/mt8365-evk.dts (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021-2022 BayLibre, SAS.
4 * Authors:
5 * Fabien Parent <fparent@baylibre.com>
6 * Bernhard Rosenkränzer <bero@baylibre.com>
7 * Alexandre Mergnat <amergnat@baylibre.com>
8 */
9
10/dts-v1/;
11
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
15#include "mt8365.dtsi"
16#include "mt6357.dtsi"
17
18/ {
19	model = "MediaTek MT8365 Open Platform EVK";
20	compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
21
22	aliases {
23		serial0 = &uart0;
24	};
25
26	chosen {
27		stdout-path = "serial0:921600n8";
28	};
29
30	firmware {
31		optee {
32			compatible = "linaro,optee-tz";
33			method = "smc";
34		};
35	};
36
37	gpio-keys {
38		compatible = "gpio-keys";
39		pinctrl-names = "default";
40		pinctrl-0 = <&gpio_keys>;
41
42		key-volume-up {
43			gpios = <&pio 24 GPIO_ACTIVE_LOW>;
44			label = "volume_up";
45			linux,code = <KEY_VOLUMEUP>;
46			wakeup-source;
47			debounce-interval = <15>;
48		};
49	};
50
51	memory@40000000 {
52		device_type = "memory";
53		reg = <0 0x40000000 0 0xc0000000>;
54	};
55
56	usb_otg_vbus: regulator-0 {
57		compatible = "regulator-fixed";
58		regulator-name = "otg_vbus";
59		regulator-min-microvolt = <5000000>;
60		regulator-max-microvolt = <5000000>;
61		gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
62		enable-active-high;
63	};
64
65	reserved-memory {
66		#address-cells = <2>;
67		#size-cells = <2>;
68		ranges;
69
70		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
71		bl31_secmon_reserved: secmon@43000000 {
72			no-map;
73			reg = <0 0x43000000 0 0x30000>;
74		};
75
76		/* 12 MiB reserved for OP-TEE (BL32)
77		 * +-----------------------+ 0x43e0_0000
78		 * |      SHMEM 2MiB       |
79		 * +-----------------------+ 0x43c0_0000
80		 * |        | TA_RAM  8MiB |
81		 * + TZDRAM +--------------+ 0x4340_0000
82		 * |        | TEE_RAM 2MiB |
83		 * +-----------------------+ 0x4320_0000
84		 */
85		optee_reserved: optee@43200000 {
86			no-map;
87			reg = <0 0x43200000 0 0x00c00000>;
88		};
89	};
90
91	sound: sound {
92		compatible = "mediatek,mt8365-mt6357";
93		pinctrl-names = "default",
94				"dmic",
95				"miso_off",
96				"miso_on",
97				"mosi_off",
98				"mosi_on";
99		pinctrl-0 = <&aud_default_pins>;
100		pinctrl-1 = <&aud_dmic_pins>;
101		pinctrl-2 = <&aud_miso_off_pins>;
102		pinctrl-3 = <&aud_miso_on_pins>;
103		pinctrl-4 = <&aud_mosi_off_pins>;
104		pinctrl-5 = <&aud_mosi_on_pins>;
105		mediatek,platform = <&afe>;
106	};
107};
108
109&afe {
110	mediatek,dmic-mode = <1>;
111	status = "okay";
112};
113
114&cpu0 {
115	proc-supply = <&mt6357_vproc_reg>;
116	sram-supply = <&mt6357_vsram_proc_reg>;
117};
118
119&cpu1 {
120	proc-supply = <&mt6357_vproc_reg>;
121	sram-supply = <&mt6357_vsram_proc_reg>;
122};
123
124&cpu2 {
125	proc-supply = <&mt6357_vproc_reg>;
126	sram-supply = <&mt6357_vsram_proc_reg>;
127};
128
129&cpu3 {
130	proc-supply = <&mt6357_vproc_reg>;
131	sram-supply = <&mt6357_vsram_proc_reg>;
132};
133
134&ethernet {
135	pinctrl-0 = <&ethernet_pins>;
136	pinctrl-names = "default";
137	phy-handle = <&eth_phy>;
138	phy-mode = "rmii";
139	/*
140	 * Ethernet and HDMI (DSI0) are sharing pins.
141	 * Only one can be enabled at a time and require the physical switch
142	 * SW2101 to be set on LAN position
143	 * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet
144	 */
145	status = "disabled";
146
147	mdio {
148		#address-cells = <1>;
149		#size-cells = <0>;
150
151		eth_phy: ethernet-phy@0 {
152			reg = <0>;
153		};
154	};
155};
156
157&i2c0 {
158	clock-frequency = <100000>;
159	pinctrl-0 = <&i2c0_pins>;
160	pinctrl-names = "default";
161	status = "okay";
162};
163
164&mmc0 {
165	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
166	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
167	bus-width = <8>;
168	cap-mmc-highspeed;
169	cap-mmc-hw-reset;
170	hs400-ds-delay = <0x12012>;
171	max-frequency = <200000000>;
172	mmc-hs200-1_8v;
173	mmc-hs400-1_8v;
174	no-sd;
175	no-sdio;
176	non-removable;
177	pinctrl-0 = <&mmc0_default_pins>;
178	pinctrl-1 = <&mmc0_uhs_pins>;
179	pinctrl-names = "default", "state_uhs";
180	vmmc-supply = <&mt6357_vemc_reg>;
181	vqmmc-supply = <&mt6357_vio18_reg>;
182	status = "okay";
183};
184
185&mmc1 {
186	bus-width = <4>;
187	cap-sd-highspeed;
188	cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
189	max-frequency = <200000000>;
190	pinctrl-0 = <&mmc1_default_pins>;
191	pinctrl-1 = <&mmc1_uhs_pins>;
192	pinctrl-names = "default", "state_uhs";
193	sd-uhs-sdr104;
194	sd-uhs-sdr50;
195	vmmc-supply = <&mt6357_vmch_reg>;
196	vqmmc-supply = <&mt6357_vmc_reg>;
197	status = "okay";
198};
199
200&mt6357_pmic {
201	interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
202	interrupt-controller;
203	#interrupt-cells = <2>;
204	mediatek,micbias0-microvolt = <1900000>;
205	mediatek,micbias1-microvolt = <1700000>;
206};
207
208&pio {
209	aud_default_pins: audiodefault-pins {
210		clk-dat-pins {
211			pinmux = <MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK>,
212				 <MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK>,
213				 <MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK>,
214				 <MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO>;
215		};
216	};
217
218	aud_dmic_pins: audiodmic-pins {
219		clk-dat-pins {
220			pinmux = <MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK>,
221				 <MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0>,
222				 <MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1>;
223		};
224	};
225
226	aud_miso_off_pins: misooff-pins {
227		clk-dat-pins {
228			pinmux = <MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53>,
229				 <MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54>,
230				 <MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55>,
231				 <MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56>;
232			input-enable;
233			bias-pull-down;
234			drive-strength = <2>;
235		};
236	};
237
238	aud_miso_on_pins: misoon-pins {
239		clk-dat-pins {
240			pinmux = <MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO>,
241				 <MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO>,
242				 <MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0>,
243				 <MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1>;
244			drive-strength = <6>;
245		};
246	};
247
248	aud_mosi_off_pins: mosioff-pins {
249		clk-dat-pins {
250			pinmux = <MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49>,
251				 <MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50>,
252				 <MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51>,
253				 <MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52>;
254			input-enable;
255			bias-pull-down;
256			drive-strength = <2>;
257		};
258	};
259
260	aud_mosi_on_pins: mosion-pins {
261		clk-dat-pins {
262			pinmux = <MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI>,
263				 <MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI>,
264				 <MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0>,
265				 <MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1>;
266			drive-strength = <6>;
267		};
268	};
269
270	ethernet_pins: ethernet-pins {
271		phy_reset_pins {
272			pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
273		};
274
275		rmii_pins {
276			pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
277				 <MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
278				 <MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
279				 <MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
280				 <MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
281				 <MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
282				 <MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
283				 <MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
284				 <MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
285				 <MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
286				 <MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
287				 <MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
288				 <MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
289				 <MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
290				 <MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
291				 <MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
292		};
293	};
294
295	gpio_keys: gpio-keys-pins {
296		pins {
297			pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
298			bias-pull-up;
299			input-enable;
300		};
301	};
302
303	i2c0_pins: i2c0-pins {
304		pins {
305			pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
306				 <MT8365_PIN_58_SCL0__FUNC_SCL0_0>;
307			bias-pull-up;
308		};
309	};
310
311	mmc0_default_pins: mmc0-default-pins {
312		clk-pins {
313			pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
314			bias-pull-down;
315		};
316
317		cmd-dat-pins {
318			pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
319				 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
320				 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
321				 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
322				 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
323				 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
324				 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
325				 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
326				 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
327			input-enable;
328			bias-pull-up;
329		};
330
331		rst-pins {
332			pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
333			bias-pull-up;
334		};
335	};
336
337	mmc0_uhs_pins: mmc0-uhs-pins {
338		clk-pins {
339			pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
340			drive-strength = <MTK_DRIVE_10mA>;
341			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
342		};
343
344		cmd-dat-pins {
345			pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
346				 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
347				 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
348				 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
349				 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
350				 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
351				 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
352				 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
353				 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
354			input-enable;
355			drive-strength = <MTK_DRIVE_10mA>;
356			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
357		};
358
359		ds-pins {
360			pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
361			drive-strength = <MTK_DRIVE_10mA>;
362			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
363		};
364
365		rst-pins {
366			pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
367			drive-strength = <MTK_DRIVE_10mA>;
368			bias-pull-up;
369		};
370	};
371
372	mmc1_default_pins: mmc1-default-pins {
373		cd-pins {
374			pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
375			bias-pull-up;
376		};
377
378		clk-pins {
379			pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
380			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
381		};
382
383		cmd-dat-pins {
384			pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
385				 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
386				 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
387				 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
388				 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
389			input-enable;
390			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
391		};
392	};
393
394	mmc1_uhs_pins: mmc1-uhs-pins {
395		clk-pins {
396			pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
397			drive-strength = <8>;
398			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
399		};
400
401		cmd-dat-pins {
402			pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
403				 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
404				 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
405				 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
406				 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
407			input-enable;
408			drive-strength = <6>;
409			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
410		};
411	};
412
413	uart0_pins: uart0-pins {
414		pins {
415			pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
416				 <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
417		};
418	};
419
420	uart1_pins: uart1-pins {
421		pins {
422			pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
423				 <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
424		};
425	};
426
427	uart2_pins: uart2-pins {
428		pins {
429			pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
430				 <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
431		};
432	};
433
434	usb_pins: usb-pins {
435		id-pins {
436			pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
437			input-enable;
438			bias-pull-up;
439		};
440
441		usb0-vbus-pins {
442			pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
443			output-high;
444		};
445
446		usb1-vbus-pins {
447			pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
448			output-high;
449		};
450	};
451
452	pwm_pins: pwm-pins {
453		pins {
454			pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
455				 <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
456		};
457	};
458};
459
460&pwm {
461	pinctrl-0 = <&pwm_pins>;
462	pinctrl-names = "default";
463	status = "okay";
464};
465
466&ssusb {
467	dr_mode = "otg";
468	maximum-speed = "high-speed";
469	pinctrl-0 = <&usb_pins>;
470	pinctrl-names = "default";
471	usb-role-switch;
472	vusb33-supply = <&mt6357_vusb33_reg>;
473	status = "okay";
474
475	connector {
476		compatible = "gpio-usb-b-connector", "usb-b-connector";
477		id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
478		type = "micro";
479		vbus-supply = <&usb_otg_vbus>;
480	};
481};
482
483&usb_host {
484	vusb33-supply = <&mt6357_vusb33_reg>;
485	status = "okay";
486};
487
488&uart0 {
489	pinctrl-0 = <&uart0_pins>;
490	pinctrl-names = "default";
491	status = "okay";
492};
493
494&uart1 {
495	pinctrl-0 = <&uart1_pins>;
496	pinctrl-names = "default";
497	status = "okay";
498};
499
500&uart2 {
501	pinctrl-0 = <&uart2_pins>;
502	pinctrl-names = "default";
503	status = "okay";
504};
505