1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/gce/mt8195-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8195-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/power/mt8195-power.h> 16#include <dt-bindings/reset/mt8195-resets.h> 17 18/ { 19 compatible = "mediatek,mt8195"; 20 interrupt-parent = <&gic>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 gce0 = &gce0; 26 gce1 = &gce1; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a55"; 36 reg = <0x000>; 37 enable-method = "psci"; 38 performance-domains = <&performance 0>; 39 clock-frequency = <1701000000>; 40 capacity-dmips-mhz = <308>; 41 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 42 i-cache-size = <32768>; 43 i-cache-line-size = <64>; 44 i-cache-sets = <128>; 45 d-cache-size = <32768>; 46 d-cache-line-size = <64>; 47 d-cache-sets = <128>; 48 next-level-cache = <&l2_0>; 49 #cooling-cells = <2>; 50 }; 51 52 cpu1: cpu@100 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x100>; 56 enable-method = "psci"; 57 performance-domains = <&performance 0>; 58 clock-frequency = <1701000000>; 59 capacity-dmips-mhz = <308>; 60 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 61 i-cache-size = <32768>; 62 i-cache-line-size = <64>; 63 i-cache-sets = <128>; 64 d-cache-size = <32768>; 65 d-cache-line-size = <64>; 66 d-cache-sets = <128>; 67 next-level-cache = <&l2_0>; 68 #cooling-cells = <2>; 69 }; 70 71 cpu2: cpu@200 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x200>; 75 enable-method = "psci"; 76 performance-domains = <&performance 0>; 77 clock-frequency = <1701000000>; 78 capacity-dmips-mhz = <308>; 79 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 80 i-cache-size = <32768>; 81 i-cache-line-size = <64>; 82 i-cache-sets = <128>; 83 d-cache-size = <32768>; 84 d-cache-line-size = <64>; 85 d-cache-sets = <128>; 86 next-level-cache = <&l2_0>; 87 #cooling-cells = <2>; 88 }; 89 90 cpu3: cpu@300 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a55"; 93 reg = <0x300>; 94 enable-method = "psci"; 95 performance-domains = <&performance 0>; 96 clock-frequency = <1701000000>; 97 capacity-dmips-mhz = <308>; 98 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 99 i-cache-size = <32768>; 100 i-cache-line-size = <64>; 101 i-cache-sets = <128>; 102 d-cache-size = <32768>; 103 d-cache-line-size = <64>; 104 d-cache-sets = <128>; 105 next-level-cache = <&l2_0>; 106 #cooling-cells = <2>; 107 }; 108 109 cpu4: cpu@400 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a78"; 112 reg = <0x400>; 113 enable-method = "psci"; 114 performance-domains = <&performance 1>; 115 clock-frequency = <2171000000>; 116 capacity-dmips-mhz = <1024>; 117 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 118 i-cache-size = <65536>; 119 i-cache-line-size = <64>; 120 i-cache-sets = <256>; 121 d-cache-size = <65536>; 122 d-cache-line-size = <64>; 123 d-cache-sets = <256>; 124 next-level-cache = <&l2_1>; 125 #cooling-cells = <2>; 126 }; 127 128 cpu5: cpu@500 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a78"; 131 reg = <0x500>; 132 enable-method = "psci"; 133 performance-domains = <&performance 1>; 134 clock-frequency = <2171000000>; 135 capacity-dmips-mhz = <1024>; 136 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 137 i-cache-size = <65536>; 138 i-cache-line-size = <64>; 139 i-cache-sets = <256>; 140 d-cache-size = <65536>; 141 d-cache-line-size = <64>; 142 d-cache-sets = <256>; 143 next-level-cache = <&l2_1>; 144 #cooling-cells = <2>; 145 }; 146 147 cpu6: cpu@600 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a78"; 150 reg = <0x600>; 151 enable-method = "psci"; 152 performance-domains = <&performance 1>; 153 clock-frequency = <2171000000>; 154 capacity-dmips-mhz = <1024>; 155 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 156 i-cache-size = <65536>; 157 i-cache-line-size = <64>; 158 i-cache-sets = <256>; 159 d-cache-size = <65536>; 160 d-cache-line-size = <64>; 161 d-cache-sets = <256>; 162 next-level-cache = <&l2_1>; 163 #cooling-cells = <2>; 164 }; 165 166 cpu7: cpu@700 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a78"; 169 reg = <0x700>; 170 enable-method = "psci"; 171 performance-domains = <&performance 1>; 172 clock-frequency = <2171000000>; 173 capacity-dmips-mhz = <1024>; 174 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 175 i-cache-size = <65536>; 176 i-cache-line-size = <64>; 177 i-cache-sets = <256>; 178 d-cache-size = <65536>; 179 d-cache-line-size = <64>; 180 d-cache-sets = <256>; 181 next-level-cache = <&l2_1>; 182 #cooling-cells = <2>; 183 }; 184 185 cpu-map { 186 cluster0 { 187 core0 { 188 cpu = <&cpu0>; 189 }; 190 191 core1 { 192 cpu = <&cpu1>; 193 }; 194 195 core2 { 196 cpu = <&cpu2>; 197 }; 198 199 core3 { 200 cpu = <&cpu3>; 201 }; 202 }; 203 204 cluster1 { 205 core0 { 206 cpu = <&cpu4>; 207 }; 208 209 core1 { 210 cpu = <&cpu5>; 211 }; 212 213 core2 { 214 cpu = <&cpu6>; 215 }; 216 217 core3 { 218 cpu = <&cpu7>; 219 }; 220 }; 221 }; 222 223 idle-states { 224 entry-method = "psci"; 225 226 cpu_off_l: cpu-off-l { 227 compatible = "arm,idle-state"; 228 arm,psci-suspend-param = <0x00010001>; 229 local-timer-stop; 230 entry-latency-us = <50>; 231 exit-latency-us = <95>; 232 min-residency-us = <580>; 233 }; 234 235 cpu_off_b: cpu-off-b { 236 compatible = "arm,idle-state"; 237 arm,psci-suspend-param = <0x00010001>; 238 local-timer-stop; 239 entry-latency-us = <45>; 240 exit-latency-us = <140>; 241 min-residency-us = <740>; 242 }; 243 244 cluster_off_l: cluster-off-l { 245 compatible = "arm,idle-state"; 246 arm,psci-suspend-param = <0x01010002>; 247 local-timer-stop; 248 entry-latency-us = <55>; 249 exit-latency-us = <155>; 250 min-residency-us = <840>; 251 }; 252 253 cluster_off_b: cluster-off-b { 254 compatible = "arm,idle-state"; 255 arm,psci-suspend-param = <0x01010002>; 256 local-timer-stop; 257 entry-latency-us = <50>; 258 exit-latency-us = <200>; 259 min-residency-us = <1000>; 260 }; 261 }; 262 263 l2_0: l2-cache0 { 264 compatible = "cache"; 265 cache-level = <2>; 266 cache-size = <131072>; 267 cache-line-size = <64>; 268 cache-sets = <512>; 269 next-level-cache = <&l3_0>; 270 }; 271 272 l2_1: l2-cache1 { 273 compatible = "cache"; 274 cache-level = <2>; 275 cache-size = <262144>; 276 cache-line-size = <64>; 277 cache-sets = <512>; 278 next-level-cache = <&l3_0>; 279 }; 280 281 l3_0: l3-cache { 282 compatible = "cache"; 283 cache-level = <3>; 284 cache-size = <2097152>; 285 cache-line-size = <64>; 286 cache-sets = <2048>; 287 cache-unified; 288 }; 289 }; 290 291 dsu-pmu { 292 compatible = "arm,dsu-pmu"; 293 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 294 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 295 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 296 }; 297 298 dmic_codec: dmic-codec { 299 compatible = "dmic-codec"; 300 num-channels = <2>; 301 wakeup-delay-ms = <50>; 302 }; 303 304 sound: mt8195-sound { 305 mediatek,platform = <&afe>; 306 status = "disabled"; 307 }; 308 309 clk13m: fixed-factor-clock-13m { 310 compatible = "fixed-factor-clock"; 311 #clock-cells = <0>; 312 clocks = <&clk26m>; 313 clock-div = <2>; 314 clock-mult = <1>; 315 clock-output-names = "clk13m"; 316 }; 317 318 clk26m: oscillator-26m { 319 compatible = "fixed-clock"; 320 #clock-cells = <0>; 321 clock-frequency = <26000000>; 322 clock-output-names = "clk26m"; 323 }; 324 325 clk32k: oscillator-32k { 326 compatible = "fixed-clock"; 327 #clock-cells = <0>; 328 clock-frequency = <32768>; 329 clock-output-names = "clk32k"; 330 }; 331 332 performance: performance-controller@11bc10 { 333 compatible = "mediatek,cpufreq-hw"; 334 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 335 #performance-domain-cells = <1>; 336 }; 337 338 pmu-a55 { 339 compatible = "arm,cortex-a55-pmu"; 340 interrupt-parent = <&gic>; 341 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 342 }; 343 344 pmu-a78 { 345 compatible = "arm,cortex-a78-pmu"; 346 interrupt-parent = <&gic>; 347 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 348 }; 349 350 psci { 351 compatible = "arm,psci-1.0"; 352 method = "smc"; 353 }; 354 355 timer: timer { 356 compatible = "arm,armv8-timer"; 357 interrupt-parent = <&gic>; 358 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 359 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 360 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 361 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 362 }; 363 364 soc { 365 #address-cells = <2>; 366 #size-cells = <2>; 367 compatible = "simple-bus"; 368 ranges; 369 370 gic: interrupt-controller@c000000 { 371 compatible = "arm,gic-v3"; 372 #interrupt-cells = <4>; 373 #redistributor-regions = <1>; 374 interrupt-parent = <&gic>; 375 interrupt-controller; 376 reg = <0 0x0c000000 0 0x40000>, 377 <0 0x0c040000 0 0x200000>; 378 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 379 380 ppi-partitions { 381 ppi_cluster0: interrupt-partition-0 { 382 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 383 }; 384 385 ppi_cluster1: interrupt-partition-1 { 386 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 387 }; 388 }; 389 }; 390 391 topckgen: syscon@10000000 { 392 compatible = "mediatek,mt8195-topckgen", "syscon"; 393 reg = <0 0x10000000 0 0x1000>; 394 #clock-cells = <1>; 395 }; 396 397 infracfg_ao: syscon@10001000 { 398 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 399 reg = <0 0x10001000 0 0x1000>; 400 #clock-cells = <1>; 401 #reset-cells = <1>; 402 }; 403 404 pericfg: syscon@10003000 { 405 compatible = "mediatek,mt8195-pericfg", "syscon"; 406 reg = <0 0x10003000 0 0x1000>; 407 #clock-cells = <1>; 408 }; 409 410 pio: pinctrl@10005000 { 411 compatible = "mediatek,mt8195-pinctrl"; 412 reg = <0 0x10005000 0 0x1000>, 413 <0 0x11d10000 0 0x1000>, 414 <0 0x11d30000 0 0x1000>, 415 <0 0x11d40000 0 0x1000>, 416 <0 0x11e20000 0 0x1000>, 417 <0 0x11eb0000 0 0x1000>, 418 <0 0x11f40000 0 0x1000>, 419 <0 0x1000b000 0 0x1000>; 420 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 421 "iocfg_br", "iocfg_lm", "iocfg_rb", 422 "iocfg_tl", "eint"; 423 gpio-controller; 424 #gpio-cells = <2>; 425 gpio-ranges = <&pio 0 0 144>; 426 interrupt-controller; 427 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 428 #interrupt-cells = <2>; 429 }; 430 431 scpsys: syscon@10006000 { 432 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 433 reg = <0 0x10006000 0 0x1000>; 434 435 /* System Power Manager */ 436 spm: power-controller { 437 compatible = "mediatek,mt8195-power-controller"; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 #power-domain-cells = <1>; 441 442 /* power domain of the SoC */ 443 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 444 reg = <MT8195_POWER_DOMAIN_MFG0>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 #power-domain-cells = <1>; 448 449 power-domain@MT8195_POWER_DOMAIN_MFG1 { 450 reg = <MT8195_POWER_DOMAIN_MFG1>; 451 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; 452 clock-names = "mfg"; 453 mediatek,infracfg = <&infracfg_ao>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 #power-domain-cells = <1>; 457 458 power-domain@MT8195_POWER_DOMAIN_MFG2 { 459 reg = <MT8195_POWER_DOMAIN_MFG2>; 460 #power-domain-cells = <0>; 461 }; 462 463 power-domain@MT8195_POWER_DOMAIN_MFG3 { 464 reg = <MT8195_POWER_DOMAIN_MFG3>; 465 #power-domain-cells = <0>; 466 }; 467 468 power-domain@MT8195_POWER_DOMAIN_MFG4 { 469 reg = <MT8195_POWER_DOMAIN_MFG4>; 470 #power-domain-cells = <0>; 471 }; 472 473 power-domain@MT8195_POWER_DOMAIN_MFG5 { 474 reg = <MT8195_POWER_DOMAIN_MFG5>; 475 #power-domain-cells = <0>; 476 }; 477 478 power-domain@MT8195_POWER_DOMAIN_MFG6 { 479 reg = <MT8195_POWER_DOMAIN_MFG6>; 480 #power-domain-cells = <0>; 481 }; 482 }; 483 }; 484 485 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 486 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 487 clocks = <&topckgen CLK_TOP_VPP>, 488 <&topckgen CLK_TOP_CAM>, 489 <&topckgen CLK_TOP_CCU>, 490 <&topckgen CLK_TOP_IMG>, 491 <&topckgen CLK_TOP_VENC>, 492 <&topckgen CLK_TOP_VDEC>, 493 <&topckgen CLK_TOP_WPE_VPP>, 494 <&topckgen CLK_TOP_CFG_VPP0>, 495 <&vppsys0 CLK_VPP0_SMI_COMMON>, 496 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 497 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 498 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 499 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 500 <&vppsys0 CLK_VPP0_GALS_INFRA>, 501 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 502 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 503 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 504 <&vppsys0 CLK_VPP0_SMI_REORDER>, 505 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 506 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 507 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 508 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 509 <&vppsys0 CLK_VPP0_SMI_RSI>, 510 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 511 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 512 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 513 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 514 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 515 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 516 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 517 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 518 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 519 "vppsys0-12", "vppsys0-13", "vppsys0-14", 520 "vppsys0-15", "vppsys0-16", "vppsys0-17", 521 "vppsys0-18"; 522 mediatek,infracfg = <&infracfg_ao>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 #power-domain-cells = <1>; 526 527 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 528 reg = <MT8195_POWER_DOMAIN_VDEC1>; 529 clocks = <&vdecsys CLK_VDEC_LARB1>; 530 clock-names = "vdec1-0"; 531 mediatek,infracfg = <&infracfg_ao>; 532 #power-domain-cells = <0>; 533 }; 534 535 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 536 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 537 mediatek,infracfg = <&infracfg_ao>; 538 #power-domain-cells = <0>; 539 }; 540 541 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 542 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 543 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 544 <&vdosys0 CLK_VDO0_SMI_GALS>, 545 <&vdosys0 CLK_VDO0_SMI_COMMON>, 546 <&vdosys0 CLK_VDO0_SMI_EMI>, 547 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 548 <&vdosys0 CLK_VDO0_SMI_LARB>, 549 <&vdosys0 CLK_VDO0_SMI_RSI>; 550 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 551 "vdosys0-2", "vdosys0-3", 552 "vdosys0-4", "vdosys0-5"; 553 mediatek,infracfg = <&infracfg_ao>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 #power-domain-cells = <1>; 557 558 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 559 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 560 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 561 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 562 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 563 clock-names = "vppsys1", "vppsys1-0", 564 "vppsys1-1"; 565 mediatek,infracfg = <&infracfg_ao>; 566 #power-domain-cells = <0>; 567 }; 568 569 power-domain@MT8195_POWER_DOMAIN_WPESYS { 570 reg = <MT8195_POWER_DOMAIN_WPESYS>; 571 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 572 <&wpesys CLK_WPE_SMI_LARB8>, 573 <&wpesys CLK_WPE_SMI_LARB7_P>, 574 <&wpesys CLK_WPE_SMI_LARB8_P>; 575 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 576 "wepsys-3"; 577 mediatek,infracfg = <&infracfg_ao>; 578 #power-domain-cells = <0>; 579 }; 580 581 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 582 reg = <MT8195_POWER_DOMAIN_VDEC0>; 583 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 584 clock-names = "vdec0-0"; 585 mediatek,infracfg = <&infracfg_ao>; 586 #power-domain-cells = <0>; 587 }; 588 589 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 590 reg = <MT8195_POWER_DOMAIN_VDEC2>; 591 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 592 clock-names = "vdec2-0"; 593 mediatek,infracfg = <&infracfg_ao>; 594 #power-domain-cells = <0>; 595 }; 596 597 power-domain@MT8195_POWER_DOMAIN_VENC { 598 reg = <MT8195_POWER_DOMAIN_VENC>; 599 mediatek,infracfg = <&infracfg_ao>; 600 #power-domain-cells = <0>; 601 }; 602 603 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 604 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 605 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 606 <&vdosys1 CLK_VDO1_SMI_LARB2>, 607 <&vdosys1 CLK_VDO1_SMI_LARB3>, 608 <&vdosys1 CLK_VDO1_GALS>; 609 clock-names = "vdosys1", "vdosys1-0", 610 "vdosys1-1", "vdosys1-2"; 611 mediatek,infracfg = <&infracfg_ao>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 #power-domain-cells = <1>; 615 616 power-domain@MT8195_POWER_DOMAIN_DP_TX { 617 reg = <MT8195_POWER_DOMAIN_DP_TX>; 618 mediatek,infracfg = <&infracfg_ao>; 619 #power-domain-cells = <0>; 620 }; 621 622 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 623 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 624 mediatek,infracfg = <&infracfg_ao>; 625 #power-domain-cells = <0>; 626 }; 627 628 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 629 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 630 clocks = <&topckgen CLK_TOP_HDMI_APB>; 631 clock-names = "hdmi_tx"; 632 #power-domain-cells = <0>; 633 }; 634 }; 635 636 power-domain@MT8195_POWER_DOMAIN_IMG { 637 reg = <MT8195_POWER_DOMAIN_IMG>; 638 clocks = <&imgsys CLK_IMG_LARB9>, 639 <&imgsys CLK_IMG_GALS>; 640 clock-names = "img-0", "img-1"; 641 mediatek,infracfg = <&infracfg_ao>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 #power-domain-cells = <1>; 645 646 power-domain@MT8195_POWER_DOMAIN_DIP { 647 reg = <MT8195_POWER_DOMAIN_DIP>; 648 #power-domain-cells = <0>; 649 }; 650 651 power-domain@MT8195_POWER_DOMAIN_IPE { 652 reg = <MT8195_POWER_DOMAIN_IPE>; 653 clocks = <&topckgen CLK_TOP_IPE>, 654 <&imgsys CLK_IMG_IPE>, 655 <&ipesys CLK_IPE_SMI_LARB12>; 656 clock-names = "ipe", "ipe-0", "ipe-1"; 657 mediatek,infracfg = <&infracfg_ao>; 658 #power-domain-cells = <0>; 659 }; 660 }; 661 662 power-domain@MT8195_POWER_DOMAIN_CAM { 663 reg = <MT8195_POWER_DOMAIN_CAM>; 664 clocks = <&camsys CLK_CAM_LARB13>, 665 <&camsys CLK_CAM_LARB14>, 666 <&camsys CLK_CAM_CAM2MM0_GALS>, 667 <&camsys CLK_CAM_CAM2MM1_GALS>, 668 <&camsys CLK_CAM_CAM2SYS_GALS>; 669 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 670 "cam-4"; 671 mediatek,infracfg = <&infracfg_ao>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 #power-domain-cells = <1>; 675 676 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 677 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 678 #power-domain-cells = <0>; 679 }; 680 681 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 682 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 683 #power-domain-cells = <0>; 684 }; 685 686 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 687 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 688 #power-domain-cells = <0>; 689 }; 690 }; 691 }; 692 }; 693 694 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 695 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 696 mediatek,infracfg = <&infracfg_ao>; 697 #power-domain-cells = <0>; 698 }; 699 700 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 701 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 702 mediatek,infracfg = <&infracfg_ao>; 703 #power-domain-cells = <0>; 704 }; 705 706 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 707 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 708 #power-domain-cells = <0>; 709 }; 710 711 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 712 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 713 #power-domain-cells = <0>; 714 }; 715 716 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 717 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 718 clocks = <&topckgen CLK_TOP_SENINF>, 719 <&topckgen CLK_TOP_SENINF2>; 720 clock-names = "csi_rx_top", "csi_rx_top1"; 721 #power-domain-cells = <0>; 722 }; 723 724 power-domain@MT8195_POWER_DOMAIN_ETHER { 725 reg = <MT8195_POWER_DOMAIN_ETHER>; 726 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 727 clock-names = "ether"; 728 #power-domain-cells = <0>; 729 }; 730 731 power-domain@MT8195_POWER_DOMAIN_ADSP { 732 reg = <MT8195_POWER_DOMAIN_ADSP>; 733 clocks = <&topckgen CLK_TOP_ADSP>, 734 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 735 clock-names = "adsp", "adsp1"; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 mediatek,infracfg = <&infracfg_ao>; 739 #power-domain-cells = <1>; 740 741 power-domain@MT8195_POWER_DOMAIN_AUDIO { 742 reg = <MT8195_POWER_DOMAIN_AUDIO>; 743 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 744 <&topckgen CLK_TOP_AUD_INTBUS>, 745 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 746 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 747 clock-names = "audio", "audio1", "audio2", 748 "audio3"; 749 mediatek,infracfg = <&infracfg_ao>; 750 #power-domain-cells = <0>; 751 }; 752 }; 753 }; 754 }; 755 756 watchdog: watchdog@10007000 { 757 compatible = "mediatek,mt8195-wdt", 758 "mediatek,mt6589-wdt"; 759 mediatek,disable-extrst; 760 reg = <0 0x10007000 0 0x100>; 761 #reset-cells = <1>; 762 }; 763 764 apmixedsys: syscon@1000c000 { 765 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 766 reg = <0 0x1000c000 0 0x1000>; 767 #clock-cells = <1>; 768 }; 769 770 systimer: timer@10017000 { 771 compatible = "mediatek,mt8195-timer", 772 "mediatek,mt6765-timer"; 773 reg = <0 0x10017000 0 0x1000>; 774 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 775 clocks = <&clk13m>; 776 }; 777 778 pwrap: pwrap@10024000 { 779 compatible = "mediatek,mt8195-pwrap", "syscon"; 780 reg = <0 0x10024000 0 0x1000>; 781 reg-names = "pwrap"; 782 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 783 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 784 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 785 clock-names = "spi", "wrap"; 786 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 787 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 788 }; 789 790 spmi: spmi@10027000 { 791 compatible = "mediatek,mt8195-spmi"; 792 reg = <0 0x10027000 0 0x000e00>, 793 <0 0x10029000 0 0x000100>; 794 reg-names = "pmif", "spmimst"; 795 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 796 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 797 <&topckgen CLK_TOP_SPMI_M_MST>; 798 clock-names = "pmif_sys_ck", 799 "pmif_tmr_ck", 800 "spmimst_clk_mux"; 801 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 802 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 803 }; 804 805 iommu_infra: infra-iommu@10315000 { 806 compatible = "mediatek,mt8195-iommu-infra"; 807 reg = <0 0x10315000 0 0x5000>; 808 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 809 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 810 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 811 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 812 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 813 #iommu-cells = <1>; 814 }; 815 816 gce0: mailbox@10320000 { 817 compatible = "mediatek,mt8195-gce"; 818 reg = <0 0x10320000 0 0x4000>; 819 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 820 #mbox-cells = <2>; 821 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 822 }; 823 824 gce1: mailbox@10330000 { 825 compatible = "mediatek,mt8195-gce"; 826 reg = <0 0x10330000 0 0x4000>; 827 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 828 #mbox-cells = <2>; 829 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 830 }; 831 832 scp: scp@10500000 { 833 compatible = "mediatek,mt8195-scp"; 834 reg = <0 0x10500000 0 0x100000>, 835 <0 0x10720000 0 0xe0000>, 836 <0 0x10700000 0 0x8000>; 837 reg-names = "sram", "cfg", "l1tcm"; 838 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 839 status = "disabled"; 840 }; 841 842 scp_adsp: clock-controller@10720000 { 843 compatible = "mediatek,mt8195-scp_adsp"; 844 reg = <0 0x10720000 0 0x1000>; 845 #clock-cells = <1>; 846 }; 847 848 adsp: dsp@10803000 { 849 compatible = "mediatek,mt8195-dsp"; 850 reg = <0 0x10803000 0 0x1000>, 851 <0 0x10840000 0 0x40000>; 852 reg-names = "cfg", "sram"; 853 clocks = <&topckgen CLK_TOP_ADSP>, 854 <&clk26m>, 855 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 856 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 857 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 858 <&topckgen CLK_TOP_AUDIO_H>; 859 clock-names = "adsp_sel", 860 "clk26m_ck", 861 "audio_local_bus", 862 "mainpll_d7_d2", 863 "scp_adsp_audiodsp", 864 "audio_h"; 865 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 866 mbox-names = "rx", "tx"; 867 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 868 status = "disabled"; 869 }; 870 871 adsp_mailbox0: mailbox@10816000 { 872 compatible = "mediatek,mt8195-adsp-mbox"; 873 #mbox-cells = <0>; 874 reg = <0 0x10816000 0 0x1000>; 875 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 876 }; 877 878 adsp_mailbox1: mailbox@10817000 { 879 compatible = "mediatek,mt8195-adsp-mbox"; 880 #mbox-cells = <0>; 881 reg = <0 0x10817000 0 0x1000>; 882 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 883 }; 884 885 afe: mt8195-afe-pcm@10890000 { 886 compatible = "mediatek,mt8195-audio"; 887 reg = <0 0x10890000 0 0x10000>; 888 mediatek,topckgen = <&topckgen>; 889 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 890 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 891 resets = <&watchdog 14>; 892 reset-names = "audiosys"; 893 clocks = <&clk26m>, 894 <&apmixedsys CLK_APMIXED_APLL1>, 895 <&apmixedsys CLK_APMIXED_APLL2>, 896 <&topckgen CLK_TOP_APLL12_DIV0>, 897 <&topckgen CLK_TOP_APLL12_DIV1>, 898 <&topckgen CLK_TOP_APLL12_DIV2>, 899 <&topckgen CLK_TOP_APLL12_DIV3>, 900 <&topckgen CLK_TOP_APLL12_DIV9>, 901 <&topckgen CLK_TOP_A1SYS_HP>, 902 <&topckgen CLK_TOP_AUD_INTBUS>, 903 <&topckgen CLK_TOP_AUDIO_H>, 904 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 905 <&topckgen CLK_TOP_DPTX_MCK>, 906 <&topckgen CLK_TOP_I2SO1_MCK>, 907 <&topckgen CLK_TOP_I2SO2_MCK>, 908 <&topckgen CLK_TOP_I2SI1_MCK>, 909 <&topckgen CLK_TOP_I2SI2_MCK>, 910 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 911 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 912 clock-names = "clk26m", 913 "apll1_ck", 914 "apll2_ck", 915 "apll12_div0", 916 "apll12_div1", 917 "apll12_div2", 918 "apll12_div3", 919 "apll12_div9", 920 "a1sys_hp_sel", 921 "aud_intbus_sel", 922 "audio_h_sel", 923 "audio_local_bus_sel", 924 "dptx_m_sel", 925 "i2so1_m_sel", 926 "i2so2_m_sel", 927 "i2si1_m_sel", 928 "i2si2_m_sel", 929 "infra_ao_audio_26m_b", 930 "scp_adsp_audiodsp"; 931 status = "disabled"; 932 }; 933 934 uart0: serial@11001100 { 935 compatible = "mediatek,mt8195-uart", 936 "mediatek,mt6577-uart"; 937 reg = <0 0x11001100 0 0x100>; 938 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 939 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 940 clock-names = "baud", "bus"; 941 status = "disabled"; 942 }; 943 944 uart1: serial@11001200 { 945 compatible = "mediatek,mt8195-uart", 946 "mediatek,mt6577-uart"; 947 reg = <0 0x11001200 0 0x100>; 948 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 949 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 950 clock-names = "baud", "bus"; 951 status = "disabled"; 952 }; 953 954 uart2: serial@11001300 { 955 compatible = "mediatek,mt8195-uart", 956 "mediatek,mt6577-uart"; 957 reg = <0 0x11001300 0 0x100>; 958 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 959 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 960 clock-names = "baud", "bus"; 961 status = "disabled"; 962 }; 963 964 uart3: serial@11001400 { 965 compatible = "mediatek,mt8195-uart", 966 "mediatek,mt6577-uart"; 967 reg = <0 0x11001400 0 0x100>; 968 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 969 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 970 clock-names = "baud", "bus"; 971 status = "disabled"; 972 }; 973 974 uart4: serial@11001500 { 975 compatible = "mediatek,mt8195-uart", 976 "mediatek,mt6577-uart"; 977 reg = <0 0x11001500 0 0x100>; 978 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 979 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 980 clock-names = "baud", "bus"; 981 status = "disabled"; 982 }; 983 984 uart5: serial@11001600 { 985 compatible = "mediatek,mt8195-uart", 986 "mediatek,mt6577-uart"; 987 reg = <0 0x11001600 0 0x100>; 988 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 989 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 990 clock-names = "baud", "bus"; 991 status = "disabled"; 992 }; 993 994 auxadc: auxadc@11002000 { 995 compatible = "mediatek,mt8195-auxadc", 996 "mediatek,mt8173-auxadc"; 997 reg = <0 0x11002000 0 0x1000>; 998 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 999 clock-names = "main"; 1000 #io-channel-cells = <1>; 1001 status = "disabled"; 1002 }; 1003 1004 pericfg_ao: syscon@11003000 { 1005 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 1006 reg = <0 0x11003000 0 0x1000>; 1007 #clock-cells = <1>; 1008 }; 1009 1010 spi0: spi@1100a000 { 1011 compatible = "mediatek,mt8195-spi", 1012 "mediatek,mt6765-spi"; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 reg = <0 0x1100a000 0 0x1000>; 1016 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1017 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1018 <&topckgen CLK_TOP_SPI>, 1019 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1020 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1021 status = "disabled"; 1022 }; 1023 1024 spi1: spi@11010000 { 1025 compatible = "mediatek,mt8195-spi", 1026 "mediatek,mt6765-spi"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 reg = <0 0x11010000 0 0x1000>; 1030 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1031 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1032 <&topckgen CLK_TOP_SPI>, 1033 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1034 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1035 status = "disabled"; 1036 }; 1037 1038 spi2: spi@11012000 { 1039 compatible = "mediatek,mt8195-spi", 1040 "mediatek,mt6765-spi"; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 reg = <0 0x11012000 0 0x1000>; 1044 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1045 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1046 <&topckgen CLK_TOP_SPI>, 1047 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1048 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1049 status = "disabled"; 1050 }; 1051 1052 spi3: spi@11013000 { 1053 compatible = "mediatek,mt8195-spi", 1054 "mediatek,mt6765-spi"; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 reg = <0 0x11013000 0 0x1000>; 1058 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1059 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1060 <&topckgen CLK_TOP_SPI>, 1061 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1062 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1063 status = "disabled"; 1064 }; 1065 1066 spi4: spi@11018000 { 1067 compatible = "mediatek,mt8195-spi", 1068 "mediatek,mt6765-spi"; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 reg = <0 0x11018000 0 0x1000>; 1072 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1073 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1074 <&topckgen CLK_TOP_SPI>, 1075 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1076 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1077 status = "disabled"; 1078 }; 1079 1080 spi5: spi@11019000 { 1081 compatible = "mediatek,mt8195-spi", 1082 "mediatek,mt6765-spi"; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 reg = <0 0x11019000 0 0x1000>; 1086 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1087 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1088 <&topckgen CLK_TOP_SPI>, 1089 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1090 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1091 status = "disabled"; 1092 }; 1093 1094 spis0: spi@1101d000 { 1095 compatible = "mediatek,mt8195-spi-slave"; 1096 reg = <0 0x1101d000 0 0x1000>; 1097 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1098 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1099 clock-names = "spi"; 1100 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1102 status = "disabled"; 1103 }; 1104 1105 spis1: spi@1101e000 { 1106 compatible = "mediatek,mt8195-spi-slave"; 1107 reg = <0 0x1101e000 0 0x1000>; 1108 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1109 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1110 clock-names = "spi"; 1111 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1112 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1113 status = "disabled"; 1114 }; 1115 1116 eth: ethernet@11021000 { 1117 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; 1118 reg = <0 0x11021000 0 0x4000>; 1119 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1120 interrupt-names = "macirq"; 1121 clock-names = "axi", 1122 "apb", 1123 "mac_main", 1124 "ptp_ref", 1125 "rmii_internal", 1126 "mac_cg"; 1127 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1128 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1129 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1130 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1131 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1132 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1133 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1134 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1135 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1136 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1137 <&topckgen CLK_TOP_ETHPLL_D8>, 1138 <&topckgen CLK_TOP_ETHPLL_D10>; 1139 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; 1140 mediatek,pericfg = <&infracfg_ao>; 1141 snps,axi-config = <&stmmac_axi_setup>; 1142 snps,mtl-rx-config = <&mtl_rx_setup>; 1143 snps,mtl-tx-config = <&mtl_tx_setup>; 1144 snps,txpbl = <16>; 1145 snps,rxpbl = <16>; 1146 snps,clk-csr = <0>; 1147 status = "disabled"; 1148 1149 mdio { 1150 compatible = "snps,dwmac-mdio"; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 }; 1154 1155 stmmac_axi_setup: stmmac-axi-config { 1156 snps,wr_osr_lmt = <0x7>; 1157 snps,rd_osr_lmt = <0x7>; 1158 snps,blen = <0 0 0 0 16 8 4>; 1159 }; 1160 1161 mtl_rx_setup: rx-queues-config { 1162 snps,rx-queues-to-use = <4>; 1163 snps,rx-sched-sp; 1164 queue0 { 1165 snps,dcb-algorithm; 1166 snps,map-to-dma-channel = <0x0>; 1167 }; 1168 queue1 { 1169 snps,dcb-algorithm; 1170 snps,map-to-dma-channel = <0x0>; 1171 }; 1172 queue2 { 1173 snps,dcb-algorithm; 1174 snps,map-to-dma-channel = <0x0>; 1175 }; 1176 queue3 { 1177 snps,dcb-algorithm; 1178 snps,map-to-dma-channel = <0x0>; 1179 }; 1180 }; 1181 1182 mtl_tx_setup: tx-queues-config { 1183 snps,tx-queues-to-use = <4>; 1184 snps,tx-sched-wrr; 1185 queue0 { 1186 snps,weight = <0x10>; 1187 snps,dcb-algorithm; 1188 snps,priority = <0x0>; 1189 }; 1190 queue1 { 1191 snps,weight = <0x11>; 1192 snps,dcb-algorithm; 1193 snps,priority = <0x1>; 1194 }; 1195 queue2 { 1196 snps,weight = <0x12>; 1197 snps,dcb-algorithm; 1198 snps,priority = <0x2>; 1199 }; 1200 queue3 { 1201 snps,weight = <0x13>; 1202 snps,dcb-algorithm; 1203 snps,priority = <0x3>; 1204 }; 1205 }; 1206 }; 1207 1208 xhci0: usb@11200000 { 1209 compatible = "mediatek,mt8195-xhci", 1210 "mediatek,mtk-xhci"; 1211 reg = <0 0x11200000 0 0x1000>, 1212 <0 0x11203e00 0 0x0100>; 1213 reg-names = "mac", "ippc"; 1214 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1215 phys = <&u2port0 PHY_TYPE_USB2>, 1216 <&u3port0 PHY_TYPE_USB3>; 1217 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1218 <&topckgen CLK_TOP_SSUSB_XHCI>; 1219 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1220 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1221 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1222 <&topckgen CLK_TOP_SSUSB_REF>, 1223 <&apmixedsys CLK_APMIXED_USB1PLL>, 1224 <&clk26m>, 1225 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1226 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1227 "xhci_ck"; 1228 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1229 wakeup-source; 1230 status = "disabled"; 1231 }; 1232 1233 mmc0: mmc@11230000 { 1234 compatible = "mediatek,mt8195-mmc", 1235 "mediatek,mt8183-mmc"; 1236 reg = <0 0x11230000 0 0x10000>, 1237 <0 0x11f50000 0 0x1000>; 1238 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1239 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1240 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1241 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1242 clock-names = "source", "hclk", "source_cg"; 1243 status = "disabled"; 1244 }; 1245 1246 mmc1: mmc@11240000 { 1247 compatible = "mediatek,mt8195-mmc", 1248 "mediatek,mt8183-mmc"; 1249 reg = <0 0x11240000 0 0x1000>, 1250 <0 0x11c70000 0 0x1000>; 1251 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1252 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1253 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1254 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1255 clock-names = "source", "hclk", "source_cg"; 1256 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1257 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1258 status = "disabled"; 1259 }; 1260 1261 mmc2: mmc@11250000 { 1262 compatible = "mediatek,mt8195-mmc", 1263 "mediatek,mt8183-mmc"; 1264 reg = <0 0x11250000 0 0x1000>, 1265 <0 0x11e60000 0 0x1000>; 1266 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1267 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1268 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1269 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1270 clock-names = "source", "hclk", "source_cg"; 1271 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1272 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1273 status = "disabled"; 1274 }; 1275 1276 xhci1: usb@11290000 { 1277 compatible = "mediatek,mt8195-xhci", 1278 "mediatek,mtk-xhci"; 1279 reg = <0 0x11290000 0 0x1000>, 1280 <0 0x11293e00 0 0x0100>; 1281 reg-names = "mac", "ippc"; 1282 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1283 phys = <&u2port1 PHY_TYPE_USB2>; 1284 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1285 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1286 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1287 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1288 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1289 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1290 <&apmixedsys CLK_APMIXED_USB1PLL>, 1291 <&clk26m>, 1292 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1293 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1294 "xhci_ck"; 1295 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1296 wakeup-source; 1297 status = "disabled"; 1298 }; 1299 1300 xhci2: usb@112a0000 { 1301 compatible = "mediatek,mt8195-xhci", 1302 "mediatek,mtk-xhci"; 1303 reg = <0 0x112a0000 0 0x1000>, 1304 <0 0x112a3e00 0 0x0100>; 1305 reg-names = "mac", "ippc"; 1306 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1307 phys = <&u2port2 PHY_TYPE_USB2>; 1308 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 1309 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1310 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1311 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1312 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1313 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1314 <&clk26m>, 1315 <&clk26m>, 1316 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1317 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1318 "xhci_ck"; 1319 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1320 wakeup-source; 1321 status = "disabled"; 1322 }; 1323 1324 xhci3: usb@112b0000 { 1325 compatible = "mediatek,mt8195-xhci", 1326 "mediatek,mtk-xhci"; 1327 reg = <0 0x112b0000 0 0x1000>, 1328 <0 0x112b3e00 0 0x0100>; 1329 reg-names = "mac", "ippc"; 1330 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1331 phys = <&u2port3 PHY_TYPE_USB2>; 1332 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 1333 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1334 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1335 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1336 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1337 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1338 <&clk26m>, 1339 <&clk26m>, 1340 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1341 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1342 "xhci_ck"; 1343 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1344 wakeup-source; 1345 status = "disabled"; 1346 }; 1347 1348 pcie0: pcie@112f0000 { 1349 compatible = "mediatek,mt8195-pcie", 1350 "mediatek,mt8192-pcie"; 1351 device_type = "pci"; 1352 #address-cells = <3>; 1353 #size-cells = <2>; 1354 reg = <0 0x112f0000 0 0x4000>; 1355 reg-names = "pcie-mac"; 1356 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1357 bus-range = <0x00 0xff>; 1358 ranges = <0x81000000 0 0x20000000 1359 0x0 0x20000000 0 0x200000>, 1360 <0x82000000 0 0x20200000 1361 0x0 0x20200000 0 0x3e00000>; 1362 1363 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; 1364 iommu-map-mask = <0x0>; 1365 1366 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1367 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1368 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1369 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1370 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1371 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1372 clock-names = "pl_250m", "tl_26m", "tl_96m", 1373 "tl_32k", "peri_26m", "peri_mem"; 1374 assigned-clocks = <&topckgen CLK_TOP_TL>; 1375 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1376 1377 phys = <&pciephy>; 1378 phy-names = "pcie-phy"; 1379 1380 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 1381 1382 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; 1383 reset-names = "mac"; 1384 1385 #interrupt-cells = <1>; 1386 interrupt-map-mask = <0 0 0 7>; 1387 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1388 <0 0 0 2 &pcie_intc0 1>, 1389 <0 0 0 3 &pcie_intc0 2>, 1390 <0 0 0 4 &pcie_intc0 3>; 1391 status = "disabled"; 1392 1393 pcie_intc0: interrupt-controller { 1394 interrupt-controller; 1395 #address-cells = <0>; 1396 #interrupt-cells = <1>; 1397 }; 1398 }; 1399 1400 pcie1: pcie@112f8000 { 1401 compatible = "mediatek,mt8195-pcie", 1402 "mediatek,mt8192-pcie"; 1403 device_type = "pci"; 1404 #address-cells = <3>; 1405 #size-cells = <2>; 1406 reg = <0 0x112f8000 0 0x4000>; 1407 reg-names = "pcie-mac"; 1408 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; 1409 bus-range = <0x00 0xff>; 1410 ranges = <0x81000000 0 0x24000000 1411 0x0 0x24000000 0 0x200000>, 1412 <0x82000000 0 0x24200000 1413 0x0 0x24200000 0 0x3e00000>; 1414 1415 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1416 iommu-map-mask = <0x0>; 1417 1418 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1419 <&clk26m>, 1420 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, 1421 <&clk26m>, 1422 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, 1423 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1424 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1425 clock-names = "pl_250m", "tl_26m", "tl_96m", 1426 "tl_32k", "peri_26m", "peri_mem"; 1427 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1428 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1429 1430 phys = <&u3port1 PHY_TYPE_PCIE>; 1431 phy-names = "pcie-phy"; 1432 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 1433 1434 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; 1435 reset-names = "mac"; 1436 1437 #interrupt-cells = <1>; 1438 interrupt-map-mask = <0 0 0 7>; 1439 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 1440 <0 0 0 2 &pcie_intc1 1>, 1441 <0 0 0 3 &pcie_intc1 2>, 1442 <0 0 0 4 &pcie_intc1 3>; 1443 status = "disabled"; 1444 1445 pcie_intc1: interrupt-controller { 1446 interrupt-controller; 1447 #address-cells = <0>; 1448 #interrupt-cells = <1>; 1449 }; 1450 }; 1451 1452 nor_flash: spi@1132c000 { 1453 compatible = "mediatek,mt8195-nor", 1454 "mediatek,mt8173-nor"; 1455 reg = <0 0x1132c000 0 0x1000>; 1456 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1457 clocks = <&topckgen CLK_TOP_SPINOR>, 1458 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1459 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1460 clock-names = "spi", "sf", "axi"; 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 status = "disabled"; 1464 }; 1465 1466 efuse: efuse@11c10000 { 1467 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1468 reg = <0 0x11c10000 0 0x1000>; 1469 #address-cells = <1>; 1470 #size-cells = <1>; 1471 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1472 reg = <0x184 0x1>; 1473 bits = <0 5>; 1474 }; 1475 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1476 reg = <0x184 0x2>; 1477 bits = <5 5>; 1478 }; 1479 u3_intr_p0: usb3-intr@185 { 1480 reg = <0x185 0x1>; 1481 bits = <2 6>; 1482 }; 1483 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1484 reg = <0x186 0x1>; 1485 bits = <0 5>; 1486 }; 1487 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1488 reg = <0x186 0x2>; 1489 bits = <5 5>; 1490 }; 1491 comb_intr_p1: usb3-intr@187 { 1492 reg = <0x187 0x1>; 1493 bits = <2 6>; 1494 }; 1495 u2_intr_p0: usb2-intr-p0@188,1 { 1496 reg = <0x188 0x1>; 1497 bits = <0 5>; 1498 }; 1499 u2_intr_p1: usb2-intr-p1@188,2 { 1500 reg = <0x188 0x2>; 1501 bits = <5 5>; 1502 }; 1503 u2_intr_p2: usb2-intr-p2@189,1 { 1504 reg = <0x189 0x1>; 1505 bits = <2 5>; 1506 }; 1507 u2_intr_p3: usb2-intr-p3@189,2 { 1508 reg = <0x189 0x2>; 1509 bits = <7 5>; 1510 }; 1511 pciephy_rx_ln1: pciephy-rx-ln1@190,1 { 1512 reg = <0x190 0x1>; 1513 bits = <0 4>; 1514 }; 1515 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { 1516 reg = <0x190 0x1>; 1517 bits = <4 4>; 1518 }; 1519 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { 1520 reg = <0x191 0x1>; 1521 bits = <0 4>; 1522 }; 1523 pciephy_rx_ln0: pciephy-rx-ln0@191,2 { 1524 reg = <0x191 0x1>; 1525 bits = <4 4>; 1526 }; 1527 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { 1528 reg = <0x192 0x1>; 1529 bits = <0 4>; 1530 }; 1531 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { 1532 reg = <0x192 0x1>; 1533 bits = <4 4>; 1534 }; 1535 pciephy_glb_intr: pciephy-glb-intr@193 { 1536 reg = <0x193 0x1>; 1537 bits = <0 4>; 1538 }; 1539 dp_calibration: dp-data@1ac { 1540 reg = <0x1ac 0x10>; 1541 }; 1542 lvts_efuse_data1: lvts1-calib@1bc { 1543 reg = <0x1bc 0x14>; 1544 }; 1545 lvts_efuse_data2: lvts2-calib@1d0 { 1546 reg = <0x1d0 0x38>; 1547 }; 1548 }; 1549 1550 u3phy2: t-phy@11c40000 { 1551 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1552 #address-cells = <1>; 1553 #size-cells = <1>; 1554 ranges = <0 0 0x11c40000 0x700>; 1555 status = "disabled"; 1556 1557 u2port2: usb-phy@0 { 1558 reg = <0x0 0x700>; 1559 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1560 clock-names = "ref"; 1561 #phy-cells = <1>; 1562 }; 1563 }; 1564 1565 u3phy3: t-phy@11c50000 { 1566 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1567 #address-cells = <1>; 1568 #size-cells = <1>; 1569 ranges = <0 0 0x11c50000 0x700>; 1570 status = "disabled"; 1571 1572 u2port3: usb-phy@0 { 1573 reg = <0x0 0x700>; 1574 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1575 clock-names = "ref"; 1576 #phy-cells = <1>; 1577 }; 1578 }; 1579 1580 i2c5: i2c@11d00000 { 1581 compatible = "mediatek,mt8195-i2c", 1582 "mediatek,mt8192-i2c"; 1583 reg = <0 0x11d00000 0 0x1000>, 1584 <0 0x10220580 0 0x80>; 1585 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1586 clock-div = <1>; 1587 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1588 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1589 clock-names = "main", "dma"; 1590 #address-cells = <1>; 1591 #size-cells = <0>; 1592 status = "disabled"; 1593 }; 1594 1595 i2c6: i2c@11d01000 { 1596 compatible = "mediatek,mt8195-i2c", 1597 "mediatek,mt8192-i2c"; 1598 reg = <0 0x11d01000 0 0x1000>, 1599 <0 0x10220600 0 0x80>; 1600 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1601 clock-div = <1>; 1602 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1603 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1604 clock-names = "main", "dma"; 1605 #address-cells = <1>; 1606 #size-cells = <0>; 1607 status = "disabled"; 1608 }; 1609 1610 i2c7: i2c@11d02000 { 1611 compatible = "mediatek,mt8195-i2c", 1612 "mediatek,mt8192-i2c"; 1613 reg = <0 0x11d02000 0 0x1000>, 1614 <0 0x10220680 0 0x80>; 1615 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1616 clock-div = <1>; 1617 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1618 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1619 clock-names = "main", "dma"; 1620 #address-cells = <1>; 1621 #size-cells = <0>; 1622 status = "disabled"; 1623 }; 1624 1625 imp_iic_wrap_s: clock-controller@11d03000 { 1626 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1627 reg = <0 0x11d03000 0 0x1000>; 1628 #clock-cells = <1>; 1629 }; 1630 1631 i2c0: i2c@11e00000 { 1632 compatible = "mediatek,mt8195-i2c", 1633 "mediatek,mt8192-i2c"; 1634 reg = <0 0x11e00000 0 0x1000>, 1635 <0 0x10220080 0 0x80>; 1636 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1637 clock-div = <1>; 1638 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1639 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1640 clock-names = "main", "dma"; 1641 #address-cells = <1>; 1642 #size-cells = <0>; 1643 status = "disabled"; 1644 }; 1645 1646 i2c1: i2c@11e01000 { 1647 compatible = "mediatek,mt8195-i2c", 1648 "mediatek,mt8192-i2c"; 1649 reg = <0 0x11e01000 0 0x1000>, 1650 <0 0x10220200 0 0x80>; 1651 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1652 clock-div = <1>; 1653 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1654 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1655 clock-names = "main", "dma"; 1656 #address-cells = <1>; 1657 #size-cells = <0>; 1658 status = "disabled"; 1659 }; 1660 1661 i2c2: i2c@11e02000 { 1662 compatible = "mediatek,mt8195-i2c", 1663 "mediatek,mt8192-i2c"; 1664 reg = <0 0x11e02000 0 0x1000>, 1665 <0 0x10220380 0 0x80>; 1666 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1667 clock-div = <1>; 1668 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1669 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1670 clock-names = "main", "dma"; 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 status = "disabled"; 1674 }; 1675 1676 i2c3: i2c@11e03000 { 1677 compatible = "mediatek,mt8195-i2c", 1678 "mediatek,mt8192-i2c"; 1679 reg = <0 0x11e03000 0 0x1000>, 1680 <0 0x10220480 0 0x80>; 1681 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1682 clock-div = <1>; 1683 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1684 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1685 clock-names = "main", "dma"; 1686 #address-cells = <1>; 1687 #size-cells = <0>; 1688 status = "disabled"; 1689 }; 1690 1691 i2c4: i2c@11e04000 { 1692 compatible = "mediatek,mt8195-i2c", 1693 "mediatek,mt8192-i2c"; 1694 reg = <0 0x11e04000 0 0x1000>, 1695 <0 0x10220500 0 0x80>; 1696 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1697 clock-div = <1>; 1698 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1699 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1700 clock-names = "main", "dma"; 1701 #address-cells = <1>; 1702 #size-cells = <0>; 1703 status = "disabled"; 1704 }; 1705 1706 imp_iic_wrap_w: clock-controller@11e05000 { 1707 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1708 reg = <0 0x11e05000 0 0x1000>; 1709 #clock-cells = <1>; 1710 }; 1711 1712 u3phy1: t-phy@11e30000 { 1713 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1714 #address-cells = <1>; 1715 #size-cells = <1>; 1716 ranges = <0 0 0x11e30000 0xe00>; 1717 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 1718 status = "disabled"; 1719 1720 u2port1: usb-phy@0 { 1721 reg = <0x0 0x700>; 1722 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1723 <&clk26m>; 1724 clock-names = "ref", "da_ref"; 1725 #phy-cells = <1>; 1726 }; 1727 1728 u3port1: usb-phy@700 { 1729 reg = <0x700 0x700>; 1730 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1731 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1732 clock-names = "ref", "da_ref"; 1733 nvmem-cells = <&comb_intr_p1>, 1734 <&comb_rx_imp_p1>, 1735 <&comb_tx_imp_p1>; 1736 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1737 #phy-cells = <1>; 1738 }; 1739 }; 1740 1741 u3phy0: t-phy@11e40000 { 1742 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1743 #address-cells = <1>; 1744 #size-cells = <1>; 1745 ranges = <0 0 0x11e40000 0xe00>; 1746 status = "disabled"; 1747 1748 u2port0: usb-phy@0 { 1749 reg = <0x0 0x700>; 1750 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1751 <&clk26m>; 1752 clock-names = "ref", "da_ref"; 1753 #phy-cells = <1>; 1754 }; 1755 1756 u3port0: usb-phy@700 { 1757 reg = <0x700 0x700>; 1758 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1759 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1760 clock-names = "ref", "da_ref"; 1761 nvmem-cells = <&u3_intr_p0>, 1762 <&u3_rx_imp_p0>, 1763 <&u3_tx_imp_p0>; 1764 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1765 #phy-cells = <1>; 1766 }; 1767 }; 1768 1769 pciephy: phy@11e80000 { 1770 compatible = "mediatek,mt8195-pcie-phy"; 1771 reg = <0 0x11e80000 0 0x10000>; 1772 reg-names = "sif"; 1773 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, 1774 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, 1775 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, 1776 <&pciephy_rx_ln1>; 1777 nvmem-cell-names = "glb_intr", "tx_ln0_pmos", 1778 "tx_ln0_nmos", "rx_ln0", 1779 "tx_ln1_pmos", "tx_ln1_nmos", 1780 "rx_ln1"; 1781 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; 1782 #phy-cells = <0>; 1783 status = "disabled"; 1784 }; 1785 1786 ufsphy: ufs-phy@11fa0000 { 1787 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 1788 reg = <0 0x11fa0000 0 0xc000>; 1789 clocks = <&clk26m>, <&clk26m>; 1790 clock-names = "unipro", "mp"; 1791 #phy-cells = <0>; 1792 status = "disabled"; 1793 }; 1794 1795 mfgcfg: clock-controller@13fbf000 { 1796 compatible = "mediatek,mt8195-mfgcfg"; 1797 reg = <0 0x13fbf000 0 0x1000>; 1798 #clock-cells = <1>; 1799 }; 1800 1801 vppsys0: clock-controller@14000000 { 1802 compatible = "mediatek,mt8195-vppsys0"; 1803 reg = <0 0x14000000 0 0x1000>; 1804 #clock-cells = <1>; 1805 }; 1806 1807 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 1808 compatible = "mediatek,mt8195-smi-sub-common"; 1809 reg = <0 0x14010000 0 0x1000>; 1810 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1811 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1812 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1813 clock-names = "apb", "smi", "gals0"; 1814 mediatek,smi = <&smi_common_vpp>; 1815 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1816 }; 1817 1818 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 1819 compatible = "mediatek,mt8195-smi-sub-common"; 1820 reg = <0 0x14011000 0 0x1000>; 1821 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1822 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1823 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 1824 clock-names = "apb", "smi", "gals0"; 1825 mediatek,smi = <&smi_common_vpp>; 1826 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1827 }; 1828 1829 smi_common_vpp: smi@14012000 { 1830 compatible = "mediatek,mt8195-smi-common-vpp"; 1831 reg = <0 0x14012000 0 0x1000>; 1832 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1833 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1834 <&vppsys0 CLK_VPP0_SMI_RSI>, 1835 <&vppsys0 CLK_VPP0_SMI_RSI>; 1836 clock-names = "apb", "smi", "gals0", "gals1"; 1837 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1838 }; 1839 1840 larb4: larb@14013000 { 1841 compatible = "mediatek,mt8195-smi-larb"; 1842 reg = <0 0x14013000 0 0x1000>; 1843 mediatek,larb-id = <4>; 1844 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 1845 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 1846 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 1847 clock-names = "apb", "smi"; 1848 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1849 }; 1850 1851 iommu_vpp: iommu@14018000 { 1852 compatible = "mediatek,mt8195-iommu-vpp"; 1853 reg = <0 0x14018000 0 0x1000>; 1854 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 1855 &larb12 &larb14 &larb16 &larb18 1856 &larb20 &larb22 &larb23 &larb26 1857 &larb27>; 1858 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 1859 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 1860 clock-names = "bclk"; 1861 #iommu-cells = <1>; 1862 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 1863 }; 1864 1865 wpesys: clock-controller@14e00000 { 1866 compatible = "mediatek,mt8195-wpesys"; 1867 reg = <0 0x14e00000 0 0x1000>; 1868 #clock-cells = <1>; 1869 }; 1870 1871 wpesys_vpp0: clock-controller@14e02000 { 1872 compatible = "mediatek,mt8195-wpesys_vpp0"; 1873 reg = <0 0x14e02000 0 0x1000>; 1874 #clock-cells = <1>; 1875 }; 1876 1877 wpesys_vpp1: clock-controller@14e03000 { 1878 compatible = "mediatek,mt8195-wpesys_vpp1"; 1879 reg = <0 0x14e03000 0 0x1000>; 1880 #clock-cells = <1>; 1881 }; 1882 1883 larb7: larb@14e04000 { 1884 compatible = "mediatek,mt8195-smi-larb"; 1885 reg = <0 0x14e04000 0 0x1000>; 1886 mediatek,larb-id = <7>; 1887 mediatek,smi = <&smi_common_vdo>; 1888 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 1889 <&wpesys CLK_WPE_SMI_LARB7>; 1890 clock-names = "apb", "smi"; 1891 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 1892 }; 1893 1894 larb8: larb@14e05000 { 1895 compatible = "mediatek,mt8195-smi-larb"; 1896 reg = <0 0x14e05000 0 0x1000>; 1897 mediatek,larb-id = <8>; 1898 mediatek,smi = <&smi_common_vpp>; 1899 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 1900 <&wpesys CLK_WPE_SMI_LARB8>, 1901 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 1902 clock-names = "apb", "smi", "gals"; 1903 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 1904 }; 1905 1906 vppsys1: clock-controller@14f00000 { 1907 compatible = "mediatek,mt8195-vppsys1"; 1908 reg = <0 0x14f00000 0 0x1000>; 1909 #clock-cells = <1>; 1910 }; 1911 1912 larb5: larb@14f02000 { 1913 compatible = "mediatek,mt8195-smi-larb"; 1914 reg = <0 0x14f02000 0 0x1000>; 1915 mediatek,larb-id = <5>; 1916 mediatek,smi = <&smi_common_vdo>; 1917 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 1918 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 1919 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 1920 clock-names = "apb", "smi", "gals"; 1921 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 1922 }; 1923 1924 larb6: larb@14f03000 { 1925 compatible = "mediatek,mt8195-smi-larb"; 1926 reg = <0 0x14f03000 0 0x1000>; 1927 mediatek,larb-id = <6>; 1928 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 1929 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 1930 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 1931 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 1932 clock-names = "apb", "smi", "gals"; 1933 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 1934 }; 1935 1936 imgsys: clock-controller@15000000 { 1937 compatible = "mediatek,mt8195-imgsys"; 1938 reg = <0 0x15000000 0 0x1000>; 1939 #clock-cells = <1>; 1940 }; 1941 1942 larb9: larb@15001000 { 1943 compatible = "mediatek,mt8195-smi-larb"; 1944 reg = <0 0x15001000 0 0x1000>; 1945 mediatek,larb-id = <9>; 1946 mediatek,smi = <&smi_sub_common_img1_3x1>; 1947 clocks = <&imgsys CLK_IMG_LARB9>, 1948 <&imgsys CLK_IMG_LARB9>, 1949 <&imgsys CLK_IMG_GALS>; 1950 clock-names = "apb", "smi", "gals"; 1951 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1952 }; 1953 1954 smi_sub_common_img0_3x1: smi@15002000 { 1955 compatible = "mediatek,mt8195-smi-sub-common"; 1956 reg = <0 0x15002000 0 0x1000>; 1957 clocks = <&imgsys CLK_IMG_IPE>, 1958 <&imgsys CLK_IMG_IPE>, 1959 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 1960 clock-names = "apb", "smi", "gals0"; 1961 mediatek,smi = <&smi_common_vpp>; 1962 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1963 }; 1964 1965 smi_sub_common_img1_3x1: smi@15003000 { 1966 compatible = "mediatek,mt8195-smi-sub-common"; 1967 reg = <0 0x15003000 0 0x1000>; 1968 clocks = <&imgsys CLK_IMG_LARB9>, 1969 <&imgsys CLK_IMG_LARB9>, 1970 <&imgsys CLK_IMG_GALS>; 1971 clock-names = "apb", "smi", "gals0"; 1972 mediatek,smi = <&smi_common_vdo>; 1973 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 1974 }; 1975 1976 imgsys1_dip_top: clock-controller@15110000 { 1977 compatible = "mediatek,mt8195-imgsys1_dip_top"; 1978 reg = <0 0x15110000 0 0x1000>; 1979 #clock-cells = <1>; 1980 }; 1981 1982 larb10: larb@15120000 { 1983 compatible = "mediatek,mt8195-smi-larb"; 1984 reg = <0 0x15120000 0 0x1000>; 1985 mediatek,larb-id = <10>; 1986 mediatek,smi = <&smi_sub_common_img1_3x1>; 1987 clocks = <&imgsys CLK_IMG_DIP0>, 1988 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 1989 clock-names = "apb", "smi"; 1990 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 1991 }; 1992 1993 imgsys1_dip_nr: clock-controller@15130000 { 1994 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 1995 reg = <0 0x15130000 0 0x1000>; 1996 #clock-cells = <1>; 1997 }; 1998 1999 imgsys1_wpe: clock-controller@15220000 { 2000 compatible = "mediatek,mt8195-imgsys1_wpe"; 2001 reg = <0 0x15220000 0 0x1000>; 2002 #clock-cells = <1>; 2003 }; 2004 2005 larb11: larb@15230000 { 2006 compatible = "mediatek,mt8195-smi-larb"; 2007 reg = <0 0x15230000 0 0x1000>; 2008 mediatek,larb-id = <11>; 2009 mediatek,smi = <&smi_sub_common_img1_3x1>; 2010 clocks = <&imgsys CLK_IMG_WPE0>, 2011 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 2012 clock-names = "apb", "smi"; 2013 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2014 }; 2015 2016 ipesys: clock-controller@15330000 { 2017 compatible = "mediatek,mt8195-ipesys"; 2018 reg = <0 0x15330000 0 0x1000>; 2019 #clock-cells = <1>; 2020 }; 2021 2022 larb12: larb@15340000 { 2023 compatible = "mediatek,mt8195-smi-larb"; 2024 reg = <0 0x15340000 0 0x1000>; 2025 mediatek,larb-id = <12>; 2026 mediatek,smi = <&smi_sub_common_img0_3x1>; 2027 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 2028 <&ipesys CLK_IPE_SMI_LARB12>; 2029 clock-names = "apb", "smi"; 2030 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 2031 }; 2032 2033 camsys: clock-controller@16000000 { 2034 compatible = "mediatek,mt8195-camsys"; 2035 reg = <0 0x16000000 0 0x1000>; 2036 #clock-cells = <1>; 2037 }; 2038 2039 larb13: larb@16001000 { 2040 compatible = "mediatek,mt8195-smi-larb"; 2041 reg = <0 0x16001000 0 0x1000>; 2042 mediatek,larb-id = <13>; 2043 mediatek,smi = <&smi_sub_common_cam_4x1>; 2044 clocks = <&camsys CLK_CAM_LARB13>, 2045 <&camsys CLK_CAM_LARB13>, 2046 <&camsys CLK_CAM_CAM2MM0_GALS>; 2047 clock-names = "apb", "smi", "gals"; 2048 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2049 }; 2050 2051 larb14: larb@16002000 { 2052 compatible = "mediatek,mt8195-smi-larb"; 2053 reg = <0 0x16002000 0 0x1000>; 2054 mediatek,larb-id = <14>; 2055 mediatek,smi = <&smi_sub_common_cam_7x1>; 2056 clocks = <&camsys CLK_CAM_LARB14>, 2057 <&camsys CLK_CAM_LARB14>; 2058 clock-names = "apb", "smi"; 2059 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2060 }; 2061 2062 smi_sub_common_cam_4x1: smi@16004000 { 2063 compatible = "mediatek,mt8195-smi-sub-common"; 2064 reg = <0 0x16004000 0 0x1000>; 2065 clocks = <&camsys CLK_CAM_LARB13>, 2066 <&camsys CLK_CAM_LARB13>, 2067 <&camsys CLK_CAM_CAM2MM0_GALS>; 2068 clock-names = "apb", "smi", "gals0"; 2069 mediatek,smi = <&smi_common_vdo>; 2070 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2071 }; 2072 2073 smi_sub_common_cam_7x1: smi@16005000 { 2074 compatible = "mediatek,mt8195-smi-sub-common"; 2075 reg = <0 0x16005000 0 0x1000>; 2076 clocks = <&camsys CLK_CAM_LARB14>, 2077 <&camsys CLK_CAM_CAM2MM1_GALS>, 2078 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2079 clock-names = "apb", "smi", "gals0"; 2080 mediatek,smi = <&smi_common_vpp>; 2081 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2082 }; 2083 2084 larb16: larb@16012000 { 2085 compatible = "mediatek,mt8195-smi-larb"; 2086 reg = <0 0x16012000 0 0x1000>; 2087 mediatek,larb-id = <16>; 2088 mediatek,smi = <&smi_sub_common_cam_7x1>; 2089 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 2090 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 2091 clock-names = "apb", "smi"; 2092 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2093 }; 2094 2095 larb17: larb@16013000 { 2096 compatible = "mediatek,mt8195-smi-larb"; 2097 reg = <0 0x16013000 0 0x1000>; 2098 mediatek,larb-id = <17>; 2099 mediatek,smi = <&smi_sub_common_cam_4x1>; 2100 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 2101 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 2102 clock-names = "apb", "smi"; 2103 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2104 }; 2105 2106 larb27: larb@16014000 { 2107 compatible = "mediatek,mt8195-smi-larb"; 2108 reg = <0 0x16014000 0 0x1000>; 2109 mediatek,larb-id = <27>; 2110 mediatek,smi = <&smi_sub_common_cam_7x1>; 2111 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 2112 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 2113 clock-names = "apb", "smi"; 2114 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2115 }; 2116 2117 larb28: larb@16015000 { 2118 compatible = "mediatek,mt8195-smi-larb"; 2119 reg = <0 0x16015000 0 0x1000>; 2120 mediatek,larb-id = <28>; 2121 mediatek,smi = <&smi_sub_common_cam_4x1>; 2122 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 2123 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 2124 clock-names = "apb", "smi"; 2125 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2126 }; 2127 2128 camsys_rawa: clock-controller@1604f000 { 2129 compatible = "mediatek,mt8195-camsys_rawa"; 2130 reg = <0 0x1604f000 0 0x1000>; 2131 #clock-cells = <1>; 2132 }; 2133 2134 camsys_yuva: clock-controller@1606f000 { 2135 compatible = "mediatek,mt8195-camsys_yuva"; 2136 reg = <0 0x1606f000 0 0x1000>; 2137 #clock-cells = <1>; 2138 }; 2139 2140 camsys_rawb: clock-controller@1608f000 { 2141 compatible = "mediatek,mt8195-camsys_rawb"; 2142 reg = <0 0x1608f000 0 0x1000>; 2143 #clock-cells = <1>; 2144 }; 2145 2146 camsys_yuvb: clock-controller@160af000 { 2147 compatible = "mediatek,mt8195-camsys_yuvb"; 2148 reg = <0 0x160af000 0 0x1000>; 2149 #clock-cells = <1>; 2150 }; 2151 2152 camsys_mraw: clock-controller@16140000 { 2153 compatible = "mediatek,mt8195-camsys_mraw"; 2154 reg = <0 0x16140000 0 0x1000>; 2155 #clock-cells = <1>; 2156 }; 2157 2158 larb25: larb@16141000 { 2159 compatible = "mediatek,mt8195-smi-larb"; 2160 reg = <0 0x16141000 0 0x1000>; 2161 mediatek,larb-id = <25>; 2162 mediatek,smi = <&smi_sub_common_cam_4x1>; 2163 clocks = <&camsys CLK_CAM_LARB13>, 2164 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2165 <&camsys CLK_CAM_CAM2MM0_GALS>; 2166 clock-names = "apb", "smi", "gals"; 2167 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2168 }; 2169 2170 larb26: larb@16142000 { 2171 compatible = "mediatek,mt8195-smi-larb"; 2172 reg = <0 0x16142000 0 0x1000>; 2173 mediatek,larb-id = <26>; 2174 mediatek,smi = <&smi_sub_common_cam_7x1>; 2175 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2176 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 2177 clock-names = "apb", "smi"; 2178 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2179 2180 }; 2181 2182 ccusys: clock-controller@17200000 { 2183 compatible = "mediatek,mt8195-ccusys"; 2184 reg = <0 0x17200000 0 0x1000>; 2185 #clock-cells = <1>; 2186 }; 2187 2188 larb18: larb@17201000 { 2189 compatible = "mediatek,mt8195-smi-larb"; 2190 reg = <0 0x17201000 0 0x1000>; 2191 mediatek,larb-id = <18>; 2192 mediatek,smi = <&smi_sub_common_cam_7x1>; 2193 clocks = <&ccusys CLK_CCU_LARB18>, 2194 <&ccusys CLK_CCU_LARB18>; 2195 clock-names = "apb", "smi"; 2196 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2197 }; 2198 2199 larb24: larb@1800d000 { 2200 compatible = "mediatek,mt8195-smi-larb"; 2201 reg = <0 0x1800d000 0 0x1000>; 2202 mediatek,larb-id = <24>; 2203 mediatek,smi = <&smi_common_vdo>; 2204 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 2205 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2206 clock-names = "apb", "smi"; 2207 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2208 }; 2209 2210 larb23: larb@1800e000 { 2211 compatible = "mediatek,mt8195-smi-larb"; 2212 reg = <0 0x1800e000 0 0x1000>; 2213 mediatek,larb-id = <23>; 2214 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2215 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2216 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2217 clock-names = "apb", "smi"; 2218 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2219 }; 2220 2221 vdecsys_soc: clock-controller@1800f000 { 2222 compatible = "mediatek,mt8195-vdecsys_soc"; 2223 reg = <0 0x1800f000 0 0x1000>; 2224 #clock-cells = <1>; 2225 }; 2226 2227 larb21: larb@1802e000 { 2228 compatible = "mediatek,mt8195-smi-larb"; 2229 reg = <0 0x1802e000 0 0x1000>; 2230 mediatek,larb-id = <21>; 2231 mediatek,smi = <&smi_common_vdo>; 2232 clocks = <&vdecsys CLK_VDEC_LARB1>, 2233 <&vdecsys CLK_VDEC_LARB1>; 2234 clock-names = "apb", "smi"; 2235 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2236 }; 2237 2238 vdecsys: clock-controller@1802f000 { 2239 compatible = "mediatek,mt8195-vdecsys"; 2240 reg = <0 0x1802f000 0 0x1000>; 2241 #clock-cells = <1>; 2242 }; 2243 2244 larb22: larb@1803e000 { 2245 compatible = "mediatek,mt8195-smi-larb"; 2246 reg = <0 0x1803e000 0 0x1000>; 2247 mediatek,larb-id = <22>; 2248 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2249 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2250 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 2251 clock-names = "apb", "smi"; 2252 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2253 }; 2254 2255 vdecsys_core1: clock-controller@1803f000 { 2256 compatible = "mediatek,mt8195-vdecsys_core1"; 2257 reg = <0 0x1803f000 0 0x1000>; 2258 #clock-cells = <1>; 2259 }; 2260 2261 apusys_pll: clock-controller@190f3000 { 2262 compatible = "mediatek,mt8195-apusys_pll"; 2263 reg = <0 0x190f3000 0 0x1000>; 2264 #clock-cells = <1>; 2265 }; 2266 2267 vencsys: clock-controller@1a000000 { 2268 compatible = "mediatek,mt8195-vencsys"; 2269 reg = <0 0x1a000000 0 0x1000>; 2270 #clock-cells = <1>; 2271 }; 2272 2273 larb19: larb@1a010000 { 2274 compatible = "mediatek,mt8195-smi-larb"; 2275 reg = <0 0x1a010000 0 0x1000>; 2276 mediatek,larb-id = <19>; 2277 mediatek,smi = <&smi_common_vdo>; 2278 clocks = <&vencsys CLK_VENC_VENC>, 2279 <&vencsys CLK_VENC_GALS>; 2280 clock-names = "apb", "smi"; 2281 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2282 }; 2283 2284 venc: video-codec@1a020000 { 2285 compatible = "mediatek,mt8195-vcodec-enc"; 2286 reg = <0 0x1a020000 0 0x10000>; 2287 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 2288 <&iommu_vdo M4U_PORT_L19_VENC_REC>, 2289 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 2290 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 2291 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 2292 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 2293 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 2294 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 2295 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 2296 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 2297 mediatek,scp = <&scp>; 2298 clocks = <&vencsys CLK_VENC_VENC>; 2299 clock-names = "venc_sel"; 2300 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2301 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2302 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2303 #address-cells = <2>; 2304 #size-cells = <2>; 2305 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 2306 }; 2307 2308 jpgdec-master { 2309 compatible = "mediatek,mt8195-jpgdec"; 2310 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2311 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2312 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2313 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2314 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2315 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2316 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2317 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 2318 #address-cells = <2>; 2319 #size-cells = <2>; 2320 ranges; 2321 2322 jpgdec@1a040000 { 2323 compatible = "mediatek,mt8195-jpgdec-hw"; 2324 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ 2325 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2326 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2327 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2328 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2329 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2330 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2331 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; 2332 clocks = <&vencsys CLK_VENC_JPGDEC>; 2333 clock-names = "jpgdec"; 2334 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2335 }; 2336 2337 jpgdec@1a050000 { 2338 compatible = "mediatek,mt8195-jpgdec-hw"; 2339 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ 2340 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 2341 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 2342 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 2343 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 2344 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 2345 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 2346 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>; 2347 clocks = <&vencsys CLK_VENC_JPGDEC_C1>; 2348 clock-names = "jpgdec"; 2349 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2350 }; 2351 2352 jpgdec@1b040000 { 2353 compatible = "mediatek,mt8195-jpgdec-hw"; 2354 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ 2355 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, 2356 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, 2357 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, 2358 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, 2359 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, 2360 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; 2361 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>; 2362 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; 2363 clock-names = "jpgdec"; 2364 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2365 }; 2366 }; 2367 2368 vencsys_core1: clock-controller@1b000000 { 2369 compatible = "mediatek,mt8195-vencsys_core1"; 2370 reg = <0 0x1b000000 0 0x1000>; 2371 #clock-cells = <1>; 2372 }; 2373 2374 vdosys0: syscon@1c01a000 { 2375 compatible = "mediatek,mt8195-mmsys", "syscon"; 2376 reg = <0 0x1c01a000 0 0x1000>; 2377 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 2378 #clock-cells = <1>; 2379 }; 2380 2381 2382 jpgenc-master { 2383 compatible = "mediatek,mt8195-jpgenc"; 2384 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2385 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 2386 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 2387 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 2388 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 2389 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 2390 #address-cells = <2>; 2391 #size-cells = <2>; 2392 ranges; 2393 2394 jpgenc@1a030000 { 2395 compatible = "mediatek,mt8195-jpgenc-hw"; 2396 reg = <0 0x1a030000 0 0x10000>; 2397 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, 2398 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, 2399 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, 2400 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; 2401 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; 2402 clocks = <&vencsys CLK_VENC_JPGENC>; 2403 clock-names = "jpgenc"; 2404 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 2405 }; 2406 2407 jpgenc@1b030000 { 2408 compatible = "mediatek,mt8195-jpgenc-hw"; 2409 reg = <0 0x1b030000 0 0x10000>; 2410 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 2411 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 2412 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 2413 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 2414 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; 2415 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; 2416 clock-names = "jpgenc"; 2417 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2418 }; 2419 }; 2420 2421 larb20: larb@1b010000 { 2422 compatible = "mediatek,mt8195-smi-larb"; 2423 reg = <0 0x1b010000 0 0x1000>; 2424 mediatek,larb-id = <20>; 2425 mediatek,smi = <&smi_common_vpp>; 2426 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>, 2427 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 2428 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2429 clock-names = "apb", "smi", "gals"; 2430 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 2431 }; 2432 2433 ovl0: ovl@1c000000 { 2434 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl"; 2435 reg = <0 0x1c000000 0 0x1000>; 2436 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 2437 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2438 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 2439 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; 2440 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 2441 }; 2442 2443 rdma0: rdma@1c002000 { 2444 compatible = "mediatek,mt8195-disp-rdma"; 2445 reg = <0 0x1c002000 0 0x1000>; 2446 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 2447 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2448 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 2449 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; 2450 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 2451 }; 2452 2453 color0: color@1c003000 { 2454 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; 2455 reg = <0 0x1c003000 0 0x1000>; 2456 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 2457 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2458 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 2459 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 2460 }; 2461 2462 ccorr0: ccorr@1c004000 { 2463 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 2464 reg = <0 0x1c004000 0 0x1000>; 2465 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 2466 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2467 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 2468 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 2469 }; 2470 2471 aal0: aal@1c005000 { 2472 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; 2473 reg = <0 0x1c005000 0 0x1000>; 2474 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 2475 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2476 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 2477 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 2478 }; 2479 2480 gamma0: gamma@1c006000 { 2481 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; 2482 reg = <0 0x1c006000 0 0x1000>; 2483 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 2484 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2485 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 2486 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 2487 }; 2488 2489 dither0: dither@1c007000 { 2490 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; 2491 reg = <0 0x1c007000 0 0x1000>; 2492 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 2493 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2494 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 2495 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 2496 }; 2497 2498 dsc0: dsc@1c009000 { 2499 compatible = "mediatek,mt8195-disp-dsc"; 2500 reg = <0 0x1c009000 0 0x1000>; 2501 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 2502 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2503 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 2504 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 2505 }; 2506 2507 merge0: merge@1c014000 { 2508 compatible = "mediatek,mt8195-disp-merge"; 2509 reg = <0 0x1c014000 0 0x1000>; 2510 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 2511 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2512 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; 2513 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 2514 }; 2515 2516 dp_intf0: dp-intf@1c015000 { 2517 compatible = "mediatek,mt8195-dp-intf"; 2518 reg = <0 0x1c015000 0 0x1000>; 2519 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 2520 clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, 2521 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 2522 <&apmixedsys CLK_APMIXED_TVDPLL1>; 2523 clock-names = "engine", "pixel", "pll"; 2524 status = "disabled"; 2525 }; 2526 2527 mutex: mutex@1c016000 { 2528 compatible = "mediatek,mt8195-disp-mutex"; 2529 reg = <0 0x1c016000 0 0x1000>; 2530 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 2531 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2532 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 2533 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 2534 }; 2535 2536 larb0: larb@1c018000 { 2537 compatible = "mediatek,mt8195-smi-larb"; 2538 reg = <0 0x1c018000 0 0x1000>; 2539 mediatek,larb-id = <0>; 2540 mediatek,smi = <&smi_common_vdo>; 2541 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2542 <&vdosys0 CLK_VDO0_SMI_LARB>, 2543 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 2544 clock-names = "apb", "smi", "gals"; 2545 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2546 }; 2547 2548 larb1: larb@1c019000 { 2549 compatible = "mediatek,mt8195-smi-larb"; 2550 reg = <0 0x1c019000 0 0x1000>; 2551 mediatek,larb-id = <1>; 2552 mediatek,smi = <&smi_common_vpp>; 2553 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 2554 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 2555 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 2556 clock-names = "apb", "smi", "gals"; 2557 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2558 }; 2559 2560 vdosys1: syscon@1c100000 { 2561 compatible = "mediatek,mt8195-mmsys", "syscon"; 2562 reg = <0 0x1c100000 0 0x1000>; 2563 #clock-cells = <1>; 2564 }; 2565 2566 smi_common_vdo: smi@1c01b000 { 2567 compatible = "mediatek,mt8195-smi-common-vdo"; 2568 reg = <0 0x1c01b000 0 0x1000>; 2569 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 2570 <&vdosys0 CLK_VDO0_SMI_EMI>, 2571 <&vdosys0 CLK_VDO0_SMI_RSI>, 2572 <&vdosys0 CLK_VDO0_SMI_GALS>; 2573 clock-names = "apb", "smi", "gals0", "gals1"; 2574 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2575 2576 }; 2577 2578 iommu_vdo: iommu@1c01f000 { 2579 compatible = "mediatek,mt8195-iommu-vdo"; 2580 reg = <0 0x1c01f000 0 0x1000>; 2581 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 2582 &larb10 &larb11 &larb13 &larb17 2583 &larb19 &larb21 &larb24 &larb25 2584 &larb28>; 2585 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 2586 #iommu-cells = <1>; 2587 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 2588 clock-names = "bclk"; 2589 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 2590 }; 2591 2592 larb2: larb@1c102000 { 2593 compatible = "mediatek,mt8195-smi-larb"; 2594 reg = <0 0x1c102000 0 0x1000>; 2595 mediatek,larb-id = <2>; 2596 mediatek,smi = <&smi_common_vdo>; 2597 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 2598 <&vdosys1 CLK_VDO1_SMI_LARB2>, 2599 <&vdosys1 CLK_VDO1_GALS>; 2600 clock-names = "apb", "smi", "gals"; 2601 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2602 }; 2603 2604 larb3: larb@1c103000 { 2605 compatible = "mediatek,mt8195-smi-larb"; 2606 reg = <0 0x1c103000 0 0x1000>; 2607 mediatek,larb-id = <3>; 2608 mediatek,smi = <&smi_common_vpp>; 2609 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 2610 <&vdosys1 CLK_VDO1_GALS>, 2611 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 2612 clock-names = "apb", "smi", "gals"; 2613 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2614 }; 2615 2616 dp_intf1: dp-intf@1c113000 { 2617 compatible = "mediatek,mt8195-dp-intf"; 2618 reg = <0 0x1c113000 0 0x1000>; 2619 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 2620 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 2621 clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, 2622 <&vdosys1 CLK_VDO1_DPINTF>, 2623 <&apmixedsys CLK_APMIXED_TVDPLL2>; 2624 clock-names = "engine", "pixel", "pll"; 2625 status = "disabled"; 2626 }; 2627 2628 edp_tx: edp-tx@1c500000 { 2629 compatible = "mediatek,mt8195-edp-tx"; 2630 reg = <0 0x1c500000 0 0x8000>; 2631 nvmem-cells = <&dp_calibration>; 2632 nvmem-cell-names = "dp_calibration_data"; 2633 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; 2634 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 2635 max-linkrate-mhz = <8100>; 2636 status = "disabled"; 2637 }; 2638 2639 dp_tx: dp-tx@1c600000 { 2640 compatible = "mediatek,mt8195-dp-tx"; 2641 reg = <0 0x1c600000 0 0x8000>; 2642 nvmem-cells = <&dp_calibration>; 2643 nvmem-cell-names = "dp_calibration_data"; 2644 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; 2645 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 2646 max-linkrate-mhz = <8100>; 2647 status = "disabled"; 2648 }; 2649 }; 2650}; 2651