1*37f25828STinghan Shen// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*37f25828STinghan Shen/* 3*37f25828STinghan Shen * Copyright (C) 2021 MediaTek Inc. 4*37f25828STinghan Shen * Author: Seiya Wang <seiya.wang@mediatek.com> 5*37f25828STinghan Shen */ 6*37f25828STinghan Shen/dts-v1/; 7*37f25828STinghan Shen#include "mt8195.dtsi" 8*37f25828STinghan Shen 9*37f25828STinghan Shen/ { 10*37f25828STinghan Shen model = "MediaTek MT8195 evaluation board"; 11*37f25828STinghan Shen compatible = "mediatek,mt8195-evb", "mediatek,mt8195"; 12*37f25828STinghan Shen 13*37f25828STinghan Shen aliases { 14*37f25828STinghan Shen serial0 = &uart0; 15*37f25828STinghan Shen }; 16*37f25828STinghan Shen 17*37f25828STinghan Shen chosen { 18*37f25828STinghan Shen stdout-path = "serial0:921600n8"; 19*37f25828STinghan Shen }; 20*37f25828STinghan Shen 21*37f25828STinghan Shen memory@40000000 { 22*37f25828STinghan Shen device_type = "memory"; 23*37f25828STinghan Shen reg = <0 0x40000000 0 0x80000000>; 24*37f25828STinghan Shen }; 25*37f25828STinghan Shen}; 26*37f25828STinghan Shen 27*37f25828STinghan Shen&auxadc { 28*37f25828STinghan Shen status = "okay"; 29*37f25828STinghan Shen}; 30*37f25828STinghan Shen 31*37f25828STinghan Shen&i2c0 { 32*37f25828STinghan Shen pinctrl-names = "default"; 33*37f25828STinghan Shen pinctrl-0 = <&i2c0_pin>; 34*37f25828STinghan Shen clock-frequency = <100000>; 35*37f25828STinghan Shen status = "okay"; 36*37f25828STinghan Shen}; 37*37f25828STinghan Shen 38*37f25828STinghan Shen&i2c1 { 39*37f25828STinghan Shen pinctrl-names = "default"; 40*37f25828STinghan Shen pinctrl-0 = <&i2c1_pin>; 41*37f25828STinghan Shen clock-frequency = <400000>; 42*37f25828STinghan Shen status = "okay"; 43*37f25828STinghan Shen}; 44*37f25828STinghan Shen 45*37f25828STinghan Shen&i2c4 { 46*37f25828STinghan Shen pinctrl-names = "default"; 47*37f25828STinghan Shen pinctrl-0 = <&i2c4_pin>; 48*37f25828STinghan Shen clock-frequency = <400000>; 49*37f25828STinghan Shen status = "okay"; 50*37f25828STinghan Shen}; 51*37f25828STinghan Shen 52*37f25828STinghan Shen&i2c6 { 53*37f25828STinghan Shen pinctrl-names = "default"; 54*37f25828STinghan Shen pinctrl-0 = <&i2c6_pin>; 55*37f25828STinghan Shen clock-frequency = <400000>; 56*37f25828STinghan Shen status = "okay"; 57*37f25828STinghan Shen}; 58*37f25828STinghan Shen 59*37f25828STinghan Shen&nor_flash { 60*37f25828STinghan Shen status = "okay"; 61*37f25828STinghan Shen pinctrl-names = "default"; 62*37f25828STinghan Shen pinctrl-0 = <&nor_pins_default>; 63*37f25828STinghan Shen 64*37f25828STinghan Shen flash@0 { 65*37f25828STinghan Shen compatible = "jedec,spi-nor"; 66*37f25828STinghan Shen reg = <0>; 67*37f25828STinghan Shen spi-max-frequency = <50000000>; 68*37f25828STinghan Shen }; 69*37f25828STinghan Shen}; 70*37f25828STinghan Shen 71*37f25828STinghan Shen&pio { 72*37f25828STinghan Shen i2c0_pin: i2c0-pins { 73*37f25828STinghan Shen pins { 74*37f25828STinghan Shen pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 75*37f25828STinghan Shen <PINMUX_GPIO9__FUNC_SCL0>; 76*37f25828STinghan Shen bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 77*37f25828STinghan Shen mediatek,drive-strength-adv = <0>; 78*37f25828STinghan Shen drive-strength = <6>; 79*37f25828STinghan Shen }; 80*37f25828STinghan Shen }; 81*37f25828STinghan Shen 82*37f25828STinghan Shen i2c1_pin: i2c1-pins { 83*37f25828STinghan Shen pins { 84*37f25828STinghan Shen pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 85*37f25828STinghan Shen <PINMUX_GPIO11__FUNC_SCL1>; 86*37f25828STinghan Shen bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 87*37f25828STinghan Shen mediatek,drive-strength-adv = <0>; 88*37f25828STinghan Shen drive-strength = <6>; 89*37f25828STinghan Shen }; 90*37f25828STinghan Shen }; 91*37f25828STinghan Shen 92*37f25828STinghan Shen i2c4_pin: i2c4-pins { 93*37f25828STinghan Shen pins { 94*37f25828STinghan Shen pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 95*37f25828STinghan Shen <PINMUX_GPIO17__FUNC_SCL4>; 96*37f25828STinghan Shen bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 97*37f25828STinghan Shen mediatek,drive-strength-adv = <7>; 98*37f25828STinghan Shen }; 99*37f25828STinghan Shen }; 100*37f25828STinghan Shen 101*37f25828STinghan Shen i2c6_pin: i2c6-pins { 102*37f25828STinghan Shen pins { 103*37f25828STinghan Shen pinmux = <PINMUX_GPIO25__FUNC_SDA6>, 104*37f25828STinghan Shen <PINMUX_GPIO26__FUNC_SCL6>; 105*37f25828STinghan Shen bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 106*37f25828STinghan Shen }; 107*37f25828STinghan Shen }; 108*37f25828STinghan Shen 109*37f25828STinghan Shen i2c7_pin: i2c7-pins { 110*37f25828STinghan Shen pins { 111*37f25828STinghan Shen pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 112*37f25828STinghan Shen <PINMUX_GPIO28__FUNC_SDA7>; 113*37f25828STinghan Shen bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 114*37f25828STinghan Shen }; 115*37f25828STinghan Shen }; 116*37f25828STinghan Shen 117*37f25828STinghan Shen nor_pins_default: nor-pins { 118*37f25828STinghan Shen pins0 { 119*37f25828STinghan Shen pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 120*37f25828STinghan Shen <PINMUX_GPIO141__FUNC_SPINOR_CK>, 121*37f25828STinghan Shen <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 122*37f25828STinghan Shen bias-pull-down; 123*37f25828STinghan Shen }; 124*37f25828STinghan Shen 125*37f25828STinghan Shen pins1 { 126*37f25828STinghan Shen pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>, 127*37f25828STinghan Shen <PINMUX_GPIO130__FUNC_SPINOR_IO2>, 128*37f25828STinghan Shen <PINMUX_GPIO131__FUNC_SPINOR_IO3>; 129*37f25828STinghan Shen bias-pull-up; 130*37f25828STinghan Shen }; 131*37f25828STinghan Shen }; 132*37f25828STinghan Shen 133*37f25828STinghan Shen uart0_pin: uart0-pins { 134*37f25828STinghan Shen pins { 135*37f25828STinghan Shen pinmux = <PINMUX_GPIO98__FUNC_UTXD0>, 136*37f25828STinghan Shen <PINMUX_GPIO99__FUNC_URXD0>; 137*37f25828STinghan Shen }; 138*37f25828STinghan Shen }; 139*37f25828STinghan Shen}; 140*37f25828STinghan Shen 141*37f25828STinghan Shen&u3phy0 { 142*37f25828STinghan Shen status="okay"; 143*37f25828STinghan Shen}; 144*37f25828STinghan Shen 145*37f25828STinghan Shen&u3phy1 { 146*37f25828STinghan Shen status="okay"; 147*37f25828STinghan Shen}; 148*37f25828STinghan Shen 149*37f25828STinghan Shen&u3phy2 { 150*37f25828STinghan Shen status="okay"; 151*37f25828STinghan Shen}; 152*37f25828STinghan Shen 153*37f25828STinghan Shen&u3phy3 { 154*37f25828STinghan Shen status="okay"; 155*37f25828STinghan Shen}; 156*37f25828STinghan Shen 157*37f25828STinghan Shen&uart0 { 158*37f25828STinghan Shen pinctrl-names = "default"; 159*37f25828STinghan Shen pinctrl-0 = <&uart0_pin>; 160*37f25828STinghan Shen status = "okay"; 161*37f25828STinghan Shen}; 162*37f25828STinghan Shen 163*37f25828STinghan Shen&xhci0 { 164*37f25828STinghan Shen status = "okay"; 165*37f25828STinghan Shen}; 166*37f25828STinghan Shen 167*37f25828STinghan Shen&xhci1 { 168*37f25828STinghan Shen status = "okay"; 169*37f25828STinghan Shen}; 170*37f25828STinghan Shen 171*37f25828STinghan Shen&xhci2 { 172*37f25828STinghan Shen status = "okay"; 173*37f25828STinghan Shen}; 174*37f25828STinghan Shen 175*37f25828STinghan Shen&xhci3 { 176*37f25828STinghan Shen /* This controller is connected with a BT device. 177*37f25828STinghan Shen * Disable usb2 lpm to prevent known issues. 178*37f25828STinghan Shen */ 179*37f25828STinghan Shen usb2-lpm-disable; 180*37f25828STinghan Shen status = "okay"; 181*37f25828STinghan Shen}; 182