xref: /linux/arch/arm64/boot/dts/mediatek/mt8195-evb.dts (revision 27f0974a982998d59c645489da9dd99e4c6bafb2)
137f25828STinghan Shen// SPDX-License-Identifier: (GPL-2.0 OR MIT)
237f25828STinghan Shen/*
337f25828STinghan Shen * Copyright (C) 2021 MediaTek Inc.
437f25828STinghan Shen * Author: Seiya Wang <seiya.wang@mediatek.com>
537f25828STinghan Shen */
637f25828STinghan Shen/dts-v1/;
737f25828STinghan Shen#include "mt8195.dtsi"
837f25828STinghan Shen
937f25828STinghan Shen/ {
1037f25828STinghan Shen	model = "MediaTek MT8195 evaluation board";
1137f25828STinghan Shen	compatible = "mediatek,mt8195-evb", "mediatek,mt8195";
1237f25828STinghan Shen
1337f25828STinghan Shen	aliases {
1437f25828STinghan Shen		serial0 = &uart0;
1537f25828STinghan Shen	};
1637f25828STinghan Shen
1737f25828STinghan Shen	chosen {
1837f25828STinghan Shen		stdout-path = "serial0:921600n8";
1937f25828STinghan Shen	};
2037f25828STinghan Shen
2137f25828STinghan Shen	memory@40000000 {
2237f25828STinghan Shen		device_type = "memory";
2337f25828STinghan Shen		reg = <0 0x40000000 0 0x80000000>;
2437f25828STinghan Shen	};
2537f25828STinghan Shen};
2637f25828STinghan Shen
2737f25828STinghan Shen&auxadc {
2837f25828STinghan Shen	status = "okay";
2937f25828STinghan Shen};
3037f25828STinghan Shen
3137f25828STinghan Shen&i2c0 {
3237f25828STinghan Shen	pinctrl-names = "default";
3337f25828STinghan Shen	pinctrl-0 = <&i2c0_pin>;
3437f25828STinghan Shen	clock-frequency = <100000>;
3537f25828STinghan Shen	status = "okay";
3637f25828STinghan Shen};
3737f25828STinghan Shen
3837f25828STinghan Shen&i2c1 {
3937f25828STinghan Shen	pinctrl-names = "default";
4037f25828STinghan Shen	pinctrl-0 = <&i2c1_pin>;
4137f25828STinghan Shen	clock-frequency = <400000>;
4237f25828STinghan Shen	status = "okay";
4337f25828STinghan Shen};
4437f25828STinghan Shen
4537f25828STinghan Shen&i2c4 {
4637f25828STinghan Shen	pinctrl-names = "default";
4737f25828STinghan Shen	pinctrl-0 = <&i2c4_pin>;
4837f25828STinghan Shen	clock-frequency = <400000>;
4937f25828STinghan Shen	status = "okay";
5037f25828STinghan Shen};
5137f25828STinghan Shen
5237f25828STinghan Shen&i2c6 {
5337f25828STinghan Shen	pinctrl-names = "default";
5437f25828STinghan Shen	pinctrl-0 = <&i2c6_pin>;
5537f25828STinghan Shen	clock-frequency = <400000>;
5637f25828STinghan Shen	status = "okay";
5737f25828STinghan Shen};
5837f25828STinghan Shen
5937f25828STinghan Shen&nor_flash {
6037f25828STinghan Shen	status = "okay";
6137f25828STinghan Shen	pinctrl-names = "default";
6237f25828STinghan Shen	pinctrl-0 = <&nor_pins_default>;
6337f25828STinghan Shen
6437f25828STinghan Shen	flash@0 {
6537f25828STinghan Shen		compatible = "jedec,spi-nor";
6637f25828STinghan Shen		reg = <0>;
6737f25828STinghan Shen		spi-max-frequency = <50000000>;
6837f25828STinghan Shen	};
6937f25828STinghan Shen};
7037f25828STinghan Shen
7137f25828STinghan Shen&pio {
7237f25828STinghan Shen	i2c0_pin: i2c0-pins {
7337f25828STinghan Shen		pins {
7437f25828STinghan Shen			pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
7537f25828STinghan Shen				 <PINMUX_GPIO9__FUNC_SCL0>;
7637f25828STinghan Shen			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
7737f25828STinghan Shen			drive-strength = <6>;
7837f25828STinghan Shen		};
7937f25828STinghan Shen	};
8037f25828STinghan Shen
8137f25828STinghan Shen	i2c1_pin: i2c1-pins {
8237f25828STinghan Shen		pins {
8337f25828STinghan Shen			pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
8437f25828STinghan Shen				 <PINMUX_GPIO11__FUNC_SCL1>;
8537f25828STinghan Shen			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
8637f25828STinghan Shen			drive-strength = <6>;
8737f25828STinghan Shen		};
8837f25828STinghan Shen	};
8937f25828STinghan Shen
9037f25828STinghan Shen	i2c4_pin: i2c4-pins {
9137f25828STinghan Shen		pins {
9237f25828STinghan Shen			pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
9337f25828STinghan Shen				 <PINMUX_GPIO17__FUNC_SCL4>;
9437f25828STinghan Shen			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
95*27f0974aSChen-Yu Tsai			drive-strength-microamp = <1000>;
9637f25828STinghan Shen		};
9737f25828STinghan Shen	};
9837f25828STinghan Shen
9937f25828STinghan Shen	i2c6_pin: i2c6-pins {
10037f25828STinghan Shen		pins {
10137f25828STinghan Shen			pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
10237f25828STinghan Shen				 <PINMUX_GPIO26__FUNC_SCL6>;
10337f25828STinghan Shen			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
10437f25828STinghan Shen		};
10537f25828STinghan Shen	};
10637f25828STinghan Shen
10737f25828STinghan Shen	i2c7_pin: i2c7-pins {
10837f25828STinghan Shen		pins {
10937f25828STinghan Shen			pinmux = <PINMUX_GPIO27__FUNC_SCL7>,
11037f25828STinghan Shen				 <PINMUX_GPIO28__FUNC_SDA7>;
11137f25828STinghan Shen			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
11237f25828STinghan Shen		};
11337f25828STinghan Shen	};
11437f25828STinghan Shen
11537f25828STinghan Shen	nor_pins_default: nor-pins {
11637f25828STinghan Shen		pins0 {
11737f25828STinghan Shen			pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
11837f25828STinghan Shen				 <PINMUX_GPIO141__FUNC_SPINOR_CK>,
11937f25828STinghan Shen				 <PINMUX_GPIO143__FUNC_SPINOR_IO1>;
12037f25828STinghan Shen			bias-pull-down;
12137f25828STinghan Shen		};
12237f25828STinghan Shen
12337f25828STinghan Shen		pins1 {
12437f25828STinghan Shen			pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>,
12537f25828STinghan Shen				 <PINMUX_GPIO130__FUNC_SPINOR_IO2>,
12637f25828STinghan Shen				 <PINMUX_GPIO131__FUNC_SPINOR_IO3>;
12737f25828STinghan Shen			bias-pull-up;
12837f25828STinghan Shen		};
12937f25828STinghan Shen	};
13037f25828STinghan Shen
13137f25828STinghan Shen	uart0_pin: uart0-pins {
13237f25828STinghan Shen		pins {
13337f25828STinghan Shen			pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
13437f25828STinghan Shen				 <PINMUX_GPIO99__FUNC_URXD0>;
13537f25828STinghan Shen		};
13637f25828STinghan Shen	};
13737f25828STinghan Shen};
13837f25828STinghan Shen
13937f25828STinghan Shen&u3phy0 {
14037f25828STinghan Shen	status = "okay";
14137f25828STinghan Shen};
14237f25828STinghan Shen
14337f25828STinghan Shen&u3phy1 {
14437f25828STinghan Shen	status = "okay";
14537f25828STinghan Shen};
14637f25828STinghan Shen
14737f25828STinghan Shen&u3phy2 {
14837f25828STinghan Shen	status = "okay";
14937f25828STinghan Shen};
15037f25828STinghan Shen
15137f25828STinghan Shen&u3phy3 {
15237f25828STinghan Shen	status = "okay";
15337f25828STinghan Shen};
15437f25828STinghan Shen
15537f25828STinghan Shen&uart0 {
15637f25828STinghan Shen	pinctrl-names = "default";
15737f25828STinghan Shen	pinctrl-0 = <&uart0_pin>;
15837f25828STinghan Shen	status = "okay";
15937f25828STinghan Shen};
16037f25828STinghan Shen
161795d5f0cSAngeloGioacchino Del Regno&ssusb0 {
162795d5f0cSAngeloGioacchino Del Regno	status = "okay";
163795d5f0cSAngeloGioacchino Del Regno};
164795d5f0cSAngeloGioacchino Del Regno
165795d5f0cSAngeloGioacchino Del Regno&ssusb2 {
166795d5f0cSAngeloGioacchino Del Regno	status = "okay";
167795d5f0cSAngeloGioacchino Del Regno};
168795d5f0cSAngeloGioacchino Del Regno
169795d5f0cSAngeloGioacchino Del Regno&ssusb3 {
170795d5f0cSAngeloGioacchino Del Regno	status = "okay";
171795d5f0cSAngeloGioacchino Del Regno};
172795d5f0cSAngeloGioacchino Del Regno
17337f25828STinghan Shen&xhci0 {
17437f25828STinghan Shen	status = "okay";
17537f25828STinghan Shen};
17637f25828STinghan Shen
17737f25828STinghan Shen&xhci1 {
17837f25828STinghan Shen	status = "okay";
17937f25828STinghan Shen};
18037f25828STinghan Shen
18137f25828STinghan Shen&xhci2 {
18237f25828STinghan Shen	status = "okay";
18337f25828STinghan Shen};
18437f25828STinghan Shen
18537f25828STinghan Shen&xhci3 {
18637f25828STinghan Shen	/* This controller is connected with a BT device.
18737f25828STinghan Shen	 * Disable usb2 lpm to prevent known issues.
18837f25828STinghan Shen	 */
18937f25828STinghan Shen	usb2-lpm-disable;
19037f25828STinghan Shen	status = "okay";
19137f25828STinghan Shen};
192