xref: /linux/arch/arm64/boot/dts/mediatek/mt8195-demo.dts (revision d7b4e3287ca3a7baf66efd9158498e551a9550da) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2022 BayLibre, SAS.
4 * Author: Fabien Parent <fparent@baylibre.com>
5 */
6/dts-v1/;
7
8#include "mt8195.dtsi"
9#include "mt6359.dtsi"
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
14#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
15
16/ {
17	model = "MediaTek MT8195 demo board";
18	compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
19
20	aliases {
21		serial0 = &uart0;
22	};
23
24	chosen {
25		stdout-path = "serial0:921600n8";
26	};
27
28	firmware {
29		optee {
30			compatible = "linaro,optee-tz";
31			method = "smc";
32		};
33	};
34
35	gpio-keys {
36		compatible = "gpio-keys";
37		pinctrl-names = "default";
38		pinctrl-0 = <&gpio_keys_pins>;
39
40		key-0 {
41			gpios = <&pio 106 GPIO_ACTIVE_LOW>;
42			label = "volume_up";
43			linux,code = <KEY_VOLUMEUP>;
44			wakeup-source;
45			debounce-interval = <15>;
46		};
47	};
48
49	memory@40000000 {
50		device_type = "memory";
51		reg = <0 0x40000000 0x2 0x00000000>;
52	};
53
54	reserved-memory {
55		#address-cells = <2>;
56		#size-cells = <2>;
57		ranges;
58
59		/*
60		 * 12 MiB reserved for OP-TEE (BL32)
61		 * +-----------------------+ 0x43e0_0000
62		 * |      SHMEM 2MiB       |
63		 * +-----------------------+ 0x43c0_0000
64		 * |        | TA_RAM  8MiB |
65		 * + TZDRAM +--------------+ 0x4340_0000
66		 * |        | TEE_RAM 2MiB |
67		 * +-----------------------+ 0x4320_0000
68		 */
69		optee_reserved: optee@43200000 {
70			no-map;
71			reg = <0 0x43200000 0 0x00c00000>;
72		};
73
74		scp_mem: memory@50000000 {
75			compatible = "shared-dma-pool";
76			reg = <0 0x50000000 0 0x2900000>;
77			no-map;
78		};
79
80		vpu_mem: memory@53000000 {
81			compatible = "shared-dma-pool";
82			reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
83		};
84
85		/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
86		bl31_secmon_mem: memory@54600000 {
87			no-map;
88			reg = <0 0x54600000 0x0 0x200000>;
89		};
90
91		snd_dma_mem: memory@60000000 {
92			compatible = "shared-dma-pool";
93			reg = <0 0x60000000 0 0x1100000>;
94			no-map;
95		};
96
97		apu_mem: memory@62000000 {
98			compatible = "shared-dma-pool";
99			reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
100		};
101	};
102};
103
104&eth {
105	phy-mode = "rgmii-id";
106	phy-handle = <&ethernet_phy0>;
107	snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
108	snps,reset-delays-us = <0 10000 80000>;
109	pinctrl-names = "default", "sleep";
110	pinctrl-0 = <&eth_default_pins>;
111	pinctrl-1 = <&eth_sleep_pins>;
112	status = "okay";
113
114	mdio {
115		ethernet_phy0: ethernet-phy@1 {
116			reg = <0x1>;
117		};
118	};
119};
120
121&i2c6 {
122	clock-frequency = <400000>;
123	pinctrl-0 = <&i2c6_pins>;
124	pinctrl-names = "default";
125	status = "okay";
126
127	mt6360: pmic@34 {
128		compatible = "mediatek,mt6360";
129		reg = <0x34>;
130		interrupt-controller;
131		#interrupt-cells = <1>;
132		interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
133		interrupt-names = "IRQB";
134
135		charger {
136			compatible = "mediatek,mt6360-chg";
137			richtek,vinovp-microvolt = <14500000>;
138
139			otg_vbus_regulator: usb-otg-vbus-regulator {
140				regulator-compatible = "usb-otg-vbus";
141				regulator-name = "usb-otg-vbus";
142				regulator-min-microvolt = <4425000>;
143				regulator-max-microvolt = <5825000>;
144			};
145		};
146
147		regulator {
148			compatible = "mediatek,mt6360-regulator";
149			LDO_VIN3-supply = <&mt6360_buck2>;
150
151			mt6360_buck1: buck1 {
152				regulator-compatible = "BUCK1";
153				regulator-name = "mt6360,buck1";
154				regulator-min-microvolt = <300000>;
155				regulator-max-microvolt = <1300000>;
156				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
157							   MT6360_OPMODE_LP
158							   MT6360_OPMODE_ULP>;
159				regulator-always-on;
160			};
161
162			mt6360_buck2: buck2 {
163				regulator-compatible = "BUCK2";
164				regulator-name = "mt6360,buck2";
165				regulator-min-microvolt = <300000>;
166				regulator-max-microvolt = <1300000>;
167				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
168							   MT6360_OPMODE_LP
169							   MT6360_OPMODE_ULP>;
170				regulator-always-on;
171			};
172
173			mt6360_ldo1: ldo1 {
174				regulator-compatible = "LDO1";
175				regulator-name = "mt6360,ldo1";
176				regulator-min-microvolt = <1200000>;
177				regulator-max-microvolt = <3600000>;
178				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
179							   MT6360_OPMODE_LP>;
180			};
181
182			mt6360_ldo2: ldo2 {
183				regulator-compatible = "LDO2";
184				regulator-name = "mt6360,ldo2";
185				regulator-min-microvolt = <1200000>;
186				regulator-max-microvolt = <3600000>;
187				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
188							   MT6360_OPMODE_LP>;
189			};
190
191			mt6360_ldo3: ldo3 {
192				regulator-compatible = "LDO3";
193				regulator-name = "mt6360,ldo3";
194				regulator-min-microvolt = <1200000>;
195				regulator-max-microvolt = <3600000>;
196				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
197							   MT6360_OPMODE_LP>;
198			};
199
200			mt6360_ldo5: ldo5 {
201				regulator-compatible = "LDO5";
202				regulator-name = "mt6360,ldo5";
203				regulator-min-microvolt = <2700000>;
204				regulator-max-microvolt = <3600000>;
205				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
206							   MT6360_OPMODE_LP>;
207			};
208
209			mt6360_ldo6: ldo6 {
210				regulator-compatible = "LDO6";
211				regulator-name = "mt6360,ldo6";
212				regulator-min-microvolt = <500000>;
213				regulator-max-microvolt = <2100000>;
214				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
215							   MT6360_OPMODE_LP>;
216			};
217
218			mt6360_ldo7: ldo7 {
219				regulator-compatible = "LDO7";
220				regulator-name = "mt6360,ldo7";
221				regulator-min-microvolt = <500000>;
222				regulator-max-microvolt = <2100000>;
223				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
224							   MT6360_OPMODE_LP>;
225				regulator-always-on;
226			};
227		};
228	};
229};
230
231&mmc0 {
232	status = "okay";
233	pinctrl-names = "default", "state_uhs";
234	pinctrl-0 = <&mmc0_default_pins>;
235	pinctrl-1 = <&mmc0_uhs_pins>;
236	bus-width = <8>;
237	max-frequency = <200000000>;
238	cap-mmc-highspeed;
239	mmc-hs200-1_8v;
240	mmc-hs400-1_8v;
241	cap-mmc-hw-reset;
242	no-sdio;
243	no-sd;
244	hs400-ds-delay = <0x14c11>;
245	vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
246	vqmmc-supply = <&mt6359_vufs_ldo_reg>;
247	non-removable;
248};
249
250&mmc1 {
251	pinctrl-names = "default", "state_uhs";
252	pinctrl-0 = <&mmc1_default_pins>;
253	pinctrl-1 = <&mmc1_uhs_pins>;
254	cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
255	bus-width = <4>;
256	max-frequency = <200000000>;
257	cap-sd-highspeed;
258	sd-uhs-sdr50;
259	sd-uhs-sdr104;
260	vmmc-supply = <&mt6360_ldo5>;
261	vqmmc-supply = <&mt6360_ldo3>;
262	status = "okay";
263};
264
265&mt6359_vbbck_ldo_reg {
266	regulator-always-on;
267};
268
269&mt6359_vcore_buck_reg {
270	regulator-always-on;
271};
272
273&mt6359_vgpu11_buck_reg {
274	regulator-always-on;
275};
276
277&mt6359_vproc1_buck_reg {
278	regulator-always-on;
279};
280
281&mt6359_vproc2_buck_reg {
282	regulator-always-on;
283};
284
285&mt6359_vpu_buck_reg {
286	regulator-always-on;
287};
288
289&mt6359_vrf12_ldo_reg {
290	regulator-always-on;
291};
292
293&mt6359_vsram_md_ldo_reg {
294	regulator-always-on;
295};
296
297&mt6359_vsram_others_ldo_reg {
298	regulator-always-on;
299};
300
301&pio {
302	eth_default_pins: eth-default-pins {
303		pins-txd {
304			pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
305				 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
306				 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
307				 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
308			drive-strength = <MTK_DRIVE_8mA>;
309		};
310		pins-cc {
311			pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
312				 <PINMUX_GPIO88__FUNC_GBE_TXEN>,
313				 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
314				 <PINMUX_GPIO86__FUNC_GBE_RXC>;
315			drive-strength = <MTK_DRIVE_8mA>;
316		};
317		pins-rxd {
318			pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
319				 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
320				 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
321				 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
322		};
323		pins-mdio {
324			pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
325				 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
326			input-enable;
327		};
328		pins-power {
329			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
330				 <PINMUX_GPIO92__FUNC_GPIO92>;
331			output-high;
332		};
333	};
334
335	eth_sleep_pins: eth-sleep-pins {
336		pins-txd {
337			pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
338				 <PINMUX_GPIO78__FUNC_GPIO78>,
339				 <PINMUX_GPIO79__FUNC_GPIO79>,
340				 <PINMUX_GPIO80__FUNC_GPIO80>;
341		};
342		pins-cc {
343			pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
344				 <PINMUX_GPIO88__FUNC_GPIO88>,
345				 <PINMUX_GPIO87__FUNC_GPIO87>,
346				 <PINMUX_GPIO86__FUNC_GPIO86>;
347		};
348		pins-rxd {
349			pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
350				 <PINMUX_GPIO82__FUNC_GPIO82>,
351				 <PINMUX_GPIO83__FUNC_GPIO83>,
352				 <PINMUX_GPIO84__FUNC_GPIO84>;
353		};
354		pins-mdio {
355			pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
356				 <PINMUX_GPIO90__FUNC_GPIO90>;
357			input-disable;
358			bias-disable;
359		};
360	};
361
362	gpio_keys_pins: gpio-keys-pins {
363		pins {
364			pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
365			input-enable;
366		};
367	};
368
369	i2c6_pins: i2c6-pins {
370		pins {
371			pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
372				 <PINMUX_GPIO26__FUNC_SCL6>;
373			bias-pull-up;
374		};
375	};
376
377	mmc0_default_pins: mmc0-default-pins {
378		pins-clk {
379			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
380			drive-strength = <MTK_DRIVE_6mA>;
381			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
382		};
383
384		pins-cmd-dat {
385			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
386				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
387				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
388				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
389				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
390				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
391				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
392				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
393				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
394			input-enable;
395			drive-strength = <MTK_DRIVE_6mA>;
396			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
397		};
398
399		pins-rst {
400			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
401			drive-strength = <MTK_DRIVE_6mA>;
402			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
403		};
404	};
405
406	mmc0_uhs_pins: mmc0-uhs-pins {
407		pins-clk {
408			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
409			drive-strength = <MTK_DRIVE_8mA>;
410			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
411		};
412
413		pins-cmd-dat {
414			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
415				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
416				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
417				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
418				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
419				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
420				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
421				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
422				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
423			input-enable;
424			drive-strength = <MTK_DRIVE_8mA>;
425			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
426		};
427
428		pins-ds {
429			pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
430			drive-strength = <MTK_DRIVE_8mA>;
431			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
432		};
433
434		pins-rst {
435			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
436			drive-strength = <MTK_DRIVE_8mA>;
437			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
438		};
439	};
440
441	mmc1_default_pins: mmc1-default-pins {
442		pins-clk {
443			pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
444			drive-strength = <MTK_DRIVE_8mA>;
445			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
446		};
447
448		pins-cmd-dat {
449			pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
450				 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
451				 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
452				 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
453				 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
454			input-enable;
455			drive-strength = <MTK_DRIVE_8mA>;
456			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
457		};
458
459		pins-insert {
460			pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
461			bias-pull-up;
462		};
463	};
464
465	mmc1_uhs_pins: mmc1-uhs-pins {
466		pins-clk {
467			pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
468			drive-strength = <MTK_DRIVE_8mA>;
469			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
470		};
471
472		pins-cmd-dat {
473			pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
474				 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
475				 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
476				 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
477				 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
478			input-enable;
479			drive-strength = <MTK_DRIVE_8mA>;
480			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
481		};
482	};
483
484	uart0_pins: uart0-pins {
485		pins {
486			pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
487				 <PINMUX_GPIO99__FUNC_URXD0>;
488		};
489	};
490
491	uart1_pins: uart1-pins {
492		pins {
493			pinmux = <PINMUX_GPIO102__FUNC_UTXD1>,
494				 <PINMUX_GPIO103__FUNC_URXD1>;
495		};
496	};
497};
498
499
500&pmic {
501	interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
502};
503
504&uart0 {
505	pinctrl-names = "default";
506	pinctrl-0 = <&uart0_pins>;
507	status = "okay";
508};
509
510&uart1 {
511	pinctrl-names = "default";
512	pinctrl-0 = <&uart1_pins>;
513	status = "okay";
514};
515
516&u3phy0 {
517	status = "okay";
518};
519
520&u3phy1 {
521	status = "okay";
522};
523
524&u3phy2 {
525	status = "okay";
526};
527
528&u3phy3 {
529	status = "okay";
530};
531
532&xhci0 {
533	vusb33-supply = <&mt6359_vusb_ldo_reg>;
534	vbus-supply = <&otg_vbus_regulator>;
535	status = "okay";
536};
537
538&xhci1 {
539	vusb33-supply = <&mt6359_vusb_ldo_reg>;
540	status = "okay";
541};
542
543&xhci2 {
544	vusb33-supply = <&mt6359_vusb_ldo_reg>;
545	status = "okay";
546};
547
548&xhci3 {
549	vusb33-supply = <&mt6359_vusb_ldo_reg>;
550	status = "okay";
551};
552