xref: /linux/arch/arm64/boot/dts/mediatek/mt8195-demo.dts (revision c5dbf04160005e07e8ca7232a7faa77ab1547ae0) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2022 BayLibre, SAS.
4 * Author: Fabien Parent <fparent@baylibre.com>
5 */
6/dts-v1/;
7
8#include "mt8195.dtsi"
9#include "mt6359.dtsi"
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
14#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
15
16/ {
17	model = "MediaTek MT8195 demo board";
18	compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
19
20	aliases {
21		serial0 = &uart0;
22	};
23
24	chosen {
25		stdout-path = "serial0:921600n8";
26	};
27
28	firmware {
29		optee {
30			compatible = "linaro,optee-tz";
31			method = "smc";
32		};
33	};
34
35	gpio-keys {
36		compatible = "gpio-keys";
37		pinctrl-names = "default";
38		pinctrl-0 = <&gpio_keys_pins>;
39
40		key-0 {
41			gpios = <&pio 106 GPIO_ACTIVE_LOW>;
42			label = "volume_up";
43			linux,code = <KEY_VOLUMEUP>;
44			wakeup-source;
45			debounce-interval = <15>;
46		};
47	};
48
49	memory@40000000 {
50		device_type = "memory";
51		reg = <0 0x40000000 0x2 0x00000000>;
52	};
53
54	reserved-memory {
55		#address-cells = <2>;
56		#size-cells = <2>;
57		ranges;
58
59		/*
60		 * 12 MiB reserved for OP-TEE (BL32)
61		 * +-----------------------+ 0x43e0_0000
62		 * |      SHMEM 2MiB       |
63		 * +-----------------------+ 0x43c0_0000
64		 * |        | TA_RAM  8MiB |
65		 * + TZDRAM +--------------+ 0x4340_0000
66		 * |        | TEE_RAM 2MiB |
67		 * +-----------------------+ 0x4320_0000
68		 */
69		optee_reserved: optee@43200000 {
70			no-map;
71			reg = <0 0x43200000 0 0x00c00000>;
72		};
73
74		scp_mem: memory@50000000 {
75			compatible = "shared-dma-pool";
76			reg = <0 0x50000000 0 0x2900000>;
77			no-map;
78		};
79
80		vpu_mem: memory@53000000 {
81			compatible = "shared-dma-pool";
82			reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
83		};
84
85		/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
86		bl31_secmon_mem: memory@54600000 {
87			no-map;
88			reg = <0 0x54600000 0x0 0x200000>;
89		};
90
91		snd_dma_mem: memory@60000000 {
92			compatible = "shared-dma-pool";
93			reg = <0 0x60000000 0 0x1100000>;
94			no-map;
95		};
96
97		apu_mem: memory@62000000 {
98			compatible = "shared-dma-pool";
99			reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
100		};
101	};
102};
103
104&eth {
105	phy-mode = "rgmii-id";
106	phy-handle = <&ethernet_phy0>;
107	snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
108	snps,reset-delays-us = <0 10000 80000>;
109	pinctrl-names = "default", "sleep";
110	pinctrl-0 = <&eth_default_pins>;
111	pinctrl-1 = <&eth_sleep_pins>;
112	status = "okay";
113
114	mdio {
115		ethernet_phy0: ethernet-phy@1 {
116			reg = <0x1>;
117		};
118	};
119};
120
121&i2c6 {
122	clock-frequency = <400000>;
123	pinctrl-0 = <&i2c6_pins>;
124	pinctrl-names = "default";
125	status = "okay";
126
127	mt6360: pmic@34 {
128		compatible = "mediatek,mt6360";
129		reg = <0x34>;
130		interrupt-controller;
131		interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
132		interrupt-names = "IRQB";
133
134		charger {
135			compatible = "mediatek,mt6360-chg";
136			richtek,vinovp-microvolt = <14500000>;
137
138			otg_vbus_regulator: usb-otg-vbus-regulator {
139				regulator-compatible = "usb-otg-vbus";
140				regulator-name = "usb-otg-vbus";
141				regulator-min-microvolt = <4425000>;
142				regulator-max-microvolt = <5825000>;
143			};
144		};
145
146		regulator {
147			compatible = "mediatek,mt6360-regulator";
148			LDO_VIN3-supply = <&mt6360_buck2>;
149
150			mt6360_buck1: buck1 {
151				regulator-compatible = "BUCK1";
152				regulator-name = "mt6360,buck1";
153				regulator-min-microvolt = <300000>;
154				regulator-max-microvolt = <1300000>;
155				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
156							   MT6360_OPMODE_LP
157							   MT6360_OPMODE_ULP>;
158				regulator-always-on;
159			};
160
161			mt6360_buck2: buck2 {
162				regulator-compatible = "BUCK2";
163				regulator-name = "mt6360,buck2";
164				regulator-min-microvolt = <300000>;
165				regulator-max-microvolt = <1300000>;
166				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
167							   MT6360_OPMODE_LP
168							   MT6360_OPMODE_ULP>;
169				regulator-always-on;
170			};
171
172			mt6360_ldo1: ldo1 {
173				regulator-compatible = "LDO1";
174				regulator-name = "mt6360,ldo1";
175				regulator-min-microvolt = <1200000>;
176				regulator-max-microvolt = <3600000>;
177				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
178							   MT6360_OPMODE_LP>;
179			};
180
181			mt6360_ldo2: ldo2 {
182				regulator-compatible = "LDO2";
183				regulator-name = "mt6360,ldo2";
184				regulator-min-microvolt = <1200000>;
185				regulator-max-microvolt = <3600000>;
186				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
187							   MT6360_OPMODE_LP>;
188			};
189
190			mt6360_ldo3: ldo3 {
191				regulator-compatible = "LDO3";
192				regulator-name = "mt6360,ldo3";
193				regulator-min-microvolt = <1200000>;
194				regulator-max-microvolt = <3600000>;
195				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
196							   MT6360_OPMODE_LP>;
197			};
198
199			mt6360_ldo5: ldo5 {
200				regulator-compatible = "LDO5";
201				regulator-name = "mt6360,ldo5";
202				regulator-min-microvolt = <2700000>;
203				regulator-max-microvolt = <3600000>;
204				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
205							   MT6360_OPMODE_LP>;
206			};
207
208			mt6360_ldo6: ldo6 {
209				regulator-compatible = "LDO6";
210				regulator-name = "mt6360,ldo6";
211				regulator-min-microvolt = <500000>;
212				regulator-max-microvolt = <2100000>;
213				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
214							   MT6360_OPMODE_LP>;
215			};
216
217			mt6360_ldo7: ldo7 {
218				regulator-compatible = "LDO7";
219				regulator-name = "mt6360,ldo7";
220				regulator-min-microvolt = <500000>;
221				regulator-max-microvolt = <2100000>;
222				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
223							   MT6360_OPMODE_LP>;
224				regulator-always-on;
225			};
226		};
227	};
228};
229
230&mmc0 {
231	status = "okay";
232	pinctrl-names = "default", "state_uhs";
233	pinctrl-0 = <&mmc0_default_pins>;
234	pinctrl-1 = <&mmc0_uhs_pins>;
235	bus-width = <8>;
236	max-frequency = <200000000>;
237	cap-mmc-highspeed;
238	mmc-hs200-1_8v;
239	mmc-hs400-1_8v;
240	cap-mmc-hw-reset;
241	no-sdio;
242	no-sd;
243	hs400-ds-delay = <0x14c11>;
244	vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
245	vqmmc-supply = <&mt6359_vufs_ldo_reg>;
246	non-removable;
247};
248
249&mmc1 {
250	pinctrl-names = "default", "state_uhs";
251	pinctrl-0 = <&mmc1_default_pins>;
252	pinctrl-1 = <&mmc1_uhs_pins>;
253	cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
254	bus-width = <4>;
255	max-frequency = <200000000>;
256	cap-sd-highspeed;
257	sd-uhs-sdr50;
258	sd-uhs-sdr104;
259	vmmc-supply = <&mt6360_ldo5>;
260	vqmmc-supply = <&mt6360_ldo3>;
261	status = "okay";
262};
263
264&mt6359_vbbck_ldo_reg {
265	regulator-always-on;
266};
267
268&mt6359_vcore_buck_reg {
269	regulator-always-on;
270};
271
272&mt6359_vgpu11_buck_reg {
273	regulator-always-on;
274};
275
276&mt6359_vproc1_buck_reg {
277	regulator-always-on;
278};
279
280&mt6359_vproc2_buck_reg {
281	regulator-always-on;
282};
283
284&mt6359_vpu_buck_reg {
285	regulator-always-on;
286};
287
288&mt6359_vrf12_ldo_reg {
289	regulator-always-on;
290};
291
292&mt6359_vsram_md_ldo_reg {
293	regulator-always-on;
294};
295
296&mt6359_vsram_others_ldo_reg {
297	regulator-always-on;
298};
299
300&pio {
301	eth_default_pins: eth-default-pins {
302		pins-txd {
303			pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
304				 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
305				 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
306				 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
307			drive-strength = <MTK_DRIVE_8mA>;
308		};
309		pins-cc {
310			pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
311				 <PINMUX_GPIO88__FUNC_GBE_TXEN>,
312				 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
313				 <PINMUX_GPIO86__FUNC_GBE_RXC>;
314			drive-strength = <MTK_DRIVE_8mA>;
315		};
316		pins-rxd {
317			pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
318				 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
319				 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
320				 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
321		};
322		pins-mdio {
323			pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
324				 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
325			input-enable;
326		};
327		pins-power {
328			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
329				 <PINMUX_GPIO92__FUNC_GPIO92>;
330			output-high;
331		};
332	};
333
334	eth_sleep_pins: eth-sleep-pins {
335		pins-txd {
336			pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
337				 <PINMUX_GPIO78__FUNC_GPIO78>,
338				 <PINMUX_GPIO79__FUNC_GPIO79>,
339				 <PINMUX_GPIO80__FUNC_GPIO80>;
340		};
341		pins-cc {
342			pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
343				 <PINMUX_GPIO88__FUNC_GPIO88>,
344				 <PINMUX_GPIO87__FUNC_GPIO87>,
345				 <PINMUX_GPIO86__FUNC_GPIO86>;
346		};
347		pins-rxd {
348			pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
349				 <PINMUX_GPIO82__FUNC_GPIO82>,
350				 <PINMUX_GPIO83__FUNC_GPIO83>,
351				 <PINMUX_GPIO84__FUNC_GPIO84>;
352		};
353		pins-mdio {
354			pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
355				 <PINMUX_GPIO90__FUNC_GPIO90>;
356			input-disable;
357			bias-disable;
358		};
359	};
360
361	gpio_keys_pins: gpio-keys-pins {
362		pins {
363			pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
364			input-enable;
365		};
366	};
367
368	i2c6_pins: i2c6-pins {
369		pins {
370			pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
371				 <PINMUX_GPIO26__FUNC_SCL6>;
372			bias-pull-up;
373		};
374	};
375
376	mmc0_default_pins: mmc0-default-pins {
377		pins-clk {
378			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
379			drive-strength = <MTK_DRIVE_6mA>;
380			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
381		};
382
383		pins-cmd-dat {
384			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
385				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
386				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
387				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
388				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
389				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
390				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
391				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
392				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
393			input-enable;
394			drive-strength = <MTK_DRIVE_6mA>;
395			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
396		};
397
398		pins-rst {
399			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
400			drive-strength = <MTK_DRIVE_6mA>;
401			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
402		};
403	};
404
405	mmc0_uhs_pins: mmc0-uhs-pins {
406		pins-clk {
407			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
408			drive-strength = <MTK_DRIVE_8mA>;
409			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
410		};
411
412		pins-cmd-dat {
413			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
414				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
415				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
416				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
417				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
418				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
419				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
420				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
421				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
422			input-enable;
423			drive-strength = <MTK_DRIVE_8mA>;
424			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
425		};
426
427		pins-ds {
428			pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
429			drive-strength = <MTK_DRIVE_8mA>;
430			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
431		};
432
433		pins-rst {
434			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
435			drive-strength = <MTK_DRIVE_8mA>;
436			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
437		};
438	};
439
440	mmc1_default_pins: mmc1-default-pins {
441		pins-clk {
442			pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
443			drive-strength = <MTK_DRIVE_8mA>;
444			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
445		};
446
447		pins-cmd-dat {
448			pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
449				 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
450				 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
451				 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
452				 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
453			input-enable;
454			drive-strength = <MTK_DRIVE_8mA>;
455			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
456		};
457
458		pins-insert {
459			pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
460			bias-pull-up;
461		};
462	};
463
464	mmc1_uhs_pins: mmc1-uhs-pins {
465		pins-clk {
466			pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
467			drive-strength = <MTK_DRIVE_8mA>;
468			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
469		};
470
471		pins-cmd-dat {
472			pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
473				 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
474				 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
475				 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
476				 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
477			input-enable;
478			drive-strength = <MTK_DRIVE_8mA>;
479			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
480		};
481	};
482
483	uart0_pins: uart0-pins {
484		pins {
485			pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
486				 <PINMUX_GPIO99__FUNC_URXD0>;
487		};
488	};
489
490	uart1_pins: uart1-pins {
491		pins {
492			pinmux = <PINMUX_GPIO102__FUNC_UTXD1>,
493				 <PINMUX_GPIO103__FUNC_URXD1>;
494		};
495	};
496};
497
498
499&pmic {
500	interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
501};
502
503&uart0 {
504	pinctrl-names = "default";
505	pinctrl-0 = <&uart0_pins>;
506	status = "okay";
507};
508
509&uart1 {
510	pinctrl-names = "default";
511	pinctrl-0 = <&uart1_pins>;
512	status = "okay";
513};
514
515&u3phy0 {
516	status = "okay";
517};
518
519&u3phy1 {
520	status = "okay";
521};
522
523&u3phy2 {
524	status = "okay";
525};
526
527&u3phy3 {
528	status = "okay";
529};
530
531&xhci0 {
532	vusb33-supply = <&mt6359_vusb_ldo_reg>;
533	vbus-supply = <&otg_vbus_regulator>;
534	status = "okay";
535};
536
537&xhci1 {
538	vusb33-supply = <&mt6359_vusb_ldo_reg>;
539	status = "okay";
540};
541
542&xhci2 {
543	vusb33-supply = <&mt6359_vusb_ldo_reg>;
544	status = "okay";
545};
546
547&xhci3 {
548	vusb33-supply = <&mt6359_vusb_ldo_reg>;
549	status = "okay";
550};
551