xref: /linux/arch/arm64/boot/dts/mediatek/mt8195-demo.dts (revision 0526b56cbc3c489642bd6a5fe4b718dea7ef0ee8) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2022 BayLibre, SAS.
4 * Author: Fabien Parent <fparent@baylibre.com>
5 */
6/dts-v1/;
7
8#include "mt8195.dtsi"
9#include "mt6359.dtsi"
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
14#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
15
16/ {
17	model = "MediaTek MT8195 demo board";
18	compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
19
20	aliases {
21		serial0 = &uart0;
22	};
23
24	chosen {
25		stdout-path = "serial0:921600n8";
26	};
27
28	firmware {
29		optee {
30			compatible = "linaro,optee-tz";
31			method = "smc";
32		};
33	};
34
35	gpio-keys {
36		compatible = "gpio-keys";
37		pinctrl-names = "default";
38		pinctrl-0 = <&gpio_keys_pins>;
39
40		key-0 {
41			gpios = <&pio 106 GPIO_ACTIVE_LOW>;
42			label = "volume_up";
43			linux,code = <KEY_VOLUMEUP>;
44			wakeup-source;
45			debounce-interval = <15>;
46		};
47	};
48
49	memory@40000000 {
50		device_type = "memory";
51		reg = <0 0x40000000 0 0x80000000>;
52	};
53
54	reserved-memory {
55		#address-cells = <2>;
56		#size-cells = <2>;
57		ranges;
58
59		/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
60		bl31_secmon_reserved: secmon@54600000 {
61			no-map;
62			reg = <0 0x54600000 0x0 0x200000>;
63		};
64
65		/* 12 MiB reserved for OP-TEE (BL32)
66		 * +-----------------------+ 0x43e0_0000
67		 * |      SHMEM 2MiB       |
68		 * +-----------------------+ 0x43c0_0000
69		 * |        | TA_RAM  8MiB |
70		 * + TZDRAM +--------------+ 0x4340_0000
71		 * |        | TEE_RAM 2MiB |
72		 * +-----------------------+ 0x4320_0000
73		 */
74		optee_reserved: optee@43200000 {
75			no-map;
76			reg = <0 0x43200000 0 0x00c00000>;
77		};
78	};
79};
80
81&eth {
82	phy-mode ="rgmii-id";
83	phy-handle = <&ethernet_phy0>;
84	snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
85	snps,reset-delays-us = <0 10000 80000>;
86	pinctrl-names = "default", "sleep";
87	pinctrl-0 = <&eth_default_pins>;
88	pinctrl-1 = <&eth_sleep_pins>;
89	status = "okay";
90
91	mdio {
92		ethernet_phy0: ethernet-phy@1 {
93			reg = <0x1>;
94		};
95	};
96};
97
98&i2c6 {
99	clock-frequency = <400000>;
100	pinctrl-0 = <&i2c6_pins>;
101	pinctrl-names = "default";
102	status = "okay";
103
104	mt6360: pmic@34 {
105		compatible = "mediatek,mt6360";
106		reg = <0x34>;
107		interrupt-controller;
108		interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
109		interrupt-names = "IRQB";
110
111		charger {
112			compatible = "mediatek,mt6360-chg";
113			richtek,vinovp-microvolt = <14500000>;
114
115			otg_vbus_regulator: usb-otg-vbus-regulator {
116				regulator-compatible = "usb-otg-vbus";
117				regulator-name = "usb-otg-vbus";
118				regulator-min-microvolt = <4425000>;
119				regulator-max-microvolt = <5825000>;
120			};
121		};
122
123		regulator {
124			compatible = "mediatek,mt6360-regulator";
125			LDO_VIN3-supply = <&mt6360_buck2>;
126
127			mt6360_buck1: buck1 {
128				regulator-compatible = "BUCK1";
129				regulator-name = "mt6360,buck1";
130				regulator-min-microvolt = <300000>;
131				regulator-max-microvolt = <1300000>;
132				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
133							   MT6360_OPMODE_LP
134							   MT6360_OPMODE_ULP>;
135				regulator-always-on;
136			};
137
138			mt6360_buck2: buck2 {
139				regulator-compatible = "BUCK2";
140				regulator-name = "mt6360,buck2";
141				regulator-min-microvolt = <300000>;
142				regulator-max-microvolt = <1300000>;
143				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
144							   MT6360_OPMODE_LP
145							   MT6360_OPMODE_ULP>;
146				regulator-always-on;
147			};
148
149			mt6360_ldo1: ldo1 {
150				regulator-compatible = "LDO1";
151				regulator-name = "mt6360,ldo1";
152				regulator-min-microvolt = <1200000>;
153				regulator-max-microvolt = <3600000>;
154				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
155							   MT6360_OPMODE_LP>;
156			};
157
158			mt6360_ldo2: ldo2 {
159				regulator-compatible = "LDO2";
160				regulator-name = "mt6360,ldo2";
161				regulator-min-microvolt = <1200000>;
162				regulator-max-microvolt = <3600000>;
163				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
164							   MT6360_OPMODE_LP>;
165			};
166
167			mt6360_ldo3: ldo3 {
168				regulator-compatible = "LDO3";
169				regulator-name = "mt6360,ldo3";
170				regulator-min-microvolt = <1200000>;
171				regulator-max-microvolt = <3600000>;
172				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
173							   MT6360_OPMODE_LP>;
174			};
175
176			mt6360_ldo5: ldo5 {
177				regulator-compatible = "LDO5";
178				regulator-name = "mt6360,ldo5";
179				regulator-min-microvolt = <2700000>;
180				regulator-max-microvolt = <3600000>;
181				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
182							   MT6360_OPMODE_LP>;
183			};
184
185			mt6360_ldo6: ldo6 {
186				regulator-compatible = "LDO6";
187				regulator-name = "mt6360,ldo6";
188				regulator-min-microvolt = <500000>;
189				regulator-max-microvolt = <2100000>;
190				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
191							   MT6360_OPMODE_LP>;
192			};
193
194			mt6360_ldo7: ldo7 {
195				regulator-compatible = "LDO7";
196				regulator-name = "mt6360,ldo7";
197				regulator-min-microvolt = <500000>;
198				regulator-max-microvolt = <2100000>;
199				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
200							   MT6360_OPMODE_LP>;
201				regulator-always-on;
202			};
203		};
204	};
205};
206
207&mmc0 {
208	status = "okay";
209	pinctrl-names = "default", "state_uhs";
210	pinctrl-0 = <&mmc0_default_pins>;
211	pinctrl-1 = <&mmc0_uhs_pins>;
212	bus-width = <8>;
213	max-frequency = <200000000>;
214	cap-mmc-highspeed;
215	mmc-hs200-1_8v;
216	mmc-hs400-1_8v;
217	cap-mmc-hw-reset;
218	no-sdio;
219	no-sd;
220	hs400-ds-delay = <0x14c11>;
221	vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
222	vqmmc-supply = <&mt6359_vufs_ldo_reg>;
223	non-removable;
224};
225
226&mmc1 {
227	pinctrl-names = "default", "state_uhs";
228	pinctrl-0 = <&mmc1_default_pins>;
229	pinctrl-1 = <&mmc1_uhs_pins>;
230	cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
231	bus-width = <4>;
232	max-frequency = <200000000>;
233	cap-sd-highspeed;
234	sd-uhs-sdr50;
235	sd-uhs-sdr104;
236	vmmc-supply = <&mt6360_ldo5>;
237	vqmmc-supply = <&mt6360_ldo3>;
238	status = "okay";
239};
240
241&mt6359_vbbck_ldo_reg {
242	regulator-always-on;
243};
244
245&mt6359_vcore_buck_reg {
246	regulator-always-on;
247};
248
249&mt6359_vgpu11_buck_reg {
250	regulator-always-on;
251};
252
253&mt6359_vproc1_buck_reg {
254	regulator-always-on;
255};
256
257&mt6359_vproc2_buck_reg {
258	regulator-always-on;
259};
260
261&mt6359_vpu_buck_reg {
262	regulator-always-on;
263};
264
265&mt6359_vrf12_ldo_reg {
266	regulator-always-on;
267};
268
269&mt6359_vsram_md_ldo_reg {
270	regulator-always-on;
271};
272
273&mt6359_vsram_others_ldo_reg {
274	regulator-always-on;
275};
276
277&pio {
278	eth_default_pins: eth-default-pins {
279		pins-txd {
280			pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
281				 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
282				 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
283				 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
284			drive-strength = <MTK_DRIVE_8mA>;
285		};
286		pins-cc {
287			pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
288				 <PINMUX_GPIO88__FUNC_GBE_TXEN>,
289				 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
290				 <PINMUX_GPIO86__FUNC_GBE_RXC>;
291			drive-strength = <MTK_DRIVE_8mA>;
292		};
293		pins-rxd {
294			pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
295				 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
296				 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
297				 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
298		};
299		pins-mdio {
300			pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
301				 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
302			input-enable;
303		};
304		pins-power {
305			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
306				 <PINMUX_GPIO92__FUNC_GPIO92>;
307			output-high;
308		};
309	};
310
311	eth_sleep_pins: eth-sleep-pins {
312		pins-txd {
313			pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
314				 <PINMUX_GPIO78__FUNC_GPIO78>,
315				 <PINMUX_GPIO79__FUNC_GPIO79>,
316				 <PINMUX_GPIO80__FUNC_GPIO80>;
317		};
318		pins-cc {
319			pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
320				 <PINMUX_GPIO88__FUNC_GPIO88>,
321				 <PINMUX_GPIO87__FUNC_GPIO87>,
322				 <PINMUX_GPIO86__FUNC_GPIO86>;
323		};
324		pins-rxd {
325			pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
326				 <PINMUX_GPIO82__FUNC_GPIO82>,
327				 <PINMUX_GPIO83__FUNC_GPIO83>,
328				 <PINMUX_GPIO84__FUNC_GPIO84>;
329		};
330		pins-mdio {
331			pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
332				 <PINMUX_GPIO90__FUNC_GPIO90>;
333			input-disable;
334			bias-disable;
335		};
336	};
337
338	gpio_keys_pins: gpio-keys-pins {
339		pins {
340			pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
341			input-enable;
342		};
343	};
344
345	i2c6_pins: i2c6-pins {
346		pins {
347			pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
348				 <PINMUX_GPIO26__FUNC_SCL6>;
349			bias-pull-up;
350		};
351	};
352
353	mmc0_default_pins: mmc0-default-pins {
354		pins-clk {
355			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
356			drive-strength = <MTK_DRIVE_6mA>;
357			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
358		};
359
360		pins-cmd-dat {
361			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
362				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
363				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
364				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
365				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
366				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
367				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
368				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
369				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
370			input-enable;
371			drive-strength = <MTK_DRIVE_6mA>;
372			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
373		};
374
375		pins-rst {
376			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
377			drive-strength = <MTK_DRIVE_6mA>;
378			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
379		};
380	};
381
382	mmc0_uhs_pins: mmc0-uhs-pins {
383		pins-clk {
384			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
385			drive-strength = <MTK_DRIVE_8mA>;
386			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
387		};
388
389		pins-cmd-dat {
390			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
391				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
392				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
393				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
394				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
395				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
396				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
397				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
398				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
399			input-enable;
400			drive-strength = <MTK_DRIVE_8mA>;
401			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
402		};
403
404		pins-ds {
405			pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
406			drive-strength = <MTK_DRIVE_8mA>;
407			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
408		};
409
410		pins-rst {
411			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
412			drive-strength = <MTK_DRIVE_8mA>;
413			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
414		};
415	};
416
417	mmc1_default_pins: mmc1-default-pins {
418		pins-clk {
419			pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
420			drive-strength = <MTK_DRIVE_8mA>;
421			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
422		};
423
424		pins-cmd-dat {
425			pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
426				 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
427				 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
428				 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
429				 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
430			input-enable;
431			drive-strength = <MTK_DRIVE_8mA>;
432			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
433		};
434
435		pins-insert {
436			pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
437			bias-pull-up;
438		};
439	};
440
441	mmc1_uhs_pins: mmc1-uhs-pins {
442		pins-clk {
443			pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
444			drive-strength = <MTK_DRIVE_8mA>;
445			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
446		};
447
448		pins-cmd-dat {
449			pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
450				 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
451				 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
452				 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
453				 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
454			input-enable;
455			drive-strength = <MTK_DRIVE_8mA>;
456			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
457		};
458	};
459
460	uart0_pins: uart0-pins {
461		pins {
462			pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
463				 <PINMUX_GPIO99__FUNC_URXD0>;
464		};
465	};
466
467	uart1_pins: uart1-pins {
468		pins {
469			pinmux = <PINMUX_GPIO102__FUNC_UTXD1>,
470				 <PINMUX_GPIO103__FUNC_URXD1>;
471		};
472	};
473};
474
475
476&pmic {
477	interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
478};
479
480&uart0 {
481	pinctrl-names = "default";
482	pinctrl-0 = <&uart0_pins>;
483	status = "okay";
484};
485
486&uart1 {
487	pinctrl-names = "default";
488	pinctrl-0 = <&uart1_pins>;
489	status = "okay";
490};
491
492&u3phy0 {
493	status = "okay";
494};
495
496&u3phy1 {
497	status = "okay";
498};
499
500&u3phy2 {
501	status = "okay";
502};
503
504&u3phy3 {
505	status = "okay";
506};
507
508&xhci0 {
509	vusb33-supply = <&mt6359_vusb_ldo_reg>;
510	vbus-supply = <&otg_vbus_regulator>;
511	status = "okay";
512};
513
514&xhci1 {
515	vusb33-supply = <&mt6359_vusb_ldo_reg>;
516	status = "okay";
517};
518
519&xhci2 {
520	vusb33-supply = <&mt6359_vusb_ldo_reg>;
521	status = "okay";
522};
523
524&xhci3 {
525	vusb33-supply = <&mt6359_vusb_ldo_reg>;
526	status = "okay";
527};
528