1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/spmi/spmi.h> 8#include "mt8195.dtsi" 9#include "mt6359.dtsi" 10 11/ { 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c7 = &i2c7; 20 mmc0 = &mmc0; 21 mmc1 = &mmc1; 22 serial0 = &uart0; 23 }; 24 25 backlight_lcd0: backlight-lcd0 { 26 compatible = "pwm-backlight"; 27 brightness-levels = <0 1023>; 28 default-brightness-level = <576>; 29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>; 30 num-interpolated-steps = <1023>; 31 pwms = <&disp_pwm0 0 500000>; 32 power-supply = <&ppvar_sys>; 33 }; 34 35 chosen { 36 stdout-path = "serial0:115200n8"; 37 }; 38 39 dmic-codec { 40 compatible = "dmic-codec"; 41 num-channels = <2>; 42 wakeup-delay-ms = <50>; 43 }; 44 45 memory@40000000 { 46 device_type = "memory"; 47 reg = <0 0x40000000 0 0x80000000>; 48 }; 49 50 pp3300_disp_x: regulator-pp3300-disp-x { 51 compatible = "regulator-fixed"; 52 regulator-name = "pp3300_disp_x"; 53 regulator-min-microvolt = <3300000>; 54 regulator-max-microvolt = <3300000>; 55 regulator-enable-ramp-delay = <2500>; 56 enable-active-high; 57 gpio = <&pio 55 GPIO_ACTIVE_HIGH>; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&panel_fixed_pins>; 60 vin-supply = <&pp3300_z2>; 61 }; 62 63 /* system wide LDO 3.3V power rail */ 64 pp3300_z5: regulator-pp3300-ldo-z5 { 65 compatible = "regulator-fixed"; 66 regulator-name = "pp3300_ldo_z5"; 67 regulator-always-on; 68 regulator-boot-on; 69 regulator-min-microvolt = <3300000>; 70 regulator-max-microvolt = <3300000>; 71 vin-supply = <&ppvar_sys>; 72 }; 73 74 /* separately switched 3.3V power rail */ 75 pp3300_s3: regulator-pp3300-s3 { 76 compatible = "regulator-fixed"; 77 regulator-name = "pp3300_s3"; 78 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 79 regulator-always-on; 80 regulator-boot-on; 81 regulator-min-microvolt = <3300000>; 82 regulator-max-microvolt = <3300000>; 83 vin-supply = <&pp3300_z2>; 84 }; 85 86 /* system wide 3.3V power rail */ 87 pp3300_z2: regulator-pp3300-z2 { 88 compatible = "regulator-fixed"; 89 regulator-name = "pp3300_z2"; 90 /* EN pin tied to pp4200_z2, which is controlled by EC */ 91 regulator-always-on; 92 regulator-boot-on; 93 regulator-min-microvolt = <3300000>; 94 regulator-max-microvolt = <3300000>; 95 vin-supply = <&ppvar_sys>; 96 }; 97 98 /* system wide 4.2V power rail */ 99 pp4200_z2: regulator-pp4200-z2 { 100 compatible = "regulator-fixed"; 101 regulator-name = "pp4200_z2"; 102 /* controlled by EC */ 103 regulator-always-on; 104 regulator-boot-on; 105 regulator-min-microvolt = <4200000>; 106 regulator-max-microvolt = <4200000>; 107 vin-supply = <&ppvar_sys>; 108 }; 109 110 /* system wide switching 5.0V power rail */ 111 pp5000_s5: regulator-pp5000-s5 { 112 compatible = "regulator-fixed"; 113 regulator-name = "pp5000_s5"; 114 /* controlled by EC */ 115 regulator-always-on; 116 regulator-boot-on; 117 regulator-min-microvolt = <5000000>; 118 regulator-max-microvolt = <5000000>; 119 vin-supply = <&ppvar_sys>; 120 }; 121 122 /* system wide semi-regulated power rail from battery or USB */ 123 ppvar_sys: regulator-ppvar-sys { 124 compatible = "regulator-fixed"; 125 regulator-name = "ppvar_sys"; 126 regulator-always-on; 127 regulator-boot-on; 128 }; 129 130 /* Murata NCP03WF104F05RL */ 131 tboard_thermistor1: thermal-sensor-t1 { 132 compatible = "generic-adc-thermal"; 133 #thermal-sensor-cells = <0>; 134 io-channels = <&auxadc 0>; 135 io-channel-names = "sensor-channel"; 136 temperature-lookup-table = < (-10000) 1553 137 (-5000) 1485 138 0 1406 139 5000 1317 140 10000 1219 141 15000 1115 142 20000 1007 143 25000 900 144 30000 796 145 35000 697 146 40000 605 147 45000 523 148 50000 449 149 55000 384 150 60000 327 151 65000 279 152 70000 237 153 75000 202 154 80000 172 155 85000 147 156 90000 125 157 95000 107 158 100000 92 159 105000 79 160 110000 68 161 115000 59 162 120000 51 163 125000 44>; 164 }; 165 166 tboard_thermistor2: thermal-sensor-t2 { 167 compatible = "generic-adc-thermal"; 168 #thermal-sensor-cells = <0>; 169 io-channels = <&auxadc 1>; 170 io-channel-names = "sensor-channel"; 171 temperature-lookup-table = < (-10000) 1553 172 (-5000) 1485 173 0 1406 174 5000 1317 175 10000 1219 176 15000 1115 177 20000 1007 178 25000 900 179 30000 796 180 35000 697 181 40000 605 182 45000 523 183 50000 449 184 55000 384 185 60000 327 186 65000 279 187 70000 237 188 75000 202 189 80000 172 190 85000 147 191 90000 125 192 95000 107 193 100000 92 194 105000 79 195 110000 68 196 115000 59 197 120000 51 198 125000 44>; 199 }; 200 201 usb_vbus: regulator-5v0-usb-vbus { 202 compatible = "regulator-fixed"; 203 regulator-name = "usb-vbus"; 204 regulator-min-microvolt = <5000000>; 205 regulator-max-microvolt = <5000000>; 206 enable-active-high; 207 regulator-always-on; 208 }; 209 210 reserved_memory: reserved-memory { 211 #address-cells = <2>; 212 #size-cells = <2>; 213 ranges; 214 215 scp_mem: memory@50000000 { 216 compatible = "shared-dma-pool"; 217 reg = <0 0x50000000 0 0x2900000>; 218 no-map; 219 }; 220 221 adsp_mem: memory@60000000 { 222 compatible = "shared-dma-pool"; 223 reg = <0 0x60000000 0 0xd80000>; 224 no-map; 225 }; 226 227 afe_mem: memory@60d80000 { 228 compatible = "shared-dma-pool"; 229 reg = <0 0x60d80000 0 0x100000>; 230 no-map; 231 }; 232 233 adsp_device_mem: memory@60e80000 { 234 compatible = "shared-dma-pool"; 235 reg = <0 0x60e80000 0 0x280000>; 236 no-map; 237 }; 238 }; 239 240 spk_amplifier: rt1019p { 241 compatible = "realtek,rt1019p"; 242 label = "rt1019p"; 243 #sound-dai-cells = <0>; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&rt1019p_pins_default>; 246 sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>; 247 }; 248}; 249 250&adsp { 251 status = "okay"; 252 253 memory-region = <&adsp_device_mem>, <&adsp_mem>; 254}; 255 256&afe { 257 status = "okay"; 258 259 mediatek,etdm-in2-cowork-source = <2>; 260 mediatek,etdm-out2-cowork-source = <0>; 261 memory-region = <&afe_mem>; 262}; 263 264&auxadc { 265 status = "okay"; 266}; 267 268&cpu0 { 269 cpu-supply = <&mt6359_vcore_buck_reg>; 270}; 271 272&cpu1 { 273 cpu-supply = <&mt6359_vcore_buck_reg>; 274}; 275 276&cpu2 { 277 cpu-supply = <&mt6359_vcore_buck_reg>; 278}; 279 280&cpu3 { 281 cpu-supply = <&mt6359_vcore_buck_reg>; 282}; 283 284&cpu4 { 285 cpu-supply = <&mt6315_6_vbuck1>; 286}; 287 288&cpu5 { 289 cpu-supply = <&mt6315_6_vbuck1>; 290}; 291 292&cpu6 { 293 cpu-supply = <&mt6315_6_vbuck1>; 294}; 295 296&cpu7 { 297 cpu-supply = <&mt6315_6_vbuck1>; 298}; 299 300&dither0_out { 301 remote-endpoint = <&dsc0_in>; 302}; 303 304&dp_intf0 { 305 status = "okay"; 306 307 ports { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 311 port@0 { 312 reg = <0>; 313 dp_intf0_in: endpoint { 314 remote-endpoint = <&merge0_out>; 315 }; 316 }; 317 318 port@1 { 319 reg = <1>; 320 dp_intf0_out: endpoint { 321 remote-endpoint = <&edp_in>; 322 }; 323 }; 324 }; 325}; 326 327&dp_intf1 { 328 status = "okay"; 329 330 ports { 331 #address-cells = <1>; 332 #size-cells = <0>; 333 334 port@0 { 335 #address-cells = <1>; 336 #size-cells = <0>; 337 reg = <0>; 338 339 dp_intf1_in: endpoint@1 { 340 reg = <1>; 341 remote-endpoint = <&merge5_out>; 342 }; 343 }; 344 345 port@1 { 346 #address-cells = <1>; 347 #size-cells = <0>; 348 reg = <1>; 349 350 dp_intf1_out: endpoint@1 { 351 reg = <1>; 352 remote-endpoint = <&dptx_in>; 353 }; 354 }; 355 }; 356}; 357 358&dsc0 { 359 ports { 360 #address-cells = <1>; 361 #size-cells = <0>; 362 363 port@0 { 364 reg = <0>; 365 dsc0_in: endpoint { 366 remote-endpoint = <&dither0_out>; 367 }; 368 }; 369 370 port@1 { 371 reg = <1>; 372 dsc0_out: endpoint { 373 remote-endpoint = <&merge0_in>; 374 }; 375 }; 376 }; 377}; 378 379&edp_tx { 380 status = "okay"; 381 382 pinctrl-names = "default"; 383 pinctrl-0 = <&edptx_pins_default>; 384 385 ports { 386 #address-cells = <1>; 387 #size-cells = <0>; 388 389 port@0 { 390 reg = <0>; 391 edp_in: endpoint { 392 remote-endpoint = <&dp_intf0_out>; 393 }; 394 }; 395 396 port@1 { 397 reg = <1>; 398 edp_out: endpoint { 399 data-lanes = <0 1 2 3>; 400 remote-endpoint = <&panel_in>; 401 }; 402 }; 403 }; 404 405 aux-bus { 406 panel { 407 compatible = "edp-panel"; 408 power-supply = <&pp3300_disp_x>; 409 backlight = <&backlight_lcd0>; 410 port { 411 panel_in: endpoint { 412 remote-endpoint = <&edp_out>; 413 }; 414 }; 415 }; 416 }; 417}; 418 419ðdr0 { 420 ports { 421 #address-cells = <1>; 422 #size-cells = <0>; 423 424 port@0 { 425 #address-cells = <1>; 426 #size-cells = <0>; 427 reg = <0>; 428 429 ethdr0_in: endpoint@1 { 430 reg = <1>; 431 remote-endpoint = <&vdosys1_ep_ext>; 432 }; 433 }; 434 435 port@1 { 436 #address-cells = <1>; 437 #size-cells = <0>; 438 reg = <1>; 439 440 ethdr0_out: endpoint@1 { 441 reg = <1>; 442 remote-endpoint = <&merge5_in>; 443 }; 444 }; 445 }; 446}; 447 448&disp_pwm0 { 449 status = "okay"; 450 451 pinctrl-names = "default"; 452 pinctrl-0 = <&disp_pwm0_pin_default>; 453}; 454 455&dp_tx { 456 status = "okay"; 457 458 #sound-dai-cells = <0>; 459 pinctrl-names = "default"; 460 pinctrl-0 = <&dptx_pin>; 461 462 ports { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 466 port@0 { 467 #address-cells = <1>; 468 #size-cells = <0>; 469 reg = <0>; 470 471 dptx_in: endpoint@1 { 472 reg = <1>; 473 remote-endpoint = <&dp_intf1_out>; 474 }; 475 }; 476 477 port@1 { 478 reg = <1>; 479 dptx_out: endpoint { 480 data-lanes = <0 1 2 3>; 481 }; 482 }; 483 }; 484}; 485 486&gic { 487 mediatek,broken-save-restore-fw; 488}; 489 490&gpu { 491 status = "okay"; 492 mali-supply = <&mt6315_7_vbuck1>; 493}; 494 495&i2c0 { 496 status = "okay"; 497 498 clock-frequency = <400000>; 499 pinctrl-names = "default"; 500 pinctrl-0 = <&i2c0_pins>; 501}; 502 503&i2c1 { 504 status = "okay"; 505 506 clock-frequency = <400000>; 507 i2c-scl-internal-delay-ns = <12500>; 508 pinctrl-names = "default"; 509 pinctrl-0 = <&i2c1_pins>; 510 511 trackpad@15 { 512 compatible = "elan,ekth3000"; 513 reg = <0x15>; 514 interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&trackpad_pins>; 517 vcc-supply = <&pp3300_s3>; 518 wakeup-source; 519 }; 520}; 521 522&i2c2 { 523 status = "okay"; 524 525 clock-frequency = <400000>; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&i2c2_pins>; 528 529 audio_codec: codec@1a { 530 /* Realtek RT5682i or RT5682s, sharing the same configuration */ 531 reg = <0x1a>; 532 interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>; 533 #sound-dai-cells = <1>; 534 realtek,jd-src = <1>; 535 536 AVDD-supply = <&mt6359_vio18_ldo_reg>; 537 DBVDD-supply = <&mt6359_vio18_ldo_reg>; 538 MICVDD-supply = <&pp3300_z2>; 539 LDO1-IN-supply = <&mt6359_vio18_ldo_reg>; 540 }; 541}; 542 543&i2c3 { 544 status = "okay"; 545 546 clock-frequency = <400000>; 547 pinctrl-names = "default"; 548 pinctrl-0 = <&i2c3_pins>; 549 550 tpm@50 { 551 compatible = "google,cr50"; 552 reg = <0x50>; 553 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&cr50_int>; 556 }; 557}; 558 559&i2c4 { 560 status = "okay"; 561 562 clock-frequency = <400000>; 563 pinctrl-names = "default"; 564 pinctrl-0 = <&i2c4_pins>; 565 566 ts_10: touchscreen@10 { 567 compatible = "hid-over-i2c"; 568 reg = <0x10>; 569 hid-descr-addr = <0x0001>; 570 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; 571 pinctrl-names = "default"; 572 pinctrl-0 = <&touchscreen_pins>; 573 post-power-on-delay-ms = <10>; 574 vdd-supply = <&pp3300_s3>; 575 status = "disabled"; 576 }; 577}; 578 579&i2c5 { 580 status = "okay"; 581 582 clock-frequency = <400000>; 583 pinctrl-names = "default"; 584 pinctrl-0 = <&i2c5_pins>; 585}; 586 587&i2c7 { 588 status = "okay"; 589 590 clock-frequency = <400000>; 591 pinctrl-names = "default"; 592 pinctrl-0 = <&i2c7_pins>; 593 594 pmic@34 { 595 #interrupt-cells = <2>; 596 compatible = "mediatek,mt6360"; 597 reg = <0x34>; 598 interrupt-controller; 599 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; 600 interrupt-names = "IRQB"; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&subpmic_default>; 603 wakeup-source; 604 }; 605}; 606 607&merge0 { 608 ports { 609 #address-cells = <1>; 610 #size-cells = <0>; 611 612 port@0 { 613 reg = <0>; 614 merge0_in: endpoint { 615 remote-endpoint = <&dsc0_out>; 616 }; 617 }; 618 619 port@1 { 620 reg = <1>; 621 merge0_out: endpoint { 622 remote-endpoint = <&dp_intf0_in>; 623 }; 624 }; 625 }; 626}; 627 628&merge5 { 629 ports { 630 #address-cells = <1>; 631 #size-cells = <0>; 632 633 port@0 { 634 #address-cells = <1>; 635 #size-cells = <0>; 636 reg = <0>; 637 638 merge5_in: endpoint@1 { 639 reg = <1>; 640 remote-endpoint = <ðdr0_out>; 641 }; 642 }; 643 644 port@1 { 645 #address-cells = <1>; 646 #size-cells = <0>; 647 reg = <1>; 648 649 merge5_out: endpoint@1 { 650 reg = <1>; 651 remote-endpoint = <&dp_intf1_in>; 652 }; 653 }; 654 }; 655}; 656 657&mfg0 { 658 domain-supply = <&mt6315_7_vbuck1>; 659}; 660 661&mfg1 { 662 domain-supply = <&mt6359_vsram_others_ldo_reg>; 663}; 664 665&mmc0 { 666 status = "okay"; 667 668 bus-width = <8>; 669 cap-mmc-highspeed; 670 cap-mmc-hw-reset; 671 hs400-ds-delay = <0x14c11>; 672 max-frequency = <200000000>; 673 mmc-hs200-1_8v; 674 mmc-hs400-1_8v; 675 no-sdio; 676 no-sd; 677 non-removable; 678 pinctrl-names = "default", "state_uhs"; 679 pinctrl-0 = <&mmc0_pins_default>; 680 pinctrl-1 = <&mmc0_pins_uhs>; 681 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 682 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 683}; 684 685&mmc1 { 686 status = "okay"; 687 688 bus-width = <4>; 689 cap-sd-highspeed; 690 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 691 max-frequency = <200000000>; 692 no-mmc; 693 no-sdio; 694 pinctrl-names = "default", "state_uhs"; 695 pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>; 696 pinctrl-1 = <&mmc1_pins_default>; 697 sd-uhs-sdr50; 698 sd-uhs-sdr104; 699 vmmc-supply = <&mt_pmic_vmch_ldo_reg>; 700 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; 701}; 702 703&mt6359codec { 704 mediatek,dmic-mode = <1>; /* one-wire */ 705 mediatek,mic-type-0 = <2>; /* DMIC */ 706}; 707 708/* for CPU-L */ 709&mt6359_vcore_buck_reg { 710 regulator-always-on; 711}; 712 713/* for CORE */ 714&mt6359_vgpu11_buck_reg { 715 regulator-always-on; 716}; 717 718&mt6359_vgpu11_sshub_buck_reg { 719 regulator-always-on; 720 regulator-min-microvolt = <550000>; 721 regulator-max-microvolt = <550000>; 722}; 723 724/* for CORE SRAM */ 725&mt6359_vpu_buck_reg { 726 regulator-always-on; 727}; 728 729&mt6359_vrf12_ldo_reg { 730 regulator-always-on; 731}; 732 733/* for GPU SRAM */ 734&mt6359_vsram_others_ldo_reg { 735 regulator-min-microvolt = <750000>; 736 regulator-max-microvolt = <750000>; 737}; 738 739&mt6359_vufs_ldo_reg { 740 regulator-always-on; 741}; 742 743&nor_flash { 744 status = "okay"; 745 746 pinctrl-names = "default"; 747 pinctrl-0 = <&nor_pins_default>; 748 749 flash@0 { 750 compatible = "jedec,spi-nor"; 751 reg = <0>; 752 spi-max-frequency = <52000000>; 753 spi-rx-bus-width = <2>; 754 spi-tx-bus-width = <2>; 755 }; 756}; 757 758&ovl0_in { 759 remote-endpoint = <&vdosys0_ep_main>; 760}; 761 762&pcie1 { 763 status = "okay"; 764 765 pinctrl-names = "default"; 766 pinctrl-0 = <&pcie1_pins_default>; 767}; 768 769&pio { 770 mediatek,rsel-resistance-in-si-unit; 771 pinctrl-names = "default"; 772 pinctrl-0 = <&pio_default>; 773 774 /* 144 lines */ 775 gpio-line-names = 776 "I2S_SPKR_MCLK", 777 "I2S_SPKR_DATAIN", 778 "I2S_SPKR_LRCK", 779 "I2S_SPKR_BCLK", 780 "EC_AP_INT_ODL", 781 /* 782 * AP_FLASH_WP_L is crossystem ABI. Schematics 783 * call it AP_FLASH_WP_ODL. 784 */ 785 "AP_FLASH_WP_L", 786 "TCHPAD_INT_ODL", 787 "EDP_HPD_1V8", 788 "AP_I2C_CAM_SDA", 789 "AP_I2C_CAM_SCL", 790 "AP_I2C_TCHPAD_SDA_1V8", 791 "AP_I2C_TCHPAD_SCL_1V8", 792 "AP_I2C_AUD_SDA", 793 "AP_I2C_AUD_SCL", 794 "AP_I2C_TPM_SDA_1V8", 795 "AP_I2C_TPM_SCL_1V8", 796 "AP_I2C_TCHSCR_SDA_1V8", 797 "AP_I2C_TCHSCR_SCL_1V8", 798 "EC_AP_HPD_OD", 799 "", 800 "PCIE_NVME_RST_L", 801 "PCIE_NVME_CLKREQ_ODL", 802 "PCIE_RST_1V8_L", 803 "PCIE_CLKREQ_1V8_ODL", 804 "PCIE_WAKE_1V8_ODL", 805 "CLK_24M_CAM0", 806 "CAM1_SEN_EN", 807 "AP_I2C_PWR_SCL_1V8", 808 "AP_I2C_PWR_SDA_1V8", 809 "AP_I2C_MISC_SCL", 810 "AP_I2C_MISC_SDA", 811 "EN_PP5000_HDMI_X", 812 "AP_HDMITX_HTPLG", 813 "", 814 "AP_HDMITX_SCL_1V8", 815 "AP_HDMITX_SDA_1V8", 816 "AP_RTC_CLK32K", 817 "AP_EC_WATCHDOG_L", 818 "SRCLKENA0", 819 "SRCLKENA1", 820 "PWRAP_SPI0_CS_L", 821 "PWRAP_SPI0_CK", 822 "PWRAP_SPI0_MOSI", 823 "PWRAP_SPI0_MISO", 824 "SPMI_SCL", 825 "SPMI_SDA", 826 "", 827 "", 828 "", 829 "I2S_HP_DATAIN", 830 "I2S_HP_MCLK", 831 "I2S_HP_BCK", 832 "I2S_HP_LRCK", 833 "I2S_HP_DATAOUT", 834 "SD_CD_ODL", 835 "EN_PP3300_DISP_X", 836 "TCHSCR_RST_1V8_L", 837 "TCHSCR_REPORT_DISABLE", 838 "EN_PP3300_WLAN_X", 839 "BT_KILL_1V8_L", 840 "I2S_SPKR_DATAOUT", 841 "WIFI_KILL_1V8_L", 842 "BEEP_ON", 843 "SCP_I2C_SENSOR_SCL_1V8", 844 "SCP_I2C_SENSOR_SDA_1V8", 845 "", 846 "", 847 "", 848 "", 849 "AUD_CLK_MOSI", 850 "AUD_SYNC_MOSI", 851 "AUD_DAT_MOSI0", 852 "AUD_DAT_MOSI1", 853 "AUD_DAT_MISO0", 854 "AUD_DAT_MISO1", 855 "AUD_DAT_MISO2", 856 "SCP_VREQ_VAO", 857 "AP_SPI_GSC_TPM_CLK", 858 "AP_SPI_GSC_TPM_MOSI", 859 "AP_SPI_GSC_TPM_CS_L", 860 "AP_SPI_GSC_TPM_MISO", 861 "EN_PP1000_CAM_X", 862 "AP_EDP_BKLTEN", 863 "", 864 "USB3_HUB_RST_L", 865 "", 866 "WLAN_ALERT_ODL", 867 "EC_IN_RW_ODL", 868 "GSC_AP_INT_ODL", 869 "HP_INT_ODL", 870 "CAM0_RST_L", 871 "CAM1_RST_L", 872 "TCHSCR_INT_1V8_L", 873 "CAM1_DET_L", 874 "RST_ALC1011_L", 875 "", 876 "", 877 "BL_PWM_1V8", 878 "UART_AP_TX_DBG_RX", 879 "UART_DBG_TX_AP_RX", 880 "EN_SPKR", 881 "AP_EC_WARM_RST_REQ", 882 "UART_SCP_TX_DBGCON_RX", 883 "UART_DBGCON_TX_SCP_RX", 884 "", 885 "", 886 "KPCOL0", 887 "", 888 "MT6315_GPU_INT", 889 "MT6315_PROC_BC_INT", 890 "SD_CMD", 891 "SD_CLK", 892 "SD_DAT0", 893 "SD_DAT1", 894 "SD_DAT2", 895 "SD_DAT3", 896 "EMMC_DAT7", 897 "EMMC_DAT6", 898 "EMMC_DAT5", 899 "EMMC_DAT4", 900 "EMMC_RSTB", 901 "EMMC_CMD", 902 "EMMC_CLK", 903 "EMMC_DAT3", 904 "EMMC_DAT2", 905 "EMMC_DAT1", 906 "EMMC_DAT0", 907 "EMMC_DSL", 908 "", 909 "", 910 "MT6360_INT_ODL", 911 "SCP_JTAG0_TRSTN", 912 "AP_SPI_EC_CS_L", 913 "AP_SPI_EC_CLK", 914 "AP_SPI_EC_MOSI", 915 "AP_SPI_EC_MISO", 916 "SCP_JTAG0_TMS", 917 "SCP_JTAG0_TCK", 918 "SCP_JTAG0_TDO", 919 "SCP_JTAG0_TDI", 920 "AP_SPI_FLASH_CS_L", 921 "AP_SPI_FLASH_CLK", 922 "AP_SPI_FLASH_MOSI", 923 "AP_SPI_FLASH_MISO"; 924 925 aud_pins_default: audio-default-pins { 926 pins-cmd-dat { 927 pinmux = <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>, 928 <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>, 929 <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>, 930 <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>, 931 <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>, 932 <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>, 933 <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>, 934 <PINMUX_GPIO0__FUNC_TDMIN_MCK>, 935 <PINMUX_GPIO1__FUNC_TDMIN_DI>, 936 <PINMUX_GPIO2__FUNC_TDMIN_LRCK>, 937 <PINMUX_GPIO3__FUNC_TDMIN_BCK>, 938 <PINMUX_GPIO60__FUNC_I2SO2_D0>, 939 <PINMUX_GPIO49__FUNC_I2SIN_D0>, 940 <PINMUX_GPIO50__FUNC_I2SO1_MCK>, 941 <PINMUX_GPIO51__FUNC_I2SO1_BCK>, 942 <PINMUX_GPIO52__FUNC_I2SO1_WS>, 943 <PINMUX_GPIO53__FUNC_I2SO1_D0>; 944 }; 945 946 pins-hp-jack-int-odl { 947 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>; 948 input-enable; 949 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 950 }; 951 }; 952 953 cr50_int: cr50-irq-default-pins { 954 pins-gsc-ap-int-odl { 955 pinmux = <PINMUX_GPIO88__FUNC_GPIO88>; 956 input-enable; 957 }; 958 }; 959 960 cros_ec_int: cros-ec-irq-default-pins { 961 pins-ec-ap-int-odl { 962 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 963 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 964 input-enable; 965 }; 966 }; 967 968 edptx_pins_default: edptx-default-pins { 969 pins-cmd-dat { 970 pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>; 971 bias-pull-up; 972 }; 973 }; 974 975 disp_pwm0_pin_default: disp-pwm0-default-pins { 976 pins-disp-pwm { 977 pinmux = <PINMUX_GPIO82__FUNC_GPIO82>, 978 <PINMUX_GPIO97__FUNC_DISP_PWM0>; 979 }; 980 }; 981 982 dptx_pin: dptx-default-pins { 983 pins-cmd-dat { 984 pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>; 985 bias-pull-up; 986 }; 987 }; 988 989 i2c0_pins: i2c0-default-pins { 990 pins-bus { 991 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 992 <PINMUX_GPIO9__FUNC_SCL0>; 993 bias-disable; 994 drive-strength-microamp = <1000>; 995 }; 996 }; 997 998 i2c1_pins: i2c1-default-pins { 999 pins-bus { 1000 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 1001 <PINMUX_GPIO11__FUNC_SCL1>; 1002 bias-pull-up = <1000>; 1003 drive-strength-microamp = <1000>; 1004 }; 1005 }; 1006 1007 i2c2_pins: i2c2-default-pins { 1008 pins-bus { 1009 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 1010 <PINMUX_GPIO13__FUNC_SCL2>; 1011 bias-disable; 1012 drive-strength-microamp = <1000>; 1013 }; 1014 }; 1015 1016 i2c3_pins: i2c3-default-pins { 1017 pins-bus { 1018 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 1019 <PINMUX_GPIO15__FUNC_SCL3>; 1020 bias-pull-up = <1000>; 1021 drive-strength-microamp = <1000>; 1022 }; 1023 }; 1024 1025 i2c4_pins: i2c4-default-pins { 1026 pins-bus { 1027 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 1028 <PINMUX_GPIO17__FUNC_SCL4>; 1029 bias-pull-up = <1000>; 1030 drive-strength = <4>; 1031 }; 1032 }; 1033 1034 i2c5_pins: i2c5-default-pins { 1035 pins-bus { 1036 pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 1037 <PINMUX_GPIO30__FUNC_SDA5>; 1038 bias-disable; 1039 drive-strength-microamp = <1000>; 1040 }; 1041 }; 1042 1043 i2c7_pins: i2c7-default-pins { 1044 pins-bus { 1045 pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 1046 <PINMUX_GPIO28__FUNC_SDA7>; 1047 bias-disable; 1048 }; 1049 }; 1050 1051 mmc0_pins_default: mmc0-default-pins { 1052 pins-cmd-dat { 1053 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 1054 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 1055 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 1056 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 1057 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 1058 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 1059 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 1060 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 1061 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 1062 input-enable; 1063 drive-strength = <6>; 1064 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1065 }; 1066 1067 pins-clk { 1068 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 1069 drive-strength = <6>; 1070 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1071 }; 1072 1073 pins-rst { 1074 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 1075 drive-strength = <6>; 1076 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1077 }; 1078 }; 1079 1080 mmc0_pins_uhs: mmc0-uhs-pins { 1081 pins-cmd-dat { 1082 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 1083 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 1084 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 1085 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 1086 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 1087 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 1088 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 1089 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 1090 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 1091 input-enable; 1092 drive-strength = <8>; 1093 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1094 }; 1095 1096 pins-clk { 1097 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 1098 drive-strength = <8>; 1099 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1100 }; 1101 1102 pins-ds { 1103 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 1104 drive-strength = <8>; 1105 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1106 }; 1107 1108 pins-rst { 1109 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 1110 drive-strength = <8>; 1111 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1112 }; 1113 }; 1114 1115 mmc1_pins_detect: mmc1-detect-pins { 1116 pins-insert { 1117 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; 1118 bias-pull-up; 1119 }; 1120 }; 1121 1122 mmc1_pins_default: mmc1-default-pins { 1123 pins-cmd-dat { 1124 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 1125 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 1126 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 1127 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 1128 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 1129 input-enable; 1130 drive-strength = <8>; 1131 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1132 }; 1133 1134 pins-clk { 1135 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 1136 drive-strength = <8>; 1137 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1138 }; 1139 }; 1140 1141 nor_pins_default: nor-default-pins { 1142 pins-ck-io { 1143 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 1144 <PINMUX_GPIO141__FUNC_SPINOR_CK>, 1145 <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 1146 drive-strength = <6>; 1147 bias-pull-down; 1148 }; 1149 1150 pins-cs { 1151 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; 1152 drive-strength = <6>; 1153 bias-pull-up; 1154 }; 1155 }; 1156 1157 pcie0_pins_default: pcie0-default-pins { 1158 pins-bus { 1159 pinmux = <PINMUX_GPIO19__FUNC_WAKEN>, 1160 <PINMUX_GPIO20__FUNC_PERSTN>, 1161 <PINMUX_GPIO21__FUNC_CLKREQN>; 1162 bias-pull-up; 1163 }; 1164 }; 1165 1166 pcie1_pins_default: pcie1-default-pins { 1167 pins-bus { 1168 pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>, 1169 <PINMUX_GPIO23__FUNC_CLKREQN_1>, 1170 <PINMUX_GPIO24__FUNC_WAKEN_1>; 1171 bias-pull-up; 1172 }; 1173 }; 1174 1175 panel_fixed_pins: panel-pwr-default-pins { 1176 pins-vreg-en { 1177 pinmux = <PINMUX_GPIO55__FUNC_GPIO55>; 1178 }; 1179 }; 1180 1181 pio_default: pio-default-pins { 1182 pins-wifi-enable { 1183 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 1184 output-high; 1185 drive-strength = <14>; 1186 }; 1187 1188 pins-low-power-pd { 1189 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 1190 <PINMUX_GPIO26__FUNC_GPIO26>, 1191 <PINMUX_GPIO46__FUNC_GPIO46>, 1192 <PINMUX_GPIO47__FUNC_GPIO47>, 1193 <PINMUX_GPIO48__FUNC_GPIO48>, 1194 <PINMUX_GPIO65__FUNC_GPIO65>, 1195 <PINMUX_GPIO66__FUNC_GPIO66>, 1196 <PINMUX_GPIO67__FUNC_GPIO67>, 1197 <PINMUX_GPIO68__FUNC_GPIO68>, 1198 <PINMUX_GPIO128__FUNC_GPIO128>, 1199 <PINMUX_GPIO129__FUNC_GPIO129>; 1200 input-enable; 1201 bias-pull-down; 1202 }; 1203 1204 pins-low-power-pupd { 1205 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 1206 <PINMUX_GPIO78__FUNC_GPIO78>, 1207 <PINMUX_GPIO79__FUNC_GPIO79>, 1208 <PINMUX_GPIO80__FUNC_GPIO80>, 1209 <PINMUX_GPIO83__FUNC_GPIO83>, 1210 <PINMUX_GPIO85__FUNC_GPIO85>, 1211 <PINMUX_GPIO90__FUNC_GPIO90>, 1212 <PINMUX_GPIO91__FUNC_GPIO91>, 1213 <PINMUX_GPIO93__FUNC_GPIO93>, 1214 <PINMUX_GPIO94__FUNC_GPIO94>, 1215 <PINMUX_GPIO95__FUNC_GPIO95>, 1216 <PINMUX_GPIO96__FUNC_GPIO96>, 1217 <PINMUX_GPIO104__FUNC_GPIO104>, 1218 <PINMUX_GPIO105__FUNC_GPIO105>, 1219 <PINMUX_GPIO107__FUNC_GPIO107>; 1220 input-enable; 1221 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1222 }; 1223 }; 1224 1225 rt1019p_pins_default: rt1019p-default-pins { 1226 pins-amp-sdb { 1227 pinmux = <PINMUX_GPIO100__FUNC_GPIO100>; 1228 output-low; 1229 }; 1230 }; 1231 1232 scp_pins: scp-default-pins { 1233 pins-vreq { 1234 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; 1235 bias-disable; 1236 input-enable; 1237 }; 1238 }; 1239 1240 spi0_pins: spi0-default-pins { 1241 pins-cs-mosi-clk { 1242 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 1243 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 1244 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 1245 bias-disable; 1246 }; 1247 1248 pins-miso { 1249 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 1250 bias-pull-down; 1251 }; 1252 }; 1253 1254 subpmic_default: subpmic-default-pins { 1255 subpmic_pin_irq: pins-subpmic-int-n { 1256 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; 1257 input-enable; 1258 bias-pull-up; 1259 }; 1260 }; 1261 1262 trackpad_pins: trackpad-default-pins { 1263 pins-int-n { 1264 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 1265 input-enable; 1266 bias-pull-up; 1267 }; 1268 }; 1269 1270 touchscreen_pins: touchscreen-default-pins { 1271 pins-int-n { 1272 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; 1273 input-enable; 1274 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1275 }; 1276 pins-rst { 1277 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; 1278 output-high; 1279 }; 1280 pins-report-sw { 1281 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; 1282 output-low; 1283 }; 1284 }; 1285}; 1286 1287&pmic { 1288 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 1289}; 1290 1291&scp { 1292 status = "okay"; 1293 1294 firmware-name = "mediatek/mt8195/scp.img"; 1295 memory-region = <&scp_mem>; 1296 pinctrl-names = "default"; 1297 pinctrl-0 = <&scp_pins>; 1298 1299 cros-ec-rpmsg { 1300 compatible = "google,cros-ec-rpmsg"; 1301 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1302 }; 1303}; 1304 1305&sound { 1306 status = "okay"; 1307 1308 mediatek,adsp = <&adsp>; 1309 mediatek,dai-link = 1310 "DL10_FE", "DPTX_BE", "ETDM1_IN_BE", "ETDM2_IN_BE", 1311 "ETDM1_OUT_BE", "ETDM2_OUT_BE","UL_SRC1_BE", 1312 "AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5"; 1313 pinctrl-names = "default"; 1314 pinctrl-0 = <&aud_pins_default>; 1315 1316 audio-routing = 1317 "Headphone", "HPOL", 1318 "Headphone", "HPOR", 1319 "IN1P", "Headset Mic", 1320 "Ext Spk", "Speaker"; 1321 1322 mm-dai-link { 1323 link-name = "ETDM1_IN_BE"; 1324 mediatek,clk-provider = "cpu"; 1325 }; 1326 1327 hs-playback-dai-link { 1328 link-name = "ETDM1_OUT_BE"; 1329 mediatek,clk-provider = "cpu"; 1330 codec { 1331 sound-dai = <&audio_codec 0>; 1332 }; 1333 }; 1334 1335 hs-capture-dai-link { 1336 link-name = "ETDM2_IN_BE"; 1337 mediatek,clk-provider = "cpu"; 1338 codec { 1339 sound-dai = <&audio_codec 0>; 1340 }; 1341 }; 1342 1343 spk-playback-dai-link { 1344 link-name = "ETDM2_OUT_BE"; 1345 mediatek,clk-provider = "cpu"; 1346 codec { 1347 sound-dai = <&spk_amplifier>; 1348 }; 1349 }; 1350 1351 displayport-dai-link { 1352 link-name = "DPTX_BE"; 1353 codec { 1354 sound-dai = <&dp_tx>; 1355 }; 1356 }; 1357}; 1358 1359&spi0 { 1360 status = "okay"; 1361 1362 pinctrl-names = "default"; 1363 pinctrl-0 = <&spi0_pins>; 1364 mediatek,pad-select = <0>; 1365 1366 cros_ec: ec@0 { 1367 #address-cells = <1>; 1368 #size-cells = <0>; 1369 1370 compatible = "google,cros-ec-spi"; 1371 reg = <0>; 1372 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; 1373 pinctrl-names = "default"; 1374 pinctrl-0 = <&cros_ec_int>; 1375 spi-max-frequency = <3000000>; 1376 wakeup-source; 1377 1378 i2c_tunnel: i2c-tunnel { 1379 compatible = "google,cros-ec-i2c-tunnel"; 1380 google,remote-bus = <0>; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 }; 1384 1385 mt_pmic_vmc_ldo_reg: regulator@0 { 1386 compatible = "google,cros-ec-regulator"; 1387 reg = <0>; 1388 regulator-name = "mt_pmic_vmc_ldo"; 1389 regulator-min-microvolt = <1200000>; 1390 regulator-max-microvolt = <3600000>; 1391 }; 1392 1393 mt_pmic_vmch_ldo_reg: regulator@1 { 1394 compatible = "google,cros-ec-regulator"; 1395 reg = <1>; 1396 regulator-name = "mt_pmic_vmch_ldo"; 1397 regulator-min-microvolt = <2700000>; 1398 regulator-max-microvolt = <3600000>; 1399 }; 1400 1401 typec { 1402 compatible = "google,cros-ec-typec"; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 1406 usb_c0: connector@0 { 1407 compatible = "usb-c-connector"; 1408 reg = <0>; 1409 power-role = "dual"; 1410 data-role = "host"; 1411 try-power-role = "source"; 1412 }; 1413 1414 usb_c1: connector@1 { 1415 compatible = "usb-c-connector"; 1416 reg = <1>; 1417 power-role = "dual"; 1418 data-role = "host"; 1419 try-power-role = "source"; 1420 }; 1421 }; 1422 }; 1423}; 1424 1425&spmi { 1426 #address-cells = <2>; 1427 #size-cells = <0>; 1428 1429 mt6315@6 { 1430 compatible = "mediatek,mt6315-regulator"; 1431 reg = <0x6 SPMI_USID>; 1432 1433 regulators { 1434 mt6315_6_vbuck1: vbuck1 { 1435 regulator-name = "Vbcpu"; 1436 regulator-min-microvolt = <400000>; 1437 regulator-max-microvolt = <1193750>; 1438 regulator-enable-ramp-delay = <256>; 1439 regulator-ramp-delay = <6250>; 1440 regulator-allowed-modes = <0 1 2>; 1441 regulator-always-on; 1442 }; 1443 }; 1444 }; 1445 1446 mt6315@7 { 1447 compatible = "mediatek,mt6315-regulator"; 1448 reg = <0x7 SPMI_USID>; 1449 1450 regulators { 1451 mt6315_7_vbuck1: vbuck1 { 1452 regulator-name = "Vgpu"; 1453 regulator-min-microvolt = <400000>; 1454 regulator-max-microvolt = <1193750>; 1455 regulator-enable-ramp-delay = <256>; 1456 regulator-ramp-delay = <6250>; 1457 regulator-allowed-modes = <0 1 2>; 1458 }; 1459 }; 1460 }; 1461}; 1462 1463&thermal_zones { 1464 soc-area-thermal { 1465 polling-delay = <1000>; 1466 polling-delay-passive = <250>; 1467 thermal-sensors = <&tboard_thermistor1>; 1468 1469 trips { 1470 trip-crit { 1471 temperature = <84000>; 1472 hysteresis = <1000>; 1473 type = "critical"; 1474 }; 1475 }; 1476 }; 1477 1478 pmic-area-thermal { 1479 polling-delay = <1000>; 1480 polling-delay-passive = <0>; 1481 thermal-sensors = <&tboard_thermistor2>; 1482 1483 trips { 1484 trip-crit { 1485 temperature = <84000>; 1486 hysteresis = <1000>; 1487 type = "critical"; 1488 }; 1489 }; 1490 }; 1491}; 1492 1493&u3phy0 { 1494 status = "okay"; 1495}; 1496 1497&u3phy1 { 1498 status = "okay"; 1499}; 1500 1501&u3phy2 { 1502 status = "okay"; 1503}; 1504 1505&u3phy3 { 1506 status = "okay"; 1507}; 1508 1509&uart0 { 1510 status = "okay"; 1511}; 1512 1513&vdosys0 { 1514 port { 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 1518 vdosys0_ep_main: endpoint@0 { 1519 reg = <0>; 1520 remote-endpoint = <&ovl0_in>; 1521 }; 1522 }; 1523}; 1524 1525/* 1526 * For the USB Type-C ports the role and alternate modes switching is 1527 * done by the EC so we set dr_mode to host to avoid interfering. 1528 */ 1529&ssusb0 { 1530 dr_mode = "host"; 1531 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1532 status = "okay"; 1533}; 1534 1535&ssusb2 { 1536 dr_mode = "host"; 1537 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1538 status = "okay"; 1539}; 1540 1541&ssusb3 { 1542 dr_mode = "host"; 1543 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1544 status = "okay"; 1545}; 1546 1547&vdosys1 { 1548 port { 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 1552 vdosys1_ep_ext: endpoint@1 { 1553 reg = <1>; 1554 remote-endpoint = <ðdr0_in>; 1555 }; 1556 }; 1557}; 1558 1559&xhci0 { 1560 status = "okay"; 1561 1562 rx-fifo-depth = <3072>; 1563 vbus-supply = <&usb_vbus>; 1564}; 1565 1566&xhci1 { 1567 status = "okay"; 1568 1569 phys = <&u2port1 PHY_TYPE_USB2>; 1570 rx-fifo-depth = <3072>; 1571 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1572 vbus-supply = <&usb_vbus>; 1573 mediatek,u3p-dis-msk = <1>; 1574}; 1575 1576&xhci2 { 1577 status = "okay"; 1578 vbus-supply = <&usb_vbus>; 1579}; 1580 1581&xhci3 { 1582 status = "okay"; 1583 1584 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 1585 usb2-lpm-disable; 1586 vbus-supply = <&usb_vbus>; 1587}; 1588 1589#include <arm/cros-ec-keyboard.dtsi> 1590#include <arm/cros-ec-sbs.dtsi> 1591 1592&keyboard_controller { 1593 function-row-physmap = < 1594 MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 1595 MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 1596 MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 1597 MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 1598 MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 1599 MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 1600 MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 1601 MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 1602 MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 1603 MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 1604 1605 /* T11 to T13 are present only on Dojo */ 1606 MATRIX_KEY(0x00, 0x01, 0) /* T11 */ 1607 MATRIX_KEY(0x01, 0x05, 0) /* T12 */ 1608 MATRIX_KEY(0x03, 0x05, 0) /* T13 */ 1609 >; 1610 1611 linux,keymap = < 1612 MATRIX_KEY(0x00, 0x02, KEY_BACK) 1613 MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 1614 MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 1615 MATRIX_KEY(0x01, 0x02, KEY_SCALE) 1616 MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) 1617 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 1618 MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 1619 MATRIX_KEY(0x02, 0x09, KEY_MUTE) 1620 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 1621 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 1622 1623 CROS_STD_MAIN_KEYMAP 1624 >; 1625}; 1626