1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/spmi/spmi.h> 8#include "mt8195.dtsi" 9#include "mt6359.dtsi" 10 11/ { 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c7 = &i2c7; 20 mmc0 = &mmc0; 21 mmc1 = &mmc1; 22 serial0 = &uart0; 23 }; 24 25 backlight_lcd0: backlight-lcd0 { 26 compatible = "pwm-backlight"; 27 brightness-levels = <0 1023>; 28 default-brightness-level = <576>; 29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>; 30 num-interpolated-steps = <1023>; 31 pwms = <&disp_pwm0 0 500000>; 32 power-supply = <&ppvar_sys>; 33 }; 34 35 chosen { 36 stdout-path = "serial0:115200n8"; 37 }; 38 39 dmic-codec { 40 compatible = "dmic-codec"; 41 num-channels = <2>; 42 wakeup-delay-ms = <50>; 43 }; 44 45 memory@40000000 { 46 device_type = "memory"; 47 reg = <0 0x40000000 0 0x80000000>; 48 }; 49 50 pp3300_disp_x: regulator-pp3300-disp-x { 51 compatible = "regulator-fixed"; 52 regulator-name = "pp3300_disp_x"; 53 regulator-min-microvolt = <3300000>; 54 regulator-max-microvolt = <3300000>; 55 regulator-enable-ramp-delay = <2500>; 56 enable-active-high; 57 gpio = <&pio 55 GPIO_ACTIVE_HIGH>; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&panel_fixed_pins>; 60 vin-supply = <&pp3300_z2>; 61 }; 62 63 /* system wide LDO 3.3V power rail */ 64 pp3300_z5: regulator-pp3300-ldo-z5 { 65 compatible = "regulator-fixed"; 66 regulator-name = "pp3300_ldo_z5"; 67 regulator-always-on; 68 regulator-boot-on; 69 regulator-min-microvolt = <3300000>; 70 regulator-max-microvolt = <3300000>; 71 vin-supply = <&ppvar_sys>; 72 }; 73 74 /* separately switched 3.3V power rail */ 75 pp3300_s3: regulator-pp3300-s3 { 76 compatible = "regulator-fixed"; 77 regulator-name = "pp3300_s3"; 78 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 79 regulator-always-on; 80 regulator-boot-on; 81 regulator-min-microvolt = <3300000>; 82 regulator-max-microvolt = <3300000>; 83 vin-supply = <&pp3300_z2>; 84 }; 85 86 /* system wide 3.3V power rail */ 87 pp3300_z2: regulator-pp3300-z2 { 88 compatible = "regulator-fixed"; 89 regulator-name = "pp3300_z2"; 90 /* EN pin tied to pp4200_z2, which is controlled by EC */ 91 regulator-always-on; 92 regulator-boot-on; 93 regulator-min-microvolt = <3300000>; 94 regulator-max-microvolt = <3300000>; 95 vin-supply = <&ppvar_sys>; 96 }; 97 98 /* system wide 4.2V power rail */ 99 pp4200_z2: regulator-pp4200-z2 { 100 compatible = "regulator-fixed"; 101 regulator-name = "pp4200_z2"; 102 /* controlled by EC */ 103 regulator-always-on; 104 regulator-boot-on; 105 regulator-min-microvolt = <4200000>; 106 regulator-max-microvolt = <4200000>; 107 vin-supply = <&ppvar_sys>; 108 }; 109 110 /* system wide switching 5.0V power rail */ 111 pp5000_s5: regulator-pp5000-s5 { 112 compatible = "regulator-fixed"; 113 regulator-name = "pp5000_s5"; 114 /* controlled by EC */ 115 regulator-always-on; 116 regulator-boot-on; 117 regulator-min-microvolt = <5000000>; 118 regulator-max-microvolt = <5000000>; 119 vin-supply = <&ppvar_sys>; 120 }; 121 122 /* system wide semi-regulated power rail from battery or USB */ 123 ppvar_sys: regulator-ppvar-sys { 124 compatible = "regulator-fixed"; 125 regulator-name = "ppvar_sys"; 126 regulator-always-on; 127 regulator-boot-on; 128 }; 129 130 /* Murata NCP03WF104F05RL */ 131 tboard_thermistor1: thermal-sensor-t1 { 132 compatible = "generic-adc-thermal"; 133 #thermal-sensor-cells = <0>; 134 io-channels = <&auxadc 0>; 135 io-channel-names = "sensor-channel"; 136 temperature-lookup-table = < (-10000) 1553 137 (-5000) 1485 138 0 1406 139 5000 1317 140 10000 1219 141 15000 1115 142 20000 1007 143 25000 900 144 30000 796 145 35000 697 146 40000 605 147 45000 523 148 50000 449 149 55000 384 150 60000 327 151 65000 279 152 70000 237 153 75000 202 154 80000 172 155 85000 147 156 90000 125 157 95000 107 158 100000 92 159 105000 79 160 110000 68 161 115000 59 162 120000 51 163 125000 44>; 164 }; 165 166 tboard_thermistor2: thermal-sensor-t2 { 167 compatible = "generic-adc-thermal"; 168 #thermal-sensor-cells = <0>; 169 io-channels = <&auxadc 1>; 170 io-channel-names = "sensor-channel"; 171 temperature-lookup-table = < (-10000) 1553 172 (-5000) 1485 173 0 1406 174 5000 1317 175 10000 1219 176 15000 1115 177 20000 1007 178 25000 900 179 30000 796 180 35000 697 181 40000 605 182 45000 523 183 50000 449 184 55000 384 185 60000 327 186 65000 279 187 70000 237 188 75000 202 189 80000 172 190 85000 147 191 90000 125 192 95000 107 193 100000 92 194 105000 79 195 110000 68 196 115000 59 197 120000 51 198 125000 44>; 199 }; 200 201 usb_vbus: regulator-5v0-usb-vbus { 202 compatible = "regulator-fixed"; 203 regulator-name = "usb-vbus"; 204 regulator-min-microvolt = <5000000>; 205 regulator-max-microvolt = <5000000>; 206 enable-active-high; 207 regulator-always-on; 208 }; 209 210 reserved_memory: reserved-memory { 211 #address-cells = <2>; 212 #size-cells = <2>; 213 ranges; 214 215 scp_mem: memory@50000000 { 216 compatible = "shared-dma-pool"; 217 reg = <0 0x50000000 0 0x2900000>; 218 no-map; 219 }; 220 221 adsp_mem: memory@60000000 { 222 compatible = "shared-dma-pool"; 223 reg = <0 0x60000000 0 0xd80000>; 224 no-map; 225 }; 226 227 afe_mem: memory@60d80000 { 228 compatible = "shared-dma-pool"; 229 reg = <0 0x60d80000 0 0x100000>; 230 no-map; 231 }; 232 233 adsp_device_mem: memory@60e80000 { 234 compatible = "shared-dma-pool"; 235 reg = <0 0x60e80000 0 0x280000>; 236 no-map; 237 }; 238 }; 239 240 spk_amplifier: rt1019p { 241 compatible = "realtek,rt1019p"; 242 label = "rt1019p"; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&rt1019p_pins_default>; 245 sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>; 246 }; 247}; 248 249&adsp { 250 status = "okay"; 251 252 memory-region = <&adsp_device_mem>, <&adsp_mem>; 253}; 254 255&afe { 256 status = "okay"; 257 258 mediatek,etdm-in2-cowork-source = <2>; 259 mediatek,etdm-out2-cowork-source = <0>; 260 memory-region = <&afe_mem>; 261}; 262 263&auxadc { 264 status = "okay"; 265}; 266 267&dp_intf0 { 268 status = "okay"; 269 270 port { 271 dp_intf0_out: endpoint { 272 remote-endpoint = <&edp_in>; 273 }; 274 }; 275}; 276 277&dp_intf1 { 278 status = "okay"; 279 280 port { 281 dp_intf1_out: endpoint { 282 remote-endpoint = <&dptx_in>; 283 }; 284 }; 285}; 286 287&edp_tx { 288 status = "okay"; 289 290 pinctrl-names = "default"; 291 pinctrl-0 = <&edptx_pins_default>; 292 293 ports { 294 #address-cells = <1>; 295 #size-cells = <0>; 296 297 port@0 { 298 reg = <0>; 299 edp_in: endpoint { 300 remote-endpoint = <&dp_intf0_out>; 301 }; 302 }; 303 304 port@1 { 305 reg = <1>; 306 edp_out: endpoint { 307 data-lanes = <0 1 2 3>; 308 remote-endpoint = <&panel_in>; 309 }; 310 }; 311 }; 312 313 aux-bus { 314 panel { 315 compatible = "edp-panel"; 316 power-supply = <&pp3300_disp_x>; 317 backlight = <&backlight_lcd0>; 318 port { 319 panel_in: endpoint { 320 remote-endpoint = <&edp_out>; 321 }; 322 }; 323 }; 324 }; 325}; 326 327&disp_pwm0 { 328 status = "okay"; 329 330 pinctrl-names = "default"; 331 pinctrl-0 = <&disp_pwm0_pin_default>; 332}; 333 334&dp_tx { 335 status = "okay"; 336 337 pinctrl-names = "default"; 338 pinctrl-0 = <&dptx_pin>; 339 340 ports { 341 #address-cells = <1>; 342 #size-cells = <0>; 343 344 port@0 { 345 reg = <0>; 346 dptx_in: endpoint { 347 remote-endpoint = <&dp_intf1_out>; 348 }; 349 }; 350 351 port@1 { 352 reg = <1>; 353 dptx_out: endpoint { 354 data-lanes = <0 1 2 3>; 355 }; 356 }; 357 }; 358}; 359 360&gic { 361 mediatek,broken-save-restore-fw; 362}; 363 364&gpu { 365 status = "okay"; 366 mali-supply = <&mt6315_7_vbuck1>; 367}; 368 369&i2c0 { 370 status = "okay"; 371 372 clock-frequency = <400000>; 373 pinctrl-names = "default"; 374 pinctrl-0 = <&i2c0_pins>; 375}; 376 377&i2c1 { 378 status = "okay"; 379 380 clock-frequency = <400000>; 381 i2c-scl-internal-delay-ns = <12500>; 382 pinctrl-names = "default"; 383 pinctrl-0 = <&i2c1_pins>; 384 385 trackpad@15 { 386 compatible = "elan,ekth3000"; 387 reg = <0x15>; 388 interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&trackpad_pins>; 391 vcc-supply = <&pp3300_s3>; 392 wakeup-source; 393 }; 394}; 395 396&i2c2 { 397 status = "okay"; 398 399 clock-frequency = <400000>; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&i2c2_pins>; 402 403 audio_codec: codec@1a { 404 /* Realtek RT5682i or RT5682s, sharing the same configuration */ 405 reg = <0x1a>; 406 interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>; 407 realtek,jd-src = <1>; 408 409 AVDD-supply = <&mt6359_vio18_ldo_reg>; 410 MICVDD-supply = <&pp3300_z2>; 411 VBAT-supply = <&pp3300_z5>; 412 }; 413}; 414 415&i2c3 { 416 status = "okay"; 417 418 clock-frequency = <400000>; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&i2c3_pins>; 421 422 tpm@50 { 423 compatible = "google,cr50"; 424 reg = <0x50>; 425 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&cr50_int>; 428 }; 429}; 430 431&i2c4 { 432 status = "okay"; 433 434 clock-frequency = <400000>; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&i2c4_pins>; 437 438 ts_10: touchscreen@10 { 439 compatible = "hid-over-i2c"; 440 reg = <0x10>; 441 hid-descr-addr = <0x0001>; 442 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&touchscreen_pins>; 445 post-power-on-delay-ms = <10>; 446 vdd-supply = <&pp3300_s3>; 447 status = "disabled"; 448 }; 449}; 450 451&i2c5 { 452 status = "okay"; 453 454 clock-frequency = <400000>; 455 pinctrl-names = "default"; 456 pinctrl-0 = <&i2c5_pins>; 457}; 458 459&i2c7 { 460 status = "okay"; 461 462 clock-frequency = <400000>; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&i2c7_pins>; 465 466 pmic@34 { 467 #interrupt-cells = <2>; 468 compatible = "mediatek,mt6360"; 469 reg = <0x34>; 470 interrupt-controller; 471 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; 472 interrupt-names = "IRQB"; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&subpmic_default>; 475 wakeup-source; 476 }; 477}; 478 479&mfg0 { 480 domain-supply = <&mt6315_7_vbuck1>; 481}; 482 483&mfg1 { 484 domain-supply = <&mt6359_vsram_others_ldo_reg>; 485}; 486 487&mmc0 { 488 status = "okay"; 489 490 bus-width = <8>; 491 cap-mmc-highspeed; 492 cap-mmc-hw-reset; 493 hs400-ds-delay = <0x14c11>; 494 max-frequency = <200000000>; 495 mmc-hs200-1_8v; 496 mmc-hs400-1_8v; 497 no-sdio; 498 no-sd; 499 non-removable; 500 pinctrl-names = "default", "state_uhs"; 501 pinctrl-0 = <&mmc0_pins_default>; 502 pinctrl-1 = <&mmc0_pins_uhs>; 503 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 504 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 505}; 506 507&mmc1 { 508 status = "okay"; 509 510 bus-width = <4>; 511 cap-sd-highspeed; 512 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 513 max-frequency = <200000000>; 514 no-mmc; 515 no-sdio; 516 pinctrl-names = "default", "state_uhs"; 517 pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>; 518 pinctrl-1 = <&mmc1_pins_default>; 519 sd-uhs-sdr50; 520 sd-uhs-sdr104; 521 vmmc-supply = <&mt_pmic_vmch_ldo_reg>; 522 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; 523}; 524 525&mt6359codec { 526 mediatek,dmic-mode = <1>; /* one-wire */ 527 mediatek,mic-type-0 = <2>; /* DMIC */ 528}; 529 530/* for CPU-L */ 531&mt6359_vcore_buck_reg { 532 regulator-always-on; 533}; 534 535/* for CORE */ 536&mt6359_vgpu11_buck_reg { 537 regulator-always-on; 538}; 539 540&mt6359_vgpu11_sshub_buck_reg { 541 regulator-always-on; 542 regulator-min-microvolt = <550000>; 543 regulator-max-microvolt = <550000>; 544}; 545 546/* for CORE SRAM */ 547&mt6359_vpu_buck_reg { 548 regulator-always-on; 549}; 550 551&mt6359_vrf12_ldo_reg { 552 regulator-always-on; 553}; 554 555/* for GPU SRAM */ 556&mt6359_vsram_others_ldo_reg { 557 regulator-min-microvolt = <750000>; 558 regulator-max-microvolt = <750000>; 559}; 560 561&mt6359_vufs_ldo_reg { 562 regulator-always-on; 563}; 564 565&nor_flash { 566 status = "okay"; 567 568 pinctrl-names = "default"; 569 pinctrl-0 = <&nor_pins_default>; 570 571 flash@0 { 572 compatible = "jedec,spi-nor"; 573 reg = <0>; 574 spi-max-frequency = <52000000>; 575 spi-rx-bus-width = <2>; 576 spi-tx-bus-width = <2>; 577 }; 578}; 579 580&pcie1 { 581 status = "okay"; 582 583 pinctrl-names = "default"; 584 pinctrl-0 = <&pcie1_pins_default>; 585}; 586 587&pio { 588 mediatek,rsel-resistance-in-si-unit; 589 pinctrl-names = "default"; 590 pinctrl-0 = <&pio_default>; 591 592 /* 144 lines */ 593 gpio-line-names = 594 "I2S_SPKR_MCLK", 595 "I2S_SPKR_DATAIN", 596 "I2S_SPKR_LRCK", 597 "I2S_SPKR_BCLK", 598 "EC_AP_INT_ODL", 599 /* 600 * AP_FLASH_WP_L is crossystem ABI. Schematics 601 * call it AP_FLASH_WP_ODL. 602 */ 603 "AP_FLASH_WP_L", 604 "TCHPAD_INT_ODL", 605 "EDP_HPD_1V8", 606 "AP_I2C_CAM_SDA", 607 "AP_I2C_CAM_SCL", 608 "AP_I2C_TCHPAD_SDA_1V8", 609 "AP_I2C_TCHPAD_SCL_1V8", 610 "AP_I2C_AUD_SDA", 611 "AP_I2C_AUD_SCL", 612 "AP_I2C_TPM_SDA_1V8", 613 "AP_I2C_TPM_SCL_1V8", 614 "AP_I2C_TCHSCR_SDA_1V8", 615 "AP_I2C_TCHSCR_SCL_1V8", 616 "EC_AP_HPD_OD", 617 "", 618 "PCIE_NVME_RST_L", 619 "PCIE_NVME_CLKREQ_ODL", 620 "PCIE_RST_1V8_L", 621 "PCIE_CLKREQ_1V8_ODL", 622 "PCIE_WAKE_1V8_ODL", 623 "CLK_24M_CAM0", 624 "CAM1_SEN_EN", 625 "AP_I2C_PWR_SCL_1V8", 626 "AP_I2C_PWR_SDA_1V8", 627 "AP_I2C_MISC_SCL", 628 "AP_I2C_MISC_SDA", 629 "EN_PP5000_HDMI_X", 630 "AP_HDMITX_HTPLG", 631 "", 632 "AP_HDMITX_SCL_1V8", 633 "AP_HDMITX_SDA_1V8", 634 "AP_RTC_CLK32K", 635 "AP_EC_WATCHDOG_L", 636 "SRCLKENA0", 637 "SRCLKENA1", 638 "PWRAP_SPI0_CS_L", 639 "PWRAP_SPI0_CK", 640 "PWRAP_SPI0_MOSI", 641 "PWRAP_SPI0_MISO", 642 "SPMI_SCL", 643 "SPMI_SDA", 644 "", 645 "", 646 "", 647 "I2S_HP_DATAIN", 648 "I2S_HP_MCLK", 649 "I2S_HP_BCK", 650 "I2S_HP_LRCK", 651 "I2S_HP_DATAOUT", 652 "SD_CD_ODL", 653 "EN_PP3300_DISP_X", 654 "TCHSCR_RST_1V8_L", 655 "TCHSCR_REPORT_DISABLE", 656 "EN_PP3300_WLAN_X", 657 "BT_KILL_1V8_L", 658 "I2S_SPKR_DATAOUT", 659 "WIFI_KILL_1V8_L", 660 "BEEP_ON", 661 "SCP_I2C_SENSOR_SCL_1V8", 662 "SCP_I2C_SENSOR_SDA_1V8", 663 "", 664 "", 665 "", 666 "", 667 "AUD_CLK_MOSI", 668 "AUD_SYNC_MOSI", 669 "AUD_DAT_MOSI0", 670 "AUD_DAT_MOSI1", 671 "AUD_DAT_MISO0", 672 "AUD_DAT_MISO1", 673 "AUD_DAT_MISO2", 674 "SCP_VREQ_VAO", 675 "AP_SPI_GSC_TPM_CLK", 676 "AP_SPI_GSC_TPM_MOSI", 677 "AP_SPI_GSC_TPM_CS_L", 678 "AP_SPI_GSC_TPM_MISO", 679 "EN_PP1000_CAM_X", 680 "AP_EDP_BKLTEN", 681 "", 682 "USB3_HUB_RST_L", 683 "", 684 "WLAN_ALERT_ODL", 685 "EC_IN_RW_ODL", 686 "GSC_AP_INT_ODL", 687 "HP_INT_ODL", 688 "CAM0_RST_L", 689 "CAM1_RST_L", 690 "TCHSCR_INT_1V8_L", 691 "CAM1_DET_L", 692 "RST_ALC1011_L", 693 "", 694 "", 695 "BL_PWM_1V8", 696 "UART_AP_TX_DBG_RX", 697 "UART_DBG_TX_AP_RX", 698 "EN_SPKR", 699 "AP_EC_WARM_RST_REQ", 700 "UART_SCP_TX_DBGCON_RX", 701 "UART_DBGCON_TX_SCP_RX", 702 "", 703 "", 704 "KPCOL0", 705 "", 706 "MT6315_GPU_INT", 707 "MT6315_PROC_BC_INT", 708 "SD_CMD", 709 "SD_CLK", 710 "SD_DAT0", 711 "SD_DAT1", 712 "SD_DAT2", 713 "SD_DAT3", 714 "EMMC_DAT7", 715 "EMMC_DAT6", 716 "EMMC_DAT5", 717 "EMMC_DAT4", 718 "EMMC_RSTB", 719 "EMMC_CMD", 720 "EMMC_CLK", 721 "EMMC_DAT3", 722 "EMMC_DAT2", 723 "EMMC_DAT1", 724 "EMMC_DAT0", 725 "EMMC_DSL", 726 "", 727 "", 728 "MT6360_INT_ODL", 729 "SCP_JTAG0_TRSTN", 730 "AP_SPI_EC_CS_L", 731 "AP_SPI_EC_CLK", 732 "AP_SPI_EC_MOSI", 733 "AP_SPI_EC_MISO", 734 "SCP_JTAG0_TMS", 735 "SCP_JTAG0_TCK", 736 "SCP_JTAG0_TDO", 737 "SCP_JTAG0_TDI", 738 "AP_SPI_FLASH_CS_L", 739 "AP_SPI_FLASH_CLK", 740 "AP_SPI_FLASH_MOSI", 741 "AP_SPI_FLASH_MISO"; 742 743 aud_pins_default: audio-default-pins { 744 pins-cmd-dat { 745 pinmux = <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>, 746 <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>, 747 <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>, 748 <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>, 749 <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>, 750 <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>, 751 <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>, 752 <PINMUX_GPIO0__FUNC_TDMIN_MCK>, 753 <PINMUX_GPIO1__FUNC_TDMIN_DI>, 754 <PINMUX_GPIO2__FUNC_TDMIN_LRCK>, 755 <PINMUX_GPIO3__FUNC_TDMIN_BCK>, 756 <PINMUX_GPIO60__FUNC_I2SO2_D0>, 757 <PINMUX_GPIO49__FUNC_I2SIN_D0>, 758 <PINMUX_GPIO50__FUNC_I2SO1_MCK>, 759 <PINMUX_GPIO51__FUNC_I2SO1_BCK>, 760 <PINMUX_GPIO52__FUNC_I2SO1_WS>, 761 <PINMUX_GPIO53__FUNC_I2SO1_D0>; 762 }; 763 764 pins-hp-jack-int-odl { 765 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>; 766 input-enable; 767 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 768 }; 769 }; 770 771 cr50_int: cr50-irq-default-pins { 772 pins-gsc-ap-int-odl { 773 pinmux = <PINMUX_GPIO88__FUNC_GPIO88>; 774 input-enable; 775 }; 776 }; 777 778 cros_ec_int: cros-ec-irq-default-pins { 779 pins-ec-ap-int-odl { 780 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 781 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 782 input-enable; 783 }; 784 }; 785 786 edptx_pins_default: edptx-default-pins { 787 pins-cmd-dat { 788 pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>; 789 bias-pull-up; 790 }; 791 }; 792 793 disp_pwm0_pin_default: disp-pwm0-default-pins { 794 pins-disp-pwm { 795 pinmux = <PINMUX_GPIO82__FUNC_GPIO82>, 796 <PINMUX_GPIO97__FUNC_DISP_PWM0>; 797 }; 798 }; 799 800 dptx_pin: dptx-default-pins { 801 pins-cmd-dat { 802 pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>; 803 bias-pull-up; 804 }; 805 }; 806 807 i2c0_pins: i2c0-default-pins { 808 pins-bus { 809 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 810 <PINMUX_GPIO9__FUNC_SCL0>; 811 bias-disable; 812 drive-strength-microamp = <1000>; 813 }; 814 }; 815 816 i2c1_pins: i2c1-default-pins { 817 pins-bus { 818 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 819 <PINMUX_GPIO11__FUNC_SCL1>; 820 bias-pull-up = <1000>; 821 drive-strength-microamp = <1000>; 822 }; 823 }; 824 825 i2c2_pins: i2c2-default-pins { 826 pins-bus { 827 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 828 <PINMUX_GPIO13__FUNC_SCL2>; 829 bias-disable; 830 drive-strength-microamp = <1000>; 831 }; 832 }; 833 834 i2c3_pins: i2c3-default-pins { 835 pins-bus { 836 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 837 <PINMUX_GPIO15__FUNC_SCL3>; 838 bias-pull-up = <1000>; 839 drive-strength-microamp = <1000>; 840 }; 841 }; 842 843 i2c4_pins: i2c4-default-pins { 844 pins-bus { 845 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 846 <PINMUX_GPIO17__FUNC_SCL4>; 847 bias-pull-up = <1000>; 848 drive-strength = <4>; 849 }; 850 }; 851 852 i2c5_pins: i2c5-default-pins { 853 pins-bus { 854 pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 855 <PINMUX_GPIO30__FUNC_SDA5>; 856 bias-disable; 857 drive-strength-microamp = <1000>; 858 }; 859 }; 860 861 i2c7_pins: i2c7-default-pins { 862 pins-bus { 863 pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 864 <PINMUX_GPIO28__FUNC_SDA7>; 865 bias-disable; 866 }; 867 }; 868 869 mmc0_pins_default: mmc0-default-pins { 870 pins-cmd-dat { 871 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 872 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 873 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 874 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 875 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 876 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 877 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 878 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 879 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 880 input-enable; 881 drive-strength = <6>; 882 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 883 }; 884 885 pins-clk { 886 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 887 drive-strength = <6>; 888 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 889 }; 890 891 pins-rst { 892 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 893 drive-strength = <6>; 894 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 895 }; 896 }; 897 898 mmc0_pins_uhs: mmc0-uhs-pins { 899 pins-cmd-dat { 900 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 901 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 902 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 903 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 904 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 905 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 906 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 907 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 908 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 909 input-enable; 910 drive-strength = <8>; 911 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 912 }; 913 914 pins-clk { 915 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 916 drive-strength = <8>; 917 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 918 }; 919 920 pins-ds { 921 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 922 drive-strength = <8>; 923 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 924 }; 925 926 pins-rst { 927 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 928 drive-strength = <8>; 929 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 930 }; 931 }; 932 933 mmc1_pins_detect: mmc1-detect-pins { 934 pins-insert { 935 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; 936 bias-pull-up; 937 }; 938 }; 939 940 mmc1_pins_default: mmc1-default-pins { 941 pins-cmd-dat { 942 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 943 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 944 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 945 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 946 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 947 input-enable; 948 drive-strength = <8>; 949 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 950 }; 951 952 pins-clk { 953 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 954 drive-strength = <8>; 955 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 956 }; 957 }; 958 959 nor_pins_default: nor-default-pins { 960 pins-ck-io { 961 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 962 <PINMUX_GPIO141__FUNC_SPINOR_CK>, 963 <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 964 drive-strength = <6>; 965 bias-pull-down; 966 }; 967 968 pins-cs { 969 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; 970 drive-strength = <6>; 971 bias-pull-up; 972 }; 973 }; 974 975 pcie0_pins_default: pcie0-default-pins { 976 pins-bus { 977 pinmux = <PINMUX_GPIO19__FUNC_WAKEN>, 978 <PINMUX_GPIO20__FUNC_PERSTN>, 979 <PINMUX_GPIO21__FUNC_CLKREQN>; 980 bias-pull-up; 981 }; 982 }; 983 984 pcie1_pins_default: pcie1-default-pins { 985 pins-bus { 986 pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>, 987 <PINMUX_GPIO23__FUNC_CLKREQN_1>, 988 <PINMUX_GPIO24__FUNC_WAKEN_1>; 989 bias-pull-up; 990 }; 991 }; 992 993 panel_fixed_pins: panel-pwr-default-pins { 994 pins-vreg-en { 995 pinmux = <PINMUX_GPIO55__FUNC_GPIO55>; 996 }; 997 }; 998 999 pio_default: pio-default-pins { 1000 pins-wifi-enable { 1001 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 1002 output-high; 1003 drive-strength = <14>; 1004 }; 1005 1006 pins-low-power-pd { 1007 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 1008 <PINMUX_GPIO26__FUNC_GPIO26>, 1009 <PINMUX_GPIO46__FUNC_GPIO46>, 1010 <PINMUX_GPIO47__FUNC_GPIO47>, 1011 <PINMUX_GPIO48__FUNC_GPIO48>, 1012 <PINMUX_GPIO65__FUNC_GPIO65>, 1013 <PINMUX_GPIO66__FUNC_GPIO66>, 1014 <PINMUX_GPIO67__FUNC_GPIO67>, 1015 <PINMUX_GPIO68__FUNC_GPIO68>, 1016 <PINMUX_GPIO128__FUNC_GPIO128>, 1017 <PINMUX_GPIO129__FUNC_GPIO129>; 1018 input-enable; 1019 bias-pull-down; 1020 }; 1021 1022 pins-low-power-pupd { 1023 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 1024 <PINMUX_GPIO78__FUNC_GPIO78>, 1025 <PINMUX_GPIO79__FUNC_GPIO79>, 1026 <PINMUX_GPIO80__FUNC_GPIO80>, 1027 <PINMUX_GPIO83__FUNC_GPIO83>, 1028 <PINMUX_GPIO85__FUNC_GPIO85>, 1029 <PINMUX_GPIO90__FUNC_GPIO90>, 1030 <PINMUX_GPIO91__FUNC_GPIO91>, 1031 <PINMUX_GPIO93__FUNC_GPIO93>, 1032 <PINMUX_GPIO94__FUNC_GPIO94>, 1033 <PINMUX_GPIO95__FUNC_GPIO95>, 1034 <PINMUX_GPIO96__FUNC_GPIO96>, 1035 <PINMUX_GPIO104__FUNC_GPIO104>, 1036 <PINMUX_GPIO105__FUNC_GPIO105>, 1037 <PINMUX_GPIO107__FUNC_GPIO107>; 1038 input-enable; 1039 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1040 }; 1041 }; 1042 1043 rt1019p_pins_default: rt1019p-default-pins { 1044 pins-amp-sdb { 1045 pinmux = <PINMUX_GPIO100__FUNC_GPIO100>; 1046 output-low; 1047 }; 1048 }; 1049 1050 scp_pins: scp-default-pins { 1051 pins-vreq { 1052 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; 1053 bias-disable; 1054 input-enable; 1055 }; 1056 }; 1057 1058 spi0_pins: spi0-default-pins { 1059 pins-cs-mosi-clk { 1060 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 1061 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 1062 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 1063 bias-disable; 1064 }; 1065 1066 pins-miso { 1067 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 1068 bias-pull-down; 1069 }; 1070 }; 1071 1072 subpmic_default: subpmic-default-pins { 1073 subpmic_pin_irq: pins-subpmic-int-n { 1074 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; 1075 input-enable; 1076 bias-pull-up; 1077 }; 1078 }; 1079 1080 trackpad_pins: trackpad-default-pins { 1081 pins-int-n { 1082 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 1083 input-enable; 1084 bias-pull-up; 1085 }; 1086 }; 1087 1088 touchscreen_pins: touchscreen-default-pins { 1089 pins-int-n { 1090 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; 1091 input-enable; 1092 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1093 }; 1094 pins-rst { 1095 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; 1096 output-high; 1097 }; 1098 pins-report-sw { 1099 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; 1100 output-low; 1101 }; 1102 }; 1103}; 1104 1105&pmic { 1106 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 1107}; 1108 1109&scp { 1110 status = "okay"; 1111 1112 firmware-name = "mediatek/mt8195/scp.img"; 1113 memory-region = <&scp_mem>; 1114 pinctrl-names = "default"; 1115 pinctrl-0 = <&scp_pins>; 1116 1117 cros-ec-rpmsg { 1118 compatible = "google,cros-ec-rpmsg"; 1119 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1120 }; 1121}; 1122 1123&sound { 1124 status = "okay"; 1125 1126 mediatek,adsp = <&adsp>; 1127 mediatek,dai-link = 1128 "DL10_FE", "DPTX_BE", "ETDM1_IN_BE", "ETDM2_IN_BE", 1129 "ETDM1_OUT_BE", "ETDM2_OUT_BE","UL_SRC1_BE", 1130 "AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5"; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&aud_pins_default>; 1133}; 1134 1135&spi0 { 1136 status = "okay"; 1137 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&spi0_pins>; 1140 mediatek,pad-select = <0>; 1141 1142 cros_ec: ec@0 { 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 1146 compatible = "google,cros-ec-spi"; 1147 reg = <0>; 1148 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; 1149 pinctrl-names = "default"; 1150 pinctrl-0 = <&cros_ec_int>; 1151 spi-max-frequency = <3000000>; 1152 wakeup-source; 1153 1154 keyboard-backlight { 1155 compatible = "google,cros-kbd-led-backlight"; 1156 }; 1157 1158 i2c_tunnel: i2c-tunnel { 1159 compatible = "google,cros-ec-i2c-tunnel"; 1160 google,remote-bus = <0>; 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 }; 1164 1165 mt_pmic_vmc_ldo_reg: regulator@0 { 1166 compatible = "google,cros-ec-regulator"; 1167 reg = <0>; 1168 regulator-name = "mt_pmic_vmc_ldo"; 1169 regulator-min-microvolt = <1200000>; 1170 regulator-max-microvolt = <3600000>; 1171 }; 1172 1173 mt_pmic_vmch_ldo_reg: regulator@1 { 1174 compatible = "google,cros-ec-regulator"; 1175 reg = <1>; 1176 regulator-name = "mt_pmic_vmch_ldo"; 1177 regulator-min-microvolt = <2700000>; 1178 regulator-max-microvolt = <3600000>; 1179 }; 1180 1181 typec { 1182 compatible = "google,cros-ec-typec"; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 1186 usb_c0: connector@0 { 1187 compatible = "usb-c-connector"; 1188 reg = <0>; 1189 power-role = "dual"; 1190 data-role = "host"; 1191 try-power-role = "source"; 1192 }; 1193 1194 usb_c1: connector@1 { 1195 compatible = "usb-c-connector"; 1196 reg = <1>; 1197 power-role = "dual"; 1198 data-role = "host"; 1199 try-power-role = "source"; 1200 }; 1201 }; 1202 }; 1203}; 1204 1205&spmi { 1206 #address-cells = <2>; 1207 #size-cells = <0>; 1208 1209 mt6315@6 { 1210 compatible = "mediatek,mt6315-regulator"; 1211 reg = <0x6 SPMI_USID>; 1212 1213 regulators { 1214 mt6315_6_vbuck1: vbuck1 { 1215 regulator-compatible = "vbuck1"; 1216 regulator-name = "Vbcpu"; 1217 regulator-min-microvolt = <300000>; 1218 regulator-max-microvolt = <1193750>; 1219 regulator-enable-ramp-delay = <256>; 1220 regulator-ramp-delay = <6250>; 1221 regulator-allowed-modes = <0 1 2>; 1222 regulator-always-on; 1223 }; 1224 }; 1225 }; 1226 1227 mt6315@7 { 1228 compatible = "mediatek,mt6315-regulator"; 1229 reg = <0x7 SPMI_USID>; 1230 1231 regulators { 1232 mt6315_7_vbuck1: vbuck1 { 1233 regulator-compatible = "vbuck1"; 1234 regulator-name = "Vgpu"; 1235 regulator-min-microvolt = <625000>; 1236 regulator-max-microvolt = <1193750>; 1237 regulator-enable-ramp-delay = <256>; 1238 regulator-ramp-delay = <6250>; 1239 regulator-allowed-modes = <0 1 2>; 1240 }; 1241 }; 1242 }; 1243}; 1244 1245&thermal_zones { 1246 soc-area-thermal { 1247 polling-delay = <1000>; 1248 polling-delay-passive = <250>; 1249 thermal-sensors = <&tboard_thermistor1>; 1250 1251 trips { 1252 trip-crit { 1253 temperature = <84000>; 1254 hysteresis = <1000>; 1255 type = "critical"; 1256 }; 1257 }; 1258 }; 1259 1260 pmic-area-thermal { 1261 polling-delay = <1000>; 1262 polling-delay-passive = <0>; 1263 thermal-sensors = <&tboard_thermistor2>; 1264 1265 trips { 1266 trip-crit { 1267 temperature = <84000>; 1268 hysteresis = <1000>; 1269 type = "critical"; 1270 }; 1271 }; 1272 }; 1273}; 1274 1275&u3phy0 { 1276 status = "okay"; 1277}; 1278 1279&u3phy1 { 1280 status = "okay"; 1281}; 1282 1283&u3phy2 { 1284 status = "okay"; 1285}; 1286 1287&u3phy3 { 1288 status = "okay"; 1289}; 1290 1291&uart0 { 1292 status = "okay"; 1293}; 1294 1295/* 1296 * For the USB Type-C ports the role and alternate modes switching is 1297 * done by the EC so we set dr_mode to host to avoid interfering. 1298 */ 1299&ssusb0 { 1300 dr_mode = "host"; 1301 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1302 status = "okay"; 1303}; 1304 1305&ssusb2 { 1306 dr_mode = "host"; 1307 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1308 status = "okay"; 1309}; 1310 1311&ssusb3 { 1312 dr_mode = "host"; 1313 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1314 status = "okay"; 1315}; 1316 1317&xhci0 { 1318 status = "okay"; 1319 1320 rx-fifo-depth = <3072>; 1321 vbus-supply = <&usb_vbus>; 1322}; 1323 1324&xhci1 { 1325 status = "okay"; 1326 1327 rx-fifo-depth = <3072>; 1328 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1329 vbus-supply = <&usb_vbus>; 1330}; 1331 1332&xhci2 { 1333 status = "okay"; 1334 vbus-supply = <&usb_vbus>; 1335}; 1336 1337&xhci3 { 1338 status = "okay"; 1339 1340 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 1341 usb2-lpm-disable; 1342 vbus-supply = <&usb_vbus>; 1343}; 1344 1345#include <arm/cros-ec-keyboard.dtsi> 1346#include <arm/cros-ec-sbs.dtsi> 1347 1348&keyboard_controller { 1349 function-row-physmap = < 1350 MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 1351 MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 1352 MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 1353 MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 1354 MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 1355 MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 1356 MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 1357 MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 1358 MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 1359 MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 1360 >; 1361 1362 linux,keymap = < 1363 MATRIX_KEY(0x00, 0x02, KEY_BACK) 1364 MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 1365 MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 1366 MATRIX_KEY(0x01, 0x02, KEY_SCALE) 1367 MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) 1368 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 1369 MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 1370 MATRIX_KEY(0x02, 0x09, KEY_MUTE) 1371 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 1372 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 1373 1374 CROS_STD_MAIN_KEYMAP 1375 >; 1376}; 1377