1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8192-clk.h> 9#include <dt-bindings/gce/mt8192-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8192-larb-port.h> 13#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/power/mt8192-power.h> 16#include <dt-bindings/reset/mt8192-resets.h> 17#include <dt-bindings/thermal/thermal.h> 18#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 19 20/ { 21 compatible = "mediatek,mt8192"; 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 ovl0 = &ovl0; 28 ovl-2l0 = &ovl_2l0; 29 ovl-2l2 = &ovl_2l2; 30 rdma0 = &rdma0; 31 rdma4 = &rdma4; 32 }; 33 34 clk13m: fixed-factor-clock-13m { 35 compatible = "fixed-factor-clock"; 36 #clock-cells = <0>; 37 clocks = <&clk26m>; 38 clock-div = <2>; 39 clock-mult = <1>; 40 clock-output-names = "clk13m"; 41 }; 42 43 clk26m: oscillator0 { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <26000000>; 47 clock-output-names = "clk26m"; 48 }; 49 50 clk32k: oscillator1 { 51 compatible = "fixed-clock"; 52 #clock-cells = <0>; 53 clock-frequency = <32768>; 54 clock-output-names = "clk32k"; 55 }; 56 57 cpus { 58 #address-cells = <1>; 59 #size-cells = <0>; 60 61 cpu0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a55"; 64 reg = <0x000>; 65 enable-method = "psci"; 66 clock-frequency = <1701000000>; 67 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 68 i-cache-size = <32768>; 69 i-cache-line-size = <64>; 70 i-cache-sets = <128>; 71 d-cache-size = <32768>; 72 d-cache-line-size = <64>; 73 d-cache-sets = <128>; 74 next-level-cache = <&l2_0>; 75 performance-domains = <&performance 0>; 76 capacity-dmips-mhz = <427>; 77 #cooling-cells = <2>; 78 }; 79 80 cpu1: cpu@100 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x100>; 84 enable-method = "psci"; 85 clock-frequency = <1701000000>; 86 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 87 i-cache-size = <32768>; 88 i-cache-line-size = <64>; 89 i-cache-sets = <128>; 90 d-cache-size = <32768>; 91 d-cache-line-size = <64>; 92 d-cache-sets = <128>; 93 next-level-cache = <&l2_0>; 94 performance-domains = <&performance 0>; 95 capacity-dmips-mhz = <427>; 96 #cooling-cells = <2>; 97 }; 98 99 cpu2: cpu@200 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a55"; 102 reg = <0x200>; 103 enable-method = "psci"; 104 clock-frequency = <1701000000>; 105 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 106 i-cache-size = <32768>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <128>; 109 d-cache-size = <32768>; 110 d-cache-line-size = <64>; 111 d-cache-sets = <128>; 112 next-level-cache = <&l2_0>; 113 performance-domains = <&performance 0>; 114 capacity-dmips-mhz = <427>; 115 #cooling-cells = <2>; 116 }; 117 118 cpu3: cpu@300 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a55"; 121 reg = <0x300>; 122 enable-method = "psci"; 123 clock-frequency = <1701000000>; 124 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 125 i-cache-size = <32768>; 126 i-cache-line-size = <64>; 127 i-cache-sets = <128>; 128 d-cache-size = <32768>; 129 d-cache-line-size = <64>; 130 d-cache-sets = <128>; 131 next-level-cache = <&l2_0>; 132 performance-domains = <&performance 0>; 133 capacity-dmips-mhz = <427>; 134 #cooling-cells = <2>; 135 }; 136 137 cpu4: cpu@400 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a76"; 140 reg = <0x400>; 141 enable-method = "psci"; 142 clock-frequency = <2171000000>; 143 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 144 i-cache-size = <65536>; 145 i-cache-line-size = <64>; 146 i-cache-sets = <256>; 147 d-cache-size = <65536>; 148 d-cache-line-size = <64>; 149 d-cache-sets = <256>; 150 next-level-cache = <&l2_1>; 151 performance-domains = <&performance 1>; 152 capacity-dmips-mhz = <1024>; 153 #cooling-cells = <2>; 154 }; 155 156 cpu5: cpu@500 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-a76"; 159 reg = <0x500>; 160 enable-method = "psci"; 161 clock-frequency = <2171000000>; 162 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 163 i-cache-size = <65536>; 164 i-cache-line-size = <64>; 165 i-cache-sets = <256>; 166 d-cache-size = <65536>; 167 d-cache-line-size = <64>; 168 d-cache-sets = <256>; 169 next-level-cache = <&l2_1>; 170 performance-domains = <&performance 1>; 171 capacity-dmips-mhz = <1024>; 172 #cooling-cells = <2>; 173 }; 174 175 cpu6: cpu@600 { 176 device_type = "cpu"; 177 compatible = "arm,cortex-a76"; 178 reg = <0x600>; 179 enable-method = "psci"; 180 clock-frequency = <2171000000>; 181 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 182 i-cache-size = <65536>; 183 i-cache-line-size = <64>; 184 i-cache-sets = <256>; 185 d-cache-size = <65536>; 186 d-cache-line-size = <64>; 187 d-cache-sets = <256>; 188 next-level-cache = <&l2_1>; 189 performance-domains = <&performance 1>; 190 capacity-dmips-mhz = <1024>; 191 #cooling-cells = <2>; 192 }; 193 194 cpu7: cpu@700 { 195 device_type = "cpu"; 196 compatible = "arm,cortex-a76"; 197 reg = <0x700>; 198 enable-method = "psci"; 199 clock-frequency = <2171000000>; 200 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 201 i-cache-size = <65536>; 202 i-cache-line-size = <64>; 203 i-cache-sets = <256>; 204 d-cache-size = <65536>; 205 d-cache-line-size = <64>; 206 d-cache-sets = <256>; 207 next-level-cache = <&l2_1>; 208 performance-domains = <&performance 1>; 209 capacity-dmips-mhz = <1024>; 210 #cooling-cells = <2>; 211 }; 212 213 cpu-map { 214 cluster0 { 215 core0 { 216 cpu = <&cpu0>; 217 }; 218 core1 { 219 cpu = <&cpu1>; 220 }; 221 core2 { 222 cpu = <&cpu2>; 223 }; 224 core3 { 225 cpu = <&cpu3>; 226 }; 227 core4 { 228 cpu = <&cpu4>; 229 }; 230 core5 { 231 cpu = <&cpu5>; 232 }; 233 core6 { 234 cpu = <&cpu6>; 235 }; 236 core7 { 237 cpu = <&cpu7>; 238 }; 239 }; 240 }; 241 242 l2_0: l2-cache0 { 243 compatible = "cache"; 244 cache-level = <2>; 245 cache-size = <131072>; 246 cache-line-size = <64>; 247 cache-sets = <512>; 248 next-level-cache = <&l3_0>; 249 cache-unified; 250 }; 251 252 l2_1: l2-cache1 { 253 compatible = "cache"; 254 cache-level = <2>; 255 cache-size = <262144>; 256 cache-line-size = <64>; 257 cache-sets = <512>; 258 next-level-cache = <&l3_0>; 259 cache-unified; 260 }; 261 262 l3_0: l3-cache { 263 compatible = "cache"; 264 cache-level = <3>; 265 cache-size = <2097152>; 266 cache-line-size = <64>; 267 cache-sets = <2048>; 268 cache-unified; 269 }; 270 271 idle-states { 272 entry-method = "psci"; 273 cpu_ret_l: cpu-retention-l { 274 compatible = "arm,idle-state"; 275 arm,psci-suspend-param = <0x00010001>; 276 local-timer-stop; 277 entry-latency-us = <55>; 278 exit-latency-us = <140>; 279 min-residency-us = <780>; 280 }; 281 cpu_ret_b: cpu-retention-b { 282 compatible = "arm,idle-state"; 283 arm,psci-suspend-param = <0x00010001>; 284 local-timer-stop; 285 entry-latency-us = <35>; 286 exit-latency-us = <145>; 287 min-residency-us = <720>; 288 }; 289 cpu_off_l: cpu-off-l { 290 compatible = "arm,idle-state"; 291 arm,psci-suspend-param = <0x01010002>; 292 local-timer-stop; 293 entry-latency-us = <60>; 294 exit-latency-us = <155>; 295 min-residency-us = <860>; 296 }; 297 cpu_off_b: cpu-off-b { 298 compatible = "arm,idle-state"; 299 arm,psci-suspend-param = <0x01010002>; 300 local-timer-stop; 301 entry-latency-us = <40>; 302 exit-latency-us = <155>; 303 min-residency-us = <780>; 304 }; 305 }; 306 }; 307 308 pmu-a55 { 309 compatible = "arm,cortex-a55-pmu"; 310 interrupt-parent = <&gic>; 311 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 312 }; 313 314 pmu-a76 { 315 compatible = "arm,cortex-a76-pmu"; 316 interrupt-parent = <&gic>; 317 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 318 }; 319 320 psci { 321 compatible = "arm,psci-1.0"; 322 method = "smc"; 323 }; 324 325 timer: timer { 326 compatible = "arm,armv8-timer"; 327 interrupt-parent = <&gic>; 328 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 329 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 330 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 331 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 332 clock-frequency = <13000000>; 333 }; 334 335 gpu_opp_table: opp-table-0 { 336 compatible = "operating-points-v2"; 337 opp-shared; 338 339 opp-358000000 { 340 opp-hz = /bits/ 64 <358000000>; 341 opp-microvolt = <606250>; 342 }; 343 344 opp-399000000 { 345 opp-hz = /bits/ 64 <399000000>; 346 opp-microvolt = <618750>; 347 }; 348 349 opp-440000000 { 350 opp-hz = /bits/ 64 <440000000>; 351 opp-microvolt = <631250>; 352 }; 353 354 opp-482000000 { 355 opp-hz = /bits/ 64 <482000000>; 356 opp-microvolt = <643750>; 357 }; 358 359 opp-523000000 { 360 opp-hz = /bits/ 64 <523000000>; 361 opp-microvolt = <656250>; 362 }; 363 364 opp-564000000 { 365 opp-hz = /bits/ 64 <564000000>; 366 opp-microvolt = <668750>; 367 }; 368 369 opp-605000000 { 370 opp-hz = /bits/ 64 <605000000>; 371 opp-microvolt = <681250>; 372 }; 373 374 opp-647000000 { 375 opp-hz = /bits/ 64 <647000000>; 376 opp-microvolt = <693750>; 377 }; 378 379 opp-688000000 { 380 opp-hz = /bits/ 64 <688000000>; 381 opp-microvolt = <706250>; 382 }; 383 384 opp-724000000 { 385 opp-hz = /bits/ 64 <724000000>; 386 opp-microvolt = <725000>; 387 }; 388 389 opp-748000000 { 390 opp-hz = /bits/ 64 <748000000>; 391 opp-microvolt = <737500>; 392 }; 393 394 opp-772000000 { 395 opp-hz = /bits/ 64 <772000000>; 396 opp-microvolt = <750000>; 397 }; 398 399 opp-795000000 { 400 opp-hz = /bits/ 64 <795000000>; 401 opp-microvolt = <762500>; 402 }; 403 404 opp-819000000 { 405 opp-hz = /bits/ 64 <819000000>; 406 opp-microvolt = <775000>; 407 }; 408 409 opp-843000000 { 410 opp-hz = /bits/ 64 <843000000>; 411 opp-microvolt = <787500>; 412 }; 413 414 opp-866000000 { 415 opp-hz = /bits/ 64 <866000000>; 416 opp-microvolt = <800000>; 417 }; 418 }; 419 420 soc { 421 #address-cells = <2>; 422 #size-cells = <2>; 423 compatible = "simple-bus"; 424 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 425 ranges; 426 427 performance: performance-controller@11bc10 { 428 compatible = "mediatek,cpufreq-hw"; 429 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 430 #performance-domain-cells = <1>; 431 }; 432 433 gic: interrupt-controller@c000000 { 434 compatible = "arm,gic-v3"; 435 #interrupt-cells = <4>; 436 #redistributor-regions = <1>; 437 interrupt-parent = <&gic>; 438 interrupt-controller; 439 reg = <0 0x0c000000 0 0x40000>, 440 <0 0x0c040000 0 0x200000>; 441 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 442 443 ppi-partitions { 444 ppi_cluster0: interrupt-partition-0 { 445 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 446 }; 447 ppi_cluster1: interrupt-partition-1 { 448 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 449 }; 450 }; 451 }; 452 453 topckgen: syscon@10000000 { 454 compatible = "mediatek,mt8192-topckgen", "syscon"; 455 reg = <0 0x10000000 0 0x1000>; 456 #clock-cells = <1>; 457 }; 458 459 infracfg: syscon@10001000 { 460 compatible = "mediatek,mt8192-infracfg", "syscon"; 461 reg = <0 0x10001000 0 0x1000>; 462 #clock-cells = <1>; 463 #reset-cells = <1>; 464 }; 465 466 pericfg: syscon@10003000 { 467 compatible = "mediatek,mt8192-pericfg", "syscon"; 468 reg = <0 0x10003000 0 0x1000>; 469 #clock-cells = <1>; 470 }; 471 472 pio: pinctrl@10005000 { 473 compatible = "mediatek,mt8192-pinctrl"; 474 reg = <0 0x10005000 0 0x1000>, 475 <0 0x11c20000 0 0x1000>, 476 <0 0x11d10000 0 0x1000>, 477 <0 0x11d30000 0 0x1000>, 478 <0 0x11d40000 0 0x1000>, 479 <0 0x11e20000 0 0x1000>, 480 <0 0x11e70000 0 0x1000>, 481 <0 0x11ea0000 0 0x1000>, 482 <0 0x11f20000 0 0x1000>, 483 <0 0x11f30000 0 0x1000>, 484 <0 0x1000b000 0 0x1000>; 485 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 486 "iocfg_bl", "iocfg_br", "iocfg_lm", 487 "iocfg_lb", "iocfg_rt", "iocfg_lt", 488 "iocfg_tl", "eint"; 489 gpio-controller; 490 #gpio-cells = <2>; 491 gpio-ranges = <&pio 0 0 220>; 492 interrupt-controller; 493 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 494 #interrupt-cells = <2>; 495 }; 496 497 scpsys: syscon@10006000 { 498 compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd"; 499 reg = <0 0x10006000 0 0x1000>; 500 501 /* System Power Manager */ 502 spm: power-controller { 503 compatible = "mediatek,mt8192-power-controller"; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 #power-domain-cells = <1>; 507 508 /* power domain of the SoC */ 509 power-domain@MT8192_POWER_DOMAIN_AUDIO { 510 reg = <MT8192_POWER_DOMAIN_AUDIO>; 511 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 512 <&infracfg CLK_INFRA_AUDIO_26M_B>, 513 <&infracfg CLK_INFRA_AUDIO>; 514 clock-names = "audio", "audio1", "audio2"; 515 mediatek,infracfg = <&infracfg>; 516 #power-domain-cells = <0>; 517 }; 518 519 power-domain@MT8192_POWER_DOMAIN_CONN { 520 reg = <MT8192_POWER_DOMAIN_CONN>; 521 clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 522 clock-names = "conn"; 523 mediatek,infracfg = <&infracfg>; 524 #power-domain-cells = <0>; 525 }; 526 527 mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 { 528 reg = <MT8192_POWER_DOMAIN_MFG0>; 529 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>, 530 <&topckgen CLK_TOP_MFG_REF_SEL>; 531 clock-names = "mfg", "alt"; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 #power-domain-cells = <1>; 535 536 mfg1: power-domain@MT8192_POWER_DOMAIN_MFG1 { 537 reg = <MT8192_POWER_DOMAIN_MFG1>; 538 mediatek,infracfg = <&infracfg>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 #power-domain-cells = <1>; 542 543 power-domain@MT8192_POWER_DOMAIN_MFG2 { 544 reg = <MT8192_POWER_DOMAIN_MFG2>; 545 #power-domain-cells = <0>; 546 }; 547 548 power-domain@MT8192_POWER_DOMAIN_MFG3 { 549 reg = <MT8192_POWER_DOMAIN_MFG3>; 550 #power-domain-cells = <0>; 551 }; 552 553 power-domain@MT8192_POWER_DOMAIN_MFG4 { 554 reg = <MT8192_POWER_DOMAIN_MFG4>; 555 #power-domain-cells = <0>; 556 }; 557 558 power-domain@MT8192_POWER_DOMAIN_MFG5 { 559 reg = <MT8192_POWER_DOMAIN_MFG5>; 560 #power-domain-cells = <0>; 561 }; 562 563 power-domain@MT8192_POWER_DOMAIN_MFG6 { 564 reg = <MT8192_POWER_DOMAIN_MFG6>; 565 #power-domain-cells = <0>; 566 }; 567 }; 568 }; 569 570 power-domain@MT8192_POWER_DOMAIN_DISP { 571 reg = <MT8192_POWER_DOMAIN_DISP>; 572 clocks = <&topckgen CLK_TOP_DISP_SEL>, 573 <&mmsys CLK_MM_SMI_INFRA>, 574 <&mmsys CLK_MM_SMI_COMMON>, 575 <&mmsys CLK_MM_SMI_GALS>, 576 <&mmsys CLK_MM_SMI_IOMMU>; 577 clock-names = "disp", "disp-0", "disp-1", "disp-2", 578 "disp-3"; 579 mediatek,infracfg = <&infracfg>; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 #power-domain-cells = <1>; 583 584 power-domain@MT8192_POWER_DOMAIN_IPE { 585 reg = <MT8192_POWER_DOMAIN_IPE>; 586 clocks = <&topckgen CLK_TOP_IPE_SEL>, 587 <&ipesys CLK_IPE_LARB19>, 588 <&ipesys CLK_IPE_LARB20>, 589 <&ipesys CLK_IPE_SMI_SUBCOM>, 590 <&ipesys CLK_IPE_GALS>; 591 clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 592 "ipe-3"; 593 mediatek,infracfg = <&infracfg>; 594 #power-domain-cells = <0>; 595 }; 596 597 power-domain@MT8192_POWER_DOMAIN_ISP { 598 reg = <MT8192_POWER_DOMAIN_ISP>; 599 clocks = <&topckgen CLK_TOP_IMG1_SEL>, 600 <&imgsys CLK_IMG_LARB9>, 601 <&imgsys CLK_IMG_GALS>; 602 clock-names = "isp", "isp-0", "isp-1"; 603 mediatek,infracfg = <&infracfg>; 604 #power-domain-cells = <0>; 605 }; 606 607 power-domain@MT8192_POWER_DOMAIN_ISP2 { 608 reg = <MT8192_POWER_DOMAIN_ISP2>; 609 clocks = <&topckgen CLK_TOP_IMG2_SEL>, 610 <&imgsys2 CLK_IMG2_LARB11>, 611 <&imgsys2 CLK_IMG2_GALS>; 612 clock-names = "isp2", "isp2-0", "isp2-1"; 613 mediatek,infracfg = <&infracfg>; 614 #power-domain-cells = <0>; 615 }; 616 617 power-domain@MT8192_POWER_DOMAIN_MDP { 618 reg = <MT8192_POWER_DOMAIN_MDP>; 619 clocks = <&topckgen CLK_TOP_MDP_SEL>, 620 <&mdpsys CLK_MDP_SMI0>; 621 clock-names = "mdp", "mdp-0"; 622 mediatek,infracfg = <&infracfg>; 623 #power-domain-cells = <0>; 624 }; 625 626 power-domain@MT8192_POWER_DOMAIN_VENC { 627 reg = <MT8192_POWER_DOMAIN_VENC>; 628 clocks = <&topckgen CLK_TOP_VENC_SEL>, 629 <&vencsys CLK_VENC_SET1_VENC>; 630 clock-names = "venc", "venc-0"; 631 mediatek,infracfg = <&infracfg>; 632 #power-domain-cells = <0>; 633 }; 634 635 power-domain@MT8192_POWER_DOMAIN_VDEC { 636 reg = <MT8192_POWER_DOMAIN_VDEC>; 637 clocks = <&topckgen CLK_TOP_VDEC_SEL>, 638 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 639 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 640 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 641 clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 642 mediatek,infracfg = <&infracfg>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 #power-domain-cells = <1>; 646 647 power-domain@MT8192_POWER_DOMAIN_VDEC2 { 648 reg = <MT8192_POWER_DOMAIN_VDEC2>; 649 clocks = <&vdecsys CLK_VDEC_VDEC>, 650 <&vdecsys CLK_VDEC_LAT>, 651 <&vdecsys CLK_VDEC_LARB1>; 652 clock-names = "vdec2-0", "vdec2-1", 653 "vdec2-2"; 654 #power-domain-cells = <0>; 655 }; 656 }; 657 658 power-domain@MT8192_POWER_DOMAIN_CAM { 659 reg = <MT8192_POWER_DOMAIN_CAM>; 660 clocks = <&topckgen CLK_TOP_CAM_SEL>, 661 <&camsys CLK_CAM_LARB13>, 662 <&camsys CLK_CAM_LARB14>, 663 <&camsys CLK_CAM_CCU_GALS>, 664 <&camsys CLK_CAM_CAM2MM_GALS>; 665 clock-names = "cam", "cam-0", "cam-1", "cam-2", 666 "cam-3"; 667 mediatek,infracfg = <&infracfg>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 #power-domain-cells = <1>; 671 672 power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 673 reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 674 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 675 clock-names = "cam_rawa-0"; 676 #power-domain-cells = <0>; 677 }; 678 679 power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 680 reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 681 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 682 clock-names = "cam_rawb-0"; 683 #power-domain-cells = <0>; 684 }; 685 686 power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 687 reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 688 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 689 clock-names = "cam_rawc-0"; 690 #power-domain-cells = <0>; 691 }; 692 }; 693 }; 694 }; 695 }; 696 697 watchdog: watchdog@10007000 { 698 compatible = "mediatek,mt8192-wdt"; 699 reg = <0 0x10007000 0 0x100>; 700 #reset-cells = <1>; 701 }; 702 703 apmixedsys: syscon@1000c000 { 704 compatible = "mediatek,mt8192-apmixedsys", "syscon"; 705 reg = <0 0x1000c000 0 0x1000>; 706 #clock-cells = <1>; 707 }; 708 709 systimer: timer@10017000 { 710 compatible = "mediatek,mt8192-timer", 711 "mediatek,mt6765-timer"; 712 reg = <0 0x10017000 0 0x1000>; 713 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 714 clocks = <&clk13m>; 715 }; 716 717 pwrap: pwrap@10026000 { 718 compatible = "mediatek,mt6873-pwrap"; 719 reg = <0 0x10026000 0 0x1000>; 720 reg-names = "pwrap"; 721 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 722 clocks = <&infracfg CLK_INFRA_PMIC_AP>, 723 <&infracfg CLK_INFRA_PMIC_TMR>; 724 clock-names = "spi", "wrap"; 725 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 726 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 727 }; 728 729 spmi: spmi@10027000 { 730 compatible = "mediatek,mt6873-spmi"; 731 reg = <0 0x10027000 0 0x000e00>, 732 <0 0x10029000 0 0x000100>; 733 reg-names = "pmif", "spmimst"; 734 clocks = <&infracfg CLK_INFRA_PMIC_AP>, 735 <&infracfg CLK_INFRA_PMIC_TMR>, 736 <&topckgen CLK_TOP_SPMI_MST_SEL>; 737 clock-names = "pmif_sys_ck", 738 "pmif_tmr_ck", 739 "spmimst_clk_mux"; 740 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 741 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 742 }; 743 744 gce: mailbox@10228000 { 745 compatible = "mediatek,mt8192-gce"; 746 reg = <0 0x10228000 0 0x4000>; 747 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 748 #mbox-cells = <2>; 749 clocks = <&infracfg CLK_INFRA_GCE>; 750 clock-names = "gce"; 751 }; 752 753 scp_adsp: clock-controller@10720000 { 754 compatible = "mediatek,mt8192-scp_adsp"; 755 reg = <0 0x10720000 0 0x1000>; 756 #clock-cells = <1>; 757 /* power domain dependency not upstreamed */ 758 status = "fail"; 759 }; 760 761 uart0: serial@11002000 { 762 compatible = "mediatek,mt8192-uart", 763 "mediatek,mt6577-uart"; 764 reg = <0 0x11002000 0 0x1000>; 765 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 766 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 767 clock-names = "baud", "bus"; 768 status = "disabled"; 769 }; 770 771 uart1: serial@11003000 { 772 compatible = "mediatek,mt8192-uart", 773 "mediatek,mt6577-uart"; 774 reg = <0 0x11003000 0 0x1000>; 775 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 776 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 777 clock-names = "baud", "bus"; 778 status = "disabled"; 779 }; 780 781 imp_iic_wrap_c: clock-controller@11007000 { 782 compatible = "mediatek,mt8192-imp_iic_wrap_c"; 783 reg = <0 0x11007000 0 0x1000>; 784 #clock-cells = <1>; 785 }; 786 787 spi0: spi@1100a000 { 788 compatible = "mediatek,mt8192-spi", 789 "mediatek,mt6765-spi"; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 reg = <0 0x1100a000 0 0x1000>; 793 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 794 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 795 <&topckgen CLK_TOP_SPI_SEL>, 796 <&infracfg CLK_INFRA_SPI0>; 797 clock-names = "parent-clk", "sel-clk", "spi-clk"; 798 status = "disabled"; 799 }; 800 801 lvts_ap: thermal-sensor@1100b000 { 802 compatible = "mediatek,mt8192-lvts-ap"; 803 reg = <0 0x1100b000 0 0xc00>; 804 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 805 clocks = <&infracfg CLK_INFRA_THERM>; 806 resets = <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>; 807 nvmem-cells = <&lvts_e_data1>; 808 nvmem-cell-names = "lvts-calib-data-1"; 809 #thermal-sensor-cells = <1>; 810 }; 811 812 svs: svs@1100bc00 { 813 compatible = "mediatek,mt8192-svs"; 814 reg = <0 0x1100bc00 0 0x400>; 815 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>; 816 clocks = <&infracfg CLK_INFRA_THERM>; 817 clock-names = "main"; 818 nvmem-cells = <&svs_calibration>, <&lvts_e_data1>; 819 nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; 820 resets = <&infracfg MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST>; 821 reset-names = "svs_rst"; 822 }; 823 824 pwm0: pwm@1100e000 { 825 compatible = "mediatek,mt8183-disp-pwm"; 826 reg = <0 0x1100e000 0 0x1000>; 827 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 828 #pwm-cells = <2>; 829 clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, 830 <&infracfg CLK_INFRA_DISP_PWM>; 831 clock-names = "main", "mm"; 832 status = "disabled"; 833 }; 834 835 spi1: spi@11010000 { 836 compatible = "mediatek,mt8192-spi", 837 "mediatek,mt6765-spi"; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 reg = <0 0x11010000 0 0x1000>; 841 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 842 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 843 <&topckgen CLK_TOP_SPI_SEL>, 844 <&infracfg CLK_INFRA_SPI1>; 845 clock-names = "parent-clk", "sel-clk", "spi-clk"; 846 status = "disabled"; 847 }; 848 849 spi2: spi@11012000 { 850 compatible = "mediatek,mt8192-spi", 851 "mediatek,mt6765-spi"; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 reg = <0 0x11012000 0 0x1000>; 855 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 856 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 857 <&topckgen CLK_TOP_SPI_SEL>, 858 <&infracfg CLK_INFRA_SPI2>; 859 clock-names = "parent-clk", "sel-clk", "spi-clk"; 860 status = "disabled"; 861 }; 862 863 spi3: spi@11013000 { 864 compatible = "mediatek,mt8192-spi", 865 "mediatek,mt6765-spi"; 866 #address-cells = <1>; 867 #size-cells = <0>; 868 reg = <0 0x11013000 0 0x1000>; 869 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 870 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 871 <&topckgen CLK_TOP_SPI_SEL>, 872 <&infracfg CLK_INFRA_SPI3>; 873 clock-names = "parent-clk", "sel-clk", "spi-clk"; 874 status = "disabled"; 875 }; 876 877 spi4: spi@11018000 { 878 compatible = "mediatek,mt8192-spi", 879 "mediatek,mt6765-spi"; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 reg = <0 0x11018000 0 0x1000>; 883 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 884 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 885 <&topckgen CLK_TOP_SPI_SEL>, 886 <&infracfg CLK_INFRA_SPI4>; 887 clock-names = "parent-clk", "sel-clk", "spi-clk"; 888 status = "disabled"; 889 }; 890 891 spi5: spi@11019000 { 892 compatible = "mediatek,mt8192-spi", 893 "mediatek,mt6765-spi"; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 reg = <0 0x11019000 0 0x1000>; 897 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 898 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 899 <&topckgen CLK_TOP_SPI_SEL>, 900 <&infracfg CLK_INFRA_SPI5>; 901 clock-names = "parent-clk", "sel-clk", "spi-clk"; 902 status = "disabled"; 903 }; 904 905 spi6: spi@1101d000 { 906 compatible = "mediatek,mt8192-spi", 907 "mediatek,mt6765-spi"; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 reg = <0 0x1101d000 0 0x1000>; 911 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 912 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 913 <&topckgen CLK_TOP_SPI_SEL>, 914 <&infracfg CLK_INFRA_SPI6>; 915 clock-names = "parent-clk", "sel-clk", "spi-clk"; 916 status = "disabled"; 917 }; 918 919 spi7: spi@1101e000 { 920 compatible = "mediatek,mt8192-spi", 921 "mediatek,mt6765-spi"; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 reg = <0 0x1101e000 0 0x1000>; 925 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 926 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 927 <&topckgen CLK_TOP_SPI_SEL>, 928 <&infracfg CLK_INFRA_SPI7>; 929 clock-names = "parent-clk", "sel-clk", "spi-clk"; 930 status = "disabled"; 931 }; 932 933 scp: scp@10500000 { 934 compatible = "mediatek,mt8192-scp"; 935 reg = <0 0x10500000 0 0x100000>, 936 <0 0x10720000 0 0xe0000>, 937 <0 0x10700000 0 0x8000>; 938 reg-names = "sram", "cfg", "l1tcm"; 939 interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; 940 clocks = <&infracfg CLK_INFRA_SCPSYS>; 941 clock-names = "main"; 942 status = "disabled"; 943 }; 944 945 xhci: usb@11200000 { 946 compatible = "mediatek,mt8192-xhci", 947 "mediatek,mtk-xhci"; 948 reg = <0 0x11200000 0 0x1000>, 949 <0 0x11203e00 0 0x0100>; 950 reg-names = "mac", "ippc"; 951 interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 952 interrupt-names = "host"; 953 phys = <&u2port0 PHY_TYPE_USB2>, 954 <&u3port0 PHY_TYPE_USB3>; 955 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, 956 <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; 957 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 958 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 959 clocks = <&infracfg CLK_INFRA_SSUSB>, 960 <&apmixedsys CLK_APMIXED_USBPLL>, 961 <&clk26m>, 962 <&clk26m>, 963 <&infracfg CLK_INFRA_SSUSB_XHCI>; 964 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 965 "xhci_ck"; 966 wakeup-source; 967 mediatek,syscon-wakeup = <&pericfg 0x420 102>; 968 status = "disabled"; 969 }; 970 971 audsys: syscon@11210000 { 972 compatible = "mediatek,mt8192-audsys", "syscon"; 973 reg = <0 0x11210000 0 0x2000>; 974 #clock-cells = <1>; 975 976 afe: mt8192-afe-pcm { 977 compatible = "mediatek,mt8192-audio"; 978 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 979 resets = <&watchdog 17>; 980 reset-names = "audiosys"; 981 mediatek,apmixedsys = <&apmixedsys>; 982 mediatek,infracfg = <&infracfg>; 983 mediatek,topckgen = <&topckgen>; 984 power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; 985 clocks = <&audsys CLK_AUD_AFE>, 986 <&audsys CLK_AUD_DAC>, 987 <&audsys CLK_AUD_DAC_PREDIS>, 988 <&audsys CLK_AUD_ADC>, 989 <&audsys CLK_AUD_ADDA6_ADC>, 990 <&audsys CLK_AUD_22M>, 991 <&audsys CLK_AUD_24M>, 992 <&audsys CLK_AUD_APLL_TUNER>, 993 <&audsys CLK_AUD_APLL2_TUNER>, 994 <&audsys CLK_AUD_TDM>, 995 <&audsys CLK_AUD_TML>, 996 <&audsys CLK_AUD_NLE>, 997 <&audsys CLK_AUD_DAC_HIRES>, 998 <&audsys CLK_AUD_ADC_HIRES>, 999 <&audsys CLK_AUD_ADC_HIRES_TML>, 1000 <&audsys CLK_AUD_ADDA6_ADC_HIRES>, 1001 <&audsys CLK_AUD_3RD_DAC>, 1002 <&audsys CLK_AUD_3RD_DAC_PREDIS>, 1003 <&audsys CLK_AUD_3RD_DAC_TML>, 1004 <&audsys CLK_AUD_3RD_DAC_HIRES>, 1005 <&infracfg CLK_INFRA_AUDIO>, 1006 <&infracfg CLK_INFRA_AUDIO_26M_B>, 1007 <&topckgen CLK_TOP_AUDIO_SEL>, 1008 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 1009 <&topckgen CLK_TOP_MAINPLL_D4_D4>, 1010 <&topckgen CLK_TOP_AUD_1_SEL>, 1011 <&topckgen CLK_TOP_APLL1>, 1012 <&topckgen CLK_TOP_AUD_2_SEL>, 1013 <&topckgen CLK_TOP_APLL2>, 1014 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 1015 <&topckgen CLK_TOP_APLL1_D4>, 1016 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 1017 <&topckgen CLK_TOP_APLL2_D4>, 1018 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, 1019 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, 1020 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, 1021 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, 1022 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, 1023 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, 1024 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, 1025 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, 1026 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, 1027 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, 1028 <&topckgen CLK_TOP_APLL12_DIV0>, 1029 <&topckgen CLK_TOP_APLL12_DIV1>, 1030 <&topckgen CLK_TOP_APLL12_DIV2>, 1031 <&topckgen CLK_TOP_APLL12_DIV3>, 1032 <&topckgen CLK_TOP_APLL12_DIV4>, 1033 <&topckgen CLK_TOP_APLL12_DIVB>, 1034 <&topckgen CLK_TOP_APLL12_DIV5>, 1035 <&topckgen CLK_TOP_APLL12_DIV6>, 1036 <&topckgen CLK_TOP_APLL12_DIV7>, 1037 <&topckgen CLK_TOP_APLL12_DIV8>, 1038 <&topckgen CLK_TOP_APLL12_DIV9>, 1039 <&topckgen CLK_TOP_AUDIO_H_SEL>, 1040 <&clk26m>; 1041 clock-names = "aud_afe_clk", 1042 "aud_dac_clk", 1043 "aud_dac_predis_clk", 1044 "aud_adc_clk", 1045 "aud_adda6_adc_clk", 1046 "aud_apll22m_clk", 1047 "aud_apll24m_clk", 1048 "aud_apll1_tuner_clk", 1049 "aud_apll2_tuner_clk", 1050 "aud_tdm_clk", 1051 "aud_tml_clk", 1052 "aud_nle", 1053 "aud_dac_hires_clk", 1054 "aud_adc_hires_clk", 1055 "aud_adc_hires_tml", 1056 "aud_adda6_adc_hires_clk", 1057 "aud_3rd_dac_clk", 1058 "aud_3rd_dac_predis_clk", 1059 "aud_3rd_dac_tml", 1060 "aud_3rd_dac_hires_clk", 1061 "aud_infra_clk", 1062 "aud_infra_26m_clk", 1063 "top_mux_audio", 1064 "top_mux_audio_int", 1065 "top_mainpll_d4_d4", 1066 "top_mux_aud_1", 1067 "top_apll1_ck", 1068 "top_mux_aud_2", 1069 "top_apll2_ck", 1070 "top_mux_aud_eng1", 1071 "top_apll1_d4", 1072 "top_mux_aud_eng2", 1073 "top_apll2_d4", 1074 "top_i2s0_m_sel", 1075 "top_i2s1_m_sel", 1076 "top_i2s2_m_sel", 1077 "top_i2s3_m_sel", 1078 "top_i2s4_m_sel", 1079 "top_i2s5_m_sel", 1080 "top_i2s6_m_sel", 1081 "top_i2s7_m_sel", 1082 "top_i2s8_m_sel", 1083 "top_i2s9_m_sel", 1084 "top_apll12_div0", 1085 "top_apll12_div1", 1086 "top_apll12_div2", 1087 "top_apll12_div3", 1088 "top_apll12_div4", 1089 "top_apll12_divb", 1090 "top_apll12_div5", 1091 "top_apll12_div6", 1092 "top_apll12_div7", 1093 "top_apll12_div8", 1094 "top_apll12_div9", 1095 "top_mux_audio_h", 1096 "top_clk26m_clk"; 1097 }; 1098 }; 1099 1100 pcie: pcie@11230000 { 1101 compatible = "mediatek,mt8192-pcie"; 1102 device_type = "pci"; 1103 reg = <0 0x11230000 0 0x2000>; 1104 reg-names = "pcie-mac"; 1105 #address-cells = <3>; 1106 #size-cells = <2>; 1107 clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, 1108 <&infracfg CLK_INFRA_PCIE_TL_26M>, 1109 <&infracfg CLK_INFRA_PCIE_TL_96M>, 1110 <&infracfg CLK_INFRA_PCIE_TL_32K>, 1111 <&infracfg CLK_INFRA_PCIE_PERI_26M>, 1112 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; 1113 clock-names = "pl_250m", "tl_26m", "tl_96m", 1114 "tl_32k", "peri_26m", "top_133m"; 1115 assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; 1116 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; 1117 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 1118 bus-range = <0x00 0xff>; 1119 ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, 1120 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; 1121 #interrupt-cells = <1>; 1122 interrupt-map-mask = <0 0 0 7>; 1123 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1124 <0 0 0 2 &pcie_intc0 1>, 1125 <0 0 0 3 &pcie_intc0 2>, 1126 <0 0 0 4 &pcie_intc0 3>; 1127 1128 pcie_intc0: interrupt-controller { 1129 interrupt-controller; 1130 #address-cells = <0>; 1131 #interrupt-cells = <1>; 1132 }; 1133 }; 1134 1135 nor_flash: spi@11234000 { 1136 compatible = "mediatek,mt8192-nor"; 1137 reg = <0 0x11234000 0 0xe0>; 1138 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 1139 clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 1140 <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 1141 <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 1142 clock-names = "spi", "sf", "axi"; 1143 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 1144 assigned-clock-parents = <&clk26m>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 status = "disabled"; 1148 }; 1149 1150 lvts_mcu: thermal-sensor@11278000 { 1151 compatible = "mediatek,mt8192-lvts-mcu"; 1152 reg = <0 0x11278000 0 0x1000>; 1153 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 1154 clocks = <&infracfg CLK_INFRA_THERM>; 1155 resets = <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>; 1156 nvmem-cells = <&lvts_e_data1>; 1157 nvmem-cell-names = "lvts-calib-data-1"; 1158 #thermal-sensor-cells = <1>; 1159 }; 1160 1161 efuse: efuse@11c10000 { 1162 compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; 1163 reg = <0 0x11c10000 0 0x1000>; 1164 #address-cells = <1>; 1165 #size-cells = <1>; 1166 1167 socinfo-data1@44 { 1168 reg = <0x044 0x4>; 1169 }; 1170 1171 socinfo-data2@50 { 1172 reg = <0x050 0x4>; 1173 }; 1174 1175 lvts_e_data1: data1@1c0 { 1176 reg = <0x1c0 0x58>; 1177 }; 1178 1179 svs_calibration: calib@580 { 1180 reg = <0x580 0x68>; 1181 }; 1182 }; 1183 1184 i2c3: i2c@11cb0000 { 1185 compatible = "mediatek,mt8192-i2c"; 1186 reg = <0 0x11cb0000 0 0x1000>, 1187 <0 0x10217300 0 0x80>; 1188 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1189 clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 1190 <&infracfg CLK_INFRA_AP_DMA>; 1191 clock-names = "main", "dma"; 1192 clock-div = <1>; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 status = "disabled"; 1196 }; 1197 1198 imp_iic_wrap_e: clock-controller@11cb1000 { 1199 compatible = "mediatek,mt8192-imp_iic_wrap_e"; 1200 reg = <0 0x11cb1000 0 0x1000>; 1201 #clock-cells = <1>; 1202 }; 1203 1204 i2c7: i2c@11d00000 { 1205 compatible = "mediatek,mt8192-i2c"; 1206 reg = <0 0x11d00000 0 0x1000>, 1207 <0 0x10217600 0 0x180>; 1208 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1209 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1210 <&infracfg CLK_INFRA_AP_DMA>; 1211 clock-names = "main", "dma"; 1212 clock-div = <1>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 status = "disabled"; 1216 }; 1217 1218 i2c8: i2c@11d01000 { 1219 compatible = "mediatek,mt8192-i2c"; 1220 reg = <0 0x11d01000 0 0x1000>, 1221 <0 0x10217780 0 0x180>; 1222 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1223 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 1224 <&infracfg CLK_INFRA_AP_DMA>; 1225 clock-names = "main", "dma"; 1226 clock-div = <1>; 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 status = "disabled"; 1230 }; 1231 1232 i2c9: i2c@11d02000 { 1233 compatible = "mediatek,mt8192-i2c"; 1234 reg = <0 0x11d02000 0 0x1000>, 1235 <0 0x10217900 0 0x180>; 1236 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 1237 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 1238 <&infracfg CLK_INFRA_AP_DMA>; 1239 clock-names = "main", "dma"; 1240 clock-div = <1>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 status = "disabled"; 1244 }; 1245 1246 imp_iic_wrap_s: clock-controller@11d03000 { 1247 compatible = "mediatek,mt8192-imp_iic_wrap_s"; 1248 reg = <0 0x11d03000 0 0x1000>; 1249 #clock-cells = <1>; 1250 }; 1251 1252 i2c1: i2c@11d20000 { 1253 compatible = "mediatek,mt8192-i2c"; 1254 reg = <0 0x11d20000 0 0x1000>, 1255 <0 0x10217100 0 0x80>; 1256 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1257 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 1258 <&infracfg CLK_INFRA_AP_DMA>; 1259 clock-names = "main", "dma"; 1260 clock-div = <1>; 1261 #address-cells = <1>; 1262 #size-cells = <0>; 1263 status = "disabled"; 1264 }; 1265 1266 i2c2: i2c@11d21000 { 1267 compatible = "mediatek,mt8192-i2c"; 1268 reg = <0 0x11d21000 0 0x1000>, 1269 <0 0x10217180 0 0x180>; 1270 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 1271 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 1272 <&infracfg CLK_INFRA_AP_DMA>; 1273 clock-names = "main", "dma"; 1274 clock-div = <1>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 status = "disabled"; 1278 }; 1279 1280 i2c4: i2c@11d22000 { 1281 compatible = "mediatek,mt8192-i2c"; 1282 reg = <0 0x11d22000 0 0x1000>, 1283 <0 0x10217380 0 0x180>; 1284 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1285 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 1286 <&infracfg CLK_INFRA_AP_DMA>; 1287 clock-names = "main", "dma"; 1288 clock-div = <1>; 1289 #address-cells = <1>; 1290 #size-cells = <0>; 1291 status = "disabled"; 1292 }; 1293 1294 imp_iic_wrap_ws: clock-controller@11d23000 { 1295 compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 1296 reg = <0 0x11d23000 0 0x1000>; 1297 #clock-cells = <1>; 1298 }; 1299 1300 i2c5: i2c@11e00000 { 1301 compatible = "mediatek,mt8192-i2c"; 1302 reg = <0 0x11e00000 0 0x1000>, 1303 <0 0x10217500 0 0x80>; 1304 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1305 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 1306 <&infracfg CLK_INFRA_AP_DMA>; 1307 clock-names = "main", "dma"; 1308 clock-div = <1>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 status = "disabled"; 1312 }; 1313 1314 imp_iic_wrap_w: clock-controller@11e01000 { 1315 compatible = "mediatek,mt8192-imp_iic_wrap_w"; 1316 reg = <0 0x11e01000 0 0x1000>; 1317 #clock-cells = <1>; 1318 }; 1319 1320 u3phy0: t-phy@11e40000 { 1321 compatible = "mediatek,mt8192-tphy", 1322 "mediatek,generic-tphy-v2"; 1323 #address-cells = <1>; 1324 #size-cells = <1>; 1325 ranges = <0x0 0x0 0x11e40000 0x1000>; 1326 1327 u2port0: usb-phy@0 { 1328 reg = <0x0 0x700>; 1329 clocks = <&clk26m>; 1330 clock-names = "ref"; 1331 #phy-cells = <1>; 1332 }; 1333 1334 u3port0: usb-phy@700 { 1335 reg = <0x700 0x900>; 1336 clocks = <&clk26m>; 1337 clock-names = "ref"; 1338 #phy-cells = <1>; 1339 }; 1340 }; 1341 1342 mipi_tx0: dsi-phy@11e50000 { 1343 compatible = "mediatek,mt8183-mipi-tx"; 1344 reg = <0 0x11e50000 0 0x1000>; 1345 clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; 1346 #clock-cells = <0>; 1347 #phy-cells = <0>; 1348 clock-output-names = "mipi_tx0_pll"; 1349 status = "disabled"; 1350 }; 1351 1352 i2c0: i2c@11f00000 { 1353 compatible = "mediatek,mt8192-i2c"; 1354 reg = <0 0x11f00000 0 0x1000>, 1355 <0 0x10217080 0 0x80>; 1356 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 1357 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 1358 <&infracfg CLK_INFRA_AP_DMA>; 1359 clock-names = "main", "dma"; 1360 clock-div = <1>; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 status = "disabled"; 1364 }; 1365 1366 i2c6: i2c@11f01000 { 1367 compatible = "mediatek,mt8192-i2c"; 1368 reg = <0 0x11f01000 0 0x1000>, 1369 <0 0x10217580 0 0x80>; 1370 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1371 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 1372 <&infracfg CLK_INFRA_AP_DMA>; 1373 clock-names = "main", "dma"; 1374 clock-div = <1>; 1375 #address-cells = <1>; 1376 #size-cells = <0>; 1377 status = "disabled"; 1378 }; 1379 1380 imp_iic_wrap_n: clock-controller@11f02000 { 1381 compatible = "mediatek,mt8192-imp_iic_wrap_n"; 1382 reg = <0 0x11f02000 0 0x1000>; 1383 #clock-cells = <1>; 1384 }; 1385 1386 msdc_top: clock-controller@11f10000 { 1387 compatible = "mediatek,mt8192-msdc_top"; 1388 reg = <0 0x11f10000 0 0x1000>; 1389 #clock-cells = <1>; 1390 }; 1391 1392 mmc0: mmc@11f60000 { 1393 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1394 reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; 1395 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 1396 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 1397 <&msdc_top CLK_MSDC_TOP_H_MST_0P>, 1398 <&msdc_top CLK_MSDC_TOP_SRC_0P>, 1399 <&msdc_top CLK_MSDC_TOP_P_CFG>, 1400 <&msdc_top CLK_MSDC_TOP_P_MSDC0>, 1401 <&msdc_top CLK_MSDC_TOP_AXI>, 1402 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1403 clock-names = "source", "hclk", "source_cg", "sys_cg", 1404 "pclk_cg", "axi_cg", "ahb_cg"; 1405 status = "disabled"; 1406 }; 1407 1408 mmc1: mmc@11f70000 { 1409 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1410 reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; 1411 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; 1412 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 1413 <&msdc_top CLK_MSDC_TOP_H_MST_1P>, 1414 <&msdc_top CLK_MSDC_TOP_SRC_1P>, 1415 <&msdc_top CLK_MSDC_TOP_P_CFG>, 1416 <&msdc_top CLK_MSDC_TOP_P_MSDC1>, 1417 <&msdc_top CLK_MSDC_TOP_AXI>, 1418 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1419 clock-names = "source", "hclk", "source_cg", "sys_cg", 1420 "pclk_cg", "axi_cg", "ahb_cg"; 1421 status = "disabled"; 1422 }; 1423 1424 gpu: gpu@13000000 { 1425 compatible = "mediatek,mt8192-mali", "arm,mali-valhall-jm"; 1426 reg = <0 0x13000000 0 0x4000>; 1427 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>, 1428 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>, 1429 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 1430 interrupt-names = "job", "mmu", "gpu"; 1431 1432 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; 1433 1434 power-domains = <&spm MT8192_POWER_DOMAIN_MFG2>, 1435 <&spm MT8192_POWER_DOMAIN_MFG3>, 1436 <&spm MT8192_POWER_DOMAIN_MFG4>, 1437 <&spm MT8192_POWER_DOMAIN_MFG5>, 1438 <&spm MT8192_POWER_DOMAIN_MFG6>; 1439 power-domain-names = "core0", "core1", "core2", "core3", "core4"; 1440 1441 operating-points-v2 = <&gpu_opp_table>; 1442 1443 status = "disabled"; 1444 }; 1445 1446 mfgcfg: clock-controller@13fbf000 { 1447 compatible = "mediatek,mt8192-mfgcfg"; 1448 reg = <0 0x13fbf000 0 0x1000>; 1449 #clock-cells = <1>; 1450 }; 1451 1452 mmsys: syscon@14000000 { 1453 compatible = "mediatek,mt8192-mmsys", "syscon"; 1454 reg = <0 0x14000000 0 0x1000>; 1455 #clock-cells = <1>; 1456 #reset-cells = <1>; 1457 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1458 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1459 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1460 }; 1461 1462 mutex: mutex@14001000 { 1463 compatible = "mediatek,mt8192-disp-mutex"; 1464 reg = <0 0x14001000 0 0x1000>; 1465 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; 1466 clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1467 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; 1468 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1469 <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1470 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1471 }; 1472 1473 smi_common: smi@14002000 { 1474 compatible = "mediatek,mt8192-smi-common"; 1475 reg = <0 0x14002000 0 0x1000>; 1476 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1477 <&mmsys CLK_MM_SMI_INFRA>, 1478 <&mmsys CLK_MM_SMI_GALS>, 1479 <&mmsys CLK_MM_SMI_GALS>; 1480 clock-names = "apb", "smi", "gals0", "gals1"; 1481 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1482 }; 1483 1484 larb0: larb@14003000 { 1485 compatible = "mediatek,mt8192-smi-larb"; 1486 reg = <0 0x14003000 0 0x1000>; 1487 mediatek,larb-id = <0>; 1488 mediatek,smi = <&smi_common>; 1489 clocks = <&clk26m>, <&clk26m>; 1490 clock-names = "apb", "smi"; 1491 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1492 }; 1493 1494 larb1: larb@14004000 { 1495 compatible = "mediatek,mt8192-smi-larb"; 1496 reg = <0 0x14004000 0 0x1000>; 1497 mediatek,larb-id = <1>; 1498 mediatek,smi = <&smi_common>; 1499 clocks = <&clk26m>, <&clk26m>; 1500 clock-names = "apb", "smi"; 1501 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1502 }; 1503 1504 ovl0: ovl@14005000 { 1505 compatible = "mediatek,mt8192-disp-ovl"; 1506 reg = <0 0x14005000 0 0x1000>; 1507 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 1508 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1509 iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, 1510 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; 1511 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1512 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1513 }; 1514 1515 ovl_2l0: ovl@14006000 { 1516 compatible = "mediatek,mt8192-disp-ovl-2l"; 1517 reg = <0 0x14006000 0 0x1000>; 1518 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; 1519 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1520 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1521 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, 1522 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; 1523 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1524 }; 1525 1526 rdma0: rdma@14007000 { 1527 compatible = "mediatek,mt8192-disp-rdma", 1528 "mediatek,mt8183-disp-rdma"; 1529 reg = <0 0x14007000 0 0x1000>; 1530 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; 1531 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1532 iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; 1533 mediatek,rdma-fifo-size = <5120>; 1534 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1535 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1536 }; 1537 1538 color0: color@14009000 { 1539 compatible = "mediatek,mt8192-disp-color", 1540 "mediatek,mt8173-disp-color"; 1541 reg = <0 0x14009000 0 0x1000>; 1542 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; 1543 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1544 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1545 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1546 }; 1547 1548 ccorr0: ccorr@1400a000 { 1549 compatible = "mediatek,mt8192-disp-ccorr"; 1550 reg = <0 0x1400a000 0 0x1000>; 1551 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 1552 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1553 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1554 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1555 }; 1556 1557 aal0: aal@1400b000 { 1558 compatible = "mediatek,mt8192-disp-aal", 1559 "mediatek,mt8183-disp-aal"; 1560 reg = <0 0x1400b000 0 0x1000>; 1561 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; 1562 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1563 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1564 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1565 }; 1566 1567 gamma0: gamma@1400c000 { 1568 compatible = "mediatek,mt8192-disp-gamma", 1569 "mediatek,mt8183-disp-gamma"; 1570 reg = <0 0x1400c000 0 0x1000>; 1571 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; 1572 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1573 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1574 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1575 }; 1576 1577 postmask0: postmask@1400d000 { 1578 compatible = "mediatek,mt8192-disp-postmask"; 1579 reg = <0 0x1400d000 0 0x1000>; 1580 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; 1581 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1582 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1583 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1584 }; 1585 1586 dither0: dither@1400e000 { 1587 compatible = "mediatek,mt8192-disp-dither", 1588 "mediatek,mt8183-disp-dither"; 1589 reg = <0 0x1400e000 0 0x1000>; 1590 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; 1591 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1592 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1593 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1594 }; 1595 1596 dsi0: dsi@14010000 { 1597 compatible = "mediatek,mt8183-dsi"; 1598 reg = <0 0x14010000 0 0x1000>; 1599 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 1600 clocks = <&mmsys CLK_MM_DSI0>, 1601 <&mmsys CLK_MM_DSI_DSI0>, 1602 <&mipi_tx0>; 1603 clock-names = "engine", "digital", "hs"; 1604 phys = <&mipi_tx0>; 1605 phy-names = "dphy"; 1606 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1607 resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; 1608 status = "disabled"; 1609 1610 port { 1611 dsi_out: endpoint { }; 1612 }; 1613 }; 1614 1615 ovl_2l2: ovl@14014000 { 1616 compatible = "mediatek,mt8192-disp-ovl-2l"; 1617 reg = <0 0x14014000 0 0x1000>; 1618 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; 1619 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1620 clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; 1621 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, 1622 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; 1623 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1624 }; 1625 1626 rdma4: rdma@14015000 { 1627 compatible = "mediatek,mt8192-disp-rdma", 1628 "mediatek,mt8183-disp-rdma"; 1629 reg = <0 0x14015000 0 0x1000>; 1630 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; 1631 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1632 clocks = <&mmsys CLK_MM_DISP_RDMA4>; 1633 iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; 1634 mediatek,rdma-fifo-size = <2048>; 1635 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1636 }; 1637 1638 dpi0: dpi@14016000 { 1639 compatible = "mediatek,mt8192-dpi"; 1640 reg = <0 0x14016000 0 0x1000>; 1641 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 1642 clocks = <&mmsys CLK_MM_DPI_DPI0>, 1643 <&mmsys CLK_MM_DISP_DPI0>, 1644 <&apmixedsys CLK_APMIXED_TVDPLL>; 1645 clock-names = "pixel", "engine", "pll"; 1646 status = "disabled"; 1647 }; 1648 1649 iommu0: m4u@1401d000 { 1650 compatible = "mediatek,mt8192-m4u"; 1651 reg = <0 0x1401d000 0 0x1000>; 1652 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 1653 <&larb4>, <&larb5>, <&larb7>, 1654 <&larb9>, <&larb11>, <&larb13>, 1655 <&larb14>, <&larb16>, <&larb17>, 1656 <&larb18>, <&larb19>, <&larb20>; 1657 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 1658 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1659 clock-names = "bclk"; 1660 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1661 #iommu-cells = <1>; 1662 }; 1663 1664 imgsys: clock-controller@15020000 { 1665 compatible = "mediatek,mt8192-imgsys"; 1666 reg = <0 0x15020000 0 0x1000>; 1667 #clock-cells = <1>; 1668 }; 1669 1670 larb9: larb@1502e000 { 1671 compatible = "mediatek,mt8192-smi-larb"; 1672 reg = <0 0x1502e000 0 0x1000>; 1673 mediatek,larb-id = <9>; 1674 mediatek,smi = <&smi_common>; 1675 clocks = <&imgsys CLK_IMG_LARB9>, 1676 <&imgsys CLK_IMG_LARB9>; 1677 clock-names = "apb", "smi"; 1678 power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; 1679 }; 1680 1681 imgsys2: clock-controller@15820000 { 1682 compatible = "mediatek,mt8192-imgsys2"; 1683 reg = <0 0x15820000 0 0x1000>; 1684 #clock-cells = <1>; 1685 }; 1686 1687 larb11: larb@1582e000 { 1688 compatible = "mediatek,mt8192-smi-larb"; 1689 reg = <0 0x1582e000 0 0x1000>; 1690 mediatek,larb-id = <11>; 1691 mediatek,smi = <&smi_common>; 1692 clocks = <&imgsys2 CLK_IMG2_LARB11>, 1693 <&imgsys2 CLK_IMG2_LARB11>; 1694 clock-names = "apb", "smi"; 1695 power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; 1696 }; 1697 1698 vcodec_dec: video-codec@16000000 { 1699 compatible = "mediatek,mt8192-vcodec-dec"; 1700 reg = <0 0x16000000 0 0x1000>; 1701 mediatek,scp = <&scp>; 1702 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; 1703 #address-cells = <2>; 1704 #size-cells = <2>; 1705 ranges = <0 0 0 0x16000000 0 0x26000>; 1706 1707 video-codec@10000 { 1708 compatible = "mediatek,mtk-vcodec-lat"; 1709 reg = <0x0 0x10000 0 0x800>; 1710 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>; 1711 iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, 1712 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, 1713 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, 1714 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, 1715 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, 1716 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, 1717 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, 1718 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; 1719 clocks = <&topckgen CLK_TOP_VDEC_SEL>, 1720 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 1721 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 1722 <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 1723 <&topckgen CLK_TOP_MAINPLL_D4>; 1724 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; 1725 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; 1726 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; 1727 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 1728 }; 1729 1730 video-codec@25000 { 1731 compatible = "mediatek,mtk-vcodec-core"; 1732 reg = <0 0x25000 0 0x1000>; 1733 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>; 1734 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, 1735 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, 1736 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, 1737 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, 1738 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, 1739 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, 1740 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, 1741 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, 1742 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, 1743 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, 1744 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; 1745 clocks = <&topckgen CLK_TOP_VDEC_SEL>, 1746 <&vdecsys CLK_VDEC_VDEC>, 1747 <&vdecsys CLK_VDEC_LAT>, 1748 <&vdecsys CLK_VDEC_LARB1>, 1749 <&topckgen CLK_TOP_MAINPLL_D4>; 1750 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; 1751 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; 1752 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; 1753 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 1754 }; 1755 }; 1756 1757 larb5: larb@1600d000 { 1758 compatible = "mediatek,mt8192-smi-larb"; 1759 reg = <0 0x1600d000 0 0x1000>; 1760 mediatek,larb-id = <5>; 1761 mediatek,smi = <&smi_common>; 1762 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 1763 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 1764 clock-names = "apb", "smi"; 1765 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 1766 }; 1767 1768 vdecsys_soc: clock-controller@1600f000 { 1769 compatible = "mediatek,mt8192-vdecsys_soc"; 1770 reg = <0 0x1600f000 0 0x1000>; 1771 #clock-cells = <1>; 1772 }; 1773 1774 larb4: larb@1602e000 { 1775 compatible = "mediatek,mt8192-smi-larb"; 1776 reg = <0 0x1602e000 0 0x1000>; 1777 mediatek,larb-id = <4>; 1778 mediatek,smi = <&smi_common>; 1779 clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, 1780 <&vdecsys CLK_VDEC_SOC_LARB1>; 1781 clock-names = "apb", "smi"; 1782 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 1783 }; 1784 1785 vdecsys: clock-controller@1602f000 { 1786 compatible = "mediatek,mt8192-vdecsys"; 1787 reg = <0 0x1602f000 0 0x1000>; 1788 #clock-cells = <1>; 1789 }; 1790 1791 vencsys: clock-controller@17000000 { 1792 compatible = "mediatek,mt8192-vencsys"; 1793 reg = <0 0x17000000 0 0x1000>; 1794 #clock-cells = <1>; 1795 }; 1796 1797 larb7: larb@17010000 { 1798 compatible = "mediatek,mt8192-smi-larb"; 1799 reg = <0 0x17010000 0 0x1000>; 1800 mediatek,larb-id = <7>; 1801 mediatek,smi = <&smi_common>; 1802 clocks = <&vencsys CLK_VENC_SET0_LARB>, 1803 <&vencsys CLK_VENC_SET1_VENC>; 1804 clock-names = "apb", "smi"; 1805 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1806 }; 1807 1808 vcodec_enc: vcodec@17020000 { 1809 compatible = "mediatek,mt8192-vcodec-enc"; 1810 reg = <0 0x17020000 0 0x2000>; 1811 iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, 1812 <&iommu0 M4U_PORT_L7_VENC_REC>, 1813 <&iommu0 M4U_PORT_L7_VENC_BSDMA>, 1814 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, 1815 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, 1816 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, 1817 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, 1818 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, 1819 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, 1820 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, 1821 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; 1822 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; 1823 mediatek,scp = <&scp>; 1824 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1825 clocks = <&vencsys CLK_VENC_SET1_VENC>; 1826 clock-names = "venc_sel"; 1827 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1828 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 1829 }; 1830 1831 camsys: clock-controller@1a000000 { 1832 compatible = "mediatek,mt8192-camsys"; 1833 reg = <0 0x1a000000 0 0x1000>; 1834 #clock-cells = <1>; 1835 }; 1836 1837 larb13: larb@1a001000 { 1838 compatible = "mediatek,mt8192-smi-larb"; 1839 reg = <0 0x1a001000 0 0x1000>; 1840 mediatek,larb-id = <13>; 1841 mediatek,smi = <&smi_common>; 1842 clocks = <&camsys CLK_CAM_CAM>, 1843 <&camsys CLK_CAM_LARB13>; 1844 clock-names = "apb", "smi"; 1845 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 1846 }; 1847 1848 larb14: larb@1a002000 { 1849 compatible = "mediatek,mt8192-smi-larb"; 1850 reg = <0 0x1a002000 0 0x1000>; 1851 mediatek,larb-id = <14>; 1852 mediatek,smi = <&smi_common>; 1853 clocks = <&camsys CLK_CAM_CAM>, 1854 <&camsys CLK_CAM_LARB14>; 1855 clock-names = "apb", "smi"; 1856 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 1857 }; 1858 1859 larb16: larb@1a00f000 { 1860 compatible = "mediatek,mt8192-smi-larb"; 1861 reg = <0 0x1a00f000 0 0x1000>; 1862 mediatek,larb-id = <16>; 1863 mediatek,smi = <&smi_common>; 1864 clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, 1865 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 1866 clock-names = "apb", "smi"; 1867 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; 1868 }; 1869 1870 larb17: larb@1a010000 { 1871 compatible = "mediatek,mt8192-smi-larb"; 1872 reg = <0 0x1a010000 0 0x1000>; 1873 mediatek,larb-id = <17>; 1874 mediatek,smi = <&smi_common>; 1875 clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, 1876 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 1877 clock-names = "apb", "smi"; 1878 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; 1879 }; 1880 1881 larb18: larb@1a011000 { 1882 compatible = "mediatek,mt8192-smi-larb"; 1883 reg = <0 0x1a011000 0 0x1000>; 1884 mediatek,larb-id = <18>; 1885 mediatek,smi = <&smi_common>; 1886 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, 1887 <&camsys_rawc CLK_CAM_RAWC_CAM>; 1888 clock-names = "apb", "smi"; 1889 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; 1890 }; 1891 1892 camsys_rawa: clock-controller@1a04f000 { 1893 compatible = "mediatek,mt8192-camsys_rawa"; 1894 reg = <0 0x1a04f000 0 0x1000>; 1895 #clock-cells = <1>; 1896 }; 1897 1898 camsys_rawb: clock-controller@1a06f000 { 1899 compatible = "mediatek,mt8192-camsys_rawb"; 1900 reg = <0 0x1a06f000 0 0x1000>; 1901 #clock-cells = <1>; 1902 }; 1903 1904 camsys_rawc: clock-controller@1a08f000 { 1905 compatible = "mediatek,mt8192-camsys_rawc"; 1906 reg = <0 0x1a08f000 0 0x1000>; 1907 #clock-cells = <1>; 1908 }; 1909 1910 ipesys: clock-controller@1b000000 { 1911 compatible = "mediatek,mt8192-ipesys"; 1912 reg = <0 0x1b000000 0 0x1000>; 1913 #clock-cells = <1>; 1914 }; 1915 1916 larb20: larb@1b00f000 { 1917 compatible = "mediatek,mt8192-smi-larb"; 1918 reg = <0 0x1b00f000 0 0x1000>; 1919 mediatek,larb-id = <20>; 1920 mediatek,smi = <&smi_common>; 1921 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 1922 <&ipesys CLK_IPE_LARB20>; 1923 clock-names = "apb", "smi"; 1924 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 1925 }; 1926 1927 larb19: larb@1b10f000 { 1928 compatible = "mediatek,mt8192-smi-larb"; 1929 reg = <0 0x1b10f000 0 0x1000>; 1930 mediatek,larb-id = <19>; 1931 mediatek,smi = <&smi_common>; 1932 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 1933 <&ipesys CLK_IPE_LARB19>; 1934 clock-names = "apb", "smi"; 1935 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 1936 }; 1937 1938 mdpsys: clock-controller@1f000000 { 1939 compatible = "mediatek,mt8192-mdpsys"; 1940 reg = <0 0x1f000000 0 0x1000>; 1941 #clock-cells = <1>; 1942 }; 1943 1944 larb2: larb@1f002000 { 1945 compatible = "mediatek,mt8192-smi-larb"; 1946 reg = <0 0x1f002000 0 0x1000>; 1947 mediatek,larb-id = <2>; 1948 mediatek,smi = <&smi_common>; 1949 clocks = <&mdpsys CLK_MDP_SMI0>, 1950 <&mdpsys CLK_MDP_SMI0>; 1951 clock-names = "apb", "smi"; 1952 power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; 1953 }; 1954 }; 1955 1956 thermal_zones: thermal-zones { 1957 cpu0-thermal { 1958 polling-delay = <1000>; 1959 polling-delay-passive = <250>; 1960 thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU0>; 1961 1962 trips { 1963 cpu0_alert: trip-alert { 1964 temperature = <85000>; 1965 hysteresis = <2000>; 1966 type = "passive"; 1967 }; 1968 1969 cpu0_crit: trip-crit { 1970 temperature = <100000>; 1971 hysteresis = <2000>; 1972 type = "critical"; 1973 }; 1974 }; 1975 1976 cooling-maps { 1977 map0 { 1978 trip = <&cpu0_alert>; 1979 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1980 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1981 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1982 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1983 }; 1984 }; 1985 }; 1986 1987 cpu1-thermal { 1988 polling-delay = <1000>; 1989 polling-delay-passive = <250>; 1990 thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU1>; 1991 1992 trips { 1993 cpu1_alert: trip-alert { 1994 temperature = <85000>; 1995 hysteresis = <2000>; 1996 type = "passive"; 1997 }; 1998 1999 cpu1_crit: trip-crit { 2000 temperature = <100000>; 2001 hysteresis = <2000>; 2002 type = "critical"; 2003 }; 2004 }; 2005 2006 cooling-maps { 2007 map0 { 2008 trip = <&cpu1_alert>; 2009 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2010 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2011 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2012 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2013 }; 2014 }; 2015 }; 2016 2017 cpu2-thermal { 2018 polling-delay = <1000>; 2019 polling-delay-passive = <250>; 2020 thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU2>; 2021 2022 trips { 2023 cpu2_alert: trip-alert { 2024 temperature = <85000>; 2025 hysteresis = <2000>; 2026 type = "passive"; 2027 }; 2028 2029 cpu2_crit: trip-crit { 2030 temperature = <100000>; 2031 hysteresis = <2000>; 2032 type = "critical"; 2033 }; 2034 }; 2035 2036 cooling-maps { 2037 map0 { 2038 trip = <&cpu2_alert>; 2039 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2040 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2041 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2042 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2043 }; 2044 }; 2045 }; 2046 2047 cpu3-thermal { 2048 polling-delay = <1000>; 2049 polling-delay-passive = <250>; 2050 thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU3>; 2051 2052 trips { 2053 cpu3_alert: trip-alert { 2054 temperature = <85000>; 2055 hysteresis = <2000>; 2056 type = "passive"; 2057 }; 2058 2059 cpu3_crit: trip-crit { 2060 temperature = <100000>; 2061 hysteresis = <2000>; 2062 type = "critical"; 2063 }; 2064 }; 2065 2066 cooling-maps { 2067 map0 { 2068 trip = <&cpu3_alert>; 2069 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2070 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2071 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2072 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2073 }; 2074 }; 2075 }; 2076 2077 cpu4-thermal { 2078 polling-delay = <1000>; 2079 polling-delay-passive = <250>; 2080 thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU0>; 2081 2082 trips { 2083 cpu4_alert: trip-alert { 2084 temperature = <85000>; 2085 hysteresis = <2000>; 2086 type = "passive"; 2087 }; 2088 2089 cpu4_crit: trip-crit { 2090 temperature = <100000>; 2091 hysteresis = <2000>; 2092 type = "critical"; 2093 }; 2094 }; 2095 2096 cooling-maps { 2097 map0 { 2098 trip = <&cpu4_alert>; 2099 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2100 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2101 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2102 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2103 }; 2104 }; 2105 }; 2106 2107 cpu5-thermal { 2108 polling-delay = <1000>; 2109 polling-delay-passive = <250>; 2110 thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU1>; 2111 2112 trips { 2113 cpu5_alert: trip-alert { 2114 temperature = <85000>; 2115 hysteresis = <2000>; 2116 type = "passive"; 2117 }; 2118 2119 cpu5_crit: trip-crit { 2120 temperature = <100000>; 2121 hysteresis = <2000>; 2122 type = "critical"; 2123 }; 2124 }; 2125 2126 cooling-maps { 2127 map0 { 2128 trip = <&cpu5_alert>; 2129 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2130 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2131 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2132 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2133 }; 2134 }; 2135 }; 2136 2137 cpu6-thermal { 2138 polling-delay = <1000>; 2139 polling-delay-passive = <250>; 2140 thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU2>; 2141 2142 trips { 2143 cpu6_alert: trip-alert { 2144 temperature = <85000>; 2145 hysteresis = <2000>; 2146 type = "passive"; 2147 }; 2148 2149 cpu6_crit: trip-crit { 2150 temperature = <100000>; 2151 hysteresis = <2000>; 2152 type = "critical"; 2153 }; 2154 }; 2155 2156 cooling-maps { 2157 map0 { 2158 trip = <&cpu6_alert>; 2159 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2160 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2161 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2162 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2163 }; 2164 }; 2165 }; 2166 2167 cpu7-thermal { 2168 polling-delay = <1000>; 2169 polling-delay-passive = <250>; 2170 thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU3>; 2171 2172 trips { 2173 cpu7_alert: trip-alert { 2174 temperature = <85000>; 2175 hysteresis = <2000>; 2176 type = "passive"; 2177 }; 2178 2179 cpu7_crit: trip-crit { 2180 temperature = <100000>; 2181 hysteresis = <2000>; 2182 type = "critical"; 2183 }; 2184 }; 2185 2186 cooling-maps { 2187 map0 { 2188 trip = <&cpu7_alert>; 2189 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2190 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2191 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2192 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2193 }; 2194 }; 2195 }; 2196 2197 vpu0-thermal { 2198 polling-delay = <1000>; 2199 polling-delay-passive = <250>; 2200 thermal-sensors = <&lvts_ap MT8192_AP_VPU0>; 2201 2202 trips { 2203 vpu0_alert: trip-alert { 2204 temperature = <85000>; 2205 hysteresis = <2000>; 2206 type = "passive"; 2207 }; 2208 2209 vpu0_crit: trip-crit { 2210 temperature = <100000>; 2211 hysteresis = <2000>; 2212 type = "critical"; 2213 }; 2214 }; 2215 }; 2216 2217 vpu1-thermal { 2218 polling-delay = <1000>; 2219 polling-delay-passive = <250>; 2220 thermal-sensors = <&lvts_ap MT8192_AP_VPU1>; 2221 2222 trips { 2223 vpu1_alert: trip-alert { 2224 temperature = <85000>; 2225 hysteresis = <2000>; 2226 type = "passive"; 2227 }; 2228 2229 vpu1_crit: trip-crit { 2230 temperature = <100000>; 2231 hysteresis = <2000>; 2232 type = "critical"; 2233 }; 2234 }; 2235 }; 2236 2237 gpu-thermal { 2238 polling-delay = <1000>; 2239 polling-delay-passive = <250>; 2240 thermal-sensors = <&lvts_ap MT8192_AP_GPU0>; 2241 2242 trips { 2243 gpu0_alert: trip-alert { 2244 temperature = <85000>; 2245 hysteresis = <2000>; 2246 type = "passive"; 2247 }; 2248 2249 gpu0_crit: trip-crit { 2250 temperature = <100000>; 2251 hysteresis = <2000>; 2252 type = "critical"; 2253 }; 2254 }; 2255 }; 2256 2257 gpu1-thermal { 2258 polling-delay = <1000>; 2259 polling-delay-passive = <250>; 2260 thermal-sensors = <&lvts_ap MT8192_AP_GPU1>; 2261 2262 trips { 2263 gpu1_alert: trip-alert { 2264 temperature = <85000>; 2265 hysteresis = <2000>; 2266 type = "passive"; 2267 }; 2268 2269 gpu1_crit: trip-crit { 2270 temperature = <100000>; 2271 hysteresis = <2000>; 2272 type = "critical"; 2273 }; 2274 }; 2275 }; 2276 2277 infra-thermal { 2278 polling-delay = <1000>; 2279 polling-delay-passive = <250>; 2280 thermal-sensors = <&lvts_ap MT8192_AP_INFRA>; 2281 2282 trips { 2283 infra_alert: trip-alert { 2284 temperature = <85000>; 2285 hysteresis = <2000>; 2286 type = "passive"; 2287 }; 2288 2289 infra_crit: trip-crit { 2290 temperature = <100000>; 2291 hysteresis = <2000>; 2292 type = "critical"; 2293 }; 2294 }; 2295 }; 2296 2297 cam-thermal { 2298 polling-delay = <1000>; 2299 polling-delay-passive = <250>; 2300 thermal-sensors = <&lvts_ap MT8192_AP_CAM>; 2301 2302 trips { 2303 cam_alert: trip-alert { 2304 temperature = <85000>; 2305 hysteresis = <2000>; 2306 type = "passive"; 2307 }; 2308 2309 cam_crit: trip-crit { 2310 temperature = <100000>; 2311 hysteresis = <2000>; 2312 type = "critical"; 2313 }; 2314 }; 2315 }; 2316 2317 md0-thermal { 2318 polling-delay = <1000>; 2319 polling-delay-passive = <250>; 2320 thermal-sensors = <&lvts_ap MT8192_AP_MD0>; 2321 2322 trips { 2323 md0_alert: trip-alert { 2324 temperature = <85000>; 2325 hysteresis = <2000>; 2326 type = "passive"; 2327 }; 2328 2329 md0_crit: trip-crit { 2330 temperature = <100000>; 2331 hysteresis = <2000>; 2332 type = "critical"; 2333 }; 2334 }; 2335 }; 2336 2337 md1-thermal { 2338 polling-delay = <1000>; 2339 polling-delay-passive = <250>; 2340 thermal-sensors = <&lvts_ap MT8192_AP_MD1>; 2341 2342 trips { 2343 md1_alert: trip-alert { 2344 temperature = <85000>; 2345 hysteresis = <2000>; 2346 type = "passive"; 2347 }; 2348 2349 md1_crit: trip-crit { 2350 temperature = <100000>; 2351 hysteresis = <2000>; 2352 type = "critical"; 2353 }; 2354 }; 2355 }; 2356 2357 md2-thermal { 2358 polling-delay = <1000>; 2359 polling-delay-passive = <250>; 2360 thermal-sensors = <&lvts_ap MT8192_AP_MD2>; 2361 2362 trips { 2363 md2_alert: trip-alert { 2364 temperature = <85000>; 2365 hysteresis = <2000>; 2366 type = "passive"; 2367 }; 2368 2369 md2_crit: trip-crit { 2370 temperature = <100000>; 2371 hysteresis = <2000>; 2372 type = "critical"; 2373 }; 2374 }; 2375 }; 2376 }; 2377}; 2378