1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c7 = &i2c7; 19 mmc0 = &mmc0; 20 mmc1 = &mmc1; 21 serial0 = &uart0; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 memory@40000000 { 29 device_type = "memory"; 30 reg = <0 0x40000000 0 0x80000000>; 31 }; 32 33 backlight_lcd0: backlight-lcd0 { 34 compatible = "pwm-backlight"; 35 pwms = <&pwm0 0 500000>; 36 power-supply = <&ppvar_sys>; 37 enable-gpios = <&pio 152 0>; 38 brightness-levels = <0 1023>; 39 num-interpolated-steps = <1023>; 40 default-brightness-level = <576>; 41 }; 42 43 dmic_codec: dmic-codec { 44 compatible = "dmic-codec"; 45 num-channels = <2>; 46 wakeup-delay-ms = <50>; 47 }; 48 49 pp1000_dpbrdg: regulator-1v0-dpbrdg { 50 compatible = "regulator-fixed"; 51 regulator-name = "pp1000_dpbrdg"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pp1000_dpbrdg_en_pins>; 54 regulator-min-microvolt = <1000000>; 55 regulator-max-microvolt = <1000000>; 56 enable-active-high; 57 regulator-boot-on; 58 gpio = <&pio 19 GPIO_ACTIVE_HIGH>; 59 vin-supply = <&mt6359_vs2_buck_reg>; 60 }; 61 62 pp1000_mipibrdg: regulator-1v0-mipibrdg { 63 compatible = "regulator-fixed"; 64 regulator-name = "pp1000_mipibrdg"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pp1000_mipibrdg_en_pins>; 67 regulator-min-microvolt = <1000000>; 68 regulator-max-microvolt = <1000000>; 69 enable-active-high; 70 regulator-boot-on; 71 gpio = <&pio 129 GPIO_ACTIVE_HIGH>; 72 vin-supply = <&mt6359_vs2_buck_reg>; 73 }; 74 75 pp1800_dpbrdg: regulator-1v8-dpbrdg { 76 compatible = "regulator-fixed"; 77 regulator-name = "pp1800_dpbrdg"; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pp1800_dpbrdg_en_pins>; 80 enable-active-high; 81 regulator-boot-on; 82 gpio = <&pio 126 GPIO_ACTIVE_HIGH>; 83 vin-supply = <&mt6359_vio18_ldo_reg>; 84 }; 85 86 /* system wide LDO 1.8V power rail */ 87 pp1800_ldo_g: regulator-1v8-g { 88 compatible = "regulator-fixed"; 89 regulator-name = "pp1800_ldo_g"; 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <1800000>; 93 regulator-max-microvolt = <1800000>; 94 vin-supply = <&pp3300_g>; 95 }; 96 97 pp1800_mipibrdg: regulator-1v8-mipibrdg { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp1800_mipibrdg"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pp1800_mipibrdg_en_pins>; 102 enable-active-high; 103 regulator-boot-on; 104 gpio = <&pio 128 GPIO_ACTIVE_HIGH>; 105 vin-supply = <&mt6359_vio18_ldo_reg>; 106 }; 107 108 pp3300_dpbrdg: regulator-3v3-dpbrdg { 109 compatible = "regulator-fixed"; 110 regulator-name = "pp3300_dpbrdg"; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pp3300_dpbrdg_en_pins>; 113 enable-active-high; 114 regulator-boot-on; 115 gpio = <&pio 26 GPIO_ACTIVE_HIGH>; 116 vin-supply = <&pp3300_g>; 117 }; 118 119 /* system wide switching 3.3V power rail */ 120 pp3300_g: regulator-3v3-g { 121 compatible = "regulator-fixed"; 122 regulator-name = "pp3300_g"; 123 regulator-always-on; 124 regulator-boot-on; 125 regulator-min-microvolt = <3300000>; 126 regulator-max-microvolt = <3300000>; 127 vin-supply = <&ppvar_sys>; 128 }; 129 130 /* system wide LDO 3.3V power rail */ 131 pp3300_ldo_z: regulator-3v3-z { 132 compatible = "regulator-fixed"; 133 regulator-name = "pp3300_ldo_z"; 134 regulator-always-on; 135 regulator-boot-on; 136 regulator-min-microvolt = <3300000>; 137 regulator-max-microvolt = <3300000>; 138 vin-supply = <&ppvar_sys>; 139 }; 140 141 pp3300_mipibrdg: regulator-3v3-mipibrdg { 142 compatible = "regulator-fixed"; 143 regulator-name = "pp3300_mipibrdg"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pp3300_mipibrdg_en_pins>; 146 enable-active-high; 147 regulator-boot-on; 148 gpio = <&pio 127 GPIO_ACTIVE_HIGH>; 149 vin-supply = <&pp3300_g>; 150 off-on-delay-us = <500000>; 151 }; 152 153 /* separately switched 3.3V power rail */ 154 pp3300_u: regulator-3v3-u { 155 compatible = "regulator-fixed"; 156 regulator-name = "pp3300_u"; 157 regulator-always-on; 158 regulator-boot-on; 159 regulator-min-microvolt = <3300000>; 160 regulator-max-microvolt = <3300000>; 161 /* enable pin wired to GPIO controlled by EC */ 162 vin-supply = <&pp3300_g>; 163 }; 164 165 pp3300_wlan: regulator-3v3-wlan { 166 compatible = "regulator-fixed"; 167 regulator-name = "pp3300_wlan"; 168 regulator-always-on; 169 regulator-boot-on; 170 regulator-min-microvolt = <3300000>; 171 regulator-max-microvolt = <3300000>; 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pp3300_wlan_pins>; 174 enable-active-high; 175 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 176 }; 177 178 /* system wide switching 5.0V power rail */ 179 pp5000_a: regulator-5v0-a { 180 compatible = "regulator-fixed"; 181 regulator-name = "pp5000_a"; 182 regulator-always-on; 183 regulator-boot-on; 184 regulator-min-microvolt = <5000000>; 185 regulator-max-microvolt = <5000000>; 186 vin-supply = <&ppvar_sys>; 187 }; 188 189 /* system wide semi-regulated power rail from battery or USB */ 190 ppvar_sys: regulator-var-sys { 191 compatible = "regulator-fixed"; 192 regulator-name = "ppvar_sys"; 193 regulator-always-on; 194 regulator-boot-on; 195 }; 196 197 reserved_memory: reserved-memory { 198 #address-cells = <2>; 199 #size-cells = <2>; 200 ranges; 201 202 scp_mem_reserved: scp@50000000 { 203 compatible = "shared-dma-pool"; 204 reg = <0 0x50000000 0 0x2900000>; 205 no-map; 206 }; 207 208 wifi_restricted_dma_region: wifi@c0000000 { 209 compatible = "restricted-dma-pool"; 210 reg = <0 0xc0000000 0 0x4000000>; 211 }; 212 }; 213 214 rt1015p: audio-codec { 215 compatible = "realtek,rt1015p"; 216 pinctrl-names = "default"; 217 pinctrl-0 = <&rt1015p_pins>; 218 sdb-gpios = <&pio 147 GPIO_ACTIVE_HIGH>; 219 #sound-dai-cells = <0>; 220 }; 221 222 sound: sound { 223 mediatek,platform = <&afe>; 224 pinctrl-names = "aud_clk_mosi_off", 225 "aud_clk_mosi_on", 226 "aud_dat_mosi_off", 227 "aud_dat_mosi_on", 228 "aud_dat_miso_off", 229 "aud_dat_miso_on", 230 "vow_dat_miso_off", 231 "vow_dat_miso_on", 232 "vow_clk_miso_off", 233 "vow_clk_miso_on", 234 "aud_nle_mosi_off", 235 "aud_nle_mosi_on", 236 "aud_dat_miso2_off", 237 "aud_dat_miso2_on", 238 "aud_gpio_i2s3_off", 239 "aud_gpio_i2s3_on", 240 "aud_gpio_i2s8_off", 241 "aud_gpio_i2s8_on", 242 "aud_gpio_i2s9_off", 243 "aud_gpio_i2s9_on", 244 "aud_dat_mosi_ch34_off", 245 "aud_dat_mosi_ch34_on", 246 "aud_dat_miso_ch34_off", 247 "aud_dat_miso_ch34_on", 248 "aud_gpio_tdm_off", 249 "aud_gpio_tdm_on"; 250 pinctrl-0 = <&aud_clk_mosi_off_pins>; 251 pinctrl-1 = <&aud_clk_mosi_on_pins>; 252 pinctrl-2 = <&aud_dat_mosi_off_pins>; 253 pinctrl-3 = <&aud_dat_mosi_on_pins>; 254 pinctrl-4 = <&aud_dat_miso_off_pins>; 255 pinctrl-5 = <&aud_dat_miso_on_pins>; 256 pinctrl-6 = <&vow_dat_miso_off_pins>; 257 pinctrl-7 = <&vow_dat_miso_on_pins>; 258 pinctrl-8 = <&vow_clk_miso_off_pins>; 259 pinctrl-9 = <&vow_clk_miso_on_pins>; 260 pinctrl-10 = <&aud_nle_mosi_off_pins>; 261 pinctrl-11 = <&aud_nle_mosi_on_pins>; 262 pinctrl-12 = <&aud_dat_miso2_off_pins>; 263 pinctrl-13 = <&aud_dat_miso2_on_pins>; 264 pinctrl-14 = <&aud_gpio_i2s3_off_pins>; 265 pinctrl-15 = <&aud_gpio_i2s3_on_pins>; 266 pinctrl-16 = <&aud_gpio_i2s8_off_pins>; 267 pinctrl-17 = <&aud_gpio_i2s8_on_pins>; 268 pinctrl-18 = <&aud_gpio_i2s9_off_pins>; 269 pinctrl-19 = <&aud_gpio_i2s9_on_pins>; 270 pinctrl-20 = <&aud_dat_mosi_ch34_off_pins>; 271 pinctrl-21 = <&aud_dat_mosi_ch34_on_pins>; 272 pinctrl-22 = <&aud_dat_miso_ch34_off_pins>; 273 pinctrl-23 = <&aud_dat_miso_ch34_on_pins>; 274 pinctrl-24 = <&aud_gpio_tdm_off_pins>; 275 pinctrl-25 = <&aud_gpio_tdm_on_pins>; 276 }; 277}; 278 279&dsi0 { 280 status = "okay"; 281}; 282 283&dsi_out { 284 remote-endpoint = <&anx7625_in>; 285}; 286 287&gic { 288 mediatek,broken-save-restore-fw; 289}; 290 291&gpu { 292 mali-supply = <&mt6315_7_vbuck1>; 293 status = "okay"; 294}; 295 296&i2c0 { 297 status = "okay"; 298 299 clock-frequency = <400000>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&i2c0_pins>; 302 303 touchscreen: touchscreen@10 { 304 reg = <0x10>; 305 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&touchscreen_pins>; 308 }; 309}; 310 311&i2c1 { 312 status = "okay"; 313 314 clock-frequency = <400000>; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&i2c1_pins>; 317 318 rt5682: audio-codec@1a { 319 /* Realtek RT5682i or RT5682s, sharing the same configuration */ 320 reg = <0x1a>; 321 interrupts-extended = <&pio 18 IRQ_TYPE_LEVEL_LOW>; 322 realtek,jd-src = <1>; 323 #sound-dai-cells = <1>; 324 325 AVDD-supply = <&mt6359_vio18_ldo_reg>; 326 DBVDD-supply = <&mt6359_vio18_ldo_reg>; 327 LDO1-IN-supply = <&mt6359_vio18_ldo_reg>; 328 MICVDD-supply = <&pp3300_g>; 329 }; 330}; 331 332&i2c2 { 333 status = "okay"; 334 335 clock-frequency = <400000>; 336 clock-stretch-ns = <12600>; 337 pinctrl-names = "default"; 338 pinctrl-0 = <&i2c2_pins>, <&trackpad_pins>; 339 340 trackpad@15 { 341 compatible = "elan,ekth3000"; 342 reg = <0x15>; 343 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 344 vcc-supply = <&pp3300_u>; 345 wakeup-source; 346 }; 347}; 348 349&i2c3 { 350 status = "okay"; 351 352 clock-frequency = <400000>; 353 pinctrl-names = "default"; 354 pinctrl-0 = <&i2c3_pins>; 355 356 anx_bridge: anx7625@58 { 357 compatible = "analogix,anx7625"; 358 reg = <0x58>; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&anx7625_pins>; 361 enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>; 362 reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; 363 vdd10-supply = <&pp1000_mipibrdg>; 364 vdd18-supply = <&pp1800_mipibrdg>; 365 vdd33-supply = <&pp3300_mipibrdg>; 366 367 ports { 368 #address-cells = <1>; 369 #size-cells = <0>; 370 371 port@0 { 372 reg = <0>; 373 374 anx7625_in: endpoint { 375 remote-endpoint = <&dsi_out>; 376 }; 377 }; 378 379 port@1 { 380 reg = <1>; 381 382 anx7625_out: endpoint { 383 remote-endpoint = <&panel_in>; 384 }; 385 }; 386 }; 387 388 aux-bus { 389 panel: panel { 390 compatible = "edp-panel"; 391 power-supply = <&pp3300_mipibrdg>; 392 backlight = <&backlight_lcd0>; 393 394 port { 395 panel_in: endpoint { 396 remote-endpoint = <&anx7625_out>; 397 }; 398 }; 399 }; 400 }; 401 }; 402}; 403 404&i2c7 { 405 status = "okay"; 406 407 clock-frequency = <400000>; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&i2c7_pins>; 410}; 411 412&mfg0 { 413 domain-supply = <&mt6315_7_vbuck1>; 414}; 415 416&mfg1 { 417 domain-supply = <&mt6359_vsram_others_ldo_reg>; 418}; 419 420&mipi_tx0 { 421 status = "okay"; 422}; 423 424&mmc0 { 425 status = "okay"; 426 427 pinctrl-names = "default", "state_uhs"; 428 pinctrl-0 = <&mmc0_default_pins>; 429 pinctrl-1 = <&mmc0_uhs_pins>; 430 bus-width = <8>; 431 max-frequency = <200000000>; 432 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 433 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 434 cap-mmc-highspeed; 435 mmc-hs200-1_8v; 436 mmc-hs400-1_8v; 437 supports-cqe; 438 cap-mmc-hw-reset; 439 mmc-hs400-enhanced-strobe; 440 hs400-ds-delay = <0x12814>; 441 no-sdio; 442 no-sd; 443 non-removable; 444}; 445 446&mmc1 { 447 status = "okay"; 448 449 pinctrl-names = "default", "state_uhs"; 450 pinctrl-0 = <&mmc1_default_pins>; 451 pinctrl-1 = <&mmc1_uhs_pins>; 452 bus-width = <4>; 453 max-frequency = <200000000>; 454 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 455 vmmc-supply = <&mt6360_ldo5_reg>; 456 vqmmc-supply = <&mt6360_ldo3_reg>; 457 cap-sd-highspeed; 458 sd-uhs-sdr50; 459 sd-uhs-sdr104; 460 no-sdio; 461 no-mmc; 462}; 463 464/* for CORE */ 465&mt6359_vgpu11_buck_reg { 466 regulator-always-on; 467}; 468 469&mt6359_vgpu11_sshub_buck_reg { 470 regulator-always-on; 471 regulator-min-microvolt = <575000>; 472 regulator-max-microvolt = <575000>; 473}; 474 475&mt6359_vrf12_ldo_reg { 476 regulator-always-on; 477}; 478 479&mt6359_vsram_others_ldo_reg { 480 regulator-min-microvolt = <750000>; 481 regulator-max-microvolt = <800000>; 482 regulator-coupled-with = <&mt6315_7_vbuck1>; 483 regulator-coupled-max-spread = <10000>; 484}; 485 486&mt6359_vufs_ldo_reg { 487 regulator-always-on; 488}; 489 490&mt6359codec { 491 mediatek,dmic-mode = <1>; /* one-wire */ 492 mediatek,mic-type-0 = <2>; /* DMIC */ 493 mediatek,mic-type-2 = <2>; /* DMIC */ 494}; 495 496&nor_flash { 497 status = "okay"; 498 499 pinctrl-names = "default"; 500 pinctrl-0 = <&nor_flash_pins>; 501 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 502 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; 503 504 flash@0 { 505 compatible = "winbond,w25q64jwm", "jedec,spi-nor"; 506 reg = <0>; 507 spi-max-frequency = <52000000>; 508 spi-rx-bus-width = <2>; 509 spi-tx-bus-width = <2>; 510 }; 511}; 512 513&pcie { 514 pinctrl-names = "default"; 515 pinctrl-0 = <&pcie_pins>; 516 517 pcie0: pcie@0,0 { 518 device_type = "pci"; 519 reg = <0x0000 0 0 0 0>; 520 num-lanes = <1>; 521 bus-range = <0x1 0x1>; 522 523 #address-cells = <3>; 524 #size-cells = <2>; 525 ranges; 526 527 wifi: wifi@0,0 { 528 reg = <0x10000 0 0 0 0x100000>, 529 <0x10000 0 0x100000 0 0x100000>; 530 memory-region = <&wifi_restricted_dma_region>; 531 }; 532 }; 533}; 534 535&pio { 536 /* 220 lines */ 537 gpio-line-names = "I2S_DP_LRCK", 538 "IS_DP_BCLK", 539 "I2S_DP_MCLK", 540 "I2S_DP_DATAOUT", 541 "SAR0_INT_ODL", 542 "EC_AP_INT_ODL", 543 "EDPBRDG_INT_ODL", 544 "DPBRDG_INT_ODL", 545 "DPBRDG_PWREN", 546 "DPBRDG_RST_ODL", 547 "I2S_HP_MCLK", 548 "I2S_HP_BCK", 549 "I2S_HP_LRCK", 550 "I2S_HP_DATAIN", 551 /* 552 * AP_FLASH_WP_L is crossystem ABI. Schematics 553 * call it AP_FLASH_WP_ODL. 554 */ 555 "AP_FLASH_WP_L", 556 "TRACKPAD_INT_ODL", 557 "EC_AP_HPD_OD", 558 "SD_CD_ODL", 559 "HP_INT_ODL_ALC", 560 "EN_PP1000_DPBRDG", 561 "AP_GPIO20", 562 "TOUCH_INT_L_1V8", 563 "UART_BT_WAKE_ODL", 564 "AP_GPIO23", 565 "AP_SPI_FLASH_CS_L", 566 "AP_SPI_FLASH_CLK", 567 "EN_PP3300_DPBRDG_DX", 568 "AP_SPI_FLASH_MOSI", 569 "AP_SPI_FLASH_MISO", 570 "I2S_HP_DATAOUT", 571 "AP_GPIO30", 572 "I2S_SPKR_MCLK", 573 "I2S_SPKR_BCLK", 574 "I2S_SPKR_LRCK", 575 "I2S_SPKR_DATAIN", 576 "I2S_SPKR_DATAOUT", 577 "AP_SPI_H1_TPM_CLK", 578 "AP_SPI_H1_TPM_CS_L", 579 "AP_SPI_H1_TPM_MISO", 580 "AP_SPI_H1_TPM_MOSI", 581 "BL_PWM", 582 "EDPBRDG_PWREN", 583 "EDPBRDG_RST_ODL", 584 "EN_PP3300_HUB", 585 "HUB_RST_L", 586 "", 587 "", 588 "", 589 "", 590 "", 591 "", 592 "SD_CLK", 593 "SD_CMD", 594 "SD_DATA3", 595 "SD_DATA0", 596 "SD_DATA2", 597 "SD_DATA1", 598 "", 599 "", 600 "", 601 "", 602 "", 603 "", 604 "PCIE_WAKE_ODL", 605 "PCIE_RST_L", 606 "PCIE_CLKREQ_ODL", 607 "", 608 "", 609 "", 610 "", 611 "", 612 "", 613 "", 614 "", 615 "", 616 "", 617 "", 618 "", 619 "", 620 "", 621 "", 622 "", 623 "", 624 "", 625 "", 626 "", 627 "", 628 "", 629 "", 630 "SPMI_SCL", 631 "SPMI_SDA", 632 "AP_GOOD", 633 "UART_DBG_TX_AP_RX", 634 "UART_AP_TX_DBG_RX", 635 "UART_AP_TX_BT_RX", 636 "UART_BT_TX_AP_RX", 637 "MIPI_DPI_D0_R", 638 "MIPI_DPI_D1_R", 639 "MIPI_DPI_D2_R", 640 "MIPI_DPI_D3_R", 641 "MIPI_DPI_D4_R", 642 "MIPI_DPI_D5_R", 643 "MIPI_DPI_D6_R", 644 "MIPI_DPI_D7_R", 645 "MIPI_DPI_D8_R", 646 "MIPI_DPI_D9_R", 647 "MIPI_DPI_D10_R", 648 "", 649 "", 650 "MIPI_DPI_DE_R", 651 "MIPI_DPI_D11_R", 652 "MIPI_DPI_VSYNC_R", 653 "MIPI_DPI_CLK_R", 654 "MIPI_DPI_HSYNC_R", 655 "PCM_BT_DATAIN", 656 "PCM_BT_SYNC", 657 "PCM_BT_DATAOUT", 658 "PCM_BT_CLK", 659 "AP_I2C_AUDIO_SCL", 660 "AP_I2C_AUDIO_SDA", 661 "SCP_I2C_SCL", 662 "SCP_I2C_SDA", 663 "AP_I2C_WLAN_SCL", 664 "AP_I2C_WLAN_SDA", 665 "AP_I2C_DPBRDG_SCL", 666 "AP_I2C_DPBRDG_SDA", 667 "EN_PP1800_DPBRDG_DX", 668 "EN_PP3300_EDP_DX", 669 "EN_PP1800_EDPBRDG_DX", 670 "EN_PP1000_EDPBRDG", 671 "SCP_JTAG0_TDO", 672 "SCP_JTAG0_TDI", 673 "SCP_JTAG0_TMS", 674 "SCP_JTAG0_TCK", 675 "SCP_JTAG0_TRSTN", 676 "EN_PP3000_VMC_PMU", 677 "EN_PP3300_DISPLAY_DX", 678 "TOUCH_RST_L_1V8", 679 "TOUCH_REPORT_DISABLE", 680 "", 681 "", 682 "AP_I2C_TRACKPAD_SCL_1V8", 683 "AP_I2C_TRACKPAD_SDA_1V8", 684 "EN_PP3300_WLAN", 685 "BT_KILL_L", 686 "WIFI_KILL_L", 687 "SET_VMC_VOLT_AT_1V8", 688 "EN_SPK", 689 "AP_WARM_RST_REQ", 690 "", 691 "", 692 "EN_PP3000_SD_S3", 693 "AP_EDP_BKLTEN", 694 "", 695 "", 696 "", 697 "AP_SPI_EC_CLK", 698 "AP_SPI_EC_CS_L", 699 "AP_SPI_EC_MISO", 700 "AP_SPI_EC_MOSI", 701 "AP_I2C_EDPBRDG_SCL", 702 "AP_I2C_EDPBRDG_SDA", 703 "MT6315_PROC_INT", 704 "MT6315_GPU_INT", 705 "UART_SERVO_TX_SCP_RX", 706 "UART_SCP_TX_SERVO_RX", 707 "BT_RTS_AP_CTS", 708 "AP_RTS_BT_CTS", 709 "UART_AP_WAKE_BT_ODL", 710 "WLAN_ALERT_ODL", 711 "EC_IN_RW_ODL", 712 "H1_AP_INT_ODL", 713 "", 714 "", 715 "", 716 "", 717 "", 718 "", 719 "", 720 "", 721 "", 722 "", 723 "", 724 "MSDC0_CMD", 725 "MSDC0_DAT0", 726 "MSDC0_DAT2", 727 "MSDC0_DAT4", 728 "MSDC0_DAT6", 729 "MSDC0_DAT1", 730 "MSDC0_DAT5", 731 "MSDC0_DAT7", 732 "MSDC0_DSL", 733 "MSDC0_CLK", 734 "MSDC0_DAT3", 735 "MSDC0_RST_L", 736 "SCP_VREQ_VAO", 737 "AUD_DAT_MOSI2", 738 "AUD_NLE_MOSI1", 739 "AUD_NLE_MOSI0", 740 "AUD_DAT_MISO2", 741 "AP_I2C_SAR_SDA", 742 "AP_I2C_SAR_SCL", 743 "AP_I2C_PWR_SCL", 744 "AP_I2C_PWR_SDA", 745 "AP_I2C_TS_SCL_1V8", 746 "AP_I2C_TS_SDA_1V8", 747 "SRCLKENA0", 748 "SRCLKENA1", 749 "AP_EC_WATCHDOG_L", 750 "PWRAP_SPI0_MI", 751 "PWRAP_SPI0_CSN", 752 "PWRAP_SPI0_MO", 753 "PWRAP_SPI0_CK", 754 "AP_RTC_CLK32K", 755 "AUD_CLK_MOSI", 756 "AUD_SYNC_MOSI", 757 "AUD_DAT_MOSI0", 758 "AUD_DAT_MOSI1", 759 "AUD_DAT_MISO0", 760 "AUD_DAT_MISO1"; 761 762 anx7625_pins: anx7625-default-pins { 763 pins-out { 764 pinmux = <PINMUX_GPIO41__FUNC_GPIO41>, 765 <PINMUX_GPIO42__FUNC_GPIO42>; 766 output-low; 767 }; 768 769 pins-in { 770 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 771 input-enable; 772 bias-pull-up; 773 }; 774 }; 775 776 aud_clk_mosi_off_pins: aud-clk-mosi-off-pins { 777 pins-mosi-off { 778 pinmux = <PINMUX_GPIO214__FUNC_GPIO214>, 779 <PINMUX_GPIO215__FUNC_GPIO215>; 780 }; 781 }; 782 783 aud_clk_mosi_on_pins: aud-clk-mosi-on-pins { 784 pins-mosi-on { 785 pinmux = <PINMUX_GPIO214__FUNC_AUD_CLK_MOSI>, 786 <PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI>; 787 drive-strength = <10>; 788 }; 789 }; 790 791 aud_dat_miso_ch34_off_pins: aud-dat-miso-ch34-off-pins { 792 pins-miso-off { 793 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 794 }; 795 }; 796 797 aud_dat_miso_ch34_on_pins: aud-dat-miso-ch34-on-pins { 798 pins-miso-on { 799 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 800 }; 801 }; 802 803 aud_dat_miso_off_pins: aud-dat-miso-off-pins { 804 pins-miso-off { 805 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>, 806 <PINMUX_GPIO219__FUNC_GPIO219>; 807 }; 808 }; 809 810 aud_dat_miso_on_pins: aud-dat-miso-on-pins { 811 pins-miso-on { 812 pinmux = <PINMUX_GPIO218__FUNC_AUD_DAT_MISO0>, 813 <PINMUX_GPIO219__FUNC_AUD_DAT_MISO1>; 814 drive-strength = <10>; 815 }; 816 }; 817 818 aud_dat_miso2_off_pins: aud-dat-miso2-off-pins { 819 pins-miso-off { 820 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 821 }; 822 }; 823 824 aud_dat_miso2_on_pins: aud-dat-miso2-on-pins { 825 pins-miso-on { 826 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 827 }; 828 }; 829 830 aud_dat_mosi_ch34_off_pins: aud-dat-mosi-ch34-off-pins { 831 pins-mosi-off { 832 pinmux = <PINMUX_GPIO196__FUNC_GPIO196>; 833 }; 834 }; 835 836 aud_dat_mosi_ch34_on_pins: aud-dat-mosi-ch34-on-pins { 837 pins-mosi-on { 838 pinmux = <PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2>; 839 }; 840 }; 841 842 aud_dat_mosi_off_pins: aud-dat-mosi-off-pins { 843 pins-mosi-off { 844 pinmux = <PINMUX_GPIO216__FUNC_GPIO216>, 845 <PINMUX_GPIO217__FUNC_GPIO217>; 846 }; 847 }; 848 849 aud_dat_mosi_on_pins: aud-dat-mosi-on-pins { 850 pins-mosi-on { 851 pinmux = <PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0>, 852 <PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1>; 853 drive-strength = <10>; 854 }; 855 }; 856 857 aud_gpio_i2s3_off_pins: aud-gpio-i2s3-off-pins { 858 pins-i2s3-off { 859 pinmux = <PINMUX_GPIO32__FUNC_GPIO32>, 860 <PINMUX_GPIO33__FUNC_GPIO33>, 861 <PINMUX_GPIO35__FUNC_GPIO35>; 862 }; 863 }; 864 865 aud_gpio_i2s3_on_pins: aud-gpio-i2s3-on-pins { 866 pins-i2s3-on { 867 pinmux = <PINMUX_GPIO32__FUNC_I2S3_BCK>, 868 <PINMUX_GPIO33__FUNC_I2S3_LRCK>, 869 <PINMUX_GPIO35__FUNC_I2S3_DO>; 870 }; 871 }; 872 873 aud_gpio_i2s8_off_pins: aud-gpio-i2s8-off-pins { 874 pins-i2s8-off { 875 pinmux = <PINMUX_GPIO10__FUNC_GPIO10>, 876 <PINMUX_GPIO11__FUNC_GPIO11>, 877 <PINMUX_GPIO12__FUNC_GPIO12>, 878 <PINMUX_GPIO13__FUNC_GPIO13>; 879 }; 880 }; 881 882 aud_gpio_i2s8_on_pins: aud-gpio-i2s8-on-pins { 883 pins-i2s8-on { 884 pinmux = <PINMUX_GPIO10__FUNC_I2S8_MCK>, 885 <PINMUX_GPIO11__FUNC_I2S8_BCK>, 886 <PINMUX_GPIO12__FUNC_I2S8_LRCK>, 887 <PINMUX_GPIO13__FUNC_I2S8_DI>; 888 }; 889 }; 890 891 aud_gpio_i2s9_off_pins: aud-gpio-i2s9-off-pins { 892 pins-i2s9-off { 893 pinmux = <PINMUX_GPIO29__FUNC_GPIO29>; 894 }; 895 }; 896 897 aud_gpio_i2s9_on_pins: aud-gpio-i2s9-on-pins { 898 pins-i2s9-on { 899 pinmux = <PINMUX_GPIO29__FUNC_I2S9_DO>; 900 }; 901 }; 902 903 aud_gpio_tdm_off_pins: aud-gpio-tdm-off-pins { 904 pins-tdm-off { 905 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>, 906 <PINMUX_GPIO1__FUNC_GPIO1>, 907 <PINMUX_GPIO2__FUNC_GPIO2>, 908 <PINMUX_GPIO3__FUNC_GPIO3>; 909 }; 910 }; 911 912 aud_gpio_tdm_on_pins: aud-gpio-tdm-on-pins { 913 pins-tdm-on { 914 pinmux = <PINMUX_GPIO0__FUNC_TDM_LRCK>, 915 <PINMUX_GPIO1__FUNC_TDM_BCK>, 916 <PINMUX_GPIO2__FUNC_TDM_MCK>, 917 <PINMUX_GPIO3__FUNC_TDM_DATA0>; 918 }; 919 }; 920 921 aud_nle_mosi_off_pins: aud-nle-mosi-off-pins { 922 pins-nle-mosi-off { 923 pinmux = <PINMUX_GPIO197__FUNC_GPIO197>, 924 <PINMUX_GPIO198__FUNC_GPIO198>; 925 }; 926 }; 927 928 aud_nle_mosi_on_pins: aud-nle-mosi-on-pins { 929 pins-nle-mosi-on { 930 pinmux = <PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1>, 931 <PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0>; 932 }; 933 }; 934 935 cr50_int: cr50-irq-default-pins { 936 pins-gsc-ap-int-odl { 937 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 938 input-enable; 939 }; 940 }; 941 942 cros_ec_int: cros-ec-irq-default-pins { 943 pins-ec-ap-int-odl { 944 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 945 input-enable; 946 bias-pull-up; 947 }; 948 }; 949 950 i2c0_pins: i2c0-default-pins { 951 pins-bus { 952 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 953 <PINMUX_GPIO205__FUNC_SDA0>; 954 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 955 drive-strength-microamp = <1000>; 956 }; 957 }; 958 959 i2c1_pins: i2c1-default-pins { 960 pins-bus { 961 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 962 <PINMUX_GPIO119__FUNC_SDA1>; 963 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 964 drive-strength-microamp = <1000>; 965 }; 966 }; 967 968 i2c2_pins: i2c2-default-pins { 969 pins-bus { 970 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 971 <PINMUX_GPIO142__FUNC_SDA2>; 972 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 973 }; 974 }; 975 976 i2c3_pins: i2c3-default-pins { 977 pins-bus { 978 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 979 <PINMUX_GPIO161__FUNC_SDA3>; 980 bias-disable; 981 drive-strength-microamp = <1000>; 982 }; 983 }; 984 985 i2c7_pins: i2c7-default-pins { 986 pins-bus { 987 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 988 <PINMUX_GPIO125__FUNC_SDA7>; 989 bias-disable; 990 drive-strength-microamp = <1000>; 991 }; 992 }; 993 994 mmc0_default_pins: mmc0-default-pins { 995 pins-cmd-dat { 996 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 997 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 998 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 999 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 1000 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 1001 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 1002 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 1003 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 1004 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 1005 input-enable; 1006 drive-strength = <8>; 1007 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1008 }; 1009 1010 pins-clk { 1011 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 1012 drive-strength = <8>; 1013 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1014 }; 1015 1016 pins-rst { 1017 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 1018 drive-strength = <8>; 1019 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1020 }; 1021 }; 1022 1023 mmc0_uhs_pins: mmc0-uhs-pins { 1024 pins-cmd-dat { 1025 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 1026 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 1027 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 1028 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 1029 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 1030 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 1031 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 1032 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 1033 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 1034 input-enable; 1035 drive-strength = <10>; 1036 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1037 }; 1038 1039 pins-clk { 1040 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 1041 drive-strength = <10>; 1042 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1043 }; 1044 1045 pins-rst { 1046 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 1047 drive-strength = <8>; 1048 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1049 }; 1050 1051 pins-ds { 1052 pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 1053 drive-strength = <10>; 1054 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1055 }; 1056 }; 1057 1058 mmc1_default_pins: mmc1-default-pins { 1059 pins-cmd-dat { 1060 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1061 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1062 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1063 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1064 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1065 input-enable; 1066 drive-strength = <8>; 1067 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1068 }; 1069 1070 pins-clk { 1071 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1072 drive-strength = <8>; 1073 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1074 }; 1075 1076 pins-insert { 1077 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 1078 input-enable; 1079 bias-pull-up; 1080 }; 1081 }; 1082 1083 mmc1_uhs_pins: mmc1-uhs-pins { 1084 pins-cmd-dat { 1085 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1086 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1087 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1088 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1089 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1090 input-enable; 1091 drive-strength = <8>; 1092 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1093 }; 1094 1095 pins-clk { 1096 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1097 input-enable; 1098 drive-strength = <8>; 1099 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1100 }; 1101 }; 1102 1103 nor_flash_pins: nor-flash-default-pins { 1104 pins-cs-io1 { 1105 pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, 1106 <PINMUX_GPIO28__FUNC_SPINOR_IO1>; 1107 input-enable; 1108 bias-pull-up; 1109 drive-strength = <10>; 1110 }; 1111 1112 pins-io0 { 1113 pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; 1114 bias-pull-up; 1115 drive-strength = <10>; 1116 }; 1117 1118 pins-clk { 1119 pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; 1120 input-enable; 1121 bias-pull-up; 1122 drive-strength = <10>; 1123 }; 1124 }; 1125 1126 pcie_pins: pcie-default-pins { 1127 pins-pcie-wake { 1128 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 1129 bias-pull-up; 1130 }; 1131 1132 pins-pcie-pereset { 1133 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 1134 }; 1135 1136 pins-pcie-clkreq { 1137 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 1138 bias-pull-up; 1139 }; 1140 1141 pins-wifi-kill { 1142 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 1143 output-high; 1144 }; 1145 }; 1146 1147 pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { 1148 pins-en { 1149 pinmux = <PINMUX_GPIO19__FUNC_GPIO19>; 1150 output-low; 1151 }; 1152 }; 1153 1154 pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { 1155 pins-en { 1156 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 1157 output-low; 1158 }; 1159 }; 1160 1161 pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { 1162 pins-en { 1163 pinmux = <PINMUX_GPIO126__FUNC_GPIO126>; 1164 output-low; 1165 }; 1166 }; 1167 1168 pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { 1169 pins-en { 1170 pinmux = <PINMUX_GPIO128__FUNC_GPIO128>; 1171 output-low; 1172 }; 1173 }; 1174 1175 pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { 1176 pins-en { 1177 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>; 1178 output-low; 1179 }; 1180 }; 1181 1182 pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { 1183 pins-en { 1184 pinmux = <PINMUX_GPIO127__FUNC_GPIO127>; 1185 output-low; 1186 }; 1187 }; 1188 1189 pp3300_wlan_pins: pp3300-wlan-pins { 1190 pins-pcie-en-pp3300-wlan { 1191 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 1192 output-high; 1193 }; 1194 }; 1195 1196 pwm0_pins: pwm0-default-pins { 1197 pins-pwm { 1198 pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>; 1199 }; 1200 1201 pins-inhibit { 1202 pinmux = <PINMUX_GPIO152__FUNC_GPIO152>; 1203 output-high; 1204 }; 1205 }; 1206 1207 rt1015p_pins: rt1015p-default-pins { 1208 pins { 1209 pinmux = <PINMUX_GPIO147__FUNC_GPIO147>; 1210 output-low; 1211 }; 1212 }; 1213 1214 scp_pins: scp-pins { 1215 pins-vreq-vao { 1216 pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; 1217 }; 1218 }; 1219 1220 spi1_pins: spi1-default-pins { 1221 pins-cs-mosi-clk { 1222 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 1223 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 1224 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 1225 bias-disable; 1226 }; 1227 1228 pins-miso { 1229 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 1230 bias-pull-down; 1231 }; 1232 }; 1233 1234 spi5_pins: spi5-default-pins { 1235 pins-bus { 1236 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 1237 <PINMUX_GPIO37__FUNC_GPIO37>, 1238 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 1239 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 1240 bias-disable; 1241 }; 1242 }; 1243 1244 trackpad_pins: trackpad-default-pins { 1245 pins-int-n { 1246 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 1247 input-enable; 1248 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 1249 }; 1250 }; 1251 1252 touchscreen_pins: touchscreen-default-pins { 1253 pins-irq { 1254 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 1255 input-enable; 1256 bias-pull-up; 1257 }; 1258 1259 pins-reset { 1260 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 1261 output-high; 1262 }; 1263 1264 pins-report-sw { 1265 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 1266 output-low; 1267 }; 1268 }; 1269 1270 vow_clk_miso_off_pins: vow-clk-miso-off-pins { 1271 pins-miso-off { 1272 pinmux = <PINMUX_GPIO219__FUNC_GPIO219>; 1273 }; 1274 }; 1275 1276 vow_clk_miso_on_pins: vow-clk-miso-on-pins { 1277 pins-miso-on { 1278 pinmux = <PINMUX_GPIO219__FUNC_VOW_CLK_MISO>; 1279 }; 1280 }; 1281 1282 vow_dat_miso_off_pins: vow-dat-miso-off-pins { 1283 pins-miso-off { 1284 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>; 1285 }; 1286 }; 1287 1288 vow_dat_miso_on_pins: vow-dat-miso-on-pins { 1289 pins-miso-on { 1290 pinmux = <PINMUX_GPIO218__FUNC_VOW_DAT_MISO>; 1291 }; 1292 }; 1293}; 1294 1295&pmic { 1296 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 1297}; 1298 1299&pwm0 { 1300 status = "okay"; 1301 1302 pinctrl-names = "default"; 1303 pinctrl-0 = <&pwm0_pins>; 1304}; 1305 1306&scp { 1307 status = "okay"; 1308 1309 firmware-name = "mediatek/mt8192/scp.img"; 1310 memory-region = <&scp_mem_reserved>; 1311 pinctrl-names = "default"; 1312 pinctrl-0 = <&scp_pins>; 1313 1314 cros-ec-rpmsg { 1315 compatible = "google,cros-ec-rpmsg"; 1316 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1317 }; 1318}; 1319 1320&spi1 { 1321 status = "okay"; 1322 1323 mediatek,pad-select = <0>; 1324 pinctrl-names = "default"; 1325 pinctrl-0 = <&spi1_pins>; 1326 1327 cros_ec: ec@0 { 1328 compatible = "google,cros-ec-spi"; 1329 reg = <0>; 1330 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 1331 spi-max-frequency = <3000000>; 1332 pinctrl-names = "default"; 1333 pinctrl-0 = <&cros_ec_int>; 1334 wakeup-source; 1335 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 1339 cros_ec_pwm: pwm { 1340 compatible = "google,cros-ec-pwm"; 1341 #pwm-cells = <1>; 1342 1343 status = "disabled"; 1344 }; 1345 1346 i2c_tunnel: i2c-tunnel { 1347 compatible = "google,cros-ec-i2c-tunnel"; 1348 google,remote-bus = <0>; 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 }; 1352 1353 mt6360_ldo3_reg: regulator@0 { 1354 compatible = "google,cros-ec-regulator"; 1355 reg = <0>; 1356 regulator-min-microvolt = <1800000>; 1357 regulator-max-microvolt = <3300000>; 1358 }; 1359 1360 mt6360_ldo5_reg: regulator@1 { 1361 compatible = "google,cros-ec-regulator"; 1362 reg = <1>; 1363 regulator-min-microvolt = <3300000>; 1364 regulator-max-microvolt = <3300000>; 1365 }; 1366 1367 typec { 1368 compatible = "google,cros-ec-typec"; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 1372 usb_c0: connector@0 { 1373 compatible = "usb-c-connector"; 1374 reg = <0>; 1375 label = "left"; 1376 power-role = "dual"; 1377 data-role = "host"; 1378 try-power-role = "source"; 1379 }; 1380 1381 usb_c1: connector@1 { 1382 compatible = "usb-c-connector"; 1383 reg = <1>; 1384 label = "right"; 1385 power-role = "dual"; 1386 data-role = "host"; 1387 try-power-role = "source"; 1388 }; 1389 }; 1390 }; 1391}; 1392 1393&spi5 { 1394 status = "okay"; 1395 1396 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 1397 mediatek,pad-select = <0>; 1398 pinctrl-names = "default"; 1399 pinctrl-0 = <&spi5_pins>; 1400 1401 tpm@0 { 1402 compatible = "google,cr50"; 1403 reg = <0>; 1404 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 1405 spi-max-frequency = <1000000>; 1406 pinctrl-names = "default"; 1407 pinctrl-0 = <&cr50_int>; 1408 }; 1409}; 1410 1411&spmi { 1412 #address-cells = <2>; 1413 #size-cells = <0>; 1414 1415 mt6315_6: pmic@6 { 1416 compatible = "mediatek,mt6315-regulator"; 1417 reg = <0x6 SPMI_USID>; 1418 1419 regulators { 1420 mt6315_6_vbuck1: vbuck1 { 1421 regulator-compatible = "vbuck1"; 1422 regulator-name = "Vbcpu"; 1423 regulator-min-microvolt = <400000>; 1424 regulator-max-microvolt = <1193750>; 1425 regulator-enable-ramp-delay = <256>; 1426 regulator-allowed-modes = <0 1 2>; 1427 regulator-always-on; 1428 }; 1429 1430 mt6315_6_vbuck3: vbuck3 { 1431 regulator-compatible = "vbuck3"; 1432 regulator-name = "Vlcpu"; 1433 regulator-min-microvolt = <400000>; 1434 regulator-max-microvolt = <1193750>; 1435 regulator-enable-ramp-delay = <256>; 1436 regulator-allowed-modes = <0 1 2>; 1437 regulator-always-on; 1438 }; 1439 }; 1440 }; 1441 1442 mt6315_7: pmic@7 { 1443 compatible = "mediatek,mt6315-regulator"; 1444 reg = <0x7 SPMI_USID>; 1445 1446 regulators { 1447 mt6315_7_vbuck1: vbuck1 { 1448 regulator-compatible = "vbuck1"; 1449 regulator-name = "Vgpu"; 1450 regulator-min-microvolt = <400000>; 1451 regulator-max-microvolt = <800000>; 1452 regulator-enable-ramp-delay = <256>; 1453 regulator-allowed-modes = <0 1 2>; 1454 regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; 1455 regulator-coupled-max-spread = <10000>; 1456 }; 1457 }; 1458 }; 1459}; 1460 1461&uart0 { 1462 status = "okay"; 1463}; 1464 1465&xhci { 1466 status = "okay"; 1467 1468 wakeup-source; 1469 vusb33-supply = <&pp3300_g>; 1470 vbus-supply = <&pp5000_a>; 1471}; 1472 1473#include <arm/cros-ec-keyboard.dtsi> 1474#include <arm/cros-ec-sbs.dtsi> 1475