1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c7 = &i2c7; 19 mmc0 = &mmc0; 20 mmc1 = &mmc1; 21 serial0 = &uart0; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 memory@40000000 { 29 device_type = "memory"; 30 reg = <0 0x40000000 0 0x80000000>; 31 }; 32 33 backlight_lcd0: backlight-lcd0 { 34 compatible = "pwm-backlight"; 35 pwms = <&pwm0 0 500000>; 36 power-supply = <&ppvar_sys>; 37 enable-gpios = <&pio 152 0>; 38 brightness-levels = <0 1023>; 39 num-interpolated-steps = <1023>; 40 default-brightness-level = <576>; 41 }; 42 43 dmic_codec: dmic-codec { 44 compatible = "dmic-codec"; 45 num-channels = <2>; 46 wakeup-delay-ms = <50>; 47 }; 48 49 pp1000_dpbrdg: regulator-1v0-dpbrdg { 50 compatible = "regulator-fixed"; 51 regulator-name = "pp1000_dpbrdg"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pp1000_dpbrdg_en_pins>; 54 regulator-min-microvolt = <1000000>; 55 regulator-max-microvolt = <1000000>; 56 enable-active-high; 57 regulator-boot-on; 58 gpio = <&pio 19 GPIO_ACTIVE_HIGH>; 59 vin-supply = <&mt6359_vs2_buck_reg>; 60 }; 61 62 pp1000_mipibrdg: regulator-1v0-mipibrdg { 63 compatible = "regulator-fixed"; 64 regulator-name = "pp1000_mipibrdg"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pp1000_mipibrdg_en_pins>; 67 regulator-min-microvolt = <1000000>; 68 regulator-max-microvolt = <1000000>; 69 enable-active-high; 70 regulator-boot-on; 71 gpio = <&pio 129 GPIO_ACTIVE_HIGH>; 72 vin-supply = <&mt6359_vs2_buck_reg>; 73 }; 74 75 pp1800_dpbrdg: regulator-1v8-dpbrdg { 76 compatible = "regulator-fixed"; 77 regulator-name = "pp1800_dpbrdg"; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pp1800_dpbrdg_en_pins>; 80 enable-active-high; 81 regulator-boot-on; 82 gpio = <&pio 126 GPIO_ACTIVE_HIGH>; 83 vin-supply = <&mt6359_vio18_ldo_reg>; 84 }; 85 86 /* system wide LDO 1.8V power rail */ 87 pp1800_ldo_g: regulator-1v8-g { 88 compatible = "regulator-fixed"; 89 regulator-name = "pp1800_ldo_g"; 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <1800000>; 93 regulator-max-microvolt = <1800000>; 94 vin-supply = <&pp3300_g>; 95 }; 96 97 pp1800_mipibrdg: regulator-1v8-mipibrdg { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp1800_mipibrdg"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pp1800_mipibrdg_en_pins>; 102 enable-active-high; 103 regulator-boot-on; 104 gpio = <&pio 128 GPIO_ACTIVE_HIGH>; 105 vin-supply = <&mt6359_vio18_ldo_reg>; 106 }; 107 108 pp3300_dpbrdg: regulator-3v3-dpbrdg { 109 compatible = "regulator-fixed"; 110 regulator-name = "pp3300_dpbrdg"; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pp3300_dpbrdg_en_pins>; 113 enable-active-high; 114 regulator-boot-on; 115 gpio = <&pio 26 GPIO_ACTIVE_HIGH>; 116 vin-supply = <&pp3300_g>; 117 }; 118 119 /* system wide switching 3.3V power rail */ 120 pp3300_g: regulator-3v3-g { 121 compatible = "regulator-fixed"; 122 regulator-name = "pp3300_g"; 123 regulator-always-on; 124 regulator-boot-on; 125 regulator-min-microvolt = <3300000>; 126 regulator-max-microvolt = <3300000>; 127 vin-supply = <&ppvar_sys>; 128 }; 129 130 /* system wide LDO 3.3V power rail */ 131 pp3300_ldo_z: regulator-3v3-z { 132 compatible = "regulator-fixed"; 133 regulator-name = "pp3300_ldo_z"; 134 regulator-always-on; 135 regulator-boot-on; 136 regulator-min-microvolt = <3300000>; 137 regulator-max-microvolt = <3300000>; 138 vin-supply = <&ppvar_sys>; 139 }; 140 141 pp3300_mipibrdg: regulator-3v3-mipibrdg { 142 compatible = "regulator-fixed"; 143 regulator-name = "pp3300_mipibrdg"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pp3300_mipibrdg_en_pins>; 146 enable-active-high; 147 regulator-boot-on; 148 gpio = <&pio 127 GPIO_ACTIVE_HIGH>; 149 vin-supply = <&pp3300_g>; 150 }; 151 152 /* separately switched 3.3V power rail */ 153 pp3300_u: regulator-3v3-u { 154 compatible = "regulator-fixed"; 155 regulator-name = "pp3300_u"; 156 regulator-always-on; 157 regulator-boot-on; 158 regulator-min-microvolt = <3300000>; 159 regulator-max-microvolt = <3300000>; 160 /* enable pin wired to GPIO controlled by EC */ 161 vin-supply = <&pp3300_g>; 162 }; 163 164 pp3300_wlan: regulator-3v3-wlan { 165 compatible = "regulator-fixed"; 166 regulator-name = "pp3300_wlan"; 167 regulator-always-on; 168 regulator-boot-on; 169 regulator-min-microvolt = <3300000>; 170 regulator-max-microvolt = <3300000>; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pp3300_wlan_pins>; 173 enable-active-high; 174 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 175 }; 176 177 /* system wide switching 5.0V power rail */ 178 pp5000_a: regulator-5v0-a { 179 compatible = "regulator-fixed"; 180 regulator-name = "pp5000_a"; 181 regulator-always-on; 182 regulator-boot-on; 183 regulator-min-microvolt = <5000000>; 184 regulator-max-microvolt = <5000000>; 185 vin-supply = <&ppvar_sys>; 186 }; 187 188 /* system wide semi-regulated power rail from battery or USB */ 189 ppvar_sys: regulator-var-sys { 190 compatible = "regulator-fixed"; 191 regulator-name = "ppvar_sys"; 192 regulator-always-on; 193 regulator-boot-on; 194 }; 195 196 reserved_memory: reserved-memory { 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges; 200 201 scp_mem_reserved: scp@50000000 { 202 compatible = "shared-dma-pool"; 203 reg = <0 0x50000000 0 0x2900000>; 204 no-map; 205 }; 206 207 wifi_restricted_dma_region: wifi@c0000000 { 208 compatible = "restricted-dma-pool"; 209 reg = <0 0xc0000000 0 0x4000000>; 210 }; 211 }; 212 213 sound: sound { 214 mediatek,platform = <&afe>; 215 pinctrl-names = "aud_clk_mosi_off", 216 "aud_clk_mosi_on", 217 "aud_dat_mosi_off", 218 "aud_dat_mosi_on", 219 "aud_dat_miso_off", 220 "aud_dat_miso_on", 221 "vow_dat_miso_off", 222 "vow_dat_miso_on", 223 "vow_clk_miso_off", 224 "vow_clk_miso_on", 225 "aud_nle_mosi_off", 226 "aud_nle_mosi_on", 227 "aud_dat_miso2_off", 228 "aud_dat_miso2_on", 229 "aud_gpio_i2s3_off", 230 "aud_gpio_i2s3_on", 231 "aud_gpio_i2s8_off", 232 "aud_gpio_i2s8_on", 233 "aud_gpio_i2s9_off", 234 "aud_gpio_i2s9_on", 235 "aud_dat_mosi_ch34_off", 236 "aud_dat_mosi_ch34_on", 237 "aud_dat_miso_ch34_off", 238 "aud_dat_miso_ch34_on", 239 "aud_gpio_tdm_off", 240 "aud_gpio_tdm_on"; 241 pinctrl-0 = <&aud_clk_mosi_off_pins>; 242 pinctrl-1 = <&aud_clk_mosi_on_pins>; 243 pinctrl-2 = <&aud_dat_mosi_off_pins>; 244 pinctrl-3 = <&aud_dat_mosi_on_pins>; 245 pinctrl-4 = <&aud_dat_miso_off_pins>; 246 pinctrl-5 = <&aud_dat_miso_on_pins>; 247 pinctrl-6 = <&vow_dat_miso_off_pins>; 248 pinctrl-7 = <&vow_dat_miso_on_pins>; 249 pinctrl-8 = <&vow_clk_miso_off_pins>; 250 pinctrl-9 = <&vow_clk_miso_on_pins>; 251 pinctrl-10 = <&aud_nle_mosi_off_pins>; 252 pinctrl-11 = <&aud_nle_mosi_on_pins>; 253 pinctrl-12 = <&aud_dat_miso2_off_pins>; 254 pinctrl-13 = <&aud_dat_miso2_on_pins>; 255 pinctrl-14 = <&aud_gpio_i2s3_off_pins>; 256 pinctrl-15 = <&aud_gpio_i2s3_on_pins>; 257 pinctrl-16 = <&aud_gpio_i2s8_off_pins>; 258 pinctrl-17 = <&aud_gpio_i2s8_on_pins>; 259 pinctrl-18 = <&aud_gpio_i2s9_off_pins>; 260 pinctrl-19 = <&aud_gpio_i2s9_on_pins>; 261 pinctrl-20 = <&aud_dat_mosi_ch34_off_pins>; 262 pinctrl-21 = <&aud_dat_mosi_ch34_on_pins>; 263 pinctrl-22 = <&aud_dat_miso_ch34_off_pins>; 264 pinctrl-23 = <&aud_dat_miso_ch34_on_pins>; 265 pinctrl-24 = <&aud_gpio_tdm_off_pins>; 266 pinctrl-25 = <&aud_gpio_tdm_on_pins>; 267 }; 268}; 269 270&dsi0 { 271 status = "okay"; 272}; 273 274&dsi_out { 275 remote-endpoint = <&anx7625_in>; 276}; 277 278&gpu { 279 mali-supply = <&mt6315_7_vbuck1>; 280 status = "okay"; 281}; 282 283&i2c0 { 284 status = "okay"; 285 286 clock-frequency = <400000>; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&i2c0_pins>; 289 290 touchscreen: touchscreen@10 { 291 reg = <0x10>; 292 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&touchscreen_pins>; 295 }; 296}; 297 298&i2c1 { 299 status = "okay"; 300 301 clock-frequency = <400000>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&i2c1_pins>; 304}; 305 306&i2c2 { 307 status = "okay"; 308 309 clock-frequency = <400000>; 310 clock-stretch-ns = <12600>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&i2c2_pins>; 313 314 trackpad@15 { 315 compatible = "elan,ekth3000"; 316 reg = <0x15>; 317 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&trackpad_pins>; 320 vcc-supply = <&pp3300_u>; 321 wakeup-source; 322 }; 323}; 324 325&i2c3 { 326 status = "okay"; 327 328 clock-frequency = <400000>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&i2c3_pins>; 331 332 anx_bridge: anx7625@58 { 333 compatible = "analogix,anx7625"; 334 reg = <0x58>; 335 pinctrl-names = "default"; 336 pinctrl-0 = <&anx7625_pins>; 337 enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>; 338 reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; 339 vdd10-supply = <&pp1000_mipibrdg>; 340 vdd18-supply = <&pp1800_mipibrdg>; 341 vdd33-supply = <&pp3300_mipibrdg>; 342 343 ports { 344 #address-cells = <1>; 345 #size-cells = <0>; 346 347 port@0 { 348 reg = <0>; 349 350 anx7625_in: endpoint { 351 remote-endpoint = <&dsi_out>; 352 }; 353 }; 354 355 port@1 { 356 reg = <1>; 357 358 anx7625_out: endpoint { 359 remote-endpoint = <&panel_in>; 360 }; 361 }; 362 }; 363 364 aux-bus { 365 panel: panel { 366 compatible = "edp-panel"; 367 power-supply = <&pp3300_mipibrdg>; 368 backlight = <&backlight_lcd0>; 369 370 port { 371 panel_in: endpoint { 372 remote-endpoint = <&anx7625_out>; 373 }; 374 }; 375 }; 376 }; 377 }; 378}; 379 380&i2c7 { 381 status = "okay"; 382 383 clock-frequency = <400000>; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&i2c7_pins>; 386}; 387 388&mfg0 { 389 domain-supply = <&mt6315_7_vbuck1>; 390}; 391 392&mfg1 { 393 domain-supply = <&mt6359_vsram_others_ldo_reg>; 394}; 395 396&mipi_tx0 { 397 status = "okay"; 398}; 399 400&mmc0 { 401 status = "okay"; 402 403 pinctrl-names = "default", "state_uhs"; 404 pinctrl-0 = <&mmc0_default_pins>; 405 pinctrl-1 = <&mmc0_uhs_pins>; 406 bus-width = <8>; 407 max-frequency = <200000000>; 408 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 409 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 410 cap-mmc-highspeed; 411 mmc-hs200-1_8v; 412 mmc-hs400-1_8v; 413 supports-cqe; 414 cap-mmc-hw-reset; 415 mmc-hs400-enhanced-strobe; 416 hs400-ds-delay = <0x12814>; 417 no-sdio; 418 no-sd; 419 non-removable; 420}; 421 422&mmc1 { 423 status = "okay"; 424 425 pinctrl-names = "default", "state_uhs"; 426 pinctrl-0 = <&mmc1_default_pins>; 427 pinctrl-1 = <&mmc1_uhs_pins>; 428 bus-width = <4>; 429 max-frequency = <200000000>; 430 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 431 vmmc-supply = <&mt6360_ldo5_reg>; 432 vqmmc-supply = <&mt6360_ldo3_reg>; 433 cap-sd-highspeed; 434 sd-uhs-sdr50; 435 sd-uhs-sdr104; 436 no-sdio; 437 no-mmc; 438}; 439 440/* for CORE */ 441&mt6359_vgpu11_buck_reg { 442 regulator-always-on; 443}; 444 445&mt6359_vgpu11_sshub_buck_reg { 446 regulator-always-on; 447 regulator-min-microvolt = <575000>; 448 regulator-max-microvolt = <575000>; 449}; 450 451&mt6359_vrf12_ldo_reg { 452 regulator-always-on; 453}; 454 455&mt6359_vsram_others_ldo_reg { 456 regulator-min-microvolt = <750000>; 457 regulator-max-microvolt = <800000>; 458 regulator-coupled-with = <&mt6315_7_vbuck1>; 459 regulator-coupled-max-spread = <10000>; 460}; 461 462&mt6359_vufs_ldo_reg { 463 regulator-always-on; 464}; 465 466&mt6359codec { 467 mediatek,dmic-mode = <1>; /* one-wire */ 468 mediatek,mic-type-0 = <2>; /* DMIC */ 469 mediatek,mic-type-2 = <2>; /* DMIC */ 470}; 471 472&nor_flash { 473 status = "okay"; 474 475 pinctrl-names = "default"; 476 pinctrl-0 = <&nor_flash_pins>; 477 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 478 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; 479 480 flash@0 { 481 compatible = "winbond,w25q64jwm", "jedec,spi-nor"; 482 reg = <0>; 483 spi-max-frequency = <52000000>; 484 spi-rx-bus-width = <2>; 485 spi-tx-bus-width = <2>; 486 }; 487}; 488 489&pcie { 490 pinctrl-names = "default"; 491 pinctrl-0 = <&pcie_pins>; 492 493 pcie0: pcie@0,0 { 494 device_type = "pci"; 495 reg = <0x0000 0 0 0 0>; 496 num-lanes = <1>; 497 bus-range = <0x1 0x1>; 498 499 #address-cells = <3>; 500 #size-cells = <2>; 501 ranges; 502 503 wifi: wifi@0,0 { 504 reg = <0x10000 0 0 0 0x100000>, 505 <0x10000 0 0x100000 0 0x100000>; 506 memory-region = <&wifi_restricted_dma_region>; 507 }; 508 }; 509}; 510 511&pio { 512 /* 220 lines */ 513 gpio-line-names = "I2S_DP_LRCK", 514 "IS_DP_BCLK", 515 "I2S_DP_MCLK", 516 "I2S_DP_DATAOUT", 517 "SAR0_INT_ODL", 518 "EC_AP_INT_ODL", 519 "EDPBRDG_INT_ODL", 520 "DPBRDG_INT_ODL", 521 "DPBRDG_PWREN", 522 "DPBRDG_RST_ODL", 523 "I2S_HP_MCLK", 524 "I2S_HP_BCK", 525 "I2S_HP_LRCK", 526 "I2S_HP_DATAIN", 527 /* 528 * AP_FLASH_WP_L is crossystem ABI. Schematics 529 * call it AP_FLASH_WP_ODL. 530 */ 531 "AP_FLASH_WP_L", 532 "TRACKPAD_INT_ODL", 533 "EC_AP_HPD_OD", 534 "SD_CD_ODL", 535 "HP_INT_ODL_ALC", 536 "EN_PP1000_DPBRDG", 537 "AP_GPIO20", 538 "TOUCH_INT_L_1V8", 539 "UART_BT_WAKE_ODL", 540 "AP_GPIO23", 541 "AP_SPI_FLASH_CS_L", 542 "AP_SPI_FLASH_CLK", 543 "EN_PP3300_DPBRDG_DX", 544 "AP_SPI_FLASH_MOSI", 545 "AP_SPI_FLASH_MISO", 546 "I2S_HP_DATAOUT", 547 "AP_GPIO30", 548 "I2S_SPKR_MCLK", 549 "I2S_SPKR_BCLK", 550 "I2S_SPKR_LRCK", 551 "I2S_SPKR_DATAIN", 552 "I2S_SPKR_DATAOUT", 553 "AP_SPI_H1_TPM_CLK", 554 "AP_SPI_H1_TPM_CS_L", 555 "AP_SPI_H1_TPM_MISO", 556 "AP_SPI_H1_TPM_MOSI", 557 "BL_PWM", 558 "EDPBRDG_PWREN", 559 "EDPBRDG_RST_ODL", 560 "EN_PP3300_HUB", 561 "HUB_RST_L", 562 "", 563 "", 564 "", 565 "", 566 "", 567 "", 568 "SD_CLK", 569 "SD_CMD", 570 "SD_DATA3", 571 "SD_DATA0", 572 "SD_DATA2", 573 "SD_DATA1", 574 "", 575 "", 576 "", 577 "", 578 "", 579 "", 580 "PCIE_WAKE_ODL", 581 "PCIE_RST_L", 582 "PCIE_CLKREQ_ODL", 583 "", 584 "", 585 "", 586 "", 587 "", 588 "", 589 "", 590 "", 591 "", 592 "", 593 "", 594 "", 595 "", 596 "", 597 "", 598 "", 599 "", 600 "", 601 "", 602 "", 603 "", 604 "", 605 "", 606 "SPMI_SCL", 607 "SPMI_SDA", 608 "AP_GOOD", 609 "UART_DBG_TX_AP_RX", 610 "UART_AP_TX_DBG_RX", 611 "UART_AP_TX_BT_RX", 612 "UART_BT_TX_AP_RX", 613 "MIPI_DPI_D0_R", 614 "MIPI_DPI_D1_R", 615 "MIPI_DPI_D2_R", 616 "MIPI_DPI_D3_R", 617 "MIPI_DPI_D4_R", 618 "MIPI_DPI_D5_R", 619 "MIPI_DPI_D6_R", 620 "MIPI_DPI_D7_R", 621 "MIPI_DPI_D8_R", 622 "MIPI_DPI_D9_R", 623 "MIPI_DPI_D10_R", 624 "", 625 "", 626 "MIPI_DPI_DE_R", 627 "MIPI_DPI_D11_R", 628 "MIPI_DPI_VSYNC_R", 629 "MIPI_DPI_CLK_R", 630 "MIPI_DPI_HSYNC_R", 631 "PCM_BT_DATAIN", 632 "PCM_BT_SYNC", 633 "PCM_BT_DATAOUT", 634 "PCM_BT_CLK", 635 "AP_I2C_AUDIO_SCL", 636 "AP_I2C_AUDIO_SDA", 637 "SCP_I2C_SCL", 638 "SCP_I2C_SDA", 639 "AP_I2C_WLAN_SCL", 640 "AP_I2C_WLAN_SDA", 641 "AP_I2C_DPBRDG_SCL", 642 "AP_I2C_DPBRDG_SDA", 643 "EN_PP1800_DPBRDG_DX", 644 "EN_PP3300_EDP_DX", 645 "EN_PP1800_EDPBRDG_DX", 646 "EN_PP1000_EDPBRDG", 647 "SCP_JTAG0_TDO", 648 "SCP_JTAG0_TDI", 649 "SCP_JTAG0_TMS", 650 "SCP_JTAG0_TCK", 651 "SCP_JTAG0_TRSTN", 652 "EN_PP3000_VMC_PMU", 653 "EN_PP3300_DISPLAY_DX", 654 "TOUCH_RST_L_1V8", 655 "TOUCH_REPORT_DISABLE", 656 "", 657 "", 658 "AP_I2C_TRACKPAD_SCL_1V8", 659 "AP_I2C_TRACKPAD_SDA_1V8", 660 "EN_PP3300_WLAN", 661 "BT_KILL_L", 662 "WIFI_KILL_L", 663 "SET_VMC_VOLT_AT_1V8", 664 "EN_SPK", 665 "AP_WARM_RST_REQ", 666 "", 667 "", 668 "EN_PP3000_SD_S3", 669 "AP_EDP_BKLTEN", 670 "", 671 "", 672 "", 673 "AP_SPI_EC_CLK", 674 "AP_SPI_EC_CS_L", 675 "AP_SPI_EC_MISO", 676 "AP_SPI_EC_MOSI", 677 "AP_I2C_EDPBRDG_SCL", 678 "AP_I2C_EDPBRDG_SDA", 679 "MT6315_PROC_INT", 680 "MT6315_GPU_INT", 681 "UART_SERVO_TX_SCP_RX", 682 "UART_SCP_TX_SERVO_RX", 683 "BT_RTS_AP_CTS", 684 "AP_RTS_BT_CTS", 685 "UART_AP_WAKE_BT_ODL", 686 "WLAN_ALERT_ODL", 687 "EC_IN_RW_ODL", 688 "H1_AP_INT_ODL", 689 "", 690 "", 691 "", 692 "", 693 "", 694 "", 695 "", 696 "", 697 "", 698 "", 699 "", 700 "MSDC0_CMD", 701 "MSDC0_DAT0", 702 "MSDC0_DAT2", 703 "MSDC0_DAT4", 704 "MSDC0_DAT6", 705 "MSDC0_DAT1", 706 "MSDC0_DAT5", 707 "MSDC0_DAT7", 708 "MSDC0_DSL", 709 "MSDC0_CLK", 710 "MSDC0_DAT3", 711 "MSDC0_RST_L", 712 "SCP_VREQ_VAO", 713 "AUD_DAT_MOSI2", 714 "AUD_NLE_MOSI1", 715 "AUD_NLE_MOSI0", 716 "AUD_DAT_MISO2", 717 "AP_I2C_SAR_SDA", 718 "AP_I2C_SAR_SCL", 719 "AP_I2C_PWR_SCL", 720 "AP_I2C_PWR_SDA", 721 "AP_I2C_TS_SCL_1V8", 722 "AP_I2C_TS_SDA_1V8", 723 "SRCLKENA0", 724 "SRCLKENA1", 725 "AP_EC_WATCHDOG_L", 726 "PWRAP_SPI0_MI", 727 "PWRAP_SPI0_CSN", 728 "PWRAP_SPI0_MO", 729 "PWRAP_SPI0_CK", 730 "AP_RTC_CLK32K", 731 "AUD_CLK_MOSI", 732 "AUD_SYNC_MOSI", 733 "AUD_DAT_MOSI0", 734 "AUD_DAT_MOSI1", 735 "AUD_DAT_MISO0", 736 "AUD_DAT_MISO1"; 737 738 anx7625_pins: anx7625-default-pins { 739 pins-out { 740 pinmux = <PINMUX_GPIO41__FUNC_GPIO41>, 741 <PINMUX_GPIO42__FUNC_GPIO42>; 742 output-low; 743 }; 744 745 pins-in { 746 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 747 input-enable; 748 bias-pull-up; 749 }; 750 }; 751 752 aud_clk_mosi_off_pins: aud-clk-mosi-off-pins { 753 pins-mosi-off { 754 pinmux = <PINMUX_GPIO214__FUNC_GPIO214>, 755 <PINMUX_GPIO215__FUNC_GPIO215>; 756 }; 757 }; 758 759 aud_clk_mosi_on_pins: aud-clk-mosi-on-pins { 760 pins-mosi-on { 761 pinmux = <PINMUX_GPIO214__FUNC_AUD_CLK_MOSI>, 762 <PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI>; 763 drive-strength = <10>; 764 }; 765 }; 766 767 aud_dat_miso_ch34_off_pins: aud-dat-miso-ch34-off-pins { 768 pins-miso-off { 769 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 770 }; 771 }; 772 773 aud_dat_miso_ch34_on_pins: aud-dat-miso-ch34-on-pins { 774 pins-miso-on { 775 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 776 }; 777 }; 778 779 aud_dat_miso_off_pins: aud-dat-miso-off-pins { 780 pins-miso-off { 781 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>, 782 <PINMUX_GPIO219__FUNC_GPIO219>; 783 }; 784 }; 785 786 aud_dat_miso_on_pins: aud-dat-miso-on-pins { 787 pins-miso-on { 788 pinmux = <PINMUX_GPIO218__FUNC_AUD_DAT_MISO0>, 789 <PINMUX_GPIO219__FUNC_AUD_DAT_MISO1>; 790 drive-strength = <10>; 791 }; 792 }; 793 794 aud_dat_miso2_off_pins: aud-dat-miso2-off-pins { 795 pins-miso-off { 796 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 797 }; 798 }; 799 800 aud_dat_miso2_on_pins: aud-dat-miso2-on-pins { 801 pins-miso-on { 802 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 803 }; 804 }; 805 806 aud_dat_mosi_ch34_off_pins: aud-dat-mosi-ch34-off-pins { 807 pins-mosi-off { 808 pinmux = <PINMUX_GPIO196__FUNC_GPIO196>; 809 }; 810 }; 811 812 aud_dat_mosi_ch34_on_pins: aud-dat-mosi-ch34-on-pins { 813 pins-mosi-on { 814 pinmux = <PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2>; 815 }; 816 }; 817 818 aud_dat_mosi_off_pins: aud-dat-mosi-off-pins { 819 pins-mosi-off { 820 pinmux = <PINMUX_GPIO216__FUNC_GPIO216>, 821 <PINMUX_GPIO217__FUNC_GPIO217>; 822 }; 823 }; 824 825 aud_dat_mosi_on_pins: aud-dat-mosi-on-pins { 826 pins-mosi-on { 827 pinmux = <PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0>, 828 <PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1>; 829 drive-strength = <10>; 830 }; 831 }; 832 833 aud_gpio_i2s3_off_pins: aud-gpio-i2s3-off-pins { 834 pins-i2s3-off { 835 pinmux = <PINMUX_GPIO32__FUNC_GPIO32>, 836 <PINMUX_GPIO33__FUNC_GPIO33>, 837 <PINMUX_GPIO35__FUNC_GPIO35>; 838 }; 839 }; 840 841 aud_gpio_i2s3_on_pins: aud-gpio-i2s3-on-pins { 842 pins-i2s3-on { 843 pinmux = <PINMUX_GPIO32__FUNC_I2S3_BCK>, 844 <PINMUX_GPIO33__FUNC_I2S3_LRCK>, 845 <PINMUX_GPIO35__FUNC_I2S3_DO>; 846 }; 847 }; 848 849 aud_gpio_i2s8_off_pins: aud-gpio-i2s8-off-pins { 850 pins-i2s8-off { 851 pinmux = <PINMUX_GPIO10__FUNC_GPIO10>, 852 <PINMUX_GPIO11__FUNC_GPIO11>, 853 <PINMUX_GPIO12__FUNC_GPIO12>, 854 <PINMUX_GPIO13__FUNC_GPIO13>; 855 }; 856 }; 857 858 aud_gpio_i2s8_on_pins: aud-gpio-i2s8-on-pins { 859 pins-i2s8-on { 860 pinmux = <PINMUX_GPIO10__FUNC_I2S8_MCK>, 861 <PINMUX_GPIO11__FUNC_I2S8_BCK>, 862 <PINMUX_GPIO12__FUNC_I2S8_LRCK>, 863 <PINMUX_GPIO13__FUNC_I2S8_DI>; 864 }; 865 }; 866 867 aud_gpio_i2s9_off_pins: aud-gpio-i2s9-off-pins { 868 pins-i2s9-off { 869 pinmux = <PINMUX_GPIO29__FUNC_GPIO29>; 870 }; 871 }; 872 873 aud_gpio_i2s9_on_pins: aud-gpio-i2s9-on-pins { 874 pins-i2s9-on { 875 pinmux = <PINMUX_GPIO29__FUNC_I2S9_DO>; 876 }; 877 }; 878 879 aud_gpio_tdm_off_pins: aud-gpio-tdm-off-pins { 880 pins-tdm-off { 881 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>, 882 <PINMUX_GPIO1__FUNC_GPIO1>, 883 <PINMUX_GPIO2__FUNC_GPIO2>, 884 <PINMUX_GPIO3__FUNC_GPIO3>; 885 }; 886 }; 887 888 aud_gpio_tdm_on_pins: aud-gpio-tdm-on-pins { 889 pins-tdm-on { 890 pinmux = <PINMUX_GPIO0__FUNC_TDM_LRCK>, 891 <PINMUX_GPIO1__FUNC_TDM_BCK>, 892 <PINMUX_GPIO2__FUNC_TDM_MCK>, 893 <PINMUX_GPIO3__FUNC_TDM_DATA0>; 894 }; 895 }; 896 897 aud_nle_mosi_off_pins: aud-nle-mosi-off-pins { 898 pins-nle-mosi-off { 899 pinmux = <PINMUX_GPIO197__FUNC_GPIO197>, 900 <PINMUX_GPIO198__FUNC_GPIO198>; 901 }; 902 }; 903 904 aud_nle_mosi_on_pins: aud-nle-mosi-on-pins { 905 pins-nle-mosi-on { 906 pinmux = <PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1>, 907 <PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0>; 908 }; 909 }; 910 911 cr50_int: cr50-irq-default-pins { 912 pins-gsc-ap-int-odl { 913 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 914 input-enable; 915 }; 916 }; 917 918 cros_ec_int: cros-ec-irq-default-pins { 919 pins-ec-ap-int-odl { 920 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 921 input-enable; 922 bias-pull-up; 923 }; 924 }; 925 926 i2c0_pins: i2c0-default-pins { 927 pins-bus { 928 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 929 <PINMUX_GPIO205__FUNC_SDA0>; 930 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 931 drive-strength-microamp = <1000>; 932 }; 933 }; 934 935 i2c1_pins: i2c1-default-pins { 936 pins-bus { 937 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 938 <PINMUX_GPIO119__FUNC_SDA1>; 939 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 940 drive-strength-microamp = <1000>; 941 }; 942 }; 943 944 i2c2_pins: i2c2-default-pins { 945 pins-bus { 946 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 947 <PINMUX_GPIO142__FUNC_SDA2>; 948 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 949 }; 950 }; 951 952 i2c3_pins: i2c3-default-pins { 953 pins-bus { 954 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 955 <PINMUX_GPIO161__FUNC_SDA3>; 956 bias-disable; 957 drive-strength-microamp = <1000>; 958 }; 959 }; 960 961 i2c7_pins: i2c7-default-pins { 962 pins-bus { 963 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 964 <PINMUX_GPIO125__FUNC_SDA7>; 965 bias-disable; 966 drive-strength-microamp = <1000>; 967 }; 968 }; 969 970 mmc0_default_pins: mmc0-default-pins { 971 pins-cmd-dat { 972 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 973 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 974 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 975 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 976 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 977 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 978 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 979 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 980 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 981 input-enable; 982 drive-strength = <8>; 983 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 984 }; 985 986 pins-clk { 987 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 988 drive-strength = <8>; 989 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 990 }; 991 992 pins-rst { 993 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 994 drive-strength = <8>; 995 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 996 }; 997 }; 998 999 mmc0_uhs_pins: mmc0-uhs-pins { 1000 pins-cmd-dat { 1001 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 1002 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 1003 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 1004 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 1005 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 1006 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 1007 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 1008 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 1009 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 1010 input-enable; 1011 drive-strength = <10>; 1012 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1013 }; 1014 1015 pins-clk { 1016 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 1017 drive-strength = <10>; 1018 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1019 }; 1020 1021 pins-rst { 1022 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 1023 drive-strength = <8>; 1024 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1025 }; 1026 1027 pins-ds { 1028 pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 1029 drive-strength = <10>; 1030 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1031 }; 1032 }; 1033 1034 mmc1_default_pins: mmc1-default-pins { 1035 pins-cmd-dat { 1036 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1037 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1038 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1039 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1040 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1041 input-enable; 1042 drive-strength = <8>; 1043 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1044 }; 1045 1046 pins-clk { 1047 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1048 drive-strength = <8>; 1049 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1050 }; 1051 1052 pins-insert { 1053 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 1054 input-enable; 1055 bias-pull-up; 1056 }; 1057 }; 1058 1059 mmc1_uhs_pins: mmc1-uhs-pins { 1060 pins-cmd-dat { 1061 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1062 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1063 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1064 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1065 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1066 input-enable; 1067 drive-strength = <8>; 1068 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1069 }; 1070 1071 pins-clk { 1072 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1073 input-enable; 1074 drive-strength = <8>; 1075 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1076 }; 1077 }; 1078 1079 nor_flash_pins: nor-flash-default-pins { 1080 pins-cs-io1 { 1081 pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, 1082 <PINMUX_GPIO28__FUNC_SPINOR_IO1>; 1083 input-enable; 1084 bias-pull-up; 1085 drive-strength = <10>; 1086 }; 1087 1088 pins-io0 { 1089 pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; 1090 bias-pull-up; 1091 drive-strength = <10>; 1092 }; 1093 1094 pins-clk { 1095 pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; 1096 input-enable; 1097 bias-pull-up; 1098 drive-strength = <10>; 1099 }; 1100 }; 1101 1102 pcie_pins: pcie-default-pins { 1103 pins-pcie-wake { 1104 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 1105 bias-pull-up; 1106 }; 1107 1108 pins-pcie-pereset { 1109 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 1110 }; 1111 1112 pins-pcie-clkreq { 1113 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 1114 bias-pull-up; 1115 }; 1116 1117 pins-wifi-kill { 1118 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 1119 output-high; 1120 }; 1121 }; 1122 1123 pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { 1124 pins-en { 1125 pinmux = <PINMUX_GPIO19__FUNC_GPIO19>; 1126 output-low; 1127 }; 1128 }; 1129 1130 pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { 1131 pins-en { 1132 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 1133 output-low; 1134 }; 1135 }; 1136 1137 pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { 1138 pins-en { 1139 pinmux = <PINMUX_GPIO126__FUNC_GPIO126>; 1140 output-low; 1141 }; 1142 }; 1143 1144 pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { 1145 pins-en { 1146 pinmux = <PINMUX_GPIO128__FUNC_GPIO128>; 1147 output-low; 1148 }; 1149 }; 1150 1151 pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { 1152 pins-en { 1153 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>; 1154 output-low; 1155 }; 1156 }; 1157 1158 pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { 1159 pins-en { 1160 pinmux = <PINMUX_GPIO127__FUNC_GPIO127>; 1161 output-low; 1162 }; 1163 }; 1164 1165 pp3300_wlan_pins: pp3300-wlan-pins { 1166 pins-pcie-en-pp3300-wlan { 1167 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 1168 output-high; 1169 }; 1170 }; 1171 1172 pwm0_pins: pwm0-default-pins { 1173 pins-pwm { 1174 pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>; 1175 }; 1176 1177 pins-inhibit { 1178 pinmux = <PINMUX_GPIO152__FUNC_GPIO152>; 1179 output-high; 1180 }; 1181 }; 1182 1183 scp_pins: scp-pins { 1184 pins-vreq-vao { 1185 pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; 1186 }; 1187 }; 1188 1189 spi1_pins: spi1-default-pins { 1190 pins-cs-mosi-clk { 1191 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 1192 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 1193 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 1194 bias-disable; 1195 }; 1196 1197 pins-miso { 1198 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 1199 bias-pull-down; 1200 }; 1201 }; 1202 1203 spi5_pins: spi5-default-pins { 1204 pins-bus { 1205 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 1206 <PINMUX_GPIO37__FUNC_GPIO37>, 1207 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 1208 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 1209 bias-disable; 1210 }; 1211 }; 1212 1213 trackpad_pins: trackpad-default-pins { 1214 pins-int-n { 1215 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 1216 input-enable; 1217 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 1218 }; 1219 }; 1220 1221 touchscreen_pins: touchscreen-default-pins { 1222 pins-irq { 1223 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 1224 input-enable; 1225 bias-pull-up; 1226 }; 1227 1228 pins-reset { 1229 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 1230 output-high; 1231 }; 1232 1233 pins-report-sw { 1234 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 1235 output-low; 1236 }; 1237 }; 1238 1239 vow_clk_miso_off_pins: vow-clk-miso-off-pins { 1240 pins-miso-off { 1241 pinmux = <PINMUX_GPIO219__FUNC_GPIO219>; 1242 }; 1243 }; 1244 1245 vow_clk_miso_on_pins: vow-clk-miso-on-pins { 1246 pins-miso-on { 1247 pinmux = <PINMUX_GPIO219__FUNC_VOW_CLK_MISO>; 1248 }; 1249 }; 1250 1251 vow_dat_miso_off_pins: vow-dat-miso-off-pins { 1252 pins-miso-off { 1253 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>; 1254 }; 1255 }; 1256 1257 vow_dat_miso_on_pins: vow-dat-miso-on-pins { 1258 pins-miso-on { 1259 pinmux = <PINMUX_GPIO218__FUNC_VOW_DAT_MISO>; 1260 }; 1261 }; 1262}; 1263 1264&pmic { 1265 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 1266}; 1267 1268&pwm0 { 1269 status = "okay"; 1270 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&pwm0_pins>; 1273}; 1274 1275&scp { 1276 status = "okay"; 1277 1278 firmware-name = "mediatek/mt8192/scp.img"; 1279 memory-region = <&scp_mem_reserved>; 1280 pinctrl-names = "default"; 1281 pinctrl-0 = <&scp_pins>; 1282 1283 cros-ec { 1284 compatible = "google,cros-ec-rpmsg"; 1285 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1286 }; 1287}; 1288 1289&spi1 { 1290 status = "okay"; 1291 1292 mediatek,pad-select = <0>; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&spi1_pins>; 1295 1296 cros_ec: ec@0 { 1297 compatible = "google,cros-ec-spi"; 1298 reg = <0>; 1299 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 1300 spi-max-frequency = <3000000>; 1301 pinctrl-names = "default"; 1302 pinctrl-0 = <&cros_ec_int>; 1303 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 1307 base_detection: cbas { 1308 compatible = "google,cros-cbas"; 1309 }; 1310 1311 cros_ec_pwm: pwm { 1312 compatible = "google,cros-ec-pwm"; 1313 #pwm-cells = <1>; 1314 1315 status = "disabled"; 1316 }; 1317 1318 i2c_tunnel: i2c-tunnel { 1319 compatible = "google,cros-ec-i2c-tunnel"; 1320 google,remote-bus = <0>; 1321 #address-cells = <1>; 1322 #size-cells = <0>; 1323 }; 1324 1325 mt6360_ldo3_reg: regulator@0 { 1326 compatible = "google,cros-ec-regulator"; 1327 reg = <0>; 1328 regulator-min-microvolt = <1800000>; 1329 regulator-max-microvolt = <3300000>; 1330 }; 1331 1332 mt6360_ldo5_reg: regulator@1 { 1333 compatible = "google,cros-ec-regulator"; 1334 reg = <1>; 1335 regulator-min-microvolt = <3300000>; 1336 regulator-max-microvolt = <3300000>; 1337 }; 1338 1339 typec { 1340 compatible = "google,cros-ec-typec"; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 1344 usb_c0: connector@0 { 1345 compatible = "usb-c-connector"; 1346 reg = <0>; 1347 label = "left"; 1348 power-role = "dual"; 1349 data-role = "host"; 1350 try-power-role = "source"; 1351 }; 1352 1353 usb_c1: connector@1 { 1354 compatible = "usb-c-connector"; 1355 reg = <1>; 1356 label = "right"; 1357 power-role = "dual"; 1358 data-role = "host"; 1359 try-power-role = "source"; 1360 }; 1361 }; 1362 }; 1363}; 1364 1365&spi5 { 1366 status = "okay"; 1367 1368 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 1369 mediatek,pad-select = <0>; 1370 pinctrl-names = "default"; 1371 pinctrl-0 = <&spi5_pins>; 1372 1373 cr50@0 { 1374 compatible = "google,cr50"; 1375 reg = <0>; 1376 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 1377 spi-max-frequency = <1000000>; 1378 pinctrl-names = "default"; 1379 pinctrl-0 = <&cr50_int>; 1380 }; 1381}; 1382 1383&spmi { 1384 #address-cells = <2>; 1385 #size-cells = <0>; 1386 1387 mt6315_6: pmic@6 { 1388 compatible = "mediatek,mt6315-regulator"; 1389 reg = <0x6 SPMI_USID>; 1390 1391 regulators { 1392 mt6315_6_vbuck1: vbuck1 { 1393 regulator-compatible = "vbuck1"; 1394 regulator-name = "Vbcpu"; 1395 regulator-min-microvolt = <300000>; 1396 regulator-max-microvolt = <1193750>; 1397 regulator-enable-ramp-delay = <256>; 1398 regulator-allowed-modes = <0 1 2>; 1399 regulator-always-on; 1400 }; 1401 1402 mt6315_6_vbuck3: vbuck3 { 1403 regulator-compatible = "vbuck3"; 1404 regulator-name = "Vlcpu"; 1405 regulator-min-microvolt = <300000>; 1406 regulator-max-microvolt = <1193750>; 1407 regulator-enable-ramp-delay = <256>; 1408 regulator-allowed-modes = <0 1 2>; 1409 regulator-always-on; 1410 }; 1411 }; 1412 }; 1413 1414 mt6315_7: pmic@7 { 1415 compatible = "mediatek,mt6315-regulator"; 1416 reg = <0x7 SPMI_USID>; 1417 1418 regulators { 1419 mt6315_7_vbuck1: vbuck1 { 1420 regulator-compatible = "vbuck1"; 1421 regulator-name = "Vgpu"; 1422 regulator-min-microvolt = <606250>; 1423 regulator-max-microvolt = <800000>; 1424 regulator-enable-ramp-delay = <256>; 1425 regulator-allowed-modes = <0 1 2>; 1426 regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; 1427 regulator-coupled-max-spread = <10000>; 1428 }; 1429 }; 1430 }; 1431}; 1432 1433&uart0 { 1434 status = "okay"; 1435}; 1436 1437&xhci { 1438 status = "okay"; 1439 1440 wakeup-source; 1441 vusb33-supply = <&pp3300_g>; 1442 vbus-supply = <&pp5000_a>; 1443}; 1444 1445#include <arm/cros-ec-keyboard.dtsi> 1446#include <arm/cros-ec-sbs.dtsi> 1447