1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2023 MediaTek Inc. 4 * 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mediatek,mt8188-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/mailbox/mediatek,mt8188-gce.h> 12#include <dt-bindings/memory/mediatek,mt8188-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> 15#include <dt-bindings/power/mediatek,mt8188-power.h> 16#include <dt-bindings/reset/mt8188-resets.h> 17#include <dt-bindings/thermal/thermal.h> 18#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 19 20/ { 21 compatible = "mediatek,mt8188"; 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 dp-intf0 = &dp_intf0; 28 dp-intf1 = &dp_intf1; 29 dpi1 = &dpi1; 30 dsc0 = &dsc0; 31 ethdr0 = ðdr0; 32 gce0 = &gce0; 33 gce1 = &gce1; 34 merge0 = &merge0; 35 merge1 = &merge1; 36 merge2 = &merge2; 37 merge3 = &merge3; 38 merge4 = &merge4; 39 merge5 = &merge5; 40 mutex0 = &mutex0; 41 mutex1 = &mutex1; 42 padding0 = &padding0; 43 padding1 = &padding1; 44 padding2 = &padding2; 45 padding3 = &padding3; 46 padding4 = &padding4; 47 padding5 = &padding5; 48 padding6 = &padding6; 49 padding7 = &padding7; 50 vdo1-rdma0 = &vdo1_rdma0; 51 vdo1-rdma1 = &vdo1_rdma1; 52 vdo1-rdma2 = &vdo1_rdma2; 53 vdo1-rdma3 = &vdo1_rdma3; 54 vdo1-rdma4 = &vdo1_rdma4; 55 vdo1-rdma5 = &vdo1_rdma5; 56 vdo1-rdma6 = &vdo1_rdma6; 57 vdo1-rdma7 = &vdo1_rdma7; 58 }; 59 60 cpus { 61 #address-cells = <1>; 62 #size-cells = <0>; 63 64 cpu0: cpu@0 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a55"; 67 reg = <0x000>; 68 enable-method = "psci"; 69 clock-frequency = <2000000000>; 70 capacity-dmips-mhz = <282>; 71 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 72 i-cache-size = <32768>; 73 i-cache-line-size = <64>; 74 i-cache-sets = <128>; 75 d-cache-size = <32768>; 76 d-cache-line-size = <64>; 77 d-cache-sets = <128>; 78 next-level-cache = <&l2_0>; 79 performance-domains = <&performance 0>; 80 #cooling-cells = <2>; 81 }; 82 83 cpu1: cpu@100 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a55"; 86 reg = <0x100>; 87 enable-method = "psci"; 88 clock-frequency = <2000000000>; 89 capacity-dmips-mhz = <282>; 90 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 91 i-cache-size = <32768>; 92 i-cache-line-size = <64>; 93 i-cache-sets = <128>; 94 d-cache-size = <32768>; 95 d-cache-line-size = <64>; 96 d-cache-sets = <128>; 97 next-level-cache = <&l2_0>; 98 performance-domains = <&performance 0>; 99 #cooling-cells = <2>; 100 }; 101 102 cpu2: cpu@200 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a55"; 105 reg = <0x200>; 106 enable-method = "psci"; 107 clock-frequency = <2000000000>; 108 capacity-dmips-mhz = <282>; 109 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 110 i-cache-size = <32768>; 111 i-cache-line-size = <64>; 112 i-cache-sets = <128>; 113 d-cache-size = <32768>; 114 d-cache-line-size = <64>; 115 d-cache-sets = <128>; 116 next-level-cache = <&l2_0>; 117 performance-domains = <&performance 0>; 118 #cooling-cells = <2>; 119 }; 120 121 cpu3: cpu@300 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a55"; 124 reg = <0x300>; 125 enable-method = "psci"; 126 clock-frequency = <2000000000>; 127 capacity-dmips-mhz = <282>; 128 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 129 i-cache-size = <32768>; 130 i-cache-line-size = <64>; 131 i-cache-sets = <128>; 132 d-cache-size = <32768>; 133 d-cache-line-size = <64>; 134 d-cache-sets = <128>; 135 next-level-cache = <&l2_0>; 136 performance-domains = <&performance 0>; 137 #cooling-cells = <2>; 138 }; 139 140 cpu4: cpu@400 { 141 device_type = "cpu"; 142 compatible = "arm,cortex-a55"; 143 reg = <0x400>; 144 enable-method = "psci"; 145 clock-frequency = <2000000000>; 146 capacity-dmips-mhz = <282>; 147 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 148 i-cache-size = <32768>; 149 i-cache-line-size = <64>; 150 i-cache-sets = <128>; 151 d-cache-size = <32768>; 152 d-cache-line-size = <64>; 153 d-cache-sets = <128>; 154 next-level-cache = <&l2_0>; 155 performance-domains = <&performance 0>; 156 #cooling-cells = <2>; 157 }; 158 159 cpu5: cpu@500 { 160 device_type = "cpu"; 161 compatible = "arm,cortex-a55"; 162 reg = <0x500>; 163 enable-method = "psci"; 164 clock-frequency = <2000000000>; 165 capacity-dmips-mhz = <282>; 166 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 167 i-cache-size = <32768>; 168 i-cache-line-size = <64>; 169 i-cache-sets = <128>; 170 d-cache-size = <32768>; 171 d-cache-line-size = <64>; 172 d-cache-sets = <128>; 173 next-level-cache = <&l2_0>; 174 performance-domains = <&performance 0>; 175 #cooling-cells = <2>; 176 }; 177 178 cpu6: cpu@600 { 179 device_type = "cpu"; 180 compatible = "arm,cortex-a78"; 181 reg = <0x600>; 182 enable-method = "psci"; 183 clock-frequency = <2600000000>; 184 capacity-dmips-mhz = <1024>; 185 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 186 i-cache-size = <65536>; 187 i-cache-line-size = <64>; 188 i-cache-sets = <256>; 189 d-cache-size = <65536>; 190 d-cache-line-size = <64>; 191 d-cache-sets = <256>; 192 next-level-cache = <&l2_1>; 193 performance-domains = <&performance 1>; 194 #cooling-cells = <2>; 195 }; 196 197 cpu7: cpu@700 { 198 device_type = "cpu"; 199 compatible = "arm,cortex-a78"; 200 reg = <0x700>; 201 enable-method = "psci"; 202 clock-frequency = <2600000000>; 203 capacity-dmips-mhz = <1024>; 204 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 205 i-cache-size = <65536>; 206 i-cache-line-size = <64>; 207 i-cache-sets = <256>; 208 d-cache-size = <65536>; 209 d-cache-line-size = <64>; 210 d-cache-sets = <256>; 211 next-level-cache = <&l2_1>; 212 performance-domains = <&performance 1>; 213 #cooling-cells = <2>; 214 }; 215 216 cpu-map { 217 cluster0 { 218 core0 { 219 cpu = <&cpu0>; 220 }; 221 222 core1 { 223 cpu = <&cpu1>; 224 }; 225 226 core2 { 227 cpu = <&cpu2>; 228 }; 229 230 core3 { 231 cpu = <&cpu3>; 232 }; 233 234 core4 { 235 cpu = <&cpu4>; 236 }; 237 238 core5 { 239 cpu = <&cpu5>; 240 }; 241 242 core6 { 243 cpu = <&cpu6>; 244 }; 245 246 core7 { 247 cpu = <&cpu7>; 248 }; 249 }; 250 }; 251 252 idle-states { 253 entry-method = "psci"; 254 255 cpu_off_l: cpu-off-l { 256 compatible = "arm,idle-state"; 257 arm,psci-suspend-param = <0x00010000>; 258 local-timer-stop; 259 entry-latency-us = <50>; 260 exit-latency-us = <95>; 261 min-residency-us = <580>; 262 }; 263 264 cpu_off_b: cpu-off-b { 265 compatible = "arm,idle-state"; 266 arm,psci-suspend-param = <0x00010000>; 267 local-timer-stop; 268 entry-latency-us = <45>; 269 exit-latency-us = <140>; 270 min-residency-us = <740>; 271 }; 272 273 cluster_off_l: cluster-off-l { 274 compatible = "arm,idle-state"; 275 arm,psci-suspend-param = <0x01010010>; 276 local-timer-stop; 277 entry-latency-us = <55>; 278 exit-latency-us = <155>; 279 min-residency-us = <840>; 280 }; 281 282 cluster_off_b: cluster-off-b { 283 compatible = "arm,idle-state"; 284 arm,psci-suspend-param = <0x01010010>; 285 local-timer-stop; 286 entry-latency-us = <50>; 287 exit-latency-us = <200>; 288 min-residency-us = <1000>; 289 }; 290 }; 291 292 l2_0: l2-cache0 { 293 compatible = "cache"; 294 cache-level = <2>; 295 cache-size = <131072>; 296 cache-line-size = <64>; 297 cache-sets = <512>; 298 next-level-cache = <&l3_0>; 299 cache-unified; 300 }; 301 302 l2_1: l2-cache1 { 303 compatible = "cache"; 304 cache-level = <2>; 305 cache-size = <262144>; 306 cache-line-size = <64>; 307 cache-sets = <512>; 308 next-level-cache = <&l3_0>; 309 cache-unified; 310 }; 311 312 l3_0: l3-cache { 313 compatible = "cache"; 314 cache-level = <3>; 315 cache-size = <2097152>; 316 cache-line-size = <64>; 317 cache-sets = <2048>; 318 cache-unified; 319 }; 320 }; 321 322 clk13m: oscillator-13m { 323 compatible = "fixed-clock"; 324 #clock-cells = <0>; 325 clock-frequency = <13000000>; 326 clock-output-names = "clk13m"; 327 }; 328 329 clk26m: oscillator-26m { 330 compatible = "fixed-clock"; 331 #clock-cells = <0>; 332 clock-frequency = <26000000>; 333 clock-output-names = "clk26m"; 334 }; 335 336 clk32k: oscillator-32k { 337 compatible = "fixed-clock"; 338 #clock-cells = <0>; 339 clock-frequency = <32768>; 340 clock-output-names = "clk32k"; 341 }; 342 343 gpu_opp_table: opp-table-gpu { 344 compatible = "operating-points-v2"; 345 opp-shared; 346 347 opp-390000000 { 348 opp-hz = /bits/ 64 <390000000>; 349 opp-microvolt = <575000>; 350 opp-supported-hw = <0xff>; 351 }; 352 opp-431000000 { 353 opp-hz = /bits/ 64 <431000000>; 354 opp-microvolt = <587500>; 355 opp-supported-hw = <0xff>; 356 }; 357 opp-473000000 { 358 opp-hz = /bits/ 64 <473000000>; 359 opp-microvolt = <600000>; 360 opp-supported-hw = <0xff>; 361 }; 362 opp-515000000 { 363 opp-hz = /bits/ 64 <515000000>; 364 opp-microvolt = <612500>; 365 opp-supported-hw = <0xff>; 366 }; 367 opp-556000000 { 368 opp-hz = /bits/ 64 <556000000>; 369 opp-microvolt = <625000>; 370 opp-supported-hw = <0xff>; 371 }; 372 opp-598000000 { 373 opp-hz = /bits/ 64 <598000000>; 374 opp-microvolt = <637500>; 375 opp-supported-hw = <0xff>; 376 }; 377 opp-640000000 { 378 opp-hz = /bits/ 64 <640000000>; 379 opp-microvolt = <650000>; 380 opp-supported-hw = <0xff>; 381 }; 382 opp-670000000 { 383 opp-hz = /bits/ 64 <670000000>; 384 opp-microvolt = <662500>; 385 opp-supported-hw = <0xff>; 386 }; 387 opp-700000000 { 388 opp-hz = /bits/ 64 <700000000>; 389 opp-microvolt = <675000>; 390 opp-supported-hw = <0xff>; 391 }; 392 opp-730000000 { 393 opp-hz = /bits/ 64 <730000000>; 394 opp-microvolt = <687500>; 395 opp-supported-hw = <0xff>; 396 }; 397 opp-760000000 { 398 opp-hz = /bits/ 64 <760000000>; 399 opp-microvolt = <700000>; 400 opp-supported-hw = <0xff>; 401 }; 402 opp-790000000 { 403 opp-hz = /bits/ 64 <790000000>; 404 opp-microvolt = <712500>; 405 opp-supported-hw = <0xff>; 406 }; 407 opp-835000000 { 408 opp-hz = /bits/ 64 <835000000>; 409 opp-microvolt = <731250>; 410 opp-supported-hw = <0xff>; 411 }; 412 opp-880000000 { 413 opp-hz = /bits/ 64 <880000000>; 414 opp-microvolt = <750000>; 415 opp-supported-hw = <0xff>; 416 }; 417 opp-915000000 { 418 opp-hz = /bits/ 64 <915000000>; 419 opp-microvolt = <775000>; 420 opp-supported-hw = <0x8f>; 421 }; 422 opp-915000000-5 { 423 opp-hz = /bits/ 64 <915000000>; 424 opp-microvolt = <762500>; 425 opp-supported-hw = <0x30>; 426 }; 427 opp-915000000-6 { 428 opp-hz = /bits/ 64 <915000000>; 429 opp-microvolt = <750000>; 430 opp-supported-hw = <0x70>; 431 }; 432 opp-950000000 { 433 opp-hz = /bits/ 64 <950000000>; 434 opp-microvolt = <800000>; 435 opp-supported-hw = <0x8f>; 436 }; 437 opp-950000000-5 { 438 opp-hz = /bits/ 64 <950000000>; 439 opp-microvolt = <775000>; 440 opp-supported-hw = <0x30>; 441 }; 442 opp-950000000-6 { 443 opp-hz = /bits/ 64 <950000000>; 444 opp-microvolt = <750000>; 445 opp-supported-hw = <0x70>; 446 }; 447 }; 448 449 pmu-a55 { 450 compatible = "arm,cortex-a55-pmu"; 451 interrupt-parent = <&gic>; 452 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 453 }; 454 455 pmu-a78 { 456 compatible = "arm,cortex-a78-pmu"; 457 interrupt-parent = <&gic>; 458 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 459 }; 460 461 psci { 462 compatible = "arm,psci-1.0"; 463 method = "smc"; 464 }; 465 466 sound: sound { 467 mediatek,platform = <&afe>; 468 status = "disabled"; 469 }; 470 471 thermal_zones: thermal-zones { 472 cpu-little0-thermal { 473 polling-delay = <1000>; 474 polling-delay-passive = <150>; 475 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU0>; 476 477 trips { 478 cpu_little0_alert0: trip-alert0 { 479 temperature = <85000>; 480 hysteresis = <2000>; 481 type = "passive"; 482 }; 483 484 cpu_little0_alert1: trip-alert1 { 485 temperature = <95000>; 486 hysteresis = <2000>; 487 type = "hot"; 488 }; 489 490 cpu_little0_crit: trip-crit { 491 temperature = <100000>; 492 hysteresis = <0>; 493 type = "critical"; 494 }; 495 }; 496 497 cooling-maps { 498 cpu_little0_cooling_map0: map0 { 499 trip = <&cpu_little0_alert0>; 500 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 501 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 502 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 503 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 504 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 505 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 506 }; 507 }; 508 }; 509 510 cpu-little1-thermal { 511 polling-delay = <1000>; 512 polling-delay-passive = <150>; 513 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU1>; 514 515 trips { 516 cpu_little1_alert0: trip-alert0 { 517 temperature = <85000>; 518 hysteresis = <2000>; 519 type = "passive"; 520 }; 521 522 cpu_little1_alert1: trip-alert1 { 523 temperature = <95000>; 524 hysteresis = <2000>; 525 type = "hot"; 526 }; 527 528 cpu_little1_crit: trip-crit { 529 temperature = <100000>; 530 hysteresis = <0>; 531 type = "critical"; 532 }; 533 }; 534 535 cooling-maps { 536 cpu_little1_cooling_map0: map0 { 537 trip = <&cpu_little1_alert0>; 538 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 539 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 540 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 541 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 542 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 543 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 544 }; 545 }; 546 }; 547 548 cpu-little2-thermal { 549 polling-delay = <1000>; 550 polling-delay-passive = <150>; 551 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU2>; 552 553 trips { 554 cpu_little2_alert0: trip-alert0 { 555 temperature = <85000>; 556 hysteresis = <2000>; 557 type = "passive"; 558 }; 559 560 cpu_little2_alert1: trip-alert1 { 561 temperature = <95000>; 562 hysteresis = <2000>; 563 type = "hot"; 564 }; 565 566 cpu_little2_crit: trip-crit { 567 temperature = <100000>; 568 hysteresis = <0>; 569 type = "critical"; 570 }; 571 }; 572 573 cooling-maps { 574 cpu_little2_cooling_map0: map0 { 575 trip = <&cpu_little2_alert0>; 576 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 577 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 578 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 579 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 580 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 581 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 582 }; 583 }; 584 }; 585 586 cpu-little3-thermal { 587 polling-delay = <1000>; 588 polling-delay-passive = <150>; 589 thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU3>; 590 591 trips { 592 cpu_little3_alert0: trip-alert0 { 593 temperature = <85000>; 594 hysteresis = <2000>; 595 type = "passive"; 596 }; 597 598 cpu_little3_alert1: trip-alert1 { 599 temperature = <95000>; 600 hysteresis = <2000>; 601 type = "hot"; 602 }; 603 604 cpu_little3_crit: trip-crit { 605 temperature = <100000>; 606 hysteresis = <0>; 607 type = "critical"; 608 }; 609 }; 610 611 cooling-maps { 612 cpu_little3_cooling_map0: map0 { 613 trip = <&cpu_little3_alert0>; 614 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 615 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 616 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 617 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 618 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 619 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 620 }; 621 }; 622 }; 623 624 cpu-big0-thermal { 625 polling-delay = <1000>; 626 polling-delay-passive = <100>; 627 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU0>; 628 629 trips { 630 cpu_big0_alert0: trip-alert0 { 631 temperature = <85000>; 632 hysteresis = <2000>; 633 type = "passive"; 634 }; 635 636 cpu_big0_alert1: trip-alert1 { 637 temperature = <95000>; 638 hysteresis = <2000>; 639 type = "hot"; 640 }; 641 642 cpu_big0_crit: trip-crit { 643 temperature = <100000>; 644 hysteresis = <0>; 645 type = "critical"; 646 }; 647 }; 648 649 cooling-maps { 650 map0 { 651 trip = <&cpu_big0_alert0>; 652 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 653 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 654 }; 655 }; 656 }; 657 658 cpu-big1-thermal { 659 polling-delay = <1000>; 660 polling-delay-passive = <100>; 661 thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU1>; 662 663 trips { 664 cpu_big1_alert0: trip-alert0 { 665 temperature = <85000>; 666 hysteresis = <2000>; 667 type = "passive"; 668 }; 669 670 cpu_big1_alert1: trip-alert1 { 671 temperature = <95000>; 672 hysteresis = <2000>; 673 type = "hot"; 674 }; 675 676 cpu_big1_crit: trip-crit { 677 temperature = <100000>; 678 hysteresis = <0>; 679 type = "critical"; 680 }; 681 }; 682 683 cooling-maps { 684 map0 { 685 trip = <&cpu_big1_alert0>; 686 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 687 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 688 }; 689 }; 690 }; 691 692 apu-thermal { 693 polling-delay = <1000>; 694 polling-delay-passive = <250>; 695 thermal-sensors = <&lvts_ap MT8188_AP_APU>; 696 697 trips { 698 apu_alert0: trip-alert0 { 699 temperature = <85000>; 700 hysteresis = <2000>; 701 type = "passive"; 702 }; 703 704 apu_alert1: trip-alert1 { 705 temperature = <95000>; 706 hysteresis = <2000>; 707 type = "hot"; 708 }; 709 710 apu_crit: trip-crit { 711 temperature = <100000>; 712 hysteresis = <0>; 713 type = "critical"; 714 }; 715 }; 716 }; 717 718 gpu-thermal { 719 polling-delay = <1000>; 720 polling-delay-passive = <250>; 721 thermal-sensors = <&lvts_ap MT8188_AP_GPU0>; 722 723 trips { 724 gpu_alert0: trip-alert0 { 725 temperature = <85000>; 726 hysteresis = <2000>; 727 type = "passive"; 728 }; 729 730 gpu_alert1: trip-alert1 { 731 temperature = <95000>; 732 hysteresis = <2000>; 733 type = "hot"; 734 }; 735 736 gpu_crit: trip-crit { 737 temperature = <100000>; 738 hysteresis = <0>; 739 type = "critical"; 740 }; 741 }; 742 743 cooling-maps { 744 map0 { 745 trip = <&gpu_alert0>; 746 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 747 }; 748 }; 749 }; 750 751 gpu1-thermal { 752 polling-delay = <1000>; 753 polling-delay-passive = <250>; 754 thermal-sensors = <&lvts_ap MT8188_AP_GPU1>; 755 756 trips { 757 gpu1_alert0: trip-alert0 { 758 temperature = <85000>; 759 hysteresis = <2000>; 760 type = "passive"; 761 }; 762 763 gpu1_alert1: trip-alert1 { 764 temperature = <95000>; 765 hysteresis = <2000>; 766 type = "hot"; 767 }; 768 769 gpu1_crit: trip-crit { 770 temperature = <100000>; 771 hysteresis = <0>; 772 type = "critical"; 773 }; 774 }; 775 776 cooling-maps { 777 map0 { 778 trip = <&gpu1_alert0>; 779 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 780 }; 781 }; 782 }; 783 784 adsp-thermal { 785 polling-delay = <1000>; 786 polling-delay-passive = <250>; 787 thermal-sensors = <&lvts_ap MT8188_AP_ADSP>; 788 789 trips { 790 soc_alert0: trip-alert0 { 791 temperature = <85000>; 792 hysteresis = <2000>; 793 type = "passive"; 794 }; 795 796 soc_alert1: trip-alert1 { 797 temperature = <95000>; 798 hysteresis = <2000>; 799 type = "hot"; 800 }; 801 802 soc_crit: trip-crit { 803 temperature = <100000>; 804 hysteresis = <0>; 805 type = "critical"; 806 }; 807 }; 808 }; 809 810 vdo-thermal { 811 polling-delay = <1000>; 812 polling-delay-passive = <250>; 813 thermal-sensors = <&lvts_ap MT8188_AP_VDO>; 814 815 trips { 816 soc1_alert0: trip-alert0 { 817 temperature = <85000>; 818 hysteresis = <2000>; 819 type = "passive"; 820 }; 821 822 soc1_alert1: trip-alert1 { 823 temperature = <95000>; 824 hysteresis = <2000>; 825 type = "hot"; 826 }; 827 828 soc1_crit: trip-crit { 829 temperature = <100000>; 830 hysteresis = <0>; 831 type = "critical"; 832 }; 833 }; 834 }; 835 836 infra-thermal { 837 polling-delay = <1000>; 838 polling-delay-passive = <250>; 839 thermal-sensors = <&lvts_ap MT8188_AP_INFRA>; 840 841 trips { 842 soc2_alert0: trip-alert0 { 843 temperature = <85000>; 844 hysteresis = <2000>; 845 type = "passive"; 846 }; 847 848 soc2_alert1: trip-alert1 { 849 temperature = <95000>; 850 hysteresis = <2000>; 851 type = "hot"; 852 }; 853 854 soc2_crit: trip-crit { 855 temperature = <100000>; 856 hysteresis = <0>; 857 type = "critical"; 858 }; 859 }; 860 }; 861 862 cam1-thermal { 863 polling-delay = <1000>; 864 polling-delay-passive = <250>; 865 thermal-sensors = <&lvts_ap MT8188_AP_CAM1>; 866 867 trips { 868 cam1_alert0: trip-alert0 { 869 temperature = <85000>; 870 hysteresis = <2000>; 871 type = "passive"; 872 }; 873 874 cam1_alert1: trip-alert1 { 875 temperature = <95000>; 876 hysteresis = <2000>; 877 type = "hot"; 878 }; 879 880 cam1_crit: trip-crit { 881 temperature = <100000>; 882 hysteresis = <0>; 883 type = "critical"; 884 }; 885 }; 886 }; 887 888 cam2-thermal { 889 polling-delay = <1000>; 890 polling-delay-passive = <250>; 891 thermal-sensors = <&lvts_ap MT8188_AP_CAM2>; 892 893 trips { 894 cam2_alert0: trip-alert0 { 895 temperature = <85000>; 896 hysteresis = <2000>; 897 type = "passive"; 898 }; 899 900 cam2_alert1: trip-alert1 { 901 temperature = <95000>; 902 hysteresis = <2000>; 903 type = "hot"; 904 }; 905 906 cam2_crit: trip-crit { 907 temperature = <100000>; 908 hysteresis = <0>; 909 type = "critical"; 910 }; 911 }; 912 }; 913 }; 914 915 timer: timer { 916 compatible = "arm,armv8-timer"; 917 interrupt-parent = <&gic>; 918 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 919 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 920 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 921 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 922 clock-frequency = <13000000>; 923 }; 924 925 soc { 926 #address-cells = <2>; 927 #size-cells = <2>; 928 compatible = "simple-bus"; 929 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 930 ranges; 931 932 performance: performance-controller@11bc10 { 933 compatible = "mediatek,cpufreq-hw"; 934 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 935 #performance-domain-cells = <1>; 936 }; 937 938 gic: interrupt-controller@c000000 { 939 compatible = "arm,gic-v3"; 940 #interrupt-cells = <4>; 941 #redistributor-regions = <1>; 942 interrupt-parent = <&gic>; 943 interrupt-controller; 944 reg = <0 0x0c000000 0 0x40000>, 945 <0 0x0c040000 0 0x200000>; 946 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 947 948 ppi-partitions { 949 ppi_cluster0: interrupt-partition-0 { 950 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 951 }; 952 953 ppi_cluster1: interrupt-partition-1 { 954 affinity = <&cpu6 &cpu7>; 955 }; 956 }; 957 }; 958 959 topckgen: syscon@10000000 { 960 compatible = "mediatek,mt8188-topckgen", "syscon"; 961 reg = <0 0x10000000 0 0x1000>; 962 #clock-cells = <1>; 963 }; 964 965 infracfg_ao: syscon@10001000 { 966 compatible = "mediatek,mt8188-infracfg-ao", "syscon"; 967 reg = <0 0x10001000 0 0x1000>; 968 #clock-cells = <1>; 969 #reset-cells = <1>; 970 }; 971 972 pericfg: syscon@10003000 { 973 compatible = "mediatek,mt8188-pericfg", "syscon"; 974 reg = <0 0x10003000 0 0x1000>; 975 #clock-cells = <1>; 976 }; 977 978 pio: pinctrl@10005000 { 979 compatible = "mediatek,mt8188-pinctrl"; 980 reg = <0 0x10005000 0 0x1000>, 981 <0 0x11c00000 0 0x1000>, 982 <0 0x11e10000 0 0x1000>, 983 <0 0x11e20000 0 0x1000>, 984 <0 0x11ea0000 0 0x1000>, 985 <0 0x1000b000 0 0x1000>; 986 reg-names = "iocfg0", "iocfg_rm", "iocfg_lt", 987 "iocfg_lm", "iocfg_rt", "eint"; 988 gpio-controller; 989 #gpio-cells = <2>; 990 gpio-ranges = <&pio 0 0 176>; 991 interrupt-controller; 992 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 993 #interrupt-cells = <2>; 994 }; 995 996 scpsys: syscon@10006000 { 997 compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd"; 998 reg = <0 0x10006000 0 0x1000>; 999 1000 /* System Power Manager */ 1001 spm: power-controller { 1002 compatible = "mediatek,mt8188-power-controller"; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 #power-domain-cells = <1>; 1006 1007 /* power domain of the SoC */ 1008 mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 { 1009 reg = <MT8188_POWER_DOMAIN_MFG0>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 #power-domain-cells = <1>; 1013 1014 mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 { 1015 reg = <MT8188_POWER_DOMAIN_MFG1>; 1016 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, 1017 <&topckgen CLK_TOP_MFG_CORE_TMP>; 1018 clock-names = "mfg", "alt"; 1019 mediatek,infracfg = <&infracfg_ao>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 #power-domain-cells = <1>; 1023 1024 power-domain@MT8188_POWER_DOMAIN_MFG2 { 1025 reg = <MT8188_POWER_DOMAIN_MFG2>; 1026 #power-domain-cells = <0>; 1027 }; 1028 1029 power-domain@MT8188_POWER_DOMAIN_MFG3 { 1030 reg = <MT8188_POWER_DOMAIN_MFG3>; 1031 #power-domain-cells = <0>; 1032 }; 1033 1034 power-domain@MT8188_POWER_DOMAIN_MFG4 { 1035 reg = <MT8188_POWER_DOMAIN_MFG4>; 1036 #power-domain-cells = <0>; 1037 }; 1038 }; 1039 }; 1040 1041 power-domain@MT8188_POWER_DOMAIN_VPPSYS0 { 1042 reg = <MT8188_POWER_DOMAIN_VPPSYS0>; 1043 clocks = <&topckgen CLK_TOP_VPP>, 1044 <&topckgen CLK_TOP_CAM>, 1045 <&topckgen CLK_TOP_CCU>, 1046 <&topckgen CLK_TOP_IMG>, 1047 <&topckgen CLK_TOP_VENC>, 1048 <&topckgen CLK_TOP_VDEC>, 1049 <&topckgen CLK_TOP_WPE_VPP>, 1050 <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>, 1051 <&topckgen CLK_TOP_CFGREG_F26M_VPP0>, 1052 <&vppsys0 CLK_VPP0_SMI_COMMON_MMSRAM>, 1053 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0_MMSRAM>, 1054 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1_MMSRAM>, 1055 <&vppsys0 CLK_VPP0_GALS_VENCSYS_MMSRAM>, 1056 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM>, 1057 <&vppsys0 CLK_VPP0_GALS_INFRA_MMSRAM>, 1058 <&vppsys0 CLK_VPP0_GALS_CAMSYS_MMSRAM>, 1059 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5_MMSRAM>, 1060 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6_MMSRAM>, 1061 <&vppsys0 CLK_VPP0_SMI_REORDER_MMSRAM>, 1062 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 1063 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 1064 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 1065 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 1066 <&vppsys0 CLK_VPP0_SMI_RSI>, 1067 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 1068 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 1069 <&vppsys0 CLK_VPP0_GALS_VPP1_WPESYS>, 1070 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 1071 clock-names = "top", "cam", "ccu", "img", "venc", 1072 "vdec", "wpe", "cfgck", "cfgxo", 1073 "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1", 1074 "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa", 1075 "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6", 1076 "ss-sram-rdr", "ss-iommu", "ss-imgcam", 1077 "ss-emi", "ss-subcmn-rdr", "ss-rsi", 1078 "ss-cmn-l4", "ss-vdec1", "ss-wpe", 1079 "ss-cvdo-ve1"; 1080 mediatek,infracfg = <&infracfg_ao>; 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 #power-domain-cells = <1>; 1084 1085 power-domain@MT8188_POWER_DOMAIN_VDOSYS0 { 1086 reg = <MT8188_POWER_DOMAIN_VDOSYS0>; 1087 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0>, 1088 <&topckgen CLK_TOP_CFGREG_F26M_VDO0>, 1089 <&vdosys0 CLK_VDO0_SMI_GALS>, 1090 <&vdosys0 CLK_VDO0_SMI_COMMON>, 1091 <&vdosys0 CLK_VDO0_SMI_EMI>, 1092 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 1093 <&vdosys0 CLK_VDO0_SMI_LARB>, 1094 <&vdosys0 CLK_VDO0_SMI_RSI>, 1095 <&vdosys0 CLK_VDO0_APB_BUS>; 1096 clock-names = "cfgck", "cfgxo", "ss-gals", 1097 "ss-cmn", "ss-emi", "ss-iommu", 1098 "ss-larb", "ss-rsi", "ss-bus"; 1099 mediatek,infracfg = <&infracfg_ao>; 1100 #address-cells = <1>; 1101 #size-cells = <0>; 1102 #power-domain-cells = <1>; 1103 1104 power-domain@MT8188_POWER_DOMAIN_VPPSYS1 { 1105 reg = <MT8188_POWER_DOMAIN_VPPSYS1>; 1106 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>, 1107 <&topckgen CLK_TOP_CFGREG_F26M_VPP1>, 1108 <&vppsys1 CLK_VPP1_GALS5>, 1109 <&vppsys1 CLK_VPP1_GALS6>, 1110 <&vppsys1 CLK_VPP1_LARB5>, 1111 <&vppsys1 CLK_VPP1_LARB6>; 1112 clock-names = "cfgck", "cfgxo", 1113 "ss-vpp1-g5", "ss-vpp1-g6", 1114 "ss-vpp1-l5", "ss-vpp1-l6"; 1115 mediatek,infracfg = <&infracfg_ao>; 1116 #power-domain-cells = <0>; 1117 }; 1118 1119 power-domain@MT8188_POWER_DOMAIN_VDEC0 { 1120 reg = <MT8188_POWER_DOMAIN_VDEC0>; 1121 clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; 1122 clock-names = "ss-vdec1-soc-l1"; 1123 mediatek,infracfg = <&infracfg_ao>; 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 #power-domain-cells = <1>; 1127 1128 power-domain@MT8188_POWER_DOMAIN_VDEC1 { 1129 reg = <MT8188_POWER_DOMAIN_VDEC1>; 1130 clocks = <&vdecsys CLK_VDEC2_LARB1>; 1131 clock-names = "ss-vdec2-l1"; 1132 mediatek,infracfg = <&infracfg_ao>; 1133 #power-domain-cells = <0>; 1134 }; 1135 }; 1136 1137 cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE { 1138 reg = <MT8188_POWER_DOMAIN_CAM_VCORE>; 1139 clocks = <&topckgen CLK_TOP_CAM>, 1140 <&topckgen CLK_TOP_CCU>, 1141 <&topckgen CLK_TOP_CCU_AHB>, 1142 <&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>; 1143 clock-names = "cam", "ccu", "bus", "cfgck"; 1144 mediatek,infracfg = <&infracfg_ao>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 #power-domain-cells = <1>; 1148 1149 power-domain@MT8188_POWER_DOMAIN_CAM_MAIN { 1150 reg = <MT8188_POWER_DOMAIN_CAM_MAIN>; 1151 clocks = <&camsys CLK_CAM_MAIN_LARB13>, 1152 <&camsys CLK_CAM_MAIN_LARB14>, 1153 <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>, 1154 <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>, 1155 <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>; 1156 clock-names= "ss-cam-l13", "ss-cam-l14", 1157 "ss-cam-mm0", "ss-cam-mm1", 1158 "ss-camsys"; 1159 mediatek,infracfg = <&infracfg_ao>; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 #power-domain-cells = <1>; 1163 1164 power-domain@MT8188_POWER_DOMAIN_CAM_SUBB { 1165 reg = <MT8188_POWER_DOMAIN_CAM_SUBB>; 1166 clocks = <&camsys CLK_CAM_MAIN_CAM_SUBB>, 1167 <&camsys_rawb CLK_CAM_RAWB_LARBX>, 1168 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 1169 clock-names = "ss-camb-sub", 1170 "ss-camb-raw", 1171 "ss-camb-yuv"; 1172 #power-domain-cells = <0>; 1173 }; 1174 1175 power-domain@MT8188_POWER_DOMAIN_CAM_SUBA { 1176 reg =<MT8188_POWER_DOMAIN_CAM_SUBA>; 1177 clocks = <&camsys CLK_CAM_MAIN_CAM_SUBA>, 1178 <&camsys_rawa CLK_CAM_RAWA_LARBX>, 1179 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 1180 clock-names = "ss-cama-sub", 1181 "ss-cama-raw", 1182 "ss-cama-yuv"; 1183 #power-domain-cells = <0>; 1184 }; 1185 }; 1186 }; 1187 1188 power-domain@MT8188_POWER_DOMAIN_VDOSYS1 { 1189 reg = <MT8188_POWER_DOMAIN_VDOSYS1>; 1190 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1>, 1191 <&topckgen CLK_TOP_CFGREG_F26M_VDO1>, 1192 <&vdosys1 CLK_VDO1_SMI_LARB2>, 1193 <&vdosys1 CLK_VDO1_SMI_LARB3>, 1194 <&vdosys1 CLK_VDO1_GALS>; 1195 clock-names = "cfgck", "cfgxo", "ss-larb2", 1196 "ss-larb3", "ss-gals"; 1197 mediatek,infracfg = <&infracfg_ao>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 #power-domain-cells = <1>; 1201 1202 power-domain@MT8188_POWER_DOMAIN_HDMI_TX { 1203 reg = <MT8188_POWER_DOMAIN_HDMI_TX>; 1204 clocks = <&topckgen CLK_TOP_HDMI_APB>, 1205 <&topckgen CLK_TOP_HDCP_24M>; 1206 clock-names = "bus", "hdcp"; 1207 mediatek,infracfg = <&infracfg_ao>; 1208 #power-domain-cells = <0>; 1209 }; 1210 1211 power-domain@MT8188_POWER_DOMAIN_DP_TX { 1212 reg = <MT8188_POWER_DOMAIN_DP_TX>; 1213 mediatek,infracfg = <&infracfg_ao>; 1214 #power-domain-cells = <0>; 1215 }; 1216 1217 power-domain@MT8188_POWER_DOMAIN_EDP_TX { 1218 reg = <MT8188_POWER_DOMAIN_EDP_TX>; 1219 mediatek,infracfg = <&infracfg_ao>; 1220 #power-domain-cells = <0>; 1221 }; 1222 }; 1223 1224 power-domain@MT8188_POWER_DOMAIN_VENC { 1225 reg = <MT8188_POWER_DOMAIN_VENC>; 1226 clocks = <&vencsys CLK_VENC1_LARB>, 1227 <&vencsys CLK_VENC1_VENC>, 1228 <&vencsys CLK_VENC1_GALS>, 1229 <&vencsys CLK_VENC1_GALS_SRAM>; 1230 clock-names = "ss-ve1-larb", "ss-ve1-core", 1231 "ss-ve1-gals", "ss-ve1-sram"; 1232 mediatek,infracfg = <&infracfg_ao>; 1233 #power-domain-cells = <0>; 1234 }; 1235 1236 power-domain@MT8188_POWER_DOMAIN_WPE { 1237 reg = <MT8188_POWER_DOMAIN_WPE>; 1238 clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>, 1239 <&wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN>; 1240 clock-names = "ss-wpe-l7", "ss-wpe-l7pce"; 1241 mediatek,infracfg = <&infracfg_ao>; 1242 #power-domain-cells = <0>; 1243 }; 1244 }; 1245 }; 1246 1247 power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 { 1248 reg = <MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; 1249 mediatek,infracfg = <&infracfg_ao>; 1250 clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; 1251 clock-names = "ss-pextp-fmem"; 1252 #power-domain-cells = <0>; 1253 }; 1254 1255 power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP { 1256 reg = <MT8188_POWER_DOMAIN_CSIRX_TOP>; 1257 clocks = <&topckgen CLK_TOP_SENINF>, 1258 <&topckgen CLK_TOP_SENINF1>; 1259 clock-names = "seninf0", "seninf1"; 1260 #power-domain-cells = <0>; 1261 }; 1262 1263 power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP { 1264 reg = <MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>; 1265 #power-domain-cells = <0>; 1266 }; 1267 1268 power-domain@MT8188_POWER_DOMAIN_ADSP_AO { 1269 reg = <MT8188_POWER_DOMAIN_ADSP_AO>; 1270 clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 1271 <&topckgen CLK_TOP_ADSP>; 1272 clock-names = "bus", "main"; 1273 mediatek,infracfg = <&infracfg_ao>; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 #power-domain-cells = <1>; 1277 1278 power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA { 1279 reg = <MT8188_POWER_DOMAIN_ADSP_INFRA>; 1280 mediatek,infracfg = <&infracfg_ao>; 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 #power-domain-cells = <1>; 1284 1285 power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC { 1286 reg = <MT8188_POWER_DOMAIN_AUDIO_ASRC>; 1287 clocks = <&topckgen CLK_TOP_ASM_H>; 1288 clock-names = "asm"; 1289 mediatek,infracfg = <&infracfg_ao>; 1290 #power-domain-cells = <0>; 1291 }; 1292 1293 power-domain@MT8188_POWER_DOMAIN_AUDIO { 1294 reg = <MT8188_POWER_DOMAIN_AUDIO>; 1295 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 1296 <&topckgen CLK_TOP_AUD_INTBUS>, 1297 <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>; 1298 clock-names = "a1sys", "intbus", "adspck"; 1299 mediatek,infracfg = <&infracfg_ao>; 1300 #power-domain-cells = <0>; 1301 }; 1302 1303 power-domain@MT8188_POWER_DOMAIN_ADSP { 1304 reg = <MT8188_POWER_DOMAIN_ADSP>; 1305 mediatek,infracfg = <&infracfg_ao>; 1306 #power-domain-cells = <0>; 1307 }; 1308 }; 1309 }; 1310 1311 power-domain@MT8188_POWER_DOMAIN_ETHER { 1312 reg = <MT8188_POWER_DOMAIN_ETHER>; 1313 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1314 clock-names = "ethermac"; 1315 mediatek,infracfg = <&infracfg_ao>; 1316 #power-domain-cells = <0>; 1317 }; 1318 }; 1319 }; 1320 1321 watchdog: watchdog@10007000 { 1322 compatible = "mediatek,mt8188-wdt"; 1323 reg = <0 0x10007000 0 0x100>; 1324 mediatek,disable-extrst; 1325 #reset-cells = <1>; 1326 }; 1327 1328 apmixedsys: syscon@1000c000 { 1329 compatible = "mediatek,mt8188-apmixedsys", "syscon"; 1330 reg = <0 0x1000c000 0 0x1000>; 1331 #clock-cells = <1>; 1332 }; 1333 1334 systimer: timer@10017000 { 1335 compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer"; 1336 reg = <0 0x10017000 0 0x1000>; 1337 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 1338 clocks = <&clk13m>; 1339 }; 1340 1341 pwrap: pwrap@10024000 { 1342 compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon"; 1343 reg = <0 0x10024000 0 0x1000>; 1344 reg-names = "pwrap"; 1345 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 1346 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 1347 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 1348 clock-names = "spi", "wrap"; 1349 }; 1350 1351 spmi: spmi@10027000 { 1352 compatible = "mediatek,mt8188-spmi", "mediatek,mt8195-spmi"; 1353 reg = <0 0x10027000 0 0xe00>, <0 0x10029000 0 0x100>; 1354 reg-names = "pmif", "spmimst"; 1355 assigned-clocks = <&topckgen CLK_TOP_SPMI_M_MST>; 1356 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 1357 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 1358 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 1359 <&topckgen CLK_TOP_SPMI_M_MST>; 1360 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; 1361 }; 1362 1363 infra_iommu: iommu@10315000 { 1364 compatible = "mediatek,mt8188-iommu-infra"; 1365 reg = <0 0x10315000 0 0x1000>; 1366 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>; 1367 #iommu-cells = <1>; 1368 }; 1369 1370 gce0: mailbox@10320000 { 1371 compatible = "mediatek,mt8188-gce"; 1372 reg = <0 0x10320000 0 0x4000>; 1373 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 1374 #mbox-cells = <2>; 1375 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 1376 }; 1377 1378 gce1: mailbox@10330000 { 1379 compatible = "mediatek,mt8188-gce"; 1380 reg = <0 0x10330000 0 0x4000>; 1381 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 1382 #mbox-cells = <2>; 1383 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 1384 }; 1385 1386 scp_cluster: scp@10720000 { 1387 compatible = "mediatek,mt8188-scp-dual"; 1388 reg = <0 0x10720000 0 0xe0000>; 1389 reg-names = "cfg"; 1390 #address-cells = <1>; 1391 #size-cells = <1>; 1392 ranges = <0 0 0x10500000 0x100000>; 1393 status = "disabled"; 1394 1395 scp_c0: scp@0 { 1396 compatible = "mediatek,scp-core"; 1397 reg = <0x0 0xd0000>; 1398 reg-names = "sram"; 1399 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 1400 status = "disabled"; 1401 }; 1402 1403 scp_c1: scp@d0000 { 1404 compatible = "mediatek,scp-core"; 1405 reg = <0xd0000 0x2f000>; 1406 reg-names = "sram"; 1407 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>; 1408 status = "disabled"; 1409 }; 1410 }; 1411 1412 afe: audio-controller@10b10000 { 1413 compatible = "mediatek,mt8188-afe"; 1414 reg = <0 0x10b10000 0 0x10000>; 1415 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>; 1416 assigned-clock-parents = <&topckgen CLK_TOP_APLL1_D4>; 1417 clocks = <&clk26m>, 1418 <&apmixedsys CLK_APMIXED_APLL1>, 1419 <&apmixedsys CLK_APMIXED_APLL2>, 1420 <&topckgen CLK_TOP_APLL12_CK_DIV0>, 1421 <&topckgen CLK_TOP_APLL12_CK_DIV1>, 1422 <&topckgen CLK_TOP_APLL12_CK_DIV2>, 1423 <&topckgen CLK_TOP_APLL12_CK_DIV3>, 1424 <&topckgen CLK_TOP_APLL12_CK_DIV9>, 1425 <&topckgen CLK_TOP_A1SYS_HP>, 1426 <&topckgen CLK_TOP_AUD_INTBUS>, 1427 <&topckgen CLK_TOP_AUDIO_H>, 1428 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 1429 <&topckgen CLK_TOP_DPTX>, 1430 <&topckgen CLK_TOP_I2SO1>, 1431 <&topckgen CLK_TOP_I2SO2>, 1432 <&topckgen CLK_TOP_I2SI1>, 1433 <&topckgen CLK_TOP_I2SI2>, 1434 <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>, 1435 <&topckgen CLK_TOP_APLL1_D4>, 1436 <&topckgen CLK_TOP_APLL2_D4>, 1437 <&topckgen CLK_TOP_APLL12_CK_DIV4>, 1438 <&topckgen CLK_TOP_A2SYS>, 1439 <&topckgen CLK_TOP_AUD_IEC>; 1440 clock-names = "clk26m", 1441 "apll1", 1442 "apll2", 1443 "apll12_div0", 1444 "apll12_div1", 1445 "apll12_div2", 1446 "apll12_div3", 1447 "apll12_div9", 1448 "top_a1sys_hp", 1449 "top_aud_intbus", 1450 "top_audio_h", 1451 "top_audio_local_bus", 1452 "top_dptx", 1453 "top_i2so1", 1454 "top_i2so2", 1455 "top_i2si1", 1456 "top_i2si2", 1457 "adsp_audio_26m", 1458 "apll1_d4", 1459 "apll2_d4", 1460 "apll12_div4", 1461 "top_a2sys", 1462 "top_aud_iec"; 1463 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 1464 power-domains = <&spm MT8188_POWER_DOMAIN_AUDIO>; 1465 resets = <&watchdog MT8188_TOPRGU_AUDIO_SW_RST>; 1466 reset-names = "audiosys"; 1467 mediatek,infracfg = <&infracfg_ao>; 1468 mediatek,topckgen = <&topckgen>; 1469 status = "disabled"; 1470 }; 1471 1472 adsp: adsp@10b80000 { 1473 compatible = "mediatek,mt8188-dsp"; 1474 reg = <0 0x10b80000 0 0x2000>, 1475 <0 0x10d00000 0 0x80000>, 1476 <0 0x10b8b000 0 0x100>, 1477 <0 0x10b8f000 0 0x1000>; 1478 reg-names = "cfg", "sram", "sec", "bus"; 1479 assigned-clocks = <&topckgen CLK_TOP_ADSP>; 1480 clocks = <&topckgen CLK_TOP_ADSP>, 1481 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 1482 clock-names = "audiodsp", "adsp_bus"; 1483 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 1484 mbox-names = "rx", "tx"; 1485 power-domains = <&spm MT8188_POWER_DOMAIN_ADSP>; 1486 status = "disabled"; 1487 }; 1488 1489 adsp_mailbox0: mailbox@10b86100 { 1490 compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox"; 1491 reg = <0 0x10b86100 0 0x1000>; 1492 interrupts = <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH 0>; 1493 #mbox-cells = <0>; 1494 }; 1495 1496 adsp_mailbox1: mailbox@10b87100 { 1497 compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox"; 1498 reg = <0 0x10b87100 0 0x1000>; 1499 interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH 0>; 1500 #mbox-cells = <0>; 1501 }; 1502 1503 adsp_audio26m: clock-controller@10b91100 { 1504 compatible = "mediatek,mt8188-adsp-audio26m"; 1505 reg = <0 0x10b91100 0 0x100>; 1506 #clock-cells = <1>; 1507 }; 1508 1509 uart0: serial@11001100 { 1510 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 1511 reg = <0 0x11001100 0 0x100>; 1512 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 1513 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1514 clock-names = "baud", "bus"; 1515 status = "disabled"; 1516 }; 1517 1518 uart1: serial@11001200 { 1519 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 1520 reg = <0 0x11001200 0 0x100>; 1521 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 1522 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1523 clock-names = "baud", "bus"; 1524 status = "disabled"; 1525 }; 1526 1527 uart2: serial@11001300 { 1528 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 1529 reg = <0 0x11001300 0 0x100>; 1530 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1531 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1532 clock-names = "baud", "bus"; 1533 status = "disabled"; 1534 }; 1535 1536 uart3: serial@11001400 { 1537 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 1538 reg = <0 0x11001400 0 0x100>; 1539 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 1540 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 1541 clock-names = "baud", "bus"; 1542 status = "disabled"; 1543 }; 1544 1545 auxadc: adc@11002000 { 1546 compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc"; 1547 reg = <0 0x11002000 0 0x1000>; 1548 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1549 clock-names = "main"; 1550 #io-channel-cells = <1>; 1551 status = "disabled"; 1552 }; 1553 1554 pericfg_ao: syscon@11003000 { 1555 compatible = "mediatek,mt8188-pericfg-ao", "syscon"; 1556 reg = <0 0x11003000 0 0x1000>; 1557 #clock-cells = <1>; 1558 }; 1559 1560 spi0: spi@1100a000 { 1561 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1562 #address-cells = <1>; 1563 #size-cells = <0>; 1564 reg = <0 0x1100a000 0 0x1000>; 1565 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1566 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1567 <&topckgen CLK_TOP_SPI>, 1568 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1569 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1570 status = "disabled"; 1571 }; 1572 1573 lvts_ap: thermal-sensor@1100b000 { 1574 compatible = "mediatek,mt8188-lvts-ap"; 1575 reg = <0 0x1100b000 0 0xc00>; 1576 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 0>; 1577 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1578 resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_CTRL_RST>; 1579 nvmem-cells = <&lvts_efuse_data1>; 1580 nvmem-cell-names = "lvts-calib-data-1"; 1581 #thermal-sensor-cells = <1>; 1582 }; 1583 1584 disp_pwm0: pwm@1100e000 { 1585 compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm"; 1586 reg = <0 0x1100e000 0 0x1000>; 1587 clocks = <&topckgen CLK_TOP_DISP_PWM0>, 1588 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1589 clock-names = "main", "mm"; 1590 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 1591 #pwm-cells = <2>; 1592 status = "disabled"; 1593 }; 1594 1595 disp_pwm1: pwm@1100f000 { 1596 compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm"; 1597 reg = <0 0x1100f000 0 0x1000>; 1598 clocks = <&topckgen CLK_TOP_DISP_PWM1>, 1599 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; 1600 clock-names = "main", "mm"; 1601 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>; 1602 #pwm-cells = <2>; 1603 status = "disabled"; 1604 }; 1605 1606 spi1: spi@11010000 { 1607 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1608 #address-cells = <1>; 1609 #size-cells = <0>; 1610 reg = <0 0x11010000 0 0x1000>; 1611 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1612 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1613 <&topckgen CLK_TOP_SPI>, 1614 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1615 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1616 status = "disabled"; 1617 }; 1618 1619 spi2: spi@11012000 { 1620 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1621 #address-cells = <1>; 1622 #size-cells = <0>; 1623 reg = <0 0x11012000 0 0x1000>; 1624 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1625 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1626 <&topckgen CLK_TOP_SPI>, 1627 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1628 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1629 status = "disabled"; 1630 }; 1631 1632 spi3: spi@11013000 { 1633 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1634 #address-cells = <1>; 1635 #size-cells = <0>; 1636 reg = <0 0x11013000 0 0x1000>; 1637 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1638 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1639 <&topckgen CLK_TOP_SPI>, 1640 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1641 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1642 status = "disabled"; 1643 }; 1644 1645 spi4: spi@11018000 { 1646 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 reg = <0 0x11018000 0 0x1000>; 1650 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1651 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1652 <&topckgen CLK_TOP_SPI>, 1653 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1654 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1655 status = "disabled"; 1656 }; 1657 1658 spi5: spi@11019000 { 1659 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 1660 #address-cells = <1>; 1661 #size-cells = <0>; 1662 reg = <0 0x11019000 0 0x1000>; 1663 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1664 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1665 <&topckgen CLK_TOP_SPI>, 1666 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1667 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1668 status = "disabled"; 1669 }; 1670 1671 ssusb1: usb@11201000 { 1672 compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; 1673 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1674 reg-names = "mac", "ippc"; 1675 ranges = <0 0 0 0x11200000 0 0x3f00>; 1676 #address-cells = <2>; 1677 #size-cells = <2>; 1678 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; 1679 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>; 1680 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1681 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>, 1682 <&topckgen CLK_TOP_SSUSB_TOP_REF>, 1683 <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; 1684 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1685 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1686 wakeup-source; 1687 mediatek,syscon-wakeup = <&pericfg 0x468 2>; 1688 status = "disabled"; 1689 1690 xhci1: usb@0 { 1691 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 1692 reg = <0 0 0 0x1000>; 1693 reg-names = "mac"; 1694 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1695 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI>; 1696 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1697 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; 1698 clock-names = "sys_ck"; 1699 status = "disabled"; 1700 }; 1701 }; 1702 1703 eth: ethernet@11021000 { 1704 compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac", 1705 "snps,dwmac-5.10a"; 1706 reg = <0 0x11021000 0 0x4000>; 1707 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1708 interrupt-names = "macirq"; 1709 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1710 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1711 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1712 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1713 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1714 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1715 clock-names = "axi", "apb", "mac_main", "ptp_ref", 1716 "rmii_internal", "mac_cg"; 1717 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1718 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1719 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1720 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1721 <&topckgen CLK_TOP_ETHPLL_D8>, 1722 <&topckgen CLK_TOP_ETHPLL_D10>; 1723 power-domains = <&spm MT8188_POWER_DOMAIN_ETHER>; 1724 mediatek,pericfg = <&infracfg_ao>; 1725 snps,axi-config = <&stmmac_axi_setup>; 1726 snps,mtl-rx-config = <&mtl_rx_setup>; 1727 snps,mtl-tx-config = <&mtl_tx_setup>; 1728 snps,txpbl = <16>; 1729 snps,rxpbl = <16>; 1730 snps,clk-csr = <0>; 1731 status = "disabled"; 1732 1733 eth_mdio: mdio { 1734 compatible = "snps,dwmac-mdio"; 1735 #address-cells = <1>; 1736 #size-cells = <0>; 1737 }; 1738 1739 stmmac_axi_setup: stmmac-axi-config { 1740 snps,blen = <0 0 0 0 16 8 4>; 1741 snps,rd_osr_lmt = <0x7>; 1742 snps,wr_osr_lmt = <0x7>; 1743 }; 1744 1745 mtl_rx_setup: rx-queues-config { 1746 snps,rx-queues-to-use = <4>; 1747 snps,rx-sched-sp; 1748 1749 queue0 { 1750 snps,dcb-algorithm; 1751 snps,map-to-dma-channel = <0x0>; 1752 }; 1753 1754 queue1 { 1755 snps,dcb-algorithm; 1756 snps,map-to-dma-channel = <0x0>; 1757 }; 1758 1759 queue2 { 1760 snps,dcb-algorithm; 1761 snps,map-to-dma-channel = <0x0>; 1762 }; 1763 1764 queue3 { 1765 snps,dcb-algorithm; 1766 snps,map-to-dma-channel = <0x0>; 1767 }; 1768 }; 1769 1770 mtl_tx_setup: tx-queues-config { 1771 snps,tx-queues-to-use = <4>; 1772 snps,tx-sched-wrr; 1773 1774 queue0 { 1775 snps,dcb-algorithm; 1776 snps,priority = <0x0>; 1777 snps,weight = <0x10>; 1778 }; 1779 1780 queue1 { 1781 snps,dcb-algorithm; 1782 snps,priority = <0x1>; 1783 snps,weight = <0x11>; 1784 }; 1785 1786 queue2 { 1787 snps,dcb-algorithm; 1788 snps,priority = <0x2>; 1789 snps,weight = <0x12>; 1790 }; 1791 1792 queue3 { 1793 snps,dcb-algorithm; 1794 snps,priority = <0x3>; 1795 snps,weight = <0x13>; 1796 }; 1797 }; 1798 }; 1799 1800 mmc0: mmc@11230000 { 1801 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 1802 reg = <0 0x11230000 0 0x10000>, 1803 <0 0x11f50000 0 0x1000>; 1804 interrupts-extended = <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1805 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1806 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1807 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1808 <&infracfg_ao CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P>; 1809 clock-names = "source", "hclk", "source_cg", "crypto_clk"; 1810 status = "disabled"; 1811 }; 1812 1813 mmc1: mmc@11240000 { 1814 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 1815 reg = <0 0x11240000 0 0x1000>, 1816 <0 0x11eb0000 0 0x1000>; 1817 interrupts-extended = <&gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1818 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1819 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1820 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1821 clock-names = "source", "hclk", "source_cg"; 1822 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1823 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1824 status = "disabled"; 1825 }; 1826 1827 mmc2: mmc@11250000 { 1828 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 1829 reg = <0 0x11250000 0 0x1000>, 1830 <0 0x11e60000 0 0x1000>; 1831 interrupts-extended = <&gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1832 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1833 <&infracfg_ao CLK_INFRA_AO_MSDC2>, 1834 <&infracfg_ao CLK_INFRA_AO_MSDC30_2>; 1835 clock-names = "source", "hclk", "source_cg"; 1836 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1837 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1838 status = "disabled"; 1839 }; 1840 1841 lvts_mcu: thermal-sensor@11278000 { 1842 compatible = "mediatek,mt8188-lvts-mcu"; 1843 reg = <0 0x11278000 0 0x1000>; 1844 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 1845 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1846 resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_MCU_RST>; 1847 nvmem-cells = <&lvts_efuse_data1>; 1848 nvmem-cell-names = "lvts-calib-data-1"; 1849 #thermal-sensor-cells = <1>; 1850 }; 1851 1852 i2c0: i2c@11280000 { 1853 compatible = "mediatek,mt8188-i2c"; 1854 reg = <0 0x11280000 0 0x1000>, 1855 <0 0x10220080 0 0x80>; 1856 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>; 1857 clock-div = <1>; 1858 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0>, 1859 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1860 clock-names = "main", "dma"; 1861 #address-cells = <1>; 1862 #size-cells = <0>; 1863 status = "disabled"; 1864 }; 1865 1866 i2c2: i2c@11281000 { 1867 compatible = "mediatek,mt8188-i2c"; 1868 reg = <0 0x11281000 0 0x1000>, 1869 <0 0x10220180 0 0x80>; 1870 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 1871 clock-div = <1>; 1872 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2>, 1873 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1874 clock-names = "main", "dma"; 1875 #address-cells = <1>; 1876 #size-cells = <0>; 1877 status = "disabled"; 1878 }; 1879 1880 i2c3: i2c@11282000 { 1881 compatible = "mediatek,mt8188-i2c"; 1882 reg = <0 0x11282000 0 0x1000>, 1883 <0 0x10220280 0 0x80>; 1884 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1885 clock-div = <1>; 1886 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3>, 1887 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1888 clock-names = "main", "dma"; 1889 #address-cells = <1>; 1890 #size-cells = <0>; 1891 status = "disabled"; 1892 }; 1893 1894 imp_iic_wrap_c: clock-controller@11283000 { 1895 compatible = "mediatek,mt8188-imp-iic-wrap-c"; 1896 reg = <0 0x11283000 0 0x1000>; 1897 #clock-cells = <1>; 1898 }; 1899 1900 ssusb2: usb@112a1000 { 1901 compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; 1902 reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>; 1903 reg-names = "mac", "ippc"; 1904 ranges = <0 0 0 0x112a0000 0 0x3f00>; 1905 #address-cells = <2>; 1906 #size-cells = <2>; 1907 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>; 1908 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>; 1909 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1910 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1911 <&topckgen CLK_TOP_SSUSB_TOP_P3_REF>, 1912 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1913 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1914 phys = <&u2port2 PHY_TYPE_USB2>; 1915 wakeup-source; 1916 mediatek,syscon-wakeup = <&pericfg 0x470 2>; 1917 status = "disabled"; 1918 1919 xhci2: usb@0 { 1920 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 1921 reg = <0 0 0 0x1000>; 1922 reg-names = "mac"; 1923 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1924 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1925 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1926 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1927 clock-names = "sys_ck"; 1928 status = "disabled"; 1929 }; 1930 }; 1931 1932 ssusb0: usb@112b1000 { 1933 compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; 1934 reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>; 1935 reg-names = "mac", "ippc"; 1936 ranges = <0 0 0 0x112b0000 0 0x3f00>; 1937 #address-cells = <2>; 1938 #size-cells = <2>; 1939 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; 1940 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1941 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1942 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1943 <&topckgen CLK_TOP_SSUSB_TOP_P2_REF>, 1944 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1945 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1946 phys = <&u2port0 PHY_TYPE_USB2>; 1947 wakeup-source; 1948 mediatek,syscon-wakeup = <&pericfg 0x460 2>; 1949 status = "disabled"; 1950 1951 xhci0: usb@0 { 1952 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 1953 reg = <0 0 0 0x1000>; 1954 reg-names = "mac"; 1955 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1956 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>; 1957 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1958 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1959 clock-names = "sys_ck"; 1960 status = "disabled"; 1961 }; 1962 }; 1963 1964 pcie: pcie@112f0000 { 1965 compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie"; 1966 reg = <0 0x112f0000 0 0x2000>; 1967 reg-names = "pcie-mac"; 1968 ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x4000000>; 1969 bus-range = <0 0xff>; 1970 device_type = "pci"; 1971 linux,pci-domain = <0>; 1972 #address-cells = <3>; 1973 #size-cells = <2>; 1974 1975 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1976 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1977 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1978 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1979 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1980 <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; 1981 clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k", 1982 "peri_26m", "peri_mem"; 1983 1984 #interrupt-cells = <1>; 1985 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1986 interrupt-map = <0 0 0 1 &pcie_intc 0>, 1987 <0 0 0 2 &pcie_intc 1>, 1988 <0 0 0 3 &pcie_intc 2>, 1989 <0 0 0 4 &pcie_intc 3>; 1990 interrupt-map-mask = <0 0 0 7>; 1991 1992 iommu-map = <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>; 1993 iommu-map-mask = <0>; 1994 1995 phys = <&pcieport PHY_TYPE_PCIE>; 1996 phy-names = "pcie-phy"; 1997 1998 power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; 1999 2000 resets = <&watchdog MT8188_TOPRGU_PCIE_SW_RST>; 2001 reset-names = "mac"; 2002 2003 status = "disabled"; 2004 2005 pcie_intc: interrupt-controller { 2006 #address-cells = <0>; 2007 #interrupt-cells = <1>; 2008 interrupt-controller; 2009 }; 2010 }; 2011 2012 nor_flash: spi@1132c000 { 2013 compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor"; 2014 reg = <0 0x1132c000 0 0x1000>; 2015 clocks = <&topckgen CLK_TOP_SPINOR>, 2016 <&pericfg_ao CLK_PERI_AO_FLASHIFLASHCK>, 2017 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 2018 clock-names = "spi", "sf", "axi"; 2019 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 2020 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 2021 #address-cells = <1>; 2022 #size-cells = <0>; 2023 status = "disabled"; 2024 }; 2025 2026 pciephy: t-phy@11c20700 { 2027 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 2028 ranges = <0 0 0x11c20700 0x700>; 2029 #address-cells = <1>; 2030 #size-cells = <1>; 2031 power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>; 2032 status = "disabled"; 2033 2034 pcieport: pcie-phy@0 { 2035 reg = <0 0x700>; 2036 clocks = <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>; 2037 clock-names = "ref"; 2038 #phy-cells = <1>; 2039 }; 2040 }; 2041 2042 hdmi_phy: hdmi-phy@11d5f000 { 2043 compatible = "mediatek,mt8188-hdmi-phy", "mediatek,mt8195-hdmi-phy"; 2044 reg = <0 0x11d5f000 0 0x100>; 2045 clocks = <&infracfg_ao CLK_INFRA_AO_HDMI_26M>; 2046 clock-names = "pll_ref"; 2047 clock-output-names = "hdmi_txpll"; 2048 #clock-cells = <0>; 2049 #phy-cells = <0>; 2050 mediatek,ibias = <0xa>; 2051 mediatek,ibias_up = <0x1c>; 2052 status = "disabled"; 2053 }; 2054 2055 mipi_tx_config0: dsi-phy@11c80000 { 2056 compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; 2057 reg = <0 0x11c80000 0 0x1000>; 2058 clocks = <&clk26m>; 2059 clock-output-names = "mipi_tx0_pll"; 2060 #clock-cells = <0>; 2061 #phy-cells = <0>; 2062 status = "disabled"; 2063 }; 2064 2065 mipi_tx_config1: dsi-phy@11c90000 { 2066 compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; 2067 reg = <0 0x11c90000 0 0x1000>; 2068 clocks = <&clk26m>; 2069 clock-output-names = "mipi_tx0_pll"; 2070 #clock-cells = <0>; 2071 #phy-cells = <0>; 2072 status = "disabled"; 2073 }; 2074 2075 i2c1: i2c@11e00000 { 2076 compatible = "mediatek,mt8188-i2c"; 2077 reg = <0 0x11e00000 0 0x1000>, 2078 <0 0x10220100 0 0x80>; 2079 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 2080 clock-div = <1>; 2081 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1>, 2082 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 2083 clock-names = "main", "dma"; 2084 #address-cells = <1>; 2085 #size-cells = <0>; 2086 status = "disabled"; 2087 }; 2088 2089 i2c4: i2c@11e01000 { 2090 compatible = "mediatek,mt8188-i2c"; 2091 reg = <0 0x11e01000 0 0x1000>, 2092 <0 0x10220380 0 0x80>; 2093 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>; 2094 clock-div = <1>; 2095 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4>, 2096 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 2097 clock-names = "main", "dma"; 2098 #address-cells = <1>; 2099 #size-cells = <0>; 2100 status = "disabled"; 2101 }; 2102 2103 imp_iic_wrap_w: clock-controller@11e02000 { 2104 compatible = "mediatek,mt8188-imp-iic-wrap-w"; 2105 reg = <0 0x11e02000 0 0x1000>; 2106 #clock-cells = <1>; 2107 }; 2108 2109 u3phy0: t-phy@11e30000 { 2110 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 2111 #address-cells = <1>; 2112 #size-cells = <1>; 2113 ranges = <0x0 0x0 0x11e30000 0x1000>; 2114 status = "disabled"; 2115 2116 u2port0: usb-phy@0 { 2117 reg = <0x0 0x700>; 2118 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>, 2119 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 2120 clock-names = "ref", "da_ref"; 2121 #phy-cells = <1>; 2122 }; 2123 }; 2124 2125 u3phy1: t-phy@11e40000 { 2126 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 2127 #address-cells = <1>; 2128 #size-cells = <1>; 2129 ranges = <0x0 0x0 0x11e40000 0x1000>; 2130 status = "disabled"; 2131 2132 u2port1: usb-phy@0 { 2133 reg = <0x0 0x700>; 2134 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 2135 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 2136 clock-names = "ref", "da_ref"; 2137 #phy-cells = <1>; 2138 }; 2139 2140 u3port1: usb-phy@700 { 2141 reg = <0x700 0x700>; 2142 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>, 2143 <&clk26m>; 2144 clock-names = "ref", "da_ref"; 2145 #phy-cells = <1>; 2146 }; 2147 }; 2148 2149 u3phy2: t-phy@11e80000 { 2150 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 2151 #address-cells = <1>; 2152 #size-cells = <1>; 2153 ranges = <0x0 0x0 0x11e80000 0x1000>; 2154 status = "disabled"; 2155 2156 u2port2: usb-phy@0 { 2157 reg = <0x0 0x700>; 2158 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>, 2159 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 2160 clock-names = "ref", "da_ref"; 2161 #phy-cells = <1>; 2162 }; 2163 }; 2164 2165 i2c5: i2c@11ec0000 { 2166 compatible = "mediatek,mt8188-i2c"; 2167 reg = <0 0x11ec0000 0 0x1000>, 2168 <0 0x10220480 0 0x80>; 2169 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>; 2170 clock-div = <1>; 2171 clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5>, 2172 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 2173 clock-names = "main", "dma"; 2174 #address-cells = <1>; 2175 #size-cells = <0>; 2176 status = "disabled"; 2177 }; 2178 2179 i2c6: i2c@11ec1000 { 2180 compatible = "mediatek,mt8188-i2c"; 2181 reg = <0 0x11ec1000 0 0x1000>, 2182 <0 0x10220600 0 0x80>; 2183 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 2184 clock-div = <1>; 2185 clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6>, 2186 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 2187 clock-names = "main", "dma"; 2188 #address-cells = <1>; 2189 #size-cells = <0>; 2190 status = "disabled"; 2191 }; 2192 2193 imp_iic_wrap_en: clock-controller@11ec2000 { 2194 compatible = "mediatek,mt8188-imp-iic-wrap-en"; 2195 reg = <0 0x11ec2000 0 0x1000>; 2196 #clock-cells = <1>; 2197 }; 2198 2199 efuse: efuse@11f20000 { 2200 compatible = "mediatek,mt8188-efuse", "mediatek,mt8186-efuse"; 2201 reg = <0 0x11f20000 0 0x1000>; 2202 #address-cells = <1>; 2203 #size-cells = <1>; 2204 2205 dp_calib_data: dp-calib@1a0 { 2206 reg = <0x1a0 0xc>; 2207 }; 2208 2209 lvts_efuse_data1: lvts1-calib@1ac { 2210 reg = <0x1ac 0x40>; 2211 }; 2212 2213 gpu_speedbin: gpu-speedbin@581 { 2214 reg = <0x581 0x1>; 2215 bits = <0 3>; 2216 }; 2217 2218 socinfo-data1@7a0 { 2219 reg = <0x7a0 0x4>; 2220 }; 2221 2222 socinfo-data2@7e0 { 2223 reg = <0x7e0 0x4>; 2224 }; 2225 }; 2226 2227 gpu: gpu@13000000 { 2228 compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm"; 2229 reg = <0 0x13000000 0 0x4000>; 2230 2231 clocks = <&mfgcfg CLK_MFGCFG_BG3D>; 2232 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, 2233 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>, 2234 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>; 2235 interrupt-names = "job", "mmu", "gpu"; 2236 nvmem-cells = <&gpu_speedbin>; 2237 nvmem-cell-names = "speed-bin"; 2238 operating-points-v2 = <&gpu_opp_table>; 2239 power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>, 2240 <&spm MT8188_POWER_DOMAIN_MFG3>, 2241 <&spm MT8188_POWER_DOMAIN_MFG4>; 2242 power-domain-names = "core0", "core1", "core2"; 2243 #cooling-cells = <2>; 2244 status = "disabled"; 2245 }; 2246 2247 mfgcfg: clock-controller@13fbf000 { 2248 compatible = "mediatek,mt8188-mfgcfg"; 2249 reg = <0 0x13fbf000 0 0x1000>; 2250 #clock-cells = <1>; 2251 }; 2252 2253 vppsys0: syscon@14000000 { 2254 compatible = "mediatek,mt8188-vppsys0", "syscon"; 2255 reg = <0 0x14000000 0 0x1000>; 2256 #clock-cells = <1>; 2257 }; 2258 2259 dma-controller@14001000 { 2260 compatible = "mediatek,mt8188-mdp3-rdma"; 2261 reg = <0 0x14001000 0 0x1000>; 2262 #dma-cells = <1>; 2263 clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>; 2264 mboxes = <&gce0 13 CMDQ_THR_PRIO_1>, 2265 <&gce0 14 CMDQ_THR_PRIO_1>, 2266 <&gce0 16 CMDQ_THR_PRIO_1>, 2267 <&gce0 21 CMDQ_THR_PRIO_1>, 2268 <&gce0 22 CMDQ_THR_PRIO_1>; 2269 iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>; 2270 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2271 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; 2272 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>, 2273 <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>; 2274 mediatek,scp = <&scp_c0>; 2275 }; 2276 2277 display@14002000 { 2278 compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg"; 2279 reg = <0 0x14002000 0 0x1000>; 2280 clocks = <&vppsys0 CLK_VPP0_MDP_FG>; 2281 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; 2282 }; 2283 2284 display@14004000 { 2285 compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr"; 2286 reg = <0 0x14004000 0 0x1000>; 2287 clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; 2288 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; 2289 }; 2290 2291 display@14005000 { 2292 compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal"; 2293 reg = <0 0x14005000 0 0x1000>; 2294 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>; 2295 clocks = <&vppsys0 CLK_VPP0_MDP_AAL>; 2296 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2297 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; 2298 }; 2299 2300 display@14006000 { 2301 compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2302 reg = <0 0x14006000 0 0x1000>; 2303 clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>; 2304 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; 2305 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>, 2306 <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>; 2307 }; 2308 2309 display@14007000 { 2310 compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp"; 2311 reg = <0 0x14007000 0 0x1000>; 2312 clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; 2313 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; 2314 }; 2315 2316 display@14008000 { 2317 compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color"; 2318 reg = <0 0x14008000 0 0x1000>; 2319 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 2320 clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>; 2321 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2322 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; 2323 }; 2324 2325 display@14009000 { 2326 compatible = "mediatek,mt8188-mdp3-ovl", "mediatek,mt8195-mdp3-ovl"; 2327 reg = <0 0x14009000 0 0x1000>; 2328 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 2329 clocks = <&vppsys0 CLK_VPP0_MDP_OVL>; 2330 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2331 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; 2332 iommus = <&vpp_iommu M4U_PORT_L4_MDP_OVL>; 2333 }; 2334 2335 display@1400a000 { 2336 compatible = "mediatek,mt8188-mdp3-padding", "mediatek,mt8195-mdp3-padding"; 2337 reg = <0 0x1400a000 0 0x1000>; 2338 clocks = <&vppsys0 CLK_VPP0_PADDING>; 2339 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2340 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; 2341 }; 2342 2343 display@1400b000 { 2344 compatible = "mediatek,mt8188-mdp3-tcc", "mediatek,mt8195-mdp3-tcc"; 2345 reg = <0 0x1400b000 0 0x1000>; 2346 clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; 2347 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; 2348 }; 2349 2350 display@1400c000 { 2351 compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2352 reg = <0 0x1400c000 0 0x1000>; 2353 #dma-cells = <1>; 2354 clocks = <&vppsys0 CLK_VPP0_MDP_WROT>; 2355 iommus = <&vpp_iommu M4U_PORT_L4_MDP_WROT>; 2356 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2357 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>; 2358 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>, 2359 <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>; 2360 }; 2361 2362 mutex@1400f000 { 2363 compatible = "mediatek,mt8188-vpp-mutex"; 2364 reg = <0 0x1400f000 0 0x1000>; 2365 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>; 2366 clocks = <&vppsys0 CLK_VPP0_MUTEX>; 2367 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2368 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; 2369 }; 2370 2371 vpp_smi_common: smi@14012000 { 2372 compatible = "mediatek,mt8188-smi-common-vpp"; 2373 reg = <0 0x14012000 0 0x1000>; 2374 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2375 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>; 2376 clock-names = "apb", "smi"; 2377 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2378 }; 2379 2380 larb4: smi@14013000 { 2381 compatible = "mediatek,mt8188-smi-larb"; 2382 reg = <0 0x14013000 0 0x1000>; 2383 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2384 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 2385 clock-names = "apb", "smi"; 2386 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2387 mediatek,larb-id = <SMI_L4_ID>; 2388 mediatek,smi = <&vpp_smi_common>; 2389 }; 2390 2391 vpp_iommu: iommu@14018000 { 2392 compatible = "mediatek,mt8188-iommu-vpp"; 2393 reg = <0 0x14018000 0 0x5000>; 2394 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 2395 clock-names = "bclk"; 2396 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 2397 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; 2398 #iommu-cells = <1>; 2399 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb7 &larb23>; 2400 }; 2401 2402 dma-controller@14f09000 { 2403 compatible = "mediatek,mt8188-mdp3-rdma"; 2404 reg = <0 0x14f09000 0 0x1000>; 2405 #dma-cells = <1>; 2406 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>; 2407 iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA>; 2408 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2409 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; 2410 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>, 2411 <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>; 2412 }; 2413 2414 dma-controller@14f0a000 { 2415 compatible = "mediatek,mt8188-mdp3-rdma"; 2416 reg = <0 0x14f0a000 0 0x1000>; 2417 #dma-cells = <1>; 2418 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>; 2419 iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA>; 2420 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2421 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; 2422 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>, 2423 <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>; 2424 }; 2425 2426 display@14f0c000 { 2427 compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg"; 2428 reg = <0 0x14f0c000 0 0x1000>; 2429 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; 2430 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; 2431 }; 2432 2433 display@14f0d000 { 2434 compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg"; 2435 reg = <0 0x14f0d000 0 0x1000>; 2436 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; 2437 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; 2438 }; 2439 2440 display@14f0f000 { 2441 compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr"; 2442 reg = <0 0x14f0f000 0 0x1000>; 2443 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; 2444 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; 2445 }; 2446 2447 display@14f10000 { 2448 compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr"; 2449 reg = <0 0x14f10000 0 0x1000>; 2450 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; 2451 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>; 2452 }; 2453 2454 display@14f12000 { 2455 compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal"; 2456 reg = <0 0x14f12000 0 0x1000>; 2457 interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>; 2458 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; 2459 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2460 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; 2461 }; 2462 2463 display@14f13000 { 2464 compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal"; 2465 reg = <0 0x14f13000 0 0x1000>; 2466 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>; 2467 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; 2468 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2469 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; 2470 }; 2471 2472 display@14f15000 { 2473 compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2474 reg = <0 0x14f15000 0 0x1000>; 2475 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>; 2476 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; 2477 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>, 2478 <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>; 2479 }; 2480 2481 display@14f16000 { 2482 compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2483 reg = <0 0x14f16000 0 0x1000>; 2484 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>; 2485 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; 2486 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>, 2487 <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>; 2488 }; 2489 2490 display@14f18000 { 2491 compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp"; 2492 reg = <0 0x14f18000 0 0x1000>; 2493 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; 2494 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; 2495 }; 2496 2497 display@14f19000 { 2498 compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp"; 2499 reg = <0 0x14f19000 0 0x1000>; 2500 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; 2501 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; 2502 }; 2503 2504 display@14f1a000 { 2505 compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge"; 2506 reg = <0 0x14f1a000 0 0x1000>; 2507 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; 2508 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2509 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; 2510 }; 2511 2512 display@14f1b000 { 2513 compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge"; 2514 reg = <0 0x14f1b000 0 0x1000>; 2515 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; 2516 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2517 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>; 2518 }; 2519 2520 display@14f1d000 { 2521 compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color"; 2522 reg = <0 0x14f1d000 0 0x1000>; 2523 interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>; 2524 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; 2525 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2526 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; 2527 }; 2528 2529 display@14f1e000 { 2530 compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color"; 2531 reg = <0 0x14f1e000 0 0x1000>; 2532 interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>; 2533 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; 2534 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2535 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; 2536 }; 2537 2538 display@14f21000 { 2539 compatible = "mediatek,mt8188-mdp3-padding", 2540 "mediatek,mt8195-mdp3-padding"; 2541 reg = <0 0x14f21000 0 0x1000>; 2542 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; 2543 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2544 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>; 2545 }; 2546 2547 display@14f22000 { 2548 compatible = "mediatek,mt8188-mdp3-padding", 2549 "mediatek,mt8195-mdp3-padding"; 2550 reg = <0 0x14f22000 0 0x1000>; 2551 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; 2552 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2553 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>; 2554 }; 2555 2556 display@14f24000 { 2557 compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2558 reg = <0 0x14f24000 0 0x1000>; 2559 #dma-cells = <1>; 2560 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; 2561 iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT>; 2562 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2563 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>; 2564 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>, 2565 <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>; 2566 }; 2567 2568 display@14f25000 { 2569 compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2570 reg = <0 0x14f25000 0 0x1000>; 2571 #dma-cells = <1>; 2572 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; 2573 iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT>; 2574 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2575 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>; 2576 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>, 2577 <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>; 2578 }; 2579 2580 wpesys: clock-controller@14e00000 { 2581 compatible = "mediatek,mt8188-wpesys"; 2582 reg = <0 0x14e00000 0 0x1000>; 2583 #clock-cells = <1>; 2584 }; 2585 2586 wpesys_vpp0: clock-controller@14e02000 { 2587 compatible = "mediatek,mt8188-wpesys-vpp0"; 2588 reg = <0 0x14e02000 0 0x1000>; 2589 #clock-cells = <1>; 2590 }; 2591 2592 larb7: smi@14e04000 { 2593 compatible = "mediatek,mt8188-smi-larb"; 2594 reg = <0 0x14e04000 0 0x1000>; 2595 clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>, 2596 <&wpesys CLK_WPE_TOP_SMI_LARB7>; 2597 clock-names = "apb", "smi"; 2598 power-domains = <&spm MT8188_POWER_DOMAIN_WPE>; 2599 mediatek,larb-id = <SMI_L7_ID>; 2600 mediatek,smi = <&vpp_smi_common>; 2601 }; 2602 2603 vppsys1: syscon@14f00000 { 2604 compatible = "mediatek,mt8188-vppsys1", "syscon"; 2605 reg = <0 0x14f00000 0 0x1000>; 2606 #clock-cells = <1>; 2607 }; 2608 2609 mutex@14f01000 { 2610 compatible = "mediatek,mt8188-vpp-mutex"; 2611 reg = <0 0x14f01000 0 0x1000>; 2612 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 2613 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; 2614 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2615 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; 2616 }; 2617 2618 larb5: smi@14f02000 { 2619 compatible = "mediatek,mt8188-smi-larb"; 2620 reg = <0 0x14f02000 0 0x1000>; 2621 clocks = <&vppsys1 CLK_VPP1_GALS5>, 2622 <&vppsys1 CLK_VPP1_LARB5>; 2623 clock-names = "apb", "smi"; 2624 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2625 mediatek,larb-id = <SMI_L5_ID>; 2626 mediatek,smi = <&vdo_smi_common>; 2627 }; 2628 2629 larb6: smi@14f03000 { 2630 compatible = "mediatek,mt8188-smi-larb"; 2631 reg = <0 0x14f03000 0 0x1000>; 2632 clocks = <&vppsys1 CLK_VPP1_GALS6>, 2633 <&vppsys1 CLK_VPP1_LARB6>; 2634 clock-names = "apb", "smi"; 2635 power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; 2636 mediatek,larb-id = <SMI_L6_ID>; 2637 mediatek,smi = <&vpp_smi_common>; 2638 }; 2639 2640 imgsys: clock-controller@15000000 { 2641 compatible = "mediatek,mt8188-imgsys"; 2642 reg = <0 0x15000000 0 0x1000>; 2643 #clock-cells = <1>; 2644 }; 2645 2646 imgsys1_dip_top: clock-controller@15110000 { 2647 compatible = "mediatek,mt8188-imgsys1-dip-top"; 2648 reg = <0 0x15110000 0 0x1000>; 2649 #clock-cells = <1>; 2650 #reset-cells = <1>; 2651 }; 2652 2653 imgsys1_dip_nr: clock-controller@15130000 { 2654 compatible = "mediatek,mt8188-imgsys1-dip-nr"; 2655 reg = <0 0x15130000 0 0x1000>; 2656 #clock-cells = <1>; 2657 #reset-cells = <1>; 2658 }; 2659 2660 imgsys_wpe1: clock-controller@15220000 { 2661 compatible = "mediatek,mt8188-imgsys-wpe1"; 2662 reg = <0 0x15220000 0 0x1000>; 2663 #clock-cells = <1>; 2664 #reset-cells = <1>; 2665 }; 2666 2667 ipesys: clock-controller@15330000 { 2668 compatible = "mediatek,mt8188-ipesys"; 2669 reg = <0 0x15330000 0 0x1000>; 2670 #clock-cells = <1>; 2671 #reset-cells = <1>; 2672 }; 2673 2674 imgsys_wpe2: clock-controller@15520000 { 2675 compatible = "mediatek,mt8188-imgsys-wpe2"; 2676 reg = <0 0x15520000 0 0x1000>; 2677 #clock-cells = <1>; 2678 #reset-cells = <1>; 2679 }; 2680 2681 imgsys_wpe3: clock-controller@15620000 { 2682 compatible = "mediatek,mt8188-imgsys-wpe3"; 2683 reg = <0 0x15620000 0 0x1000>; 2684 #clock-cells = <1>; 2685 #reset-cells = <1>; 2686 }; 2687 2688 camsys: clock-controller@16000000 { 2689 compatible = "mediatek,mt8188-camsys"; 2690 reg = <0 0x16000000 0 0x1000>; 2691 #clock-cells = <1>; 2692 }; 2693 2694 camsys_rawa: clock-controller@1604f000 { 2695 compatible = "mediatek,mt8188-camsys-rawa"; 2696 reg = <0 0x1604f000 0 0x1000>; 2697 #clock-cells = <1>; 2698 #reset-cells = <1>; 2699 }; 2700 2701 camsys_yuva: clock-controller@1606f000 { 2702 compatible = "mediatek,mt8188-camsys-yuva"; 2703 reg = <0 0x1606f000 0 0x1000>; 2704 #clock-cells = <1>; 2705 #reset-cells = <1>; 2706 }; 2707 2708 camsys_rawb: clock-controller@1608f000 { 2709 compatible = "mediatek,mt8188-camsys-rawb"; 2710 reg = <0 0x1608f000 0 0x1000>; 2711 #clock-cells = <1>; 2712 #reset-cells = <1>; 2713 }; 2714 2715 camsys_yuvb: clock-controller@160af000 { 2716 compatible = "mediatek,mt8188-camsys-yuvb"; 2717 reg = <0 0x160af000 0 0x1000>; 2718 #clock-cells = <1>; 2719 #reset-cells = <1>; 2720 }; 2721 2722 ccusys: clock-controller@17200000 { 2723 compatible = "mediatek,mt8188-ccusys"; 2724 reg = <0 0x17200000 0 0x1000>; 2725 #clock-cells = <1>; 2726 }; 2727 2728 video_decoder: video-decoder@18000000 { 2729 compatible = "mediatek,mt8188-vcodec-dec"; 2730 reg = <0 0x18000000 0 0x1000>, <0 0x18004000 0 0x1000>; 2731 ranges = <0 0 0 0x18000000 0 0x26000>; 2732 iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>; 2733 #address-cells = <2>; 2734 #size-cells = <2>; 2735 mediatek,scp = <&scp_c0>; 2736 2737 video-codec@10000 { 2738 compatible = "mediatek,mtk-vcodec-lat"; 2739 reg = <0 0x10000 0 0x800>; 2740 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2741 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 2742 clocks = <&topckgen CLK_TOP_VDEC>, 2743 <&vdecsys_soc CLK_VDEC1_SOC_VDEC>, 2744 <&vdecsys_soc CLK_VDEC1_SOC_LAT>, 2745 <&topckgen CLK_TOP_UNIVPLL_D6>; 2746 clock-names = "sel", "vdec", "lat", "top"; 2747 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; 2748 iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT>, 2749 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT>, 2750 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT>, 2751 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT>, 2752 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT>, 2753 <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT>, 2754 <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>, 2755 <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C>, 2756 <&vpp_iommu M4U_PORT_L23_HW_VDEC_MC_EXT_C>; 2757 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; 2758 }; 2759 2760 video-codec@25000 { 2761 compatible = "mediatek,mtk-vcodec-core"; 2762 reg = <0 0x25000 0 0x1000>; 2763 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2764 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 2765 clocks = <&topckgen CLK_TOP_VDEC>, 2766 <&vdecsys CLK_VDEC2_VDEC>, 2767 <&vdecsys CLK_VDEC2_LAT>, 2768 <&topckgen CLK_TOP_UNIVPLL_D6>; 2769 clock-names = "sel", "vdec", "lat", "top"; 2770 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; 2771 iommus = <&vdo_iommu M4U_PORT_L21_HW_VDEC_MC_EXT>, 2772 <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT>, 2773 <&vdo_iommu M4U_PORT_L21_HW_VDEC_PP_EXT>, 2774 <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_RD_EXT>, 2775 <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_WR_EXT>, 2776 <&vdo_iommu M4U_PORT_L21_HW_VDEC_PPWRAP_EXT>, 2777 <&vdo_iommu M4U_PORT_L21_HW_VDEC_TILE_EXT>, 2778 <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD_EXT>, 2779 <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD2_EXT>, 2780 <&vdo_iommu M4U_PORT_L21_HW_VDEC_AVC_MV_EXT>, 2781 <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT_C>; 2782 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>; 2783 }; 2784 }; 2785 2786 larb23: smi@1800d000 { 2787 compatible = "mediatek,mt8188-smi-larb"; 2788 reg = <0 0x1800d000 0 0x1000>; 2789 clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>, 2790 <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; 2791 clock-names = "apb", "smi"; 2792 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; 2793 mediatek,larb-id = <SMI_L23_ID>; 2794 mediatek,smi = <&vpp_smi_common>; 2795 }; 2796 2797 vdecsys_soc: clock-controller@1800f000 { 2798 compatible = "mediatek,mt8188-vdecsys-soc"; 2799 reg = <0 0x1800f000 0 0x1000>; 2800 #clock-cells = <1>; 2801 }; 2802 2803 larb21: smi@1802e000 { 2804 compatible = "mediatek,mt8188-smi-larb"; 2805 reg = <0 0x1802e000 0 0x1000>; 2806 clocks = <&vdecsys CLK_VDEC2_LARB1>, 2807 <&vdecsys CLK_VDEC2_LARB1>; 2808 clock-names = "apb", "smi"; 2809 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>; 2810 mediatek,larb-id = <SMI_L21_ID>; 2811 mediatek,smi = <&vdo_smi_common>; 2812 }; 2813 2814 vdecsys: clock-controller@1802f000 { 2815 compatible = "mediatek,mt8188-vdecsys"; 2816 reg = <0 0x1802f000 0 0x1000>; 2817 #clock-cells = <1>; 2818 }; 2819 2820 vencsys: clock-controller@1a000000 { 2821 compatible = "mediatek,mt8188-vencsys"; 2822 reg = <0 0x1a000000 0 0x1000>; 2823 #clock-cells = <1>; 2824 }; 2825 2826 larb19: smi@1a010000 { 2827 compatible = "mediatek,mt8188-smi-larb"; 2828 reg = <0 0x1a010000 0 0x1000>; 2829 clocks = <&vencsys CLK_VENC1_VENC>, 2830 <&vencsys CLK_VENC1_VENC>; 2831 clock-names = "apb", "smi"; 2832 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; 2833 mediatek,larb-id = <SMI_L19_ID>; 2834 mediatek,smi = <&vdo_smi_common>; 2835 }; 2836 2837 video_encoder: video-encoder@1a020000 { 2838 compatible = "mediatek,mt8188-vcodec-enc"; 2839 reg = <0 0x1a020000 0 0x10000>; 2840 #address-cells = <2>; 2841 #size-cells = <2>; 2842 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2843 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2844 clocks = <&vencsys CLK_VENC1_VENC>; 2845 clock-names = "venc_sel"; 2846 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 2847 iommus = <&vdo_iommu M4U_PORT_L19_VENC_RCPU>, 2848 <&vdo_iommu M4U_PORT_L19_VENC_REC>, 2849 <&vdo_iommu M4U_PORT_L19_VENC_BSDMA>, 2850 <&vdo_iommu M4U_PORT_L19_VENC_SV_COMV>, 2851 <&vdo_iommu M4U_PORT_L19_VENC_RD_COMV>, 2852 <&vdo_iommu M4U_PORT_L19_VENC_CUR_LUMA>, 2853 <&vdo_iommu M4U_PORT_L19_VENC_CUR_CHROMA>, 2854 <&vdo_iommu M4U_PORT_L19_VENC_REF_LUMA>, 2855 <&vdo_iommu M4U_PORT_L19_VENC_REF_CHROMA>, 2856 <&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>, 2857 <&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>; 2858 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; 2859 mediatek,scp = <&scp_c0>; 2860 }; 2861 2862 jpeg_encoder: jpeg-encoder@1a030000 { 2863 compatible = "mediatek,mt8188-jpgenc", "mediatek,mtk-jpgenc"; 2864 reg = <0 0x1a030000 0 0x10000>; 2865 clocks = <&vencsys CLK_VENC1_JPGENC>; 2866 clock-names = "jpgenc"; 2867 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 2868 iommus = <&vdo_iommu M4U_PORT_L19_JPGENC_Y_RDMA>, 2869 <&vdo_iommu M4U_PORT_L19_JPGENC_C_RDMA>, 2870 <&vdo_iommu M4U_PORT_L19_JPGENC_Q_TABLE>, 2871 <&vdo_iommu M4U_PORT_L19_JPGENC_BSDMA>; 2872 power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; 2873 }; 2874 2875 jpeg_decoder: jpeg-decoder@1a040000 { 2876 compatible = "mediatek,mt8188-jpgdec", "mediatek,mt2701-jpgdec"; 2877 reg = <0 0x1a040000 0 0x10000>; 2878 clocks = <&vencsys CLK_VENC1_LARB>, 2879 <&vencsys CLK_VENC1_JPGDEC>; 2880 clock-names = "jpgdec-smi", "jpgdec"; 2881 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 2882 iommus = <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_0>, 2883 <&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_0>, 2884 <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_1>, 2885 <&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_1>, 2886 <&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_1>, 2887 <&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_0>; 2888 power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; 2889 }; 2890 2891 ovl0: ovl@1c000000 { 2892 compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8195-disp-ovl"; 2893 reg = <0 0x1c000000 0 0x1000>; 2894 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 2895 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 2896 iommus = <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>; 2897 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2898 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 2899 2900 ports { 2901 #address-cells = <1>; 2902 #size-cells = <0>; 2903 2904 port@0 { 2905 reg = <0>; 2906 ovl0_in: endpoint { }; 2907 }; 2908 2909 port@1 { 2910 reg = <1>; 2911 ovl0_out: endpoint { 2912 remote-endpoint = <&rdma0_in>; 2913 }; 2914 }; 2915 }; 2916 }; 2917 2918 rdma0: rdma@1c002000 { 2919 compatible = "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma"; 2920 reg = <0 0x1c002000 0 0x1000>; 2921 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 2922 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 2923 iommus = <&vpp_iommu M4U_PORT_L1_DISP_RDMA0>; 2924 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2925 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 2926 2927 ports { 2928 #address-cells = <1>; 2929 #size-cells = <0>; 2930 2931 port@0 { 2932 reg = <0>; 2933 rdma0_in: endpoint { 2934 remote-endpoint = <&ovl0_out>; 2935 }; 2936 }; 2937 2938 port@1 { 2939 reg = <1>; 2940 rdma0_out: endpoint { 2941 remote-endpoint = <&color0_in>; 2942 }; 2943 }; 2944 }; 2945 }; 2946 2947 color0: color@1c003000 { 2948 compatible = "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-color"; 2949 reg = <0 0x1c003000 0 0x1000>; 2950 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 2951 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 2952 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2953 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 2954 2955 ports { 2956 #address-cells = <1>; 2957 #size-cells = <0>; 2958 2959 port@0 { 2960 reg = <0>; 2961 color0_in: endpoint { 2962 remote-endpoint = <&rdma0_out>; 2963 }; 2964 }; 2965 2966 port@1 { 2967 reg = <1>; 2968 color0_out: endpoint { 2969 remote-endpoint = <&ccorr0_in>; 2970 }; 2971 }; 2972 }; 2973 }; 2974 2975 ccorr0: ccorr@1c004000 { 2976 compatible = "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 2977 reg = <0 0x1c004000 0 0x1000>; 2978 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 2979 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 2980 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 2981 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 2982 2983 ports { 2984 #address-cells = <1>; 2985 #size-cells = <0>; 2986 2987 port@0 { 2988 reg = <0>; 2989 ccorr0_in: endpoint { 2990 remote-endpoint = <&color0_out>; 2991 }; 2992 }; 2993 2994 port@1 { 2995 reg = <1>; 2996 ccorr0_out: endpoint { 2997 remote-endpoint = <&aal0_in>; 2998 }; 2999 }; 3000 }; 3001 }; 3002 3003 aal0: aal@1c005000 { 3004 compatible = "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal"; 3005 reg = <0 0x1c005000 0 0x1000>; 3006 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 3007 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 3008 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3009 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 3010 3011 ports { 3012 #address-cells = <1>; 3013 #size-cells = <0>; 3014 3015 port@0 { 3016 reg = <0>; 3017 aal0_in: endpoint { 3018 remote-endpoint = <&ccorr0_out>; 3019 }; 3020 }; 3021 3022 port@1 { 3023 reg = <1>; 3024 aal0_out: endpoint { 3025 remote-endpoint = <&gamma0_in>; 3026 }; 3027 }; 3028 }; 3029 }; 3030 3031 gamma0: gamma@1c006000 { 3032 compatible = "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamma"; 3033 reg = <0 0x1c006000 0 0x1000>; 3034 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 3035 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 3036 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3037 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 3038 3039 ports { 3040 #address-cells = <1>; 3041 #size-cells = <0>; 3042 3043 port@0 { 3044 reg = <0>; 3045 gamma0_in: endpoint { 3046 remote-endpoint = <&aal0_out>; 3047 }; 3048 }; 3049 3050 port@1 { 3051 reg = <1>; 3052 gamma0_out: endpoint { }; 3053 }; 3054 }; 3055 }; 3056 3057 dither0: dither@1c007000 { 3058 compatible = "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dither"; 3059 reg = <0 0x1c007000 0 0x1000>; 3060 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 3061 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 3062 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3063 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 3064 3065 ports { 3066 #address-cells = <1>; 3067 #size-cells = <0>; 3068 3069 port@0 { 3070 reg = <0>; 3071 dither0_in: endpoint { }; 3072 }; 3073 3074 port@1 { 3075 reg = <1>; 3076 dither0_out: endpoint { }; 3077 }; 3078 }; 3079 }; 3080 3081 disp_dsi0: dsi@1c008000 { 3082 compatible = "mediatek,mt8188-dsi"; 3083 reg = <0 0x1c008000 0 0x1000>; 3084 clocks = <&vdosys0 CLK_VDO0_DSI0>, 3085 <&vdosys0 CLK_VDO0_DSI0_DSI>, 3086 <&mipi_tx_config0>; 3087 clock-names = "engine", "digital", "hs"; 3088 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 3089 phys = <&mipi_tx_config0>; 3090 phy-names = "dphy"; 3091 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3092 resets = <&vdosys0 MT8188_VDO0_RST_DSI0>; 3093 status = "disabled"; 3094 }; 3095 3096 dsc0: dsc@1c009000 { 3097 compatible = "mediatek,mt8188-disp-dsc", "mediatek,mt8195-disp-dsc"; 3098 reg = <0 0x1c009000 0 0x1000>; 3099 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 3100 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 3101 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3102 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 3103 }; 3104 3105 disp_dsi1: dsi@1c012000 { 3106 compatible = "mediatek,mt8188-dsi"; 3107 reg = <0 0x1c012000 0 0x1000>; 3108 clocks = <&vdosys0 CLK_VDO0_DSI1>, 3109 <&vdosys0 CLK_VDO0_DSI1_DSI>, 3110 <&mipi_tx_config1>; 3111 clock-names = "engine", "digital", "hs"; 3112 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 3113 phys = <&mipi_tx_config1>; 3114 phy-names = "dphy"; 3115 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3116 resets = <&vdosys0 MT8188_VDO0_RST_DSI1>; 3117 status = "disabled"; 3118 }; 3119 3120 merge0: merge0@1c014000 { 3121 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3122 reg = <0 0x1c014000 0 0x1000>; 3123 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>, 3124 <&vdosys1 CLK_VDO1_MERGE_VDO1_DL_ASYNC>; 3125 clock-names = "merge", "merge_async"; 3126 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 3127 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3128 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 3129 }; 3130 3131 dp_intf0: dp-intf@1c015000 { 3132 compatible = "mediatek,mt8188-dp-intf"; 3133 reg = <0 0x1c015000 0 0x1000>; 3134 clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 3135 <&vdosys0 CLK_VDO0_DP_INTF0>, 3136 <&apmixedsys CLK_APMIXED_TVDPLL1>; 3137 clock-names = "pixel", "engine", "pll"; 3138 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 3139 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3140 status = "disabled"; 3141 }; 3142 3143 mutex0: mutex@1c016000 { 3144 compatible = "mediatek,mt8188-disp-mutex"; 3145 reg = <0 0x1c016000 0 0x1000>; 3146 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 3147 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 3148 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3149 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; 3150 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 3151 }; 3152 3153 postmask0: postmask@1c01a000 { 3154 compatible = "mediatek,mt8188-disp-postmask", 3155 "mediatek,mt8192-disp-postmask"; 3156 reg = <0 0x1c01a000 0 0x1000>; 3157 clocks = <&vdosys0 CLK_VDO0_DISP_POSTMASK0>; 3158 interrupts = <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>; 3159 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3160 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; 3161 3162 ports { 3163 #address-cells = <1>; 3164 #size-cells = <0>; 3165 3166 port@0 { 3167 reg = <0>; 3168 postmask0_in: endpoint { }; 3169 }; 3170 3171 port@1 { 3172 reg = <1>; 3173 postmask0_out: endpoint { }; 3174 }; 3175 }; 3176 }; 3177 3178 vdosys0: syscon@1c01d000 { 3179 compatible = "mediatek,mt8188-vdosys0", "syscon"; 3180 reg = <0 0x1c01d000 0 0x1000>; 3181 #clock-cells = <1>; 3182 #reset-cells = <1>; 3183 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 3184 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>; 3185 }; 3186 3187 larb0: smi@1c022000 { 3188 compatible = "mediatek,mt8188-smi-larb"; 3189 reg = <0 0x1c022000 0 0x1000>; 3190 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 3191 <&vdosys0 CLK_VDO0_SMI_LARB>; 3192 clock-names = "apb", "smi"; 3193 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3194 mediatek,larb-id = <SMI_L0_ID>; 3195 mediatek,smi = <&vdo_smi_common>; 3196 }; 3197 3198 larb1: smi@1c023000 { 3199 compatible = "mediatek,mt8188-smi-larb"; 3200 reg = <0 0x1c023000 0 0x1000>; 3201 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 3202 <&vdosys0 CLK_VDO0_SMI_LARB>; 3203 clock-names = "apb", "smi"; 3204 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3205 mediatek,larb-id = <SMI_L1_ID>; 3206 mediatek,smi = <&vpp_smi_common>; 3207 }; 3208 3209 vdo_smi_common: smi@1c024000 { 3210 compatible = "mediatek,mt8188-smi-common-vdo"; 3211 reg = <0 0x1c024000 0 0x1000>; 3212 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 3213 <&vdosys0 CLK_VDO0_SMI_GALS>; 3214 clock-names = "apb", "smi"; 3215 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3216 }; 3217 3218 vdo_iommu: iommu@1c028000 { 3219 compatible = "mediatek,mt8188-iommu-vdo"; 3220 reg = <0 0x1c028000 0 0x5000>; 3221 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 3222 clock-names = "bclk"; 3223 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>; 3224 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; 3225 #iommu-cells = <1>; 3226 mediatek,larbs = <&larb0 &larb2 &larb5 &larb19 &larb21>; 3227 }; 3228 3229 vdosys1: syscon@1c100000 { 3230 compatible = "mediatek,mt8188-vdosys1", "syscon"; 3231 reg = <0 0x1c100000 0 0x1000>; 3232 #clock-cells = <1>; 3233 #reset-cells = <1>; 3234 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; 3235 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>; 3236 }; 3237 3238 mutex1: mutex@1c101000 { 3239 compatible = "mediatek,mt8188-disp-mutex"; 3240 reg = <0 0x1c101000 0 0x1000>; 3241 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; 3242 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; 3243 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3244 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; 3245 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; 3246 }; 3247 3248 larb2: smi@1c102000 { 3249 compatible = "mediatek,mt8188-smi-larb"; 3250 reg = <0 0x1c102000 0 0x1000>; 3251 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 3252 <&vdosys1 CLK_VDO1_SMI_LARB2>; 3253 clock-names = "apb", "smi"; 3254 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3255 mediatek,larb-id = <SMI_L2_ID>; 3256 mediatek,smi = <&vdo_smi_common>; 3257 }; 3258 3259 larb3: smi@1c103000 { 3260 compatible = "mediatek,mt8188-smi-larb"; 3261 reg = <0 0x1c103000 0 0x1000>; 3262 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 3263 <&vdosys1 CLK_VDO1_SMI_LARB3>; 3264 clock-names = "apb", "smi"; 3265 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3266 mediatek,larb-id = <SMI_L3_ID>; 3267 mediatek,smi = <&vpp_smi_common>; 3268 }; 3269 3270 vdo1_rdma0: rdma@1c104000 { 3271 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3272 reg = <0 0x1c104000 0 0x1000>; 3273 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; 3274 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; 3275 iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA0>; 3276 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3277 #dma-cells = <1>; 3278 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; 3279 }; 3280 3281 vdo1_rdma1: rdma@1c105000 { 3282 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3283 reg = <0 0x1c105000 0 0x1000>; 3284 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; 3285 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; 3286 iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA1>; 3287 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3288 #dma-cells = <1>; 3289 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; 3290 }; 3291 3292 vdo1_rdma2: rdma@1c106000 { 3293 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3294 reg = <0 0x1c106000 0 0x1000>; 3295 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; 3296 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; 3297 iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA2>; 3298 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3299 #dma-cells = <1>; 3300 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; 3301 }; 3302 3303 vdo1_rdma3: rdma@1c107000 { 3304 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3305 reg = <0 0x1c107000 0 0x1000>; 3306 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; 3307 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; 3308 iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA3>; 3309 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3310 #dma-cells = <1>; 3311 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; 3312 }; 3313 3314 vdo1_rdma4: rdma@1c108000 { 3315 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3316 reg = <0 0x1c108000 0 0x1000>; 3317 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; 3318 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; 3319 iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA4>; 3320 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3321 #dma-cells = <1>; 3322 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; 3323 }; 3324 3325 vdo1_rdma5: rdma@1c109000 { 3326 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3327 reg = <0 0x1c109000 0 0x1000>; 3328 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; 3329 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; 3330 iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA5>; 3331 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3332 #dma-cells = <1>; 3333 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; 3334 }; 3335 3336 vdo1_rdma6: rdma@1c10a000 { 3337 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3338 reg = <0 0x1c10a000 0 0x1000>; 3339 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; 3340 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; 3341 iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA6>; 3342 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3343 #dma-cells = <1>; 3344 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; 3345 }; 3346 3347 vdo1_rdma7: rdma@1c10b000 { 3348 compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; 3349 reg = <0 0x1c10b000 0 0x1000>; 3350 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; 3351 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; 3352 iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA7>; 3353 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3354 #dma-cells = <1>; 3355 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; 3356 }; 3357 3358 merge1: merge@1c10c000 { 3359 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3360 reg = <0 0x1c10c000 0 0x1000>; 3361 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, 3362 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; 3363 clock-names = "merge", "merge_async"; 3364 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 3365 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3366 resets = <&vdosys1 MT8188_VDO1_RST_MERGE0_DL_ASYNC>; 3367 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; 3368 mediatek,merge-mute; 3369 }; 3370 3371 merge2: merge@1c10d000 { 3372 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3373 reg = <0 0x1c10d000 0 0x1000>; 3374 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, 3375 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; 3376 clock-names = "merge", "merge_async"; 3377 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; 3378 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3379 resets = <&vdosys1 MT8188_VDO1_RST_MERGE1_DL_ASYNC>; 3380 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; 3381 mediatek,merge-mute; 3382 }; 3383 3384 merge3: merge@1c10e000 { 3385 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3386 reg = <0 0x1c10e000 0 0x1000>; 3387 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, 3388 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; 3389 clock-names = "merge", "merge_async"; 3390 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; 3391 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3392 resets = <&vdosys1 MT8188_VDO1_RST_MERGE2_DL_ASYNC>; 3393 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; 3394 mediatek,merge-mute; 3395 }; 3396 3397 merge4: merge@1c10f000 { 3398 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3399 reg = <0 0x1c10f000 0 0x1000>; 3400 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, 3401 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; 3402 clock-names = "merge", "merge_async"; 3403 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; 3404 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3405 resets = <&vdosys1 MT8188_VDO1_RST_MERGE3_DL_ASYNC>; 3406 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; 3407 mediatek,merge-mute; 3408 }; 3409 3410 merge5: merge@1c110000 { 3411 compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; 3412 reg = <0 0x1c110000 0 0x1000>; 3413 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, 3414 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; 3415 clock-names = "merge", "merge_async"; 3416 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; 3417 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3418 resets = <&vdosys1 MT8188_VDO1_RST_MERGE4_DL_ASYNC>; 3419 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; 3420 mediatek,merge-fifo-en; 3421 }; 3422 3423 dpi1: dpi@1c112000 { 3424 compatible = "mediatek,mt8188-dpi", "mediatek,mt8195-dpi"; 3425 reg = <0 0x1c112000 0 0x1000>; 3426 clocks = <&vdosys1 CLK_VDO1_DPI1>, 3427 <&vdosys1 CLK_VDO1_DPI1_MM>, 3428 <&vdosys1 CLK_VDO1_DPI1_HDMI>; 3429 clock-names = "pixel", "engine", "pll"; 3430 interrupts = <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH 0>; 3431 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3432 resets = <&vdosys1 MT8188_VDO1_RST_DPI1_MM_CK>; 3433 status = "disabled"; 3434 3435 ports { 3436 #address-cells = <1>; 3437 #size-cells = <0>; 3438 3439 port@0 { 3440 reg = <0>; 3441 dpi1_in: endpoint { }; 3442 }; 3443 3444 port@1 { 3445 reg = <1>; 3446 dpi1_out: endpoint { }; 3447 }; 3448 }; 3449 }; 3450 3451 dp_intf1: dp-intf@1c113000 { 3452 compatible = "mediatek,mt8188-dp-intf"; 3453 reg = <0 0x1c113000 0 0x1000>; 3454 clocks = <&vdosys1 CLK_VDO1_DPINTF>, 3455 <&vdosys1 CLK_VDO1_DP_INTF0_MMCK>, 3456 <&apmixedsys CLK_APMIXED_TVDPLL2>; 3457 clock-names = "pixel", "engine", "pll"; 3458 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 3459 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3460 status = "disabled"; 3461 }; 3462 3463 ethdr0: ethdr@1c114000 { 3464 compatible = "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethdr"; 3465 reg = <0 0x1c114000 0 0x1000>, 3466 <0 0x1c115000 0 0x1000>, 3467 <0 0x1c117000 0 0x1000>, 3468 <0 0x1c119000 0 0x1000>, 3469 <0 0x1c11a000 0 0x1000>, 3470 <0 0x1c11b000 0 0x1000>, 3471 <0 0x1c11c000 0 0x1000>; 3472 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3473 "vdo_be", "adl_ds"; 3474 3475 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, 3476 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, 3477 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, 3478 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, 3479 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, 3480 <&vdosys1 CLK_VDO1_HDR_VDO_BE>, 3481 <&vdosys1 CLK_VDO1_26M_SLOW>, 3482 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, 3483 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, 3484 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, 3485 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, 3486 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, 3487 <&topckgen CLK_TOP_ETHDR>; 3488 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3489 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", 3490 "gfx_fe0_async", "gfx_fe1_async", "vdo_be_async", "ethdr_top"; 3491 3492 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH 0>; 3493 iommus = <&vpp_iommu M4U_PORT_L3_HDR_DS_SMI>, 3494 <&vpp_iommu M4U_PORT_L3_HDR_ADL_SMI>; 3495 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3496 resets = <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC>, 3497 <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC>, 3498 <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC>, 3499 <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC>, 3500 <&vdosys1 MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC>; 3501 3502 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, 3503 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, 3504 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, 3505 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, 3506 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, 3507 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, 3508 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; 3509 }; 3510 3511 padding0: padding@1c11d000 { 3512 compatible = "mediatek,mt8188-disp-padding"; 3513 reg = <0 0x1c11d000 0 0x1000>; 3514 clocks = <&vdosys1 CLK_VDO1_PADDING0>; 3515 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3516 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>; 3517 }; 3518 3519 padding1: padding@1c11e000 { 3520 compatible = "mediatek,mt8188-disp-padding"; 3521 reg = <0 0x1c11e000 0 0x1000>; 3522 clocks = <&vdosys1 CLK_VDO1_PADDING1>; 3523 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3524 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xe000 0x1000>; 3525 }; 3526 3527 padding2: padding@1c11f000 { 3528 compatible = "mediatek,mt8188-disp-padding"; 3529 reg = <0 0x1c11f000 0 0x1000>; 3530 clocks = <&vdosys1 CLK_VDO1_PADDING2>; 3531 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3532 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xf000 0x1000>; 3533 }; 3534 3535 padding3: padding@1c120000 { 3536 compatible = "mediatek,mt8188-disp-padding"; 3537 reg = <0 0x1c120000 0 0x1000>; 3538 clocks = <&vdosys1 CLK_VDO1_PADDING3>; 3539 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3540 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x0000 0x1000>; 3541 }; 3542 3543 padding4: padding@1c121000 { 3544 compatible = "mediatek,mt8188-disp-padding"; 3545 reg = <0 0x1c121000 0 0x1000>; 3546 clocks = <&vdosys1 CLK_VDO1_PADDING4>; 3547 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3548 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x1000 0x1000>; 3549 }; 3550 3551 padding5: padding@1c122000 { 3552 compatible = "mediatek,mt8188-disp-padding"; 3553 reg = <0 0x1c122000 0 0x1000>; 3554 clocks = <&vdosys1 CLK_VDO1_PADDING5>; 3555 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3556 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x2000 0x1000>; 3557 }; 3558 3559 padding6: padding@1c123000 { 3560 compatible = "mediatek,mt8188-disp-padding"; 3561 reg = <0 0x1c123000 0 0x1000>; 3562 clocks = <&vdosys1 CLK_VDO1_PADDING6>; 3563 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3564 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x3000 0x1000>; 3565 }; 3566 3567 padding7: padding@1c124000 { 3568 compatible = "mediatek,mt8188-disp-padding"; 3569 reg = <0 0x1c124000 0 0x1000>; 3570 clocks = <&vdosys1 CLK_VDO1_PADDING7>; 3571 power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 3572 mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>; 3573 }; 3574 3575 hdmi: hdmi@1c300000 { 3576 compatible = "mediatek,mt8188-hdmi-tx"; 3577 #sound-dai-cells = <1>; 3578 reg = <0 0x1c300000 0 0x1000>; 3579 clocks = <&topckgen CLK_TOP_HDMI_APB>, 3580 <&topckgen CLK_TOP_HDCP>, 3581 <&topckgen CLK_TOP_HDCP_24M>, 3582 <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; 3583 clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split"; 3584 assigned-clocks = <&topckgen CLK_TOP_HDCP>; 3585 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4_D8>; 3586 interrupts = <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>; 3587 power-domains = <&spm MT8188_POWER_DOMAIN_HDMI_TX>; 3588 phys = <&hdmi_phy>; 3589 phy-names = "hdmi"; 3590 status = "disabled"; 3591 3592 hdmi_ddc: i2c { 3593 compatible = "mediatek,mt8188-hdmi-ddc", 3594 "mediatek,mt8195-hdmi-ddc"; 3595 clocks = <&clk26m>; 3596 }; 3597 3598 ports { 3599 #address-cells = <1>; 3600 #size-cells = <0>; 3601 3602 port@0 { 3603 reg = <0>; 3604 hdmi0_in: endpoint { }; 3605 }; 3606 3607 port@1 { 3608 reg = <1>; 3609 hdmi0_out: endpoint { }; 3610 }; 3611 }; 3612 }; 3613 3614 3615 edp_tx: edp-tx@1c500000 { 3616 compatible = "mediatek,mt8188-edp-tx"; 3617 reg = <0 0x1c500000 0 0x8000>; 3618 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 3619 nvmem-cells = <&dp_calib_data>; 3620 nvmem-cell-names = "dp_calibration_data"; 3621 power-domains = <&spm MT8188_POWER_DOMAIN_EDP_TX>; 3622 max-linkrate-mhz = <8100>; 3623 status = "disabled"; 3624 }; 3625 3626 dp_tx: dp-tx@1c600000 { 3627 compatible = "mediatek,mt8188-dp-tx"; 3628 reg = <0 0x1c600000 0 0x8000>; 3629 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 3630 nvmem-cells = <&dp_calib_data>; 3631 nvmem-cell-names = "dp_calibration_data"; 3632 power-domains = <&spm MT8188_POWER_DOMAIN_DP_TX>; 3633 max-linkrate-mhz = <5400>; 3634 status = "disabled"; 3635 }; 3636 }; 3637}; 3638