1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2023 MediaTek Inc. 4 * 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mediatek,mt8188-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/mailbox/mediatek,mt8188-gce.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> 14#include <dt-bindings/power/mediatek,mt8188-power.h> 15 16/ { 17 compatible = "mediatek,mt8188"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu0: cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a55"; 29 reg = <0x000>; 30 enable-method = "psci"; 31 clock-frequency = <2000000000>; 32 capacity-dmips-mhz = <282>; 33 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 34 i-cache-size = <32768>; 35 i-cache-line-size = <64>; 36 i-cache-sets = <128>; 37 d-cache-size = <32768>; 38 d-cache-line-size = <64>; 39 d-cache-sets = <128>; 40 next-level-cache = <&l2_0>; 41 #cooling-cells = <2>; 42 }; 43 44 cpu1: cpu@100 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a55"; 47 reg = <0x100>; 48 enable-method = "psci"; 49 clock-frequency = <2000000000>; 50 capacity-dmips-mhz = <282>; 51 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 52 i-cache-size = <32768>; 53 i-cache-line-size = <64>; 54 i-cache-sets = <128>; 55 d-cache-size = <32768>; 56 d-cache-line-size = <64>; 57 d-cache-sets = <128>; 58 next-level-cache = <&l2_0>; 59 #cooling-cells = <2>; 60 }; 61 62 cpu2: cpu@200 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a55"; 65 reg = <0x200>; 66 enable-method = "psci"; 67 clock-frequency = <2000000000>; 68 capacity-dmips-mhz = <282>; 69 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 70 i-cache-size = <32768>; 71 i-cache-line-size = <64>; 72 i-cache-sets = <128>; 73 d-cache-size = <32768>; 74 d-cache-line-size = <64>; 75 d-cache-sets = <128>; 76 next-level-cache = <&l2_0>; 77 #cooling-cells = <2>; 78 }; 79 80 cpu3: cpu@300 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x300>; 84 enable-method = "psci"; 85 clock-frequency = <2000000000>; 86 capacity-dmips-mhz = <282>; 87 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 88 i-cache-size = <32768>; 89 i-cache-line-size = <64>; 90 i-cache-sets = <128>; 91 d-cache-size = <32768>; 92 d-cache-line-size = <64>; 93 d-cache-sets = <128>; 94 next-level-cache = <&l2_0>; 95 #cooling-cells = <2>; 96 }; 97 98 cpu4: cpu@400 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a55"; 101 reg = <0x400>; 102 enable-method = "psci"; 103 clock-frequency = <2000000000>; 104 capacity-dmips-mhz = <282>; 105 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 106 i-cache-size = <32768>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <128>; 109 d-cache-size = <32768>; 110 d-cache-line-size = <64>; 111 d-cache-sets = <128>; 112 next-level-cache = <&l2_0>; 113 #cooling-cells = <2>; 114 }; 115 116 cpu5: cpu@500 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a55"; 119 reg = <0x500>; 120 enable-method = "psci"; 121 clock-frequency = <2000000000>; 122 capacity-dmips-mhz = <282>; 123 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 124 i-cache-size = <32768>; 125 i-cache-line-size = <64>; 126 i-cache-sets = <128>; 127 d-cache-size = <32768>; 128 d-cache-line-size = <64>; 129 d-cache-sets = <128>; 130 next-level-cache = <&l2_0>; 131 #cooling-cells = <2>; 132 }; 133 134 cpu6: cpu@600 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a78"; 137 reg = <0x600>; 138 enable-method = "psci"; 139 clock-frequency = <2600000000>; 140 capacity-dmips-mhz = <1024>; 141 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 142 i-cache-size = <65536>; 143 i-cache-line-size = <64>; 144 i-cache-sets = <256>; 145 d-cache-size = <65536>; 146 d-cache-line-size = <64>; 147 d-cache-sets = <256>; 148 next-level-cache = <&l2_1>; 149 #cooling-cells = <2>; 150 }; 151 152 cpu7: cpu@700 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a78"; 155 reg = <0x700>; 156 enable-method = "psci"; 157 clock-frequency = <2600000000>; 158 capacity-dmips-mhz = <1024>; 159 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 160 i-cache-size = <65536>; 161 i-cache-line-size = <64>; 162 i-cache-sets = <256>; 163 d-cache-size = <65536>; 164 d-cache-line-size = <64>; 165 d-cache-sets = <256>; 166 next-level-cache = <&l2_1>; 167 #cooling-cells = <2>; 168 }; 169 170 cpu-map { 171 cluster0 { 172 core0 { 173 cpu = <&cpu0>; 174 }; 175 176 core1 { 177 cpu = <&cpu1>; 178 }; 179 180 core2 { 181 cpu = <&cpu2>; 182 }; 183 184 core3 { 185 cpu = <&cpu3>; 186 }; 187 188 core4 { 189 cpu = <&cpu4>; 190 }; 191 192 core5 { 193 cpu = <&cpu5>; 194 }; 195 196 core6 { 197 cpu = <&cpu6>; 198 }; 199 200 core7 { 201 cpu = <&cpu7>; 202 }; 203 }; 204 }; 205 206 idle-states { 207 entry-method = "psci"; 208 209 cpu_off_l: cpu-off-l { 210 compatible = "arm,idle-state"; 211 arm,psci-suspend-param = <0x00010000>; 212 local-timer-stop; 213 entry-latency-us = <50>; 214 exit-latency-us = <95>; 215 min-residency-us = <580>; 216 }; 217 218 cpu_off_b: cpu-off-b { 219 compatible = "arm,idle-state"; 220 arm,psci-suspend-param = <0x00010000>; 221 local-timer-stop; 222 entry-latency-us = <45>; 223 exit-latency-us = <140>; 224 min-residency-us = <740>; 225 }; 226 227 cluster_off_l: cluster-off-l { 228 compatible = "arm,idle-state"; 229 arm,psci-suspend-param = <0x01010010>; 230 local-timer-stop; 231 entry-latency-us = <55>; 232 exit-latency-us = <155>; 233 min-residency-us = <840>; 234 }; 235 236 cluster_off_b: cluster-off-b { 237 compatible = "arm,idle-state"; 238 arm,psci-suspend-param = <0x01010010>; 239 local-timer-stop; 240 entry-latency-us = <50>; 241 exit-latency-us = <200>; 242 min-residency-us = <1000>; 243 }; 244 }; 245 246 l2_0: l2-cache0 { 247 compatible = "cache"; 248 cache-level = <2>; 249 cache-size = <131072>; 250 cache-line-size = <64>; 251 cache-sets = <512>; 252 next-level-cache = <&l3_0>; 253 cache-unified; 254 }; 255 256 l2_1: l2-cache1 { 257 compatible = "cache"; 258 cache-level = <2>; 259 cache-size = <262144>; 260 cache-line-size = <64>; 261 cache-sets = <512>; 262 next-level-cache = <&l3_0>; 263 cache-unified; 264 }; 265 266 l3_0: l3-cache { 267 compatible = "cache"; 268 cache-level = <3>; 269 cache-size = <2097152>; 270 cache-line-size = <64>; 271 cache-sets = <2048>; 272 cache-unified; 273 }; 274 }; 275 276 clk13m: oscillator-13m { 277 compatible = "fixed-clock"; 278 #clock-cells = <0>; 279 clock-frequency = <13000000>; 280 clock-output-names = "clk13m"; 281 }; 282 283 clk26m: oscillator-26m { 284 compatible = "fixed-clock"; 285 #clock-cells = <0>; 286 clock-frequency = <26000000>; 287 clock-output-names = "clk26m"; 288 }; 289 290 clk32k: oscillator-32k { 291 compatible = "fixed-clock"; 292 #clock-cells = <0>; 293 clock-frequency = <32768>; 294 clock-output-names = "clk32k"; 295 }; 296 297 gpu_opp_table: opp-table-gpu { 298 compatible = "operating-points-v2"; 299 opp-shared; 300 301 opp-390000000 { 302 opp-hz = /bits/ 64 <390000000>; 303 opp-microvolt = <575000>; 304 opp-supported-hw = <0xff>; 305 }; 306 opp-431000000 { 307 opp-hz = /bits/ 64 <431000000>; 308 opp-microvolt = <587500>; 309 opp-supported-hw = <0xff>; 310 }; 311 opp-473000000 { 312 opp-hz = /bits/ 64 <473000000>; 313 opp-microvolt = <600000>; 314 opp-supported-hw = <0xff>; 315 }; 316 opp-515000000 { 317 opp-hz = /bits/ 64 <515000000>; 318 opp-microvolt = <612500>; 319 opp-supported-hw = <0xff>; 320 }; 321 opp-556000000 { 322 opp-hz = /bits/ 64 <556000000>; 323 opp-microvolt = <625000>; 324 opp-supported-hw = <0xff>; 325 }; 326 opp-598000000 { 327 opp-hz = /bits/ 64 <598000000>; 328 opp-microvolt = <637500>; 329 opp-supported-hw = <0xff>; 330 }; 331 opp-640000000 { 332 opp-hz = /bits/ 64 <640000000>; 333 opp-microvolt = <650000>; 334 opp-supported-hw = <0xff>; 335 }; 336 opp-670000000 { 337 opp-hz = /bits/ 64 <670000000>; 338 opp-microvolt = <662500>; 339 opp-supported-hw = <0xff>; 340 }; 341 opp-700000000 { 342 opp-hz = /bits/ 64 <700000000>; 343 opp-microvolt = <675000>; 344 opp-supported-hw = <0xff>; 345 }; 346 opp-730000000 { 347 opp-hz = /bits/ 64 <730000000>; 348 opp-microvolt = <687500>; 349 opp-supported-hw = <0xff>; 350 }; 351 opp-760000000 { 352 opp-hz = /bits/ 64 <760000000>; 353 opp-microvolt = <700000>; 354 opp-supported-hw = <0xff>; 355 }; 356 opp-790000000 { 357 opp-hz = /bits/ 64 <790000000>; 358 opp-microvolt = <712500>; 359 opp-supported-hw = <0xff>; 360 }; 361 opp-835000000 { 362 opp-hz = /bits/ 64 <835000000>; 363 opp-microvolt = <731250>; 364 opp-supported-hw = <0xff>; 365 }; 366 opp-880000000 { 367 opp-hz = /bits/ 64 <880000000>; 368 opp-microvolt = <750000>; 369 opp-supported-hw = <0xff>; 370 }; 371 opp-915000000 { 372 opp-hz = /bits/ 64 <915000000>; 373 opp-microvolt = <775000>; 374 opp-supported-hw = <0x8f>; 375 }; 376 opp-915000000-5 { 377 opp-hz = /bits/ 64 <915000000>; 378 opp-microvolt = <762500>; 379 opp-supported-hw = <0x30>; 380 }; 381 opp-915000000-6 { 382 opp-hz = /bits/ 64 <915000000>; 383 opp-microvolt = <750000>; 384 opp-supported-hw = <0x70>; 385 }; 386 opp-950000000 { 387 opp-hz = /bits/ 64 <950000000>; 388 opp-microvolt = <800000>; 389 opp-supported-hw = <0x8f>; 390 }; 391 opp-950000000-5 { 392 opp-hz = /bits/ 64 <950000000>; 393 opp-microvolt = <775000>; 394 opp-supported-hw = <0x30>; 395 }; 396 opp-950000000-6 { 397 opp-hz = /bits/ 64 <950000000>; 398 opp-microvolt = <750000>; 399 opp-supported-hw = <0x70>; 400 }; 401 }; 402 403 pmu-a55 { 404 compatible = "arm,cortex-a55-pmu"; 405 interrupt-parent = <&gic>; 406 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 407 }; 408 409 pmu-a78 { 410 compatible = "arm,cortex-a78-pmu"; 411 interrupt-parent = <&gic>; 412 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 413 }; 414 415 psci { 416 compatible = "arm,psci-1.0"; 417 method = "smc"; 418 }; 419 420 timer: timer { 421 compatible = "arm,armv8-timer"; 422 interrupt-parent = <&gic>; 423 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 424 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 425 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 426 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 427 clock-frequency = <13000000>; 428 }; 429 430 soc { 431 #address-cells = <2>; 432 #size-cells = <2>; 433 compatible = "simple-bus"; 434 ranges; 435 436 gic: interrupt-controller@c000000 { 437 compatible = "arm,gic-v3"; 438 #interrupt-cells = <4>; 439 #redistributor-regions = <1>; 440 interrupt-parent = <&gic>; 441 interrupt-controller; 442 reg = <0 0x0c000000 0 0x40000>, 443 <0 0x0c040000 0 0x200000>; 444 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 445 446 ppi-partitions { 447 ppi_cluster0: interrupt-partition-0 { 448 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 449 }; 450 451 ppi_cluster1: interrupt-partition-1 { 452 affinity = <&cpu6 &cpu7>; 453 }; 454 }; 455 }; 456 457 topckgen: syscon@10000000 { 458 compatible = "mediatek,mt8188-topckgen", "syscon"; 459 reg = <0 0x10000000 0 0x1000>; 460 #clock-cells = <1>; 461 }; 462 463 infracfg_ao: syscon@10001000 { 464 compatible = "mediatek,mt8188-infracfg-ao", "syscon"; 465 reg = <0 0x10001000 0 0x1000>; 466 #clock-cells = <1>; 467 }; 468 469 pericfg: syscon@10003000 { 470 compatible = "mediatek,mt8188-pericfg", "syscon"; 471 reg = <0 0x10003000 0 0x1000>; 472 #clock-cells = <1>; 473 }; 474 475 pio: pinctrl@10005000 { 476 compatible = "mediatek,mt8188-pinctrl"; 477 reg = <0 0x10005000 0 0x1000>, 478 <0 0x11c00000 0 0x1000>, 479 <0 0x11e10000 0 0x1000>, 480 <0 0x11e20000 0 0x1000>, 481 <0 0x11ea0000 0 0x1000>, 482 <0 0x1000b000 0 0x1000>; 483 reg-names = "iocfg0", "iocfg_rm", "iocfg_lt", 484 "iocfg_lm", "iocfg_rt", "eint"; 485 gpio-controller; 486 #gpio-cells = <2>; 487 gpio-ranges = <&pio 0 0 176>; 488 interrupt-controller; 489 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 490 #interrupt-cells = <2>; 491 }; 492 493 scpsys: syscon@10006000 { 494 compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd"; 495 reg = <0 0x10006000 0 0x1000>; 496 497 /* System Power Manager */ 498 spm: power-controller { 499 compatible = "mediatek,mt8188-power-controller"; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 #power-domain-cells = <1>; 503 504 /* power domain of the SoC */ 505 mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 { 506 reg = <MT8188_POWER_DOMAIN_MFG0>; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 #power-domain-cells = <1>; 510 511 power-domain@MT8188_POWER_DOMAIN_MFG1 { 512 reg = <MT8188_POWER_DOMAIN_MFG1>; 513 clocks = <&topckgen CLK_APMIXED_MFGPLL>, 514 <&topckgen CLK_TOP_MFG_CORE_TMP>; 515 clock-names = "mfg", "alt"; 516 mediatek,infracfg = <&infracfg_ao>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 #power-domain-cells = <1>; 520 521 power-domain@MT8188_POWER_DOMAIN_MFG2 { 522 reg = <MT8188_POWER_DOMAIN_MFG2>; 523 #power-domain-cells = <0>; 524 }; 525 526 power-domain@MT8188_POWER_DOMAIN_MFG3 { 527 reg = <MT8188_POWER_DOMAIN_MFG3>; 528 #power-domain-cells = <0>; 529 }; 530 531 power-domain@MT8188_POWER_DOMAIN_MFG4 { 532 reg = <MT8188_POWER_DOMAIN_MFG4>; 533 #power-domain-cells = <0>; 534 }; 535 }; 536 }; 537 538 power-domain@MT8188_POWER_DOMAIN_VPPSYS0 { 539 reg = <MT8188_POWER_DOMAIN_VPPSYS0>; 540 clocks = <&topckgen CLK_TOP_VPP>, 541 <&topckgen CLK_TOP_CAM>, 542 <&topckgen CLK_TOP_CCU>, 543 <&topckgen CLK_TOP_IMG>, 544 <&topckgen CLK_TOP_VENC>, 545 <&topckgen CLK_TOP_VDEC>, 546 <&topckgen CLK_TOP_WPE_VPP>, 547 <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>, 548 <&topckgen CLK_TOP_CFGREG_F26M_VPP0>, 549 <&vppsys0 CLK_VPP0_SMI_COMMON_MMSRAM>, 550 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0_MMSRAM>, 551 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1_MMSRAM>, 552 <&vppsys0 CLK_VPP0_GALS_VENCSYS_MMSRAM>, 553 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM>, 554 <&vppsys0 CLK_VPP0_GALS_INFRA_MMSRAM>, 555 <&vppsys0 CLK_VPP0_GALS_CAMSYS_MMSRAM>, 556 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5_MMSRAM>, 557 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6_MMSRAM>, 558 <&vppsys0 CLK_VPP0_SMI_REORDER_MMSRAM>, 559 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 560 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 561 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 562 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 563 <&vppsys0 CLK_VPP0_SMI_RSI>, 564 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 565 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 566 <&vppsys0 CLK_VPP0_GALS_VPP1_WPESYS>, 567 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 568 clock-names = "top", "cam", "ccu", "img", "venc", 569 "vdec", "wpe", "cfgck", "cfgxo", 570 "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1", 571 "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa", 572 "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6", 573 "ss-sram-rdr", "ss-iommu", "ss-imgcam", 574 "ss-emi", "ss-subcmn-rdr", "ss-rsi", 575 "ss-cmn-l4", "ss-vdec1", "ss-wpe", 576 "ss-cvdo-ve1"; 577 mediatek,infracfg = <&infracfg_ao>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 #power-domain-cells = <1>; 581 582 power-domain@MT8188_POWER_DOMAIN_VDOSYS0 { 583 reg = <MT8188_POWER_DOMAIN_VDOSYS0>; 584 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0>, 585 <&topckgen CLK_TOP_CFGREG_F26M_VDO0>, 586 <&vdosys0 CLK_VDO0_SMI_GALS>, 587 <&vdosys0 CLK_VDO0_SMI_COMMON>, 588 <&vdosys0 CLK_VDO0_SMI_EMI>, 589 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 590 <&vdosys0 CLK_VDO0_SMI_LARB>, 591 <&vdosys0 CLK_VDO0_SMI_RSI>, 592 <&vdosys0 CLK_VDO0_APB_BUS>; 593 clock-names = "cfgck", "cfgxo", "ss-gals", 594 "ss-cmn", "ss-emi", "ss-iommu", 595 "ss-larb", "ss-rsi", "ss-bus"; 596 mediatek,infracfg = <&infracfg_ao>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 #power-domain-cells = <1>; 600 601 power-domain@MT8188_POWER_DOMAIN_VPPSYS1 { 602 reg = <MT8188_POWER_DOMAIN_VPPSYS1>; 603 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>, 604 <&topckgen CLK_TOP_CFGREG_F26M_VPP1>, 605 <&vppsys1 CLK_VPP1_GALS5>, 606 <&vppsys1 CLK_VPP1_GALS6>, 607 <&vppsys1 CLK_VPP1_LARB5>, 608 <&vppsys1 CLK_VPP1_LARB6>; 609 clock-names = "cfgck", "cfgxo", 610 "ss-vpp1-g5", "ss-vpp1-g6", 611 "ss-vpp1-l5", "ss-vpp1-l6"; 612 mediatek,infracfg = <&infracfg_ao>; 613 #power-domain-cells = <0>; 614 }; 615 616 power-domain@MT8188_POWER_DOMAIN_VDEC1 { 617 reg = <MT8188_POWER_DOMAIN_VDEC1>; 618 clocks = <&vdecsys CLK_VDEC2_LARB1>; 619 clock-names = "ss-vdec"; 620 mediatek,infracfg = <&infracfg_ao>; 621 #power-domain-cells = <0>; 622 }; 623 624 power-domain@MT8188_POWER_DOMAIN_VDEC0 { 625 reg = <MT8188_POWER_DOMAIN_VDEC0>; 626 clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; 627 clock-names = "ss-vdec"; 628 mediatek,infracfg = <&infracfg_ao>; 629 #power-domain-cells = <0>; 630 }; 631 632 cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE { 633 reg = <MT8188_POWER_DOMAIN_CAM_VCORE>; 634 clocks = <&topckgen CLK_TOP_CAM>, 635 <&topckgen CLK_TOP_CCU>, 636 <&topckgen CLK_TOP_CCU_AHB>, 637 <&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>; 638 clock-names = "cam", "ccu", "bus", "cfgck"; 639 mediatek,infracfg = <&infracfg_ao>; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 #power-domain-cells = <1>; 643 644 power-domain@MT8188_POWER_DOMAIN_CAM_MAIN { 645 reg = <MT8188_POWER_DOMAIN_CAM_MAIN>; 646 clocks = <&camsys CLK_CAM_MAIN_LARB13>, 647 <&camsys CLK_CAM_MAIN_LARB14>, 648 <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>, 649 <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>, 650 <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>; 651 clock-names= "ss-cam-l13", "ss-cam-l14", 652 "ss-cam-mm0", "ss-cam-mm1", 653 "ss-camsys"; 654 mediatek,infracfg = <&infracfg_ao>; 655 #address-cells = <1>; 656 #size-cells = <0>; 657 #power-domain-cells = <1>; 658 659 power-domain@MT8188_POWER_DOMAIN_CAM_SUBB { 660 reg = <MT8188_POWER_DOMAIN_CAM_SUBB>; 661 clocks = <&camsys CLK_CAM_MAIN_CAM_SUBB>, 662 <&camsys_rawb CLK_CAM_RAWB_LARBX>, 663 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 664 clock-names = "ss-camb-sub", 665 "ss-camb-raw", 666 "ss-camb-yuv"; 667 #power-domain-cells = <0>; 668 }; 669 670 power-domain@MT8188_POWER_DOMAIN_CAM_SUBA { 671 reg =<MT8188_POWER_DOMAIN_CAM_SUBA>; 672 clocks = <&camsys CLK_CAM_MAIN_CAM_SUBA>, 673 <&camsys_rawa CLK_CAM_RAWA_LARBX>, 674 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 675 clock-names = "ss-cama-sub", 676 "ss-cama-raw", 677 "ss-cama-yuv"; 678 #power-domain-cells = <0>; 679 }; 680 }; 681 }; 682 683 power-domain@MT8188_POWER_DOMAIN_VDOSYS1 { 684 reg = <MT8188_POWER_DOMAIN_VDOSYS1>; 685 clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1>, 686 <&topckgen CLK_TOP_CFGREG_F26M_VDO1>, 687 <&vdosys1 CLK_VDO1_SMI_LARB2>, 688 <&vdosys1 CLK_VDO1_SMI_LARB3>, 689 <&vdosys1 CLK_VDO1_GALS>; 690 clock-names = "cfgck", "cfgxo", "ss-larb2", 691 "ss-larb3", "ss-gals"; 692 mediatek,infracfg = <&infracfg_ao>; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 #power-domain-cells = <1>; 696 697 power-domain@MT8188_POWER_DOMAIN_HDMI_TX { 698 reg = <MT8188_POWER_DOMAIN_HDMI_TX>; 699 clocks = <&topckgen CLK_TOP_HDMI_APB>, 700 <&topckgen CLK_TOP_HDCP_24M>; 701 clock-names = "bus", "hdcp"; 702 mediatek,infracfg = <&infracfg_ao>; 703 #power-domain-cells = <0>; 704 }; 705 706 power-domain@MT8188_POWER_DOMAIN_DP_TX { 707 reg = <MT8188_POWER_DOMAIN_DP_TX>; 708 mediatek,infracfg = <&infracfg_ao>; 709 #power-domain-cells = <0>; 710 }; 711 712 power-domain@MT8188_POWER_DOMAIN_EDP_TX { 713 reg = <MT8188_POWER_DOMAIN_EDP_TX>; 714 mediatek,infracfg = <&infracfg_ao>; 715 #power-domain-cells = <0>; 716 }; 717 }; 718 719 power-domain@MT8188_POWER_DOMAIN_VENC { 720 reg = <MT8188_POWER_DOMAIN_VENC>; 721 clocks = <&vencsys CLK_VENC1_LARB>, 722 <&vencsys CLK_VENC1_VENC>, 723 <&vencsys CLK_VENC1_GALS>, 724 <&vencsys CLK_VENC1_GALS_SRAM>; 725 clock-names = "ss-ve1-larb", "ss-ve1-core", 726 "ss-ve1-gals", "ss-ve1-sram"; 727 mediatek,infracfg = <&infracfg_ao>; 728 #power-domain-cells = <0>; 729 }; 730 731 power-domain@MT8188_POWER_DOMAIN_WPE { 732 reg = <MT8188_POWER_DOMAIN_WPE>; 733 clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>, 734 <&wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN>; 735 clock-names = "ss-wpe-l7", "ss-wpe-l7pce"; 736 mediatek,infracfg = <&infracfg_ao>; 737 #power-domain-cells = <0>; 738 }; 739 }; 740 }; 741 742 power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 { 743 reg = <MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; 744 mediatek,infracfg = <&infracfg_ao>; 745 clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; 746 clock-names = "ss-pextp-fmem"; 747 #power-domain-cells = <0>; 748 }; 749 750 power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP { 751 reg = <MT8188_POWER_DOMAIN_CSIRX_TOP>; 752 clocks = <&topckgen CLK_TOP_SENINF>, 753 <&topckgen CLK_TOP_SENINF1>; 754 clock-names = "seninf0", "seninf1"; 755 #power-domain-cells = <0>; 756 }; 757 758 power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP { 759 reg = <MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>; 760 #power-domain-cells = <0>; 761 }; 762 763 power-domain@MT8188_POWER_DOMAIN_ADSP_AO { 764 reg = <MT8188_POWER_DOMAIN_ADSP_AO>; 765 clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 766 <&topckgen CLK_TOP_ADSP>; 767 clock-names = "bus", "main"; 768 mediatek,infracfg = <&infracfg_ao>; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 #power-domain-cells = <1>; 772 773 power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA { 774 reg = <MT8188_POWER_DOMAIN_ADSP_INFRA>; 775 mediatek,infracfg = <&infracfg_ao>; 776 #address-cells = <1>; 777 #size-cells = <0>; 778 #power-domain-cells = <1>; 779 780 power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC { 781 reg = <MT8188_POWER_DOMAIN_AUDIO_ASRC>; 782 clocks = <&topckgen CLK_TOP_ASM_H>; 783 clock-names = "asm"; 784 mediatek,infracfg = <&infracfg_ao>; 785 #power-domain-cells = <0>; 786 }; 787 788 power-domain@MT8188_POWER_DOMAIN_AUDIO { 789 reg = <MT8188_POWER_DOMAIN_AUDIO>; 790 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 791 <&topckgen CLK_TOP_AUD_INTBUS>, 792 <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>; 793 clock-names = "a1sys", "intbus", "adspck"; 794 mediatek,infracfg = <&infracfg_ao>; 795 #power-domain-cells = <0>; 796 }; 797 798 power-domain@MT8188_POWER_DOMAIN_ADSP { 799 reg = <MT8188_POWER_DOMAIN_ADSP>; 800 mediatek,infracfg = <&infracfg_ao>; 801 #power-domain-cells = <0>; 802 }; 803 }; 804 }; 805 806 power-domain@MT8188_POWER_DOMAIN_ETHER { 807 reg = <MT8188_POWER_DOMAIN_ETHER>; 808 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 809 clock-names = "ethermac"; 810 mediatek,infracfg = <&infracfg_ao>; 811 #power-domain-cells = <0>; 812 }; 813 }; 814 }; 815 816 watchdog: watchdog@10007000 { 817 compatible = "mediatek,mt8188-wdt"; 818 reg = <0 0x10007000 0 0x100>; 819 mediatek,disable-extrst; 820 #reset-cells = <1>; 821 }; 822 823 apmixedsys: syscon@1000c000 { 824 compatible = "mediatek,mt8188-apmixedsys", "syscon"; 825 reg = <0 0x1000c000 0 0x1000>; 826 #clock-cells = <1>; 827 }; 828 829 systimer: timer@10017000 { 830 compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer"; 831 reg = <0 0x10017000 0 0x1000>; 832 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 833 clocks = <&clk13m>; 834 }; 835 836 pwrap: pwrap@10024000 { 837 compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon"; 838 reg = <0 0x10024000 0 0x1000>; 839 reg-names = "pwrap"; 840 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 841 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 842 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 843 clock-names = "spi", "wrap"; 844 }; 845 846 gce0: mailbox@10320000 { 847 compatible = "mediatek,mt8188-gce"; 848 reg = <0 0x10320000 0 0x4000>; 849 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 850 #mbox-cells = <2>; 851 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 852 }; 853 854 gce1: mailbox@10330000 { 855 compatible = "mediatek,mt8188-gce"; 856 reg = <0 0x10330000 0 0x4000>; 857 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 858 #mbox-cells = <2>; 859 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 860 }; 861 862 scp: scp@10500000 { 863 compatible = "mediatek,mt8188-scp"; 864 reg = <0 0x10500000 0 0x100000>, 865 <0 0x10720000 0 0xe0000>; 866 reg-names = "sram", "cfg"; 867 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 868 }; 869 870 adsp_audio26m: clock-controller@10b91100 { 871 compatible = "mediatek,mt8188-adsp-audio26m"; 872 reg = <0 0x10b91100 0 0x100>; 873 #clock-cells = <1>; 874 }; 875 876 uart0: serial@11001100 { 877 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 878 reg = <0 0x11001100 0 0x100>; 879 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 880 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 881 clock-names = "baud", "bus"; 882 status = "disabled"; 883 }; 884 885 uart1: serial@11001200 { 886 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 887 reg = <0 0x11001200 0 0x100>; 888 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 889 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 890 clock-names = "baud", "bus"; 891 status = "disabled"; 892 }; 893 894 uart2: serial@11001300 { 895 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 896 reg = <0 0x11001300 0 0x100>; 897 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 898 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 899 clock-names = "baud", "bus"; 900 status = "disabled"; 901 }; 902 903 uart3: serial@11001400 { 904 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 905 reg = <0 0x11001400 0 0x100>; 906 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 907 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 908 clock-names = "baud", "bus"; 909 status = "disabled"; 910 }; 911 912 auxadc: adc@11002000 { 913 compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc"; 914 reg = <0 0x11002000 0 0x1000>; 915 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 916 clock-names = "main"; 917 #io-channel-cells = <1>; 918 status = "disabled"; 919 }; 920 921 pericfg_ao: syscon@11003000 { 922 compatible = "mediatek,mt8188-pericfg-ao", "syscon"; 923 reg = <0 0x11003000 0 0x1000>; 924 #clock-cells = <1>; 925 }; 926 927 spi0: spi@1100a000 { 928 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 reg = <0 0x1100a000 0 0x1000>; 932 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 933 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 934 <&topckgen CLK_TOP_SPI>, 935 <&infracfg_ao CLK_INFRA_AO_SPI0>; 936 clock-names = "parent-clk", "sel-clk", "spi-clk"; 937 status = "disabled"; 938 }; 939 940 spi1: spi@11010000 { 941 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 942 #address-cells = <1>; 943 #size-cells = <0>; 944 reg = <0 0x11010000 0 0x1000>; 945 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 946 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 947 <&topckgen CLK_TOP_SPI>, 948 <&infracfg_ao CLK_INFRA_AO_SPI1>; 949 clock-names = "parent-clk", "sel-clk", "spi-clk"; 950 status = "disabled"; 951 }; 952 953 spi2: spi@11012000 { 954 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 reg = <0 0x11012000 0 0x1000>; 958 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 959 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 960 <&topckgen CLK_TOP_SPI>, 961 <&infracfg_ao CLK_INFRA_AO_SPI2>; 962 clock-names = "parent-clk", "sel-clk", "spi-clk"; 963 status = "disabled"; 964 }; 965 966 spi3: spi@11013000 { 967 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 reg = <0 0x11013000 0 0x1000>; 971 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 972 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 973 <&topckgen CLK_TOP_SPI>, 974 <&infracfg_ao CLK_INFRA_AO_SPI3>; 975 clock-names = "parent-clk", "sel-clk", "spi-clk"; 976 status = "disabled"; 977 }; 978 979 spi4: spi@11018000 { 980 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 reg = <0 0x11018000 0 0x1000>; 984 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 985 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 986 <&topckgen CLK_TOP_SPI>, 987 <&infracfg_ao CLK_INFRA_AO_SPI4>; 988 clock-names = "parent-clk", "sel-clk", "spi-clk"; 989 status = "disabled"; 990 }; 991 992 spi5: spi@11019000 { 993 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 reg = <0 0x11019000 0 0x1000>; 997 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 998 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 999 <&topckgen CLK_TOP_SPI>, 1000 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1001 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1002 status = "disabled"; 1003 }; 1004 1005 xhci1: usb@11200000 { 1006 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 1007 reg = <0 0x11200000 0 0x1000>, 1008 <0 0x11203e00 0 0x0100>; 1009 reg-names = "mac", "ippc"; 1010 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1011 phys = <&u2port1 PHY_TYPE_USB2>, 1012 <&u3port1 PHY_TYPE_USB3>; 1013 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1014 <&topckgen CLK_TOP_SSUSB_XHCI>; 1015 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1016 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1017 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>, 1018 <&topckgen CLK_TOP_SSUSB_TOP_REF>, 1019 <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; 1020 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1021 mediatek,syscon-wakeup = <&pericfg 0x468 2>; 1022 wakeup-source; 1023 status = "disabled"; 1024 }; 1025 1026 mmc0: mmc@11230000 { 1027 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 1028 reg = <0 0x11230000 0 0x10000>, 1029 <0 0x11f50000 0 0x1000>; 1030 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1031 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1032 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1033 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1034 <&infracfg_ao CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P>; 1035 clock-names = "source", "hclk", "source_cg", "crypto_clk"; 1036 status = "disabled"; 1037 }; 1038 1039 mmc1: mmc@11240000 { 1040 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 1041 reg = <0 0x11240000 0 0x1000>, 1042 <0 0x11eb0000 0 0x1000>; 1043 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1044 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1045 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1046 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1047 clock-names = "source", "hclk", "source_cg"; 1048 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1049 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1050 status = "disabled"; 1051 }; 1052 1053 i2c0: i2c@11280000 { 1054 compatible = "mediatek,mt8188-i2c"; 1055 reg = <0 0x11280000 0 0x1000>, 1056 <0 0x10220080 0 0x80>; 1057 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>; 1058 clock-div = <1>; 1059 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0>, 1060 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1061 clock-names = "main", "dma"; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 status = "disabled"; 1065 }; 1066 1067 i2c2: i2c@11281000 { 1068 compatible = "mediatek,mt8188-i2c"; 1069 reg = <0 0x11281000 0 0x1000>, 1070 <0 0x10220180 0 0x80>; 1071 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 1072 clock-div = <1>; 1073 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2>, 1074 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1075 clock-names = "main", "dma"; 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 status = "disabled"; 1079 }; 1080 1081 i2c3: i2c@11282000 { 1082 compatible = "mediatek,mt8188-i2c"; 1083 reg = <0 0x11282000 0 0x1000>, 1084 <0 0x10220280 0 0x80>; 1085 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1086 clock-div = <1>; 1087 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3>, 1088 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1089 clock-names = "main", "dma"; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 1095 imp_iic_wrap_c: clock-controller@11283000 { 1096 compatible = "mediatek,mt8188-imp-iic-wrap-c"; 1097 reg = <0 0x11283000 0 0x1000>; 1098 #clock-cells = <1>; 1099 }; 1100 1101 xhci2: usb@112a0000 { 1102 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 1103 reg = <0 0x112a0000 0 0x1000>, 1104 <0 0x112a3e00 0 0x0100>; 1105 reg-names = "mac", "ippc"; 1106 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1107 phys = <&u2port2 PHY_TYPE_USB2>; 1108 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>, 1109 <&topckgen CLK_TOP_USB_TOP_3P>; 1110 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1111 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1112 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1113 <&topckgen CLK_TOP_SSUSB_TOP_P3_REF>, 1114 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1115 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1116 status = "disabled"; 1117 }; 1118 1119 xhci0: usb@112b0000 { 1120 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 1121 reg = <0 0x112b0000 0 0x1000>, 1122 <0 0x112b3e00 0 0x0100>; 1123 reg-names = "mac", "ippc"; 1124 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1125 phys = <&u2port0 PHY_TYPE_USB2>; 1126 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>, 1127 <&topckgen CLK_TOP_USB_TOP_2P>; 1128 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1129 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1130 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1131 <&topckgen CLK_TOP_SSUSB_TOP_P2_REF>, 1132 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1133 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1134 mediatek,syscon-wakeup = <&pericfg 0x460 2>; 1135 wakeup-source; 1136 status = "disabled"; 1137 }; 1138 1139 nor_flash: spi@1132c000 { 1140 compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor"; 1141 reg = <0 0x1132c000 0 0x1000>; 1142 clocks = <&topckgen CLK_TOP_SPINOR>, 1143 <&pericfg_ao CLK_PERI_AO_FLASHIFLASHCK>, 1144 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1145 clock-names = "spi", "sf", "axi"; 1146 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 1147 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1148 status = "disabled"; 1149 }; 1150 1151 i2c1: i2c@11e00000 { 1152 compatible = "mediatek,mt8188-i2c"; 1153 reg = <0 0x11e00000 0 0x1000>, 1154 <0 0x10220100 0 0x80>; 1155 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1156 clock-div = <1>; 1157 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1>, 1158 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1159 clock-names = "main", "dma"; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 status = "disabled"; 1163 }; 1164 1165 i2c4: i2c@11e01000 { 1166 compatible = "mediatek,mt8188-i2c"; 1167 reg = <0 0x11e01000 0 0x1000>, 1168 <0 0x10220380 0 0x80>; 1169 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>; 1170 clock-div = <1>; 1171 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4>, 1172 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1173 clock-names = "main", "dma"; 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 status = "disabled"; 1177 }; 1178 1179 imp_iic_wrap_w: clock-controller@11e02000 { 1180 compatible = "mediatek,mt8188-imp-iic-wrap-w"; 1181 reg = <0 0x11e02000 0 0x1000>; 1182 #clock-cells = <1>; 1183 }; 1184 1185 u3phy0: t-phy@11e30000 { 1186 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 1187 #address-cells = <1>; 1188 #size-cells = <1>; 1189 ranges = <0x0 0x0 0x11e30000 0x1000>; 1190 status = "disabled"; 1191 1192 u2port0: usb-phy@0 { 1193 reg = <0x0 0x700>; 1194 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>, 1195 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 1196 clock-names = "ref", "da_ref"; 1197 #phy-cells = <1>; 1198 }; 1199 }; 1200 1201 u3phy1: t-phy@11e40000 { 1202 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 1203 #address-cells = <1>; 1204 #size-cells = <1>; 1205 ranges = <0x0 0x0 0x11e40000 0x1000>; 1206 status = "disabled"; 1207 1208 u2port1: usb-phy@0 { 1209 reg = <0x0 0x700>; 1210 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1211 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 1212 clock-names = "ref", "da_ref"; 1213 #phy-cells = <1>; 1214 }; 1215 1216 u3port1: usb-phy@700 { 1217 reg = <0x700 0x700>; 1218 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>, 1219 <&clk26m>; 1220 clock-names = "ref", "da_ref"; 1221 #phy-cells = <1>; 1222 status = "disabled"; 1223 }; 1224 }; 1225 1226 u3phy2: t-phy@11e80000 { 1227 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 1228 #address-cells = <1>; 1229 #size-cells = <1>; 1230 ranges = <0x0 0x0 0x11e80000 0x1000>; 1231 status = "disabled"; 1232 1233 u2port2: usb-phy@0 { 1234 reg = <0x0 0x700>; 1235 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>, 1236 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 1237 clock-names = "ref", "da_ref"; 1238 #phy-cells = <1>; 1239 }; 1240 }; 1241 1242 i2c5: i2c@11ec0000 { 1243 compatible = "mediatek,mt8188-i2c"; 1244 reg = <0 0x11ec0000 0 0x1000>, 1245 <0 0x10220480 0 0x80>; 1246 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>; 1247 clock-div = <1>; 1248 clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5>, 1249 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1250 clock-names = "main", "dma"; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 status = "disabled"; 1254 }; 1255 1256 i2c6: i2c@11ec1000 { 1257 compatible = "mediatek,mt8188-i2c"; 1258 reg = <0 0x11ec1000 0 0x1000>, 1259 <0 0x10220600 0 0x80>; 1260 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1261 clock-div = <1>; 1262 clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6>, 1263 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 1264 clock-names = "main", "dma"; 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 status = "disabled"; 1268 }; 1269 1270 imp_iic_wrap_en: clock-controller@11ec2000 { 1271 compatible = "mediatek,mt8188-imp-iic-wrap-en"; 1272 reg = <0 0x11ec2000 0 0x1000>; 1273 #clock-cells = <1>; 1274 }; 1275 1276 gpu: gpu@13000000 { 1277 compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm"; 1278 reg = <0 0x13000000 0 0x4000>; 1279 1280 clocks = <&mfgcfg CLK_MFGCFG_BG3D>; 1281 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, 1282 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>, 1283 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>; 1284 interrupt-names = "job", "mmu", "gpu"; 1285 operating-points-v2 = <&gpu_opp_table>; 1286 power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>, 1287 <&spm MT8188_POWER_DOMAIN_MFG3>, 1288 <&spm MT8188_POWER_DOMAIN_MFG4>; 1289 power-domain-names = "core0", "core1", "core2"; 1290 status = "disabled"; 1291 }; 1292 1293 mfgcfg: clock-controller@13fbf000 { 1294 compatible = "mediatek,mt8188-mfgcfg"; 1295 reg = <0 0x13fbf000 0 0x1000>; 1296 #clock-cells = <1>; 1297 }; 1298 1299 vppsys0: clock-controller@14000000 { 1300 compatible = "mediatek,mt8188-vppsys0"; 1301 reg = <0 0x14000000 0 0x1000>; 1302 #clock-cells = <1>; 1303 }; 1304 1305 wpesys: clock-controller@14e00000 { 1306 compatible = "mediatek,mt8188-wpesys"; 1307 reg = <0 0x14e00000 0 0x1000>; 1308 #clock-cells = <1>; 1309 }; 1310 1311 wpesys_vpp0: clock-controller@14e02000 { 1312 compatible = "mediatek,mt8188-wpesys-vpp0"; 1313 reg = <0 0x14e02000 0 0x1000>; 1314 #clock-cells = <1>; 1315 }; 1316 1317 vppsys1: clock-controller@14f00000 { 1318 compatible = "mediatek,mt8188-vppsys1"; 1319 reg = <0 0x14f00000 0 0x1000>; 1320 #clock-cells = <1>; 1321 }; 1322 1323 imgsys: clock-controller@15000000 { 1324 compatible = "mediatek,mt8188-imgsys"; 1325 reg = <0 0x15000000 0 0x1000>; 1326 #clock-cells = <1>; 1327 }; 1328 1329 imgsys1_dip_top: clock-controller@15110000 { 1330 compatible = "mediatek,mt8188-imgsys1-dip-top"; 1331 reg = <0 0x15110000 0 0x1000>; 1332 #clock-cells = <1>; 1333 }; 1334 1335 imgsys1_dip_nr: clock-controller@15130000 { 1336 compatible = "mediatek,mt8188-imgsys1-dip-nr"; 1337 reg = <0 0x15130000 0 0x1000>; 1338 #clock-cells = <1>; 1339 }; 1340 1341 imgsys_wpe1: clock-controller@15220000 { 1342 compatible = "mediatek,mt8188-imgsys-wpe1"; 1343 reg = <0 0x15220000 0 0x1000>; 1344 #clock-cells = <1>; 1345 }; 1346 1347 ipesys: clock-controller@15330000 { 1348 compatible = "mediatek,mt8188-ipesys"; 1349 reg = <0 0x15330000 0 0x1000>; 1350 #clock-cells = <1>; 1351 }; 1352 1353 imgsys_wpe2: clock-controller@15520000 { 1354 compatible = "mediatek,mt8188-imgsys-wpe2"; 1355 reg = <0 0x15520000 0 0x1000>; 1356 #clock-cells = <1>; 1357 }; 1358 1359 imgsys_wpe3: clock-controller@15620000 { 1360 compatible = "mediatek,mt8188-imgsys-wpe3"; 1361 reg = <0 0x15620000 0 0x1000>; 1362 #clock-cells = <1>; 1363 }; 1364 1365 camsys: clock-controller@16000000 { 1366 compatible = "mediatek,mt8188-camsys"; 1367 reg = <0 0x16000000 0 0x1000>; 1368 #clock-cells = <1>; 1369 }; 1370 1371 camsys_rawa: clock-controller@1604f000 { 1372 compatible = "mediatek,mt8188-camsys-rawa"; 1373 reg = <0 0x1604f000 0 0x1000>; 1374 #clock-cells = <1>; 1375 }; 1376 1377 camsys_yuva: clock-controller@1606f000 { 1378 compatible = "mediatek,mt8188-camsys-yuva"; 1379 reg = <0 0x1606f000 0 0x1000>; 1380 #clock-cells = <1>; 1381 }; 1382 1383 camsys_rawb: clock-controller@1608f000 { 1384 compatible = "mediatek,mt8188-camsys-rawb"; 1385 reg = <0 0x1608f000 0 0x1000>; 1386 #clock-cells = <1>; 1387 }; 1388 1389 camsys_yuvb: clock-controller@160af000 { 1390 compatible = "mediatek,mt8188-camsys-yuvb"; 1391 reg = <0 0x160af000 0 0x1000>; 1392 #clock-cells = <1>; 1393 }; 1394 1395 ccusys: clock-controller@17200000 { 1396 compatible = "mediatek,mt8188-ccusys"; 1397 reg = <0 0x17200000 0 0x1000>; 1398 #clock-cells = <1>; 1399 }; 1400 1401 vdecsys_soc: clock-controller@1800f000 { 1402 compatible = "mediatek,mt8188-vdecsys-soc"; 1403 reg = <0 0x1800f000 0 0x1000>; 1404 #clock-cells = <1>; 1405 }; 1406 1407 vdecsys: clock-controller@1802f000 { 1408 compatible = "mediatek,mt8188-vdecsys"; 1409 reg = <0 0x1802f000 0 0x1000>; 1410 #clock-cells = <1>; 1411 }; 1412 1413 vencsys: clock-controller@1a000000 { 1414 compatible = "mediatek,mt8188-vencsys"; 1415 reg = <0 0x1a000000 0 0x1000>; 1416 #clock-cells = <1>; 1417 }; 1418 1419 vdosys0: syscon@1c01d000 { 1420 compatible = "mediatek,mt8188-vdosys0", "syscon"; 1421 reg = <0 0x1c01d000 0 0x1000>; 1422 #clock-cells = <1>; 1423 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 1424 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>; 1425 }; 1426 1427 vdosys1: syscon@1c100000 { 1428 compatible = "mediatek,mt8188-vdosys1", "syscon"; 1429 reg = <0 0x1c100000 0 0x1000>; 1430 #clock-cells = <1>; 1431 #reset-cells = <1>; 1432 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; 1433 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>; 1434 }; 1435 }; 1436}; 1437