1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2023 MediaTek Inc. 4 * 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mediatek,mt8188-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> 13#include <dt-bindings/power/mediatek,mt8188-power.h> 14 15/ { 16 compatible = "mediatek,mt8188"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a55"; 28 reg = <0x000>; 29 enable-method = "psci"; 30 clock-frequency = <2000000000>; 31 capacity-dmips-mhz = <282>; 32 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 33 i-cache-size = <32768>; 34 i-cache-line-size = <64>; 35 i-cache-sets = <128>; 36 d-cache-size = <32768>; 37 d-cache-line-size = <64>; 38 d-cache-sets = <128>; 39 next-level-cache = <&l2_0>; 40 #cooling-cells = <2>; 41 }; 42 43 cpu1: cpu@100 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a55"; 46 reg = <0x100>; 47 enable-method = "psci"; 48 clock-frequency = <2000000000>; 49 capacity-dmips-mhz = <282>; 50 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 51 i-cache-size = <32768>; 52 i-cache-line-size = <64>; 53 i-cache-sets = <128>; 54 d-cache-size = <32768>; 55 d-cache-line-size = <64>; 56 d-cache-sets = <128>; 57 next-level-cache = <&l2_0>; 58 #cooling-cells = <2>; 59 }; 60 61 cpu2: cpu@200 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a55"; 64 reg = <0x200>; 65 enable-method = "psci"; 66 clock-frequency = <2000000000>; 67 capacity-dmips-mhz = <282>; 68 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 69 i-cache-size = <32768>; 70 i-cache-line-size = <64>; 71 i-cache-sets = <128>; 72 d-cache-size = <32768>; 73 d-cache-line-size = <64>; 74 d-cache-sets = <128>; 75 next-level-cache = <&l2_0>; 76 #cooling-cells = <2>; 77 }; 78 79 cpu3: cpu@300 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a55"; 82 reg = <0x300>; 83 enable-method = "psci"; 84 clock-frequency = <2000000000>; 85 capacity-dmips-mhz = <282>; 86 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 87 i-cache-size = <32768>; 88 i-cache-line-size = <64>; 89 i-cache-sets = <128>; 90 d-cache-size = <32768>; 91 d-cache-line-size = <64>; 92 d-cache-sets = <128>; 93 next-level-cache = <&l2_0>; 94 #cooling-cells = <2>; 95 }; 96 97 cpu4: cpu@400 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a55"; 100 reg = <0x400>; 101 enable-method = "psci"; 102 clock-frequency = <2000000000>; 103 capacity-dmips-mhz = <282>; 104 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 105 i-cache-size = <32768>; 106 i-cache-line-size = <64>; 107 i-cache-sets = <128>; 108 d-cache-size = <32768>; 109 d-cache-line-size = <64>; 110 d-cache-sets = <128>; 111 next-level-cache = <&l2_0>; 112 #cooling-cells = <2>; 113 }; 114 115 cpu5: cpu@500 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a55"; 118 reg = <0x500>; 119 enable-method = "psci"; 120 clock-frequency = <2000000000>; 121 capacity-dmips-mhz = <282>; 122 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 123 i-cache-size = <32768>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <128>; 126 d-cache-size = <32768>; 127 d-cache-line-size = <64>; 128 d-cache-sets = <128>; 129 next-level-cache = <&l2_0>; 130 #cooling-cells = <2>; 131 }; 132 133 cpu6: cpu@600 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a78"; 136 reg = <0x600>; 137 enable-method = "psci"; 138 clock-frequency = <2600000000>; 139 capacity-dmips-mhz = <1024>; 140 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 141 i-cache-size = <65536>; 142 i-cache-line-size = <64>; 143 i-cache-sets = <256>; 144 d-cache-size = <65536>; 145 d-cache-line-size = <64>; 146 d-cache-sets = <256>; 147 next-level-cache = <&l2_1>; 148 #cooling-cells = <2>; 149 }; 150 151 cpu7: cpu@700 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a78"; 154 reg = <0x700>; 155 enable-method = "psci"; 156 clock-frequency = <2600000000>; 157 capacity-dmips-mhz = <1024>; 158 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 159 i-cache-size = <65536>; 160 i-cache-line-size = <64>; 161 i-cache-sets = <256>; 162 d-cache-size = <65536>; 163 d-cache-line-size = <64>; 164 d-cache-sets = <256>; 165 next-level-cache = <&l2_1>; 166 #cooling-cells = <2>; 167 }; 168 169 cpu-map { 170 cluster0 { 171 core0 { 172 cpu = <&cpu0>; 173 }; 174 175 core1 { 176 cpu = <&cpu1>; 177 }; 178 179 core2 { 180 cpu = <&cpu2>; 181 }; 182 183 core3 { 184 cpu = <&cpu3>; 185 }; 186 187 core4 { 188 cpu = <&cpu4>; 189 }; 190 191 core5 { 192 cpu = <&cpu5>; 193 }; 194 195 core6 { 196 cpu = <&cpu6>; 197 }; 198 199 core7 { 200 cpu = <&cpu7>; 201 }; 202 }; 203 }; 204 205 idle-states { 206 entry-method = "psci"; 207 208 cpu_off_l: cpu-off-l { 209 compatible = "arm,idle-state"; 210 arm,psci-suspend-param = <0x00010000>; 211 local-timer-stop; 212 entry-latency-us = <50>; 213 exit-latency-us = <95>; 214 min-residency-us = <580>; 215 }; 216 217 cpu_off_b: cpu-off-b { 218 compatible = "arm,idle-state"; 219 arm,psci-suspend-param = <0x00010000>; 220 local-timer-stop; 221 entry-latency-us = <45>; 222 exit-latency-us = <140>; 223 min-residency-us = <740>; 224 }; 225 226 cluster_off_l: cluster-off-l { 227 compatible = "arm,idle-state"; 228 arm,psci-suspend-param = <0x01010010>; 229 local-timer-stop; 230 entry-latency-us = <55>; 231 exit-latency-us = <155>; 232 min-residency-us = <840>; 233 }; 234 235 cluster_off_b: cluster-off-b { 236 compatible = "arm,idle-state"; 237 arm,psci-suspend-param = <0x01010010>; 238 local-timer-stop; 239 entry-latency-us = <50>; 240 exit-latency-us = <200>; 241 min-residency-us = <1000>; 242 }; 243 }; 244 245 l2_0: l2-cache0 { 246 compatible = "cache"; 247 cache-level = <2>; 248 cache-size = <131072>; 249 cache-line-size = <64>; 250 cache-sets = <512>; 251 next-level-cache = <&l3_0>; 252 cache-unified; 253 }; 254 255 l2_1: l2-cache1 { 256 compatible = "cache"; 257 cache-level = <2>; 258 cache-size = <262144>; 259 cache-line-size = <64>; 260 cache-sets = <512>; 261 next-level-cache = <&l3_0>; 262 cache-unified; 263 }; 264 265 l3_0: l3-cache { 266 compatible = "cache"; 267 cache-level = <3>; 268 cache-size = <2097152>; 269 cache-line-size = <64>; 270 cache-sets = <2048>; 271 cache-unified; 272 }; 273 }; 274 275 clk13m: oscillator-13m { 276 compatible = "fixed-clock"; 277 #clock-cells = <0>; 278 clock-frequency = <13000000>; 279 clock-output-names = "clk13m"; 280 }; 281 282 clk26m: oscillator-26m { 283 compatible = "fixed-clock"; 284 #clock-cells = <0>; 285 clock-frequency = <26000000>; 286 clock-output-names = "clk26m"; 287 }; 288 289 clk32k: oscillator-32k { 290 compatible = "fixed-clock"; 291 #clock-cells = <0>; 292 clock-frequency = <32768>; 293 clock-output-names = "clk32k"; 294 }; 295 296 pmu-a55 { 297 compatible = "arm,cortex-a55-pmu"; 298 interrupt-parent = <&gic>; 299 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 300 }; 301 302 pmu-a78 { 303 compatible = "arm,cortex-a78-pmu"; 304 interrupt-parent = <&gic>; 305 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 306 }; 307 308 psci { 309 compatible = "arm,psci-1.0"; 310 method = "smc"; 311 }; 312 313 timer: timer { 314 compatible = "arm,armv8-timer"; 315 interrupt-parent = <&gic>; 316 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 317 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 318 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 319 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 320 clock-frequency = <13000000>; 321 }; 322 323 soc { 324 #address-cells = <2>; 325 #size-cells = <2>; 326 compatible = "simple-bus"; 327 ranges; 328 329 gic: interrupt-controller@c000000 { 330 compatible = "arm,gic-v3"; 331 #interrupt-cells = <4>; 332 #redistributor-regions = <1>; 333 interrupt-parent = <&gic>; 334 interrupt-controller; 335 reg = <0 0x0c000000 0 0x40000>, 336 <0 0x0c040000 0 0x200000>; 337 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 338 339 ppi-partitions { 340 ppi_cluster0: interrupt-partition-0 { 341 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 342 }; 343 344 ppi_cluster1: interrupt-partition-1 { 345 affinity = <&cpu6 &cpu7>; 346 }; 347 }; 348 }; 349 350 topckgen: syscon@10000000 { 351 compatible = "mediatek,mt8188-topckgen", "syscon"; 352 reg = <0 0x10000000 0 0x1000>; 353 #clock-cells = <1>; 354 }; 355 356 infracfg_ao: syscon@10001000 { 357 compatible = "mediatek,mt8188-infracfg-ao", "syscon"; 358 reg = <0 0x10001000 0 0x1000>; 359 #clock-cells = <1>; 360 }; 361 362 pericfg: syscon@10003000 { 363 compatible = "mediatek,mt8188-pericfg", "syscon"; 364 reg = <0 0x10003000 0 0x1000>; 365 #clock-cells = <1>; 366 }; 367 368 pio: pinctrl@10005000 { 369 compatible = "mediatek,mt8188-pinctrl"; 370 reg = <0 0x10005000 0 0x1000>, 371 <0 0x11c00000 0 0x1000>, 372 <0 0x11e10000 0 0x1000>, 373 <0 0x11e20000 0 0x1000>, 374 <0 0x11ea0000 0 0x1000>, 375 <0 0x1000b000 0 0x1000>; 376 reg-names = "iocfg0", "iocfg_rm", "iocfg_lt", 377 "iocfg_lm", "iocfg_rt", "eint"; 378 gpio-controller; 379 #gpio-cells = <2>; 380 gpio-ranges = <&pio 0 0 176>; 381 interrupt-controller; 382 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 383 #interrupt-cells = <2>; 384 }; 385 386 watchdog: watchdog@10007000 { 387 compatible = "mediatek,mt8188-wdt"; 388 reg = <0 0x10007000 0 0x100>; 389 mediatek,disable-extrst; 390 #reset-cells = <1>; 391 }; 392 393 apmixedsys: syscon@1000c000 { 394 compatible = "mediatek,mt8188-apmixedsys", "syscon"; 395 reg = <0 0x1000c000 0 0x1000>; 396 #clock-cells = <1>; 397 }; 398 399 systimer: timer@10017000 { 400 compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer"; 401 reg = <0 0x10017000 0 0x1000>; 402 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 403 clocks = <&clk13m>; 404 }; 405 406 pwrap: pwrap@10024000 { 407 compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon"; 408 reg = <0 0x10024000 0 0x1000>; 409 reg-names = "pwrap"; 410 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 411 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 412 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 413 clock-names = "spi", "wrap"; 414 }; 415 416 scp: scp@10500000 { 417 compatible = "mediatek,mt8188-scp"; 418 reg = <0 0x10500000 0 0x100000>, 419 <0 0x10720000 0 0xe0000>; 420 reg-names = "sram", "cfg"; 421 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 422 }; 423 424 adsp_audio26m: clock-controller@10b91100 { 425 compatible = "mediatek,mt8188-adsp-audio26m"; 426 reg = <0 0x10b91100 0 0x100>; 427 #clock-cells = <1>; 428 }; 429 430 uart0: serial@11001100 { 431 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 432 reg = <0 0x11001100 0 0x100>; 433 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 434 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 435 clock-names = "baud", "bus"; 436 status = "disabled"; 437 }; 438 439 uart1: serial@11001200 { 440 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 441 reg = <0 0x11001200 0 0x100>; 442 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 443 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 444 clock-names = "baud", "bus"; 445 status = "disabled"; 446 }; 447 448 uart2: serial@11001300 { 449 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 450 reg = <0 0x11001300 0 0x100>; 451 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 452 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 453 clock-names = "baud", "bus"; 454 status = "disabled"; 455 }; 456 457 uart3: serial@11001400 { 458 compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; 459 reg = <0 0x11001400 0 0x100>; 460 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 461 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 462 clock-names = "baud", "bus"; 463 status = "disabled"; 464 }; 465 466 auxadc: adc@11002000 { 467 compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc"; 468 reg = <0 0x11002000 0 0x1000>; 469 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 470 clock-names = "main"; 471 #io-channel-cells = <1>; 472 status = "disabled"; 473 }; 474 475 pericfg_ao: syscon@11003000 { 476 compatible = "mediatek,mt8188-pericfg-ao", "syscon"; 477 reg = <0 0x11003000 0 0x1000>; 478 #clock-cells = <1>; 479 }; 480 481 spi0: spi@1100a000 { 482 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 reg = <0 0x1100a000 0 0x1000>; 486 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 487 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 488 <&topckgen CLK_TOP_SPI>, 489 <&infracfg_ao CLK_INFRA_AO_SPI0>; 490 clock-names = "parent-clk", "sel-clk", "spi-clk"; 491 status = "disabled"; 492 }; 493 494 spi1: spi@11010000 { 495 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 reg = <0 0x11010000 0 0x1000>; 499 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 500 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 501 <&topckgen CLK_TOP_SPI>, 502 <&infracfg_ao CLK_INFRA_AO_SPI1>; 503 clock-names = "parent-clk", "sel-clk", "spi-clk"; 504 status = "disabled"; 505 }; 506 507 spi2: spi@11012000 { 508 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 reg = <0 0x11012000 0 0x1000>; 512 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 513 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 514 <&topckgen CLK_TOP_SPI>, 515 <&infracfg_ao CLK_INFRA_AO_SPI2>; 516 clock-names = "parent-clk", "sel-clk", "spi-clk"; 517 status = "disabled"; 518 }; 519 520 spi3: spi@11013000 { 521 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 reg = <0 0x11013000 0 0x1000>; 525 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 526 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 527 <&topckgen CLK_TOP_SPI>, 528 <&infracfg_ao CLK_INFRA_AO_SPI3>; 529 clock-names = "parent-clk", "sel-clk", "spi-clk"; 530 status = "disabled"; 531 }; 532 533 spi4: spi@11018000 { 534 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 reg = <0 0x11018000 0 0x1000>; 538 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 539 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 540 <&topckgen CLK_TOP_SPI>, 541 <&infracfg_ao CLK_INFRA_AO_SPI4>; 542 clock-names = "parent-clk", "sel-clk", "spi-clk"; 543 status = "disabled"; 544 }; 545 546 spi5: spi@11019000 { 547 compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 reg = <0 0x11019000 0 0x1000>; 551 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 552 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 553 <&topckgen CLK_TOP_SPI>, 554 <&infracfg_ao CLK_INFRA_AO_SPI5>; 555 clock-names = "parent-clk", "sel-clk", "spi-clk"; 556 status = "disabled"; 557 }; 558 559 xhci1: usb@11200000 { 560 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 561 reg = <0 0x11200000 0 0x1000>, 562 <0 0x11203e00 0 0x0100>; 563 reg-names = "mac", "ippc"; 564 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 565 phys = <&u2port1 PHY_TYPE_USB2>, 566 <&u3port1 PHY_TYPE_USB3>; 567 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 568 <&topckgen CLK_TOP_SSUSB_XHCI>; 569 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 570 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 571 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>, 572 <&topckgen CLK_TOP_SSUSB_TOP_REF>, 573 <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; 574 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 575 mediatek,syscon-wakeup = <&pericfg 0x468 2>; 576 wakeup-source; 577 status = "disabled"; 578 }; 579 580 mmc0: mmc@11230000 { 581 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 582 reg = <0 0x11230000 0 0x10000>, 583 <0 0x11f50000 0 0x1000>; 584 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 585 clocks = <&topckgen CLK_TOP_MSDC50_0>, 586 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 587 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 588 <&infracfg_ao CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P>; 589 clock-names = "source", "hclk", "source_cg", "crypto_clk"; 590 status = "disabled"; 591 }; 592 593 mmc1: mmc@11240000 { 594 compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; 595 reg = <0 0x11240000 0 0x1000>, 596 <0 0x11eb0000 0 0x1000>; 597 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 598 clocks = <&topckgen CLK_TOP_MSDC30_1>, 599 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 600 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 601 clock-names = "source", "hclk", "source_cg"; 602 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 603 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 604 status = "disabled"; 605 }; 606 607 i2c0: i2c@11280000 { 608 compatible = "mediatek,mt8188-i2c"; 609 reg = <0 0x11280000 0 0x1000>, 610 <0 0x10220080 0 0x80>; 611 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>; 612 clock-div = <1>; 613 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0>, 614 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 615 clock-names = "main", "dma"; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 status = "disabled"; 619 }; 620 621 i2c2: i2c@11281000 { 622 compatible = "mediatek,mt8188-i2c"; 623 reg = <0 0x11281000 0 0x1000>, 624 <0 0x10220180 0 0x80>; 625 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 626 clock-div = <1>; 627 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2>, 628 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 629 clock-names = "main", "dma"; 630 #address-cells = <1>; 631 #size-cells = <0>; 632 status = "disabled"; 633 }; 634 635 i2c3: i2c@11282000 { 636 compatible = "mediatek,mt8188-i2c"; 637 reg = <0 0x11282000 0 0x1000>, 638 <0 0x10220280 0 0x80>; 639 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 640 clock-div = <1>; 641 clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3>, 642 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 643 clock-names = "main", "dma"; 644 #address-cells = <1>; 645 #size-cells = <0>; 646 status = "disabled"; 647 }; 648 649 imp_iic_wrap_c: clock-controller@11283000 { 650 compatible = "mediatek,mt8188-imp-iic-wrap-c"; 651 reg = <0 0x11283000 0 0x1000>; 652 #clock-cells = <1>; 653 }; 654 655 xhci2: usb@112a0000 { 656 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 657 reg = <0 0x112a0000 0 0x1000>, 658 <0 0x112a3e00 0 0x0100>; 659 reg-names = "mac", "ippc"; 660 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 661 phys = <&u2port2 PHY_TYPE_USB2>; 662 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>, 663 <&topckgen CLK_TOP_USB_TOP_3P>; 664 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 665 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 666 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 667 <&topckgen CLK_TOP_SSUSB_TOP_P3_REF>, 668 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 669 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 670 status = "disabled"; 671 }; 672 673 xhci0: usb@112b0000 { 674 compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; 675 reg = <0 0x112b0000 0 0x1000>, 676 <0 0x112b3e00 0 0x0100>; 677 reg-names = "mac", "ippc"; 678 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 679 phys = <&u2port0 PHY_TYPE_USB2>; 680 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>, 681 <&topckgen CLK_TOP_USB_TOP_2P>; 682 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 683 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 684 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 685 <&topckgen CLK_TOP_SSUSB_TOP_P2_REF>, 686 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 687 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 688 mediatek,syscon-wakeup = <&pericfg 0x460 2>; 689 wakeup-source; 690 status = "disabled"; 691 }; 692 693 nor_flash: spi@1132c000 { 694 compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor"; 695 reg = <0 0x1132c000 0 0x1000>; 696 clocks = <&topckgen CLK_TOP_SPINOR>, 697 <&pericfg_ao CLK_PERI_AO_FLASHIFLASHCK>, 698 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 699 clock-names = "spi", "sf", "axi"; 700 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 701 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 702 status = "disabled"; 703 }; 704 705 i2c1: i2c@11e00000 { 706 compatible = "mediatek,mt8188-i2c"; 707 reg = <0 0x11e00000 0 0x1000>, 708 <0 0x10220100 0 0x80>; 709 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 710 clock-div = <1>; 711 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1>, 712 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 713 clock-names = "main", "dma"; 714 #address-cells = <1>; 715 #size-cells = <0>; 716 status = "disabled"; 717 }; 718 719 i2c4: i2c@11e01000 { 720 compatible = "mediatek,mt8188-i2c"; 721 reg = <0 0x11e01000 0 0x1000>, 722 <0 0x10220380 0 0x80>; 723 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>; 724 clock-div = <1>; 725 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4>, 726 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 727 clock-names = "main", "dma"; 728 #address-cells = <1>; 729 #size-cells = <0>; 730 status = "disabled"; 731 }; 732 733 imp_iic_wrap_w: clock-controller@11e02000 { 734 compatible = "mediatek,mt8188-imp-iic-wrap-w"; 735 reg = <0 0x11e02000 0 0x1000>; 736 #clock-cells = <1>; 737 }; 738 739 u3phy0: t-phy@11e30000 { 740 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 741 #address-cells = <1>; 742 #size-cells = <1>; 743 ranges = <0x0 0x0 0x11e30000 0x1000>; 744 status = "disabled"; 745 746 u2port0: usb-phy@0 { 747 reg = <0x0 0x700>; 748 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>, 749 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 750 clock-names = "ref", "da_ref"; 751 #phy-cells = <1>; 752 }; 753 }; 754 755 u3phy1: t-phy@11e40000 { 756 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 757 #address-cells = <1>; 758 #size-cells = <1>; 759 ranges = <0x0 0x0 0x11e40000 0x1000>; 760 status = "disabled"; 761 762 u2port1: usb-phy@0 { 763 reg = <0x0 0x700>; 764 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 765 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 766 clock-names = "ref", "da_ref"; 767 #phy-cells = <1>; 768 }; 769 770 u3port1: usb-phy@700 { 771 reg = <0x700 0x700>; 772 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>, 773 <&clk26m>; 774 clock-names = "ref", "da_ref"; 775 #phy-cells = <1>; 776 status = "disabled"; 777 }; 778 }; 779 780 u3phy2: t-phy@11e80000 { 781 compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 782 #address-cells = <1>; 783 #size-cells = <1>; 784 ranges = <0x0 0x0 0x11e80000 0x1000>; 785 status = "disabled"; 786 787 u2port2: usb-phy@0 { 788 reg = <0x0 0x700>; 789 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>, 790 <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; 791 clock-names = "ref", "da_ref"; 792 #phy-cells = <1>; 793 }; 794 }; 795 796 i2c5: i2c@11ec0000 { 797 compatible = "mediatek,mt8188-i2c"; 798 reg = <0 0x11ec0000 0 0x1000>, 799 <0 0x10220480 0 0x80>; 800 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>; 801 clock-div = <1>; 802 clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5>, 803 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 804 clock-names = "main", "dma"; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 status = "disabled"; 808 }; 809 810 i2c6: i2c@11ec1000 { 811 compatible = "mediatek,mt8188-i2c"; 812 reg = <0 0x11ec1000 0 0x1000>, 813 <0 0x10220600 0 0x80>; 814 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 815 clock-div = <1>; 816 clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6>, 817 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; 818 clock-names = "main", "dma"; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 status = "disabled"; 822 }; 823 824 imp_iic_wrap_en: clock-controller@11ec2000 { 825 compatible = "mediatek,mt8188-imp-iic-wrap-en"; 826 reg = <0 0x11ec2000 0 0x1000>; 827 #clock-cells = <1>; 828 }; 829 830 mfgcfg: clock-controller@13fbf000 { 831 compatible = "mediatek,mt8188-mfgcfg"; 832 reg = <0 0x13fbf000 0 0x1000>; 833 #clock-cells = <1>; 834 }; 835 836 vppsys0: clock-controller@14000000 { 837 compatible = "mediatek,mt8188-vppsys0"; 838 reg = <0 0x14000000 0 0x1000>; 839 #clock-cells = <1>; 840 }; 841 842 wpesys: clock-controller@14e00000 { 843 compatible = "mediatek,mt8188-wpesys"; 844 reg = <0 0x14e00000 0 0x1000>; 845 #clock-cells = <1>; 846 }; 847 848 wpesys_vpp0: clock-controller@14e02000 { 849 compatible = "mediatek,mt8188-wpesys-vpp0"; 850 reg = <0 0x14e02000 0 0x1000>; 851 #clock-cells = <1>; 852 }; 853 854 vppsys1: clock-controller@14f00000 { 855 compatible = "mediatek,mt8188-vppsys1"; 856 reg = <0 0x14f00000 0 0x1000>; 857 #clock-cells = <1>; 858 }; 859 860 imgsys: clock-controller@15000000 { 861 compatible = "mediatek,mt8188-imgsys"; 862 reg = <0 0x15000000 0 0x1000>; 863 #clock-cells = <1>; 864 }; 865 866 imgsys1_dip_top: clock-controller@15110000 { 867 compatible = "mediatek,mt8188-imgsys1-dip-top"; 868 reg = <0 0x15110000 0 0x1000>; 869 #clock-cells = <1>; 870 }; 871 872 imgsys1_dip_nr: clock-controller@15130000 { 873 compatible = "mediatek,mt8188-imgsys1-dip-nr"; 874 reg = <0 0x15130000 0 0x1000>; 875 #clock-cells = <1>; 876 }; 877 878 imgsys_wpe1: clock-controller@15220000 { 879 compatible = "mediatek,mt8188-imgsys-wpe1"; 880 reg = <0 0x15220000 0 0x1000>; 881 #clock-cells = <1>; 882 }; 883 884 ipesys: clock-controller@15330000 { 885 compatible = "mediatek,mt8188-ipesys"; 886 reg = <0 0x15330000 0 0x1000>; 887 #clock-cells = <1>; 888 }; 889 890 imgsys_wpe2: clock-controller@15520000 { 891 compatible = "mediatek,mt8188-imgsys-wpe2"; 892 reg = <0 0x15520000 0 0x1000>; 893 #clock-cells = <1>; 894 }; 895 896 imgsys_wpe3: clock-controller@15620000 { 897 compatible = "mediatek,mt8188-imgsys-wpe3"; 898 reg = <0 0x15620000 0 0x1000>; 899 #clock-cells = <1>; 900 }; 901 902 camsys: clock-controller@16000000 { 903 compatible = "mediatek,mt8188-camsys"; 904 reg = <0 0x16000000 0 0x1000>; 905 #clock-cells = <1>; 906 }; 907 908 camsys_rawa: clock-controller@1604f000 { 909 compatible = "mediatek,mt8188-camsys-rawa"; 910 reg = <0 0x1604f000 0 0x1000>; 911 #clock-cells = <1>; 912 }; 913 914 camsys_yuva: clock-controller@1606f000 { 915 compatible = "mediatek,mt8188-camsys-yuva"; 916 reg = <0 0x1606f000 0 0x1000>; 917 #clock-cells = <1>; 918 }; 919 920 camsys_rawb: clock-controller@1608f000 { 921 compatible = "mediatek,mt8188-camsys-rawb"; 922 reg = <0 0x1608f000 0 0x1000>; 923 #clock-cells = <1>; 924 }; 925 926 camsys_yuvb: clock-controller@160af000 { 927 compatible = "mediatek,mt8188-camsys-yuvb"; 928 reg = <0 0x160af000 0 0x1000>; 929 #clock-cells = <1>; 930 }; 931 932 ccusys: clock-controller@17200000 { 933 compatible = "mediatek,mt8188-ccusys"; 934 reg = <0 0x17200000 0 0x1000>; 935 #clock-cells = <1>; 936 }; 937 938 vdecsys_soc: clock-controller@1800f000 { 939 compatible = "mediatek,mt8188-vdecsys-soc"; 940 reg = <0 0x1800f000 0 0x1000>; 941 #clock-cells = <1>; 942 }; 943 944 vdecsys: clock-controller@1802f000 { 945 compatible = "mediatek,mt8188-vdecsys"; 946 reg = <0 0x1802f000 0 0x1000>; 947 #clock-cells = <1>; 948 }; 949 950 vencsys: clock-controller@1a000000 { 951 compatible = "mediatek,mt8188-vencsys"; 952 reg = <0 0x1a000000 0 0x1000>; 953 #clock-cells = <1>; 954 }; 955 }; 956}; 957