xref: /linux/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi (revision 2f24482304ebd32c5aa374f31465b9941a860b92)
15e6af7f5SFei Shao// SPDX-License-Identifier: (GPL-2.0 OR MIT)
25e6af7f5SFei Shao/*
35e6af7f5SFei Shao * Copyright (C) 2022 MediaTek Inc.
45e6af7f5SFei Shao */
55e6af7f5SFei Shao/dts-v1/;
65e6af7f5SFei Shao#include <dt-bindings/gpio/gpio.h>
75e6af7f5SFei Shao#include "mt8188.dtsi"
85e6af7f5SFei Shao#include "mt6359.dtsi"
95e6af7f5SFei Shao
105e6af7f5SFei Shao/ {
115e6af7f5SFei Shao	aliases {
12*383c2ac3SAngeloGioacchino Del Regno		dsi0 = &disp_dsi0;
135e6af7f5SFei Shao		i2c0 = &i2c0;
145e6af7f5SFei Shao		i2c1 = &i2c1;
155e6af7f5SFei Shao		i2c2 = &i2c2;
165e6af7f5SFei Shao		i2c3 = &i2c3;
175e6af7f5SFei Shao		i2c4 = &i2c4;
185e6af7f5SFei Shao		i2c5 = &i2c5;
195e6af7f5SFei Shao		i2c6 = &i2c6;
205e6af7f5SFei Shao		mmc0 = &mmc0;
215e6af7f5SFei Shao		serial0 = &uart0;
225e6af7f5SFei Shao	};
235e6af7f5SFei Shao
245e6af7f5SFei Shao	backlight_lcd0: backlight-lcd0 {
255e6af7f5SFei Shao		compatible = "pwm-backlight";
265e6af7f5SFei Shao		brightness-levels = <0 1023>;
275e6af7f5SFei Shao		default-brightness-level = <576>;
285e6af7f5SFei Shao		enable-gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
295e6af7f5SFei Shao		num-interpolated-steps = <1023>;
305e6af7f5SFei Shao		power-supply = <&ppvar_sys>;
315e6af7f5SFei Shao		pwms = <&disp_pwm0 0 500000>;
325e6af7f5SFei Shao	};
335e6af7f5SFei Shao
345e6af7f5SFei Shao	chosen {
355e6af7f5SFei Shao		stdout-path = "serial0:115200n8";
365e6af7f5SFei Shao	};
375e6af7f5SFei Shao
385e6af7f5SFei Shao	dmic-codec {
395e6af7f5SFei Shao		compatible = "dmic-codec";
405e6af7f5SFei Shao		num-channels = <2>;
415e6af7f5SFei Shao		wakeup-delay-ms = <100>;
425e6af7f5SFei Shao	};
435e6af7f5SFei Shao
445e6af7f5SFei Shao	memory@40000000 {
455e6af7f5SFei Shao		device_type = "memory";
465e6af7f5SFei Shao		/* The size will be filled in by the bootloader */
475e6af7f5SFei Shao		reg = <0 0x40000000 0 0>;
485e6af7f5SFei Shao	};
495e6af7f5SFei Shao
505e6af7f5SFei Shao	/* system wide LDO 1.8V power rail */
515e6af7f5SFei Shao	pp1800_ldo_z1: regulator-pp1800-ldo-z1 {
525e6af7f5SFei Shao		compatible = "regulator-fixed";
535e6af7f5SFei Shao		regulator-name = "pp1800_ldo_z1";
545e6af7f5SFei Shao		/* controlled by PP3300_Z1 */
555e6af7f5SFei Shao		regulator-always-on;
565e6af7f5SFei Shao		regulator-boot-on;
575e6af7f5SFei Shao		regulator-min-microvolt = <1800000>;
585e6af7f5SFei Shao		regulator-max-microvolt = <1800000>;
595e6af7f5SFei Shao		vin-supply = <&pp3300_z1>;
605e6af7f5SFei Shao	};
615e6af7f5SFei Shao
625e6af7f5SFei Shao	/* separately switched 3.3V power rail */
635e6af7f5SFei Shao	pp3300_s3: regulator-pp3300-s3 {
645e6af7f5SFei Shao		compatible = "regulator-fixed";
655e6af7f5SFei Shao		regulator-name = "pp3300_s3";
665e6af7f5SFei Shao		/* controlled by PMIC */
675e6af7f5SFei Shao		regulator-always-on;
685e6af7f5SFei Shao		regulator-boot-on;
695e6af7f5SFei Shao		regulator-min-microvolt = <3300000>;
705e6af7f5SFei Shao		regulator-max-microvolt = <3300000>;
715e6af7f5SFei Shao		vin-supply = <&pp3300_z1>;
725e6af7f5SFei Shao	};
735e6af7f5SFei Shao
745e6af7f5SFei Shao	/* system wide 3.3V power rail */
755e6af7f5SFei Shao	pp3300_z1: regulator-pp3300-z1 {
765e6af7f5SFei Shao		compatible = "regulator-fixed";
775e6af7f5SFei Shao		regulator-name = "pp3300_z1";
785e6af7f5SFei Shao		/* controlled by PP3300_LDO_Z5 & EN_PWR_Z1 */
795e6af7f5SFei Shao		regulator-always-on;
805e6af7f5SFei Shao		regulator-boot-on;
815e6af7f5SFei Shao		regulator-min-microvolt = <3300000>;
825e6af7f5SFei Shao		regulator-max-microvolt = <3300000>;
835e6af7f5SFei Shao		vin-supply = <&ppvar_sys>;
845e6af7f5SFei Shao	};
855e6af7f5SFei Shao
865e6af7f5SFei Shao	pp3300_wlan: regulator-pp3300-wlan {
875e6af7f5SFei Shao		compatible = "regulator-fixed";
885e6af7f5SFei Shao		regulator-name = "pp3300_wlan";
895e6af7f5SFei Shao		regulator-always-on;
905e6af7f5SFei Shao		regulator-min-microvolt = <3300000>;
915e6af7f5SFei Shao		regulator-max-microvolt = <3300000>;
925e6af7f5SFei Shao		enable-active-high;
935e6af7f5SFei Shao		gpio = <&pio 12 GPIO_ACTIVE_HIGH>;
945e6af7f5SFei Shao		pinctrl-0 = <&wlan_en>;
955e6af7f5SFei Shao		pinctrl-names = "default";
965e6af7f5SFei Shao		vin-supply = <&pp3300_z1>;
975e6af7f5SFei Shao	};
985e6af7f5SFei Shao
995e6af7f5SFei Shao	/* system wide 4.2V power rail */
1005e6af7f5SFei Shao	pp4200_s5: regulator-pp4200-s5 {
1015e6af7f5SFei Shao		compatible = "regulator-fixed";
1025e6af7f5SFei Shao		regulator-name = "pp4200_s5";
1035e6af7f5SFei Shao		/* controlled by EC */
1045e6af7f5SFei Shao		regulator-always-on;
1055e6af7f5SFei Shao		regulator-boot-on;
1065e6af7f5SFei Shao		regulator-min-microvolt = <4200000>;
1075e6af7f5SFei Shao		regulator-max-microvolt = <4200000>;
1085e6af7f5SFei Shao		vin-supply = <&ppvar_sys>;
1095e6af7f5SFei Shao	};
1105e6af7f5SFei Shao
1115e6af7f5SFei Shao	/* system wide 5.0V power rail */
1125e6af7f5SFei Shao	pp5000_z1: regulator-pp5000-z1 {
1135e6af7f5SFei Shao		compatible = "regulator-fixed";
1145e6af7f5SFei Shao		regulator-name = "pp5000_z1";
1155e6af7f5SFei Shao		/* controlled by EC */
1165e6af7f5SFei Shao		regulator-always-on;
1175e6af7f5SFei Shao		regulator-boot-on;
1185e6af7f5SFei Shao		regulator-min-microvolt = <5000000>;
1195e6af7f5SFei Shao		regulator-max-microvolt = <5000000>;
1205e6af7f5SFei Shao		vin-supply = <&ppvar_sys>;
1215e6af7f5SFei Shao	};
1225e6af7f5SFei Shao
1235e6af7f5SFei Shao	pp5000_usb_vbus: regulator-pp5000-usb-vbus {
1245e6af7f5SFei Shao		compatible = "regulator-fixed";
1255e6af7f5SFei Shao		regulator-name = "pp5000_usb_vbus";
1265e6af7f5SFei Shao		regulator-min-microvolt = <5000000>;
1275e6af7f5SFei Shao		regulator-max-microvolt = <5000000>;
1285e6af7f5SFei Shao		enable-active-high;
1295e6af7f5SFei Shao		gpio = <&pio 150 GPIO_ACTIVE_HIGH>;
1305e6af7f5SFei Shao		vin-supply = <&pp5000_z1>;
1315e6af7f5SFei Shao	};
1325e6af7f5SFei Shao
1335e6af7f5SFei Shao	/* system wide semi-regulated power rail from battery or USB */
1345e6af7f5SFei Shao	ppvar_sys: regulator-ppvar-sys {
1355e6af7f5SFei Shao		compatible = "regulator-fixed";
1365e6af7f5SFei Shao		regulator-name = "ppvar_sys";
1375e6af7f5SFei Shao		regulator-always-on;
1385e6af7f5SFei Shao		regulator-boot-on;
1395e6af7f5SFei Shao	};
1405e6af7f5SFei Shao
1415e6af7f5SFei Shao	ppvar_mipi_disp_avdd: regulator-ppvar-mipi-disp-avdd {
1425e6af7f5SFei Shao		compatible = "regulator-fixed";
1435e6af7f5SFei Shao		regulator-name = "ppvar_mipi_disp_avdd";
1445e6af7f5SFei Shao		enable-active-high;
1455e6af7f5SFei Shao		gpio = <&pio 3 GPIO_ACTIVE_HIGH>;
1465e6af7f5SFei Shao		pinctrl-names = "default";
1475e6af7f5SFei Shao		pinctrl-0 = <&mipi_disp_avdd_en>;
1485e6af7f5SFei Shao		vin-supply = <&pp5000_z1>;
1495e6af7f5SFei Shao	};
1505e6af7f5SFei Shao
1515e6af7f5SFei Shao	ppvar_mipi_disp_avee: regulator-ppvar-mipi-disp-avee {
1525e6af7f5SFei Shao		compatible = "regulator-fixed";
1535e6af7f5SFei Shao		regulator-name = "ppvar_mipi_disp_avee";
1545e6af7f5SFei Shao		regulator-enable-ramp-delay = <10000>;
1555e6af7f5SFei Shao		enable-active-high;
1565e6af7f5SFei Shao		gpio = <&pio 4 GPIO_ACTIVE_HIGH>;
1575e6af7f5SFei Shao		pinctrl-names = "default";
1585e6af7f5SFei Shao		pinctrl-0 = <&mipi_disp_avee_en>;
1595e6af7f5SFei Shao		vin-supply = <&pp5000_z1>;
1605e6af7f5SFei Shao	};
1615e6af7f5SFei Shao
1625e6af7f5SFei Shao	reserved_memory: reserved-memory {
1635e6af7f5SFei Shao		#address-cells = <2>;
1645e6af7f5SFei Shao		#size-cells = <2>;
1655e6af7f5SFei Shao		ranges;
1665e6af7f5SFei Shao
1675e6af7f5SFei Shao		apu_mem: memory@55000000 {
1685e6af7f5SFei Shao			compatible = "shared-dma-pool";
1695e6af7f5SFei Shao			reg = <0 0x55000000 0 0x1400000>;
1705e6af7f5SFei Shao		};
1715e6af7f5SFei Shao
1725e6af7f5SFei Shao		adsp_mem: memory@60000000 {
1735e6af7f5SFei Shao			compatible = "shared-dma-pool";
1745e6af7f5SFei Shao			reg = <0 0x60000000 0 0xf00000>;
1755e6af7f5SFei Shao			no-map;
1765e6af7f5SFei Shao		};
1775e6af7f5SFei Shao
1785e6af7f5SFei Shao		afe_dma_mem: memory@60f00000 {
1795e6af7f5SFei Shao			compatible = "shared-dma-pool";
1805e6af7f5SFei Shao			reg = <0 0x60f00000 0 0x100000>;
1815e6af7f5SFei Shao			no-map;
1825e6af7f5SFei Shao		};
1835e6af7f5SFei Shao
1845e6af7f5SFei Shao		adsp_dma_mem: memory@61000000 {
1855e6af7f5SFei Shao			compatible = "shared-dma-pool";
1865e6af7f5SFei Shao			reg = <0 0x61000000 0 0x100000>;
1875e6af7f5SFei Shao			no-map;
1885e6af7f5SFei Shao		};
1895e6af7f5SFei Shao	};
1905e6af7f5SFei Shao};
1915e6af7f5SFei Shao
1925e6af7f5SFei Shao&adsp {
1935e6af7f5SFei Shao	memory-region = <&adsp_dma_mem>, <&adsp_mem>;
1945e6af7f5SFei Shao	pinctrl-names = "default";
1955e6af7f5SFei Shao	pinctrl-0 = <&adsp_uart_pins>;
1965e6af7f5SFei Shao	status = "okay";
1975e6af7f5SFei Shao};
1985e6af7f5SFei Shao
1995e6af7f5SFei Shao&afe {
2005e6af7f5SFei Shao	memory-region = <&afe_dma_mem>;
2015e6af7f5SFei Shao	mediatek,etdm-out1-cowork-source = <0>; /* in1 */
2025e6af7f5SFei Shao	mediatek,etdm-in2-cowork-source = <3>; /* out2 */
2035e6af7f5SFei Shao	status = "okay";
2045e6af7f5SFei Shao};
2055e6af7f5SFei Shao
2065e6af7f5SFei Shao&auxadc {
2075e6af7f5SFei Shao	status = "okay";
2085e6af7f5SFei Shao};
2095e6af7f5SFei Shao
2105e6af7f5SFei Shao&cam_vcore {
2115e6af7f5SFei Shao	domain-supply = <&mt6359_vproc1_buck_reg>;
2125e6af7f5SFei Shao};
2135e6af7f5SFei Shao
2145e6af7f5SFei Shao/*
2155e6af7f5SFei Shao * Geralt is the reference design and doesn't have target TDP.
2165e6af7f5SFei Shao * Ciri is (currently) the only device following Geralt, and its
2175e6af7f5SFei Shao * TDP target is 90 degrees.
2185e6af7f5SFei Shao **/
2195e6af7f5SFei Shao&cpu_little0_alert0 {
2205e6af7f5SFei Shao	temperature = <90000>;
2215e6af7f5SFei Shao	hysteresis = <2000>;
2225e6af7f5SFei Shao	type = "passive";
2235e6af7f5SFei Shao};
2245e6af7f5SFei Shao
2255e6af7f5SFei Shao&cpu_little1_alert0 {
2265e6af7f5SFei Shao	temperature = <90000>;
2275e6af7f5SFei Shao	hysteresis = <2000>;
2285e6af7f5SFei Shao	type = "passive";
2295e6af7f5SFei Shao};
2305e6af7f5SFei Shao
2315e6af7f5SFei Shao&cpu_little2_alert0 {
2325e6af7f5SFei Shao	temperature = <90000>;
2335e6af7f5SFei Shao	hysteresis = <2000>;
2345e6af7f5SFei Shao	type = "passive";
2355e6af7f5SFei Shao};
2365e6af7f5SFei Shao
2375e6af7f5SFei Shao&cpu_little3_alert0 {
2385e6af7f5SFei Shao	temperature = <90000>;
2395e6af7f5SFei Shao	hysteresis = <2000>;
2405e6af7f5SFei Shao	type = "passive";
2415e6af7f5SFei Shao};
2425e6af7f5SFei Shao
2435e6af7f5SFei Shao&cpu_big0_alert0 {
2445e6af7f5SFei Shao	temperature = <90000>;
2455e6af7f5SFei Shao	hysteresis = <2000>;
2465e6af7f5SFei Shao	type = "passive";
2475e6af7f5SFei Shao};
2485e6af7f5SFei Shao
2495e6af7f5SFei Shao&cpu_big1_alert0 {
2505e6af7f5SFei Shao	temperature = <90000>;
2515e6af7f5SFei Shao	hysteresis = <2000>;
2525e6af7f5SFei Shao	type = "passive";
2535e6af7f5SFei Shao};
2545e6af7f5SFei Shao
2555e6af7f5SFei Shao&disp_dsi0 {
2565e6af7f5SFei Shao	#address-cells = <1>;
2575e6af7f5SFei Shao	#size-cells = <0>;
2585e6af7f5SFei Shao	status = "okay";
2595e6af7f5SFei Shao
2605e6af7f5SFei Shao	dsi_panel: panel@0 {
2615e6af7f5SFei Shao		/* Compatible string for different panels can be found in each device dts */
2625e6af7f5SFei Shao		reg = <0>;
2635e6af7f5SFei Shao		enable-gpios = <&pio 25 GPIO_ACTIVE_HIGH>;
2645e6af7f5SFei Shao		pinctrl-names = "default";
2655e6af7f5SFei Shao		pinctrl-0 = <&mipi_dsi_pins>;
2665e6af7f5SFei Shao
2675e6af7f5SFei Shao		backlight = <&backlight_lcd0>;
2685e6af7f5SFei Shao		avdd-supply = <&ppvar_mipi_disp_avdd>;
2695e6af7f5SFei Shao		avee-supply = <&ppvar_mipi_disp_avee>;
2705e6af7f5SFei Shao		pp1800-supply = <&mt6359_vm18_ldo_reg>;
2715e6af7f5SFei Shao		rotation = <270>;
2725e6af7f5SFei Shao
2735e6af7f5SFei Shao		status = "okay";
2745e6af7f5SFei Shao
2755e6af7f5SFei Shao		port {
2765e6af7f5SFei Shao			dsi_panel_in: endpoint {
277*383c2ac3SAngeloGioacchino Del Regno				remote-endpoint = <&dsi0_out>;
2785e6af7f5SFei Shao			};
2795e6af7f5SFei Shao		};
2805e6af7f5SFei Shao	};
2815e6af7f5SFei Shao
282*383c2ac3SAngeloGioacchino Del Regno	ports {
283*383c2ac3SAngeloGioacchino Del Regno		#address-cells = <1>;
284*383c2ac3SAngeloGioacchino Del Regno		#size-cells = <0>;
285*383c2ac3SAngeloGioacchino Del Regno
286*383c2ac3SAngeloGioacchino Del Regno		port@0 {
287*383c2ac3SAngeloGioacchino Del Regno			reg = <0>;
288*383c2ac3SAngeloGioacchino Del Regno			dsi0_in: endpoint {
289*383c2ac3SAngeloGioacchino Del Regno				remote-endpoint = <&dither0_out>;
290*383c2ac3SAngeloGioacchino Del Regno			};
291*383c2ac3SAngeloGioacchino Del Regno		};
292*383c2ac3SAngeloGioacchino Del Regno
293*383c2ac3SAngeloGioacchino Del Regno		port@1 {
294*383c2ac3SAngeloGioacchino Del Regno			reg = <1>;
295*383c2ac3SAngeloGioacchino Del Regno			dsi0_out: endpoint {
2965e6af7f5SFei Shao				remote-endpoint = <&dsi_panel_in>;
2975e6af7f5SFei Shao			};
2985e6af7f5SFei Shao		};
2995e6af7f5SFei Shao	};
300*383c2ac3SAngeloGioacchino Del Regno};
3015e6af7f5SFei Shao
3025e6af7f5SFei Shao&disp_pwm0 {
3035e6af7f5SFei Shao	pinctrl-names = "default";
3045e6af7f5SFei Shao	pinctrl-0 = <&disp_pwm0_pins>;
3055e6af7f5SFei Shao	status = "okay";
3065e6af7f5SFei Shao};
3075e6af7f5SFei Shao
3085e6af7f5SFei Shao&disp_pwm1 {
3095e6af7f5SFei Shao	pinctrl-names = "default";
3105e6af7f5SFei Shao	pinctrl-0 = <&disp_pwm1_pins>;
3115e6af7f5SFei Shao};
3125e6af7f5SFei Shao
313*383c2ac3SAngeloGioacchino Del Regno&dither0_in {
314*383c2ac3SAngeloGioacchino Del Regno	remote-endpoint = <&postmask0_out>;
315*383c2ac3SAngeloGioacchino Del Regno};
316*383c2ac3SAngeloGioacchino Del Regno
317*383c2ac3SAngeloGioacchino Del Regno&dither0_out {
318*383c2ac3SAngeloGioacchino Del Regno	remote-endpoint = <&dsi0_in>;
319*383c2ac3SAngeloGioacchino Del Regno};
320*383c2ac3SAngeloGioacchino Del Regno
321*383c2ac3SAngeloGioacchino Del Regno&ethdr0 {
322*383c2ac3SAngeloGioacchino Del Regno	ports {
323*383c2ac3SAngeloGioacchino Del Regno		#address-cells = <1>;
324*383c2ac3SAngeloGioacchino Del Regno		#size-cells = <0>;
325*383c2ac3SAngeloGioacchino Del Regno
326*383c2ac3SAngeloGioacchino Del Regno		port@0 {
327*383c2ac3SAngeloGioacchino Del Regno			#address-cells = <1>;
328*383c2ac3SAngeloGioacchino Del Regno			#size-cells = <0>;
329*383c2ac3SAngeloGioacchino Del Regno			reg = <0>;
330*383c2ac3SAngeloGioacchino Del Regno
331*383c2ac3SAngeloGioacchino Del Regno			ethdr0_in: endpoint@1 {
332*383c2ac3SAngeloGioacchino Del Regno				reg = <1>;
333*383c2ac3SAngeloGioacchino Del Regno				remote-endpoint = <&vdosys1_ep_ext>;
334*383c2ac3SAngeloGioacchino Del Regno			};
335*383c2ac3SAngeloGioacchino Del Regno		};
336*383c2ac3SAngeloGioacchino Del Regno
337*383c2ac3SAngeloGioacchino Del Regno		port@1 {
338*383c2ac3SAngeloGioacchino Del Regno			#address-cells = <1>;
339*383c2ac3SAngeloGioacchino Del Regno			#size-cells = <0>;
340*383c2ac3SAngeloGioacchino Del Regno			reg = <1>;
341*383c2ac3SAngeloGioacchino Del Regno
342*383c2ac3SAngeloGioacchino Del Regno			ethdr0_out: endpoint@1 {
343*383c2ac3SAngeloGioacchino Del Regno				reg = <1>;
344*383c2ac3SAngeloGioacchino Del Regno				remote-endpoint = <&merge5_in>;
345*383c2ac3SAngeloGioacchino Del Regno			};
346*383c2ac3SAngeloGioacchino Del Regno		};
347*383c2ac3SAngeloGioacchino Del Regno	};
348*383c2ac3SAngeloGioacchino Del Regno};
349*383c2ac3SAngeloGioacchino Del Regno
350*383c2ac3SAngeloGioacchino Del Regno&gamma0_out {
351*383c2ac3SAngeloGioacchino Del Regno	remote-endpoint = <&postmask0_in>;
352*383c2ac3SAngeloGioacchino Del Regno};
353*383c2ac3SAngeloGioacchino Del Regno
3545e6af7f5SFei Shao&dp_intf1 {
3555e6af7f5SFei Shao	status = "okay";
3565e6af7f5SFei Shao
357*383c2ac3SAngeloGioacchino Del Regno	ports {
358*383c2ac3SAngeloGioacchino Del Regno		#address-cells = <1>;
359*383c2ac3SAngeloGioacchino Del Regno		#size-cells = <0>;
360*383c2ac3SAngeloGioacchino Del Regno
361*383c2ac3SAngeloGioacchino Del Regno		port@0 {
362*383c2ac3SAngeloGioacchino Del Regno			#address-cells = <1>;
363*383c2ac3SAngeloGioacchino Del Regno			#size-cells = <0>;
364*383c2ac3SAngeloGioacchino Del Regno			reg = <0>;
365*383c2ac3SAngeloGioacchino Del Regno
366*383c2ac3SAngeloGioacchino Del Regno			dp_intf1_in: endpoint@1 {
367*383c2ac3SAngeloGioacchino Del Regno				reg = <1>;
368*383c2ac3SAngeloGioacchino Del Regno				remote-endpoint = <&merge5_out>;
369*383c2ac3SAngeloGioacchino Del Regno			};
370*383c2ac3SAngeloGioacchino Del Regno		};
371*383c2ac3SAngeloGioacchino Del Regno
372*383c2ac3SAngeloGioacchino Del Regno		port@1 {
373*383c2ac3SAngeloGioacchino Del Regno			#address-cells = <1>;
374*383c2ac3SAngeloGioacchino Del Regno			#size-cells = <0>;
375*383c2ac3SAngeloGioacchino Del Regno			reg = <1>;
376*383c2ac3SAngeloGioacchino Del Regno
377*383c2ac3SAngeloGioacchino Del Regno			dp_intf1_out: endpoint@1 {
378*383c2ac3SAngeloGioacchino Del Regno				reg = <1>;
3795e6af7f5SFei Shao				remote-endpoint = <&dptx_in>;
3805e6af7f5SFei Shao			};
3815e6af7f5SFei Shao		};
3825e6af7f5SFei Shao	};
383*383c2ac3SAngeloGioacchino Del Regno};
3845e6af7f5SFei Shao
3855e6af7f5SFei Shao&dp_tx {
3865e6af7f5SFei Shao	pinctrl-names = "default";
3875e6af7f5SFei Shao	pinctrl-0 = <&dp_tx_hpd>;
3885e6af7f5SFei Shao	#sound-dai-cells = <0>;
3895e6af7f5SFei Shao	status = "okay";
3905e6af7f5SFei Shao
3915e6af7f5SFei Shao	ports {
3925e6af7f5SFei Shao		#address-cells = <1>;
3935e6af7f5SFei Shao		#size-cells = <0>;
3945e6af7f5SFei Shao
3955e6af7f5SFei Shao		port@0 {
3965e6af7f5SFei Shao			reg = <0>;
3975e6af7f5SFei Shao			dptx_in: endpoint {
3985e6af7f5SFei Shao				remote-endpoint = <&dp_intf1_out>;
3995e6af7f5SFei Shao			};
4005e6af7f5SFei Shao		};
4015e6af7f5SFei Shao
4025e6af7f5SFei Shao		port@1 {
4035e6af7f5SFei Shao			reg = <1>;
4045e6af7f5SFei Shao			dptx_out: endpoint {
4055e6af7f5SFei Shao				data-lanes = <0 1 2 3>;
4065e6af7f5SFei Shao			};
4075e6af7f5SFei Shao		};
4085e6af7f5SFei Shao	};
4095e6af7f5SFei Shao};
4105e6af7f5SFei Shao
4115e6af7f5SFei Shao&gpu {
4125e6af7f5SFei Shao	mali-supply = <&mt6359_vproc2_buck_reg>;
4135e6af7f5SFei Shao	status = "okay";
4145e6af7f5SFei Shao};
4155e6af7f5SFei Shao
4165e6af7f5SFei Shao&i2c0 {
4175e6af7f5SFei Shao	pinctrl-names = "default";
4185e6af7f5SFei Shao	pinctrl-0 = <&i2c0_pins>;
4195e6af7f5SFei Shao	clock-frequency = <400000>;
4205e6af7f5SFei Shao	status = "okay";
4215e6af7f5SFei Shao};
4225e6af7f5SFei Shao
4235e6af7f5SFei Shao&i2c1 {
4245e6af7f5SFei Shao	pinctrl-names = "default";
4255e6af7f5SFei Shao	pinctrl-0 = <&i2c1_pins>;
4265e6af7f5SFei Shao	clock-frequency = <400000>;
4275e6af7f5SFei Shao	status = "okay";
4285e6af7f5SFei Shao
4295e6af7f5SFei Shao	tpm@50 {
4305e6af7f5SFei Shao		compatible = "google,cr50";
4315e6af7f5SFei Shao		reg = <0x50>;
4325e6af7f5SFei Shao		interrupts-extended = <&pio 0 IRQ_TYPE_EDGE_RISING>;
4335e6af7f5SFei Shao		pinctrl-names = "default";
4345e6af7f5SFei Shao		pinctrl-0 = <&gsc_int>;
4355e6af7f5SFei Shao	};
4365e6af7f5SFei Shao};
4375e6af7f5SFei Shao
4385e6af7f5SFei Shao&i2c2 {
4395e6af7f5SFei Shao	pinctrl-names = "default";
4405e6af7f5SFei Shao	pinctrl-0 = <&i2c2_pins>;
4415e6af7f5SFei Shao	clock-frequency = <400000>;
4425e6af7f5SFei Shao	status = "okay";
4435e6af7f5SFei Shao};
4445e6af7f5SFei Shao
4455e6af7f5SFei Shao&i2c3 {
4465e6af7f5SFei Shao	pinctrl-names = "default";
4475e6af7f5SFei Shao	pinctrl-0 = <&i2c3_pins>;
4485e6af7f5SFei Shao	clock-frequency = <400000>;
4495e6af7f5SFei Shao	status = "okay";
4505e6af7f5SFei Shao};
4515e6af7f5SFei Shao
4525e6af7f5SFei Shao&i2c4 {
4535e6af7f5SFei Shao	pinctrl-names = "default";
4545e6af7f5SFei Shao	pinctrl-0 = <&i2c4_pins>;
4555e6af7f5SFei Shao	clock-frequency = <400000>;
4565e6af7f5SFei Shao	status = "okay";
4575e6af7f5SFei Shao};
4585e6af7f5SFei Shao
4595e6af7f5SFei Shao&i2c5 {
4605e6af7f5SFei Shao	pinctrl-names = "default";
4615e6af7f5SFei Shao	pinctrl-0 = <&i2c5_pins>;
4625e6af7f5SFei Shao	clock-frequency = <400000>;
4635e6af7f5SFei Shao	status = "okay";
4645e6af7f5SFei Shao};
4655e6af7f5SFei Shao
4665e6af7f5SFei Shao&i2c6 {
4675e6af7f5SFei Shao	pinctrl-names = "default";
4685e6af7f5SFei Shao	pinctrl-0 = <&i2c6_pins>;
4695e6af7f5SFei Shao	clock-frequency = <400000>;
4705e6af7f5SFei Shao	status = "okay";
4715e6af7f5SFei Shao};
4725e6af7f5SFei Shao
473*383c2ac3SAngeloGioacchino Del Regno&merge5 {
474*383c2ac3SAngeloGioacchino Del Regno	ports {
475*383c2ac3SAngeloGioacchino Del Regno		#address-cells = <1>;
476*383c2ac3SAngeloGioacchino Del Regno		#size-cells = <0>;
477*383c2ac3SAngeloGioacchino Del Regno
478*383c2ac3SAngeloGioacchino Del Regno		port@0 {
479*383c2ac3SAngeloGioacchino Del Regno			#address-cells = <1>;
480*383c2ac3SAngeloGioacchino Del Regno			#size-cells = <0>;
481*383c2ac3SAngeloGioacchino Del Regno			reg = <0>;
482*383c2ac3SAngeloGioacchino Del Regno
483*383c2ac3SAngeloGioacchino Del Regno			merge5_in: endpoint@1 {
484*383c2ac3SAngeloGioacchino Del Regno				reg = <1>;
485*383c2ac3SAngeloGioacchino Del Regno				remote-endpoint = <&ethdr0_out>;
486*383c2ac3SAngeloGioacchino Del Regno			};
487*383c2ac3SAngeloGioacchino Del Regno		};
488*383c2ac3SAngeloGioacchino Del Regno
489*383c2ac3SAngeloGioacchino Del Regno		port@1 {
490*383c2ac3SAngeloGioacchino Del Regno			#address-cells = <1>;
491*383c2ac3SAngeloGioacchino Del Regno			#size-cells = <0>;
492*383c2ac3SAngeloGioacchino Del Regno			reg = <1>;
493*383c2ac3SAngeloGioacchino Del Regno
494*383c2ac3SAngeloGioacchino Del Regno			merge5_out: endpoint@1 {
495*383c2ac3SAngeloGioacchino Del Regno				reg = <1>;
496*383c2ac3SAngeloGioacchino Del Regno				remote-endpoint = <&dp_intf1_in>;
497*383c2ac3SAngeloGioacchino Del Regno			};
498*383c2ac3SAngeloGioacchino Del Regno		};
499*383c2ac3SAngeloGioacchino Del Regno	};
500*383c2ac3SAngeloGioacchino Del Regno};
501*383c2ac3SAngeloGioacchino Del Regno
5025e6af7f5SFei Shao&mfg0 {
5035e6af7f5SFei Shao	domain-supply = <&mt6359_vproc2_buck_reg>;
5045e6af7f5SFei Shao};
5055e6af7f5SFei Shao
5065e6af7f5SFei Shao&mfg1 {
5075e6af7f5SFei Shao	domain-supply = <&mt6359_vsram_others_ldo_reg>;
5085e6af7f5SFei Shao};
5095e6af7f5SFei Shao
5105e6af7f5SFei Shao&mipi_tx_config0 {
5115e6af7f5SFei Shao	status = "okay";
5125e6af7f5SFei Shao};
5135e6af7f5SFei Shao
5145e6af7f5SFei Shao&mmc0 {
5155e6af7f5SFei Shao	bus-width = <8>;
5165e6af7f5SFei Shao	cap-mmc-highspeed;
5175e6af7f5SFei Shao	cap-mmc-hw-reset;
5185e6af7f5SFei Shao	hs400-ds-delay = <0x1481b>;
5195e6af7f5SFei Shao	max-frequency = <200000000>;
5205e6af7f5SFei Shao	mmc-hs200-1_8v;
5215e6af7f5SFei Shao	mmc-hs400-1_8v;
5225e6af7f5SFei Shao	mmc-hs400-enhanced-strobe;
5235e6af7f5SFei Shao	no-sd;
5245e6af7f5SFei Shao	no-sdio;
5255e6af7f5SFei Shao	non-removable;
5265e6af7f5SFei Shao	pinctrl-names = "default", "state_uhs";
5275e6af7f5SFei Shao	pinctrl-0 = <&mmc0_pins_default>;
5285e6af7f5SFei Shao	pinctrl-1 = <&mmc0_pins_uhs>;
5295e6af7f5SFei Shao	supports-cqe;
5305e6af7f5SFei Shao	vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
5315e6af7f5SFei Shao	vqmmc-supply = <&mt6359_vufs_ldo_reg>;
5325e6af7f5SFei Shao	status = "okay";
5335e6af7f5SFei Shao};
5345e6af7f5SFei Shao
5355e6af7f5SFei Shao&mt6359codec {
5365e6af7f5SFei Shao	mediatek,dmic-mode = <1>; /* one-wire */
5375e6af7f5SFei Shao	mediatek,mic-type-0 = <2>; /* DMIC */
5385e6af7f5SFei Shao	mediatek,mic-type-2 = <2>; /* DMIC */
5395e6af7f5SFei Shao};
5405e6af7f5SFei Shao
5415e6af7f5SFei Shao&mt6359_vcore_buck_reg {
5425e6af7f5SFei Shao	regulator-always-on;
5435e6af7f5SFei Shao};
5445e6af7f5SFei Shao
5455e6af7f5SFei Shao&mt6359_vgpu11_buck_reg {
5465e6af7f5SFei Shao	regulator-always-on;
5475e6af7f5SFei Shao};
5485e6af7f5SFei Shao
5495e6af7f5SFei Shao&mt6359_vgpu11_sshub_buck_reg {
5505e6af7f5SFei Shao	regulator-min-microvolt = <550000>;
5515e6af7f5SFei Shao	regulator-max-microvolt = <550000>;
5525e6af7f5SFei Shao	regulator-always-on;
5535e6af7f5SFei Shao};
5545e6af7f5SFei Shao
5555e6af7f5SFei Shao&mt6359_vio28_ldo_reg {
5565e6af7f5SFei Shao	/delete-property/ regulator-always-on;
5575e6af7f5SFei Shao};
5585e6af7f5SFei Shao
5595e6af7f5SFei Shao&mt6359_vm18_ldo_reg {
5605e6af7f5SFei Shao	/delete-property/ regulator-always-on;
5615e6af7f5SFei Shao};
5625e6af7f5SFei Shao
5635e6af7f5SFei Shao&mt6359_vmodem_buck_reg {
5645e6af7f5SFei Shao	regulator-min-microvolt = <775000>;
5655e6af7f5SFei Shao	regulator-max-microvolt = <775000>;
5665e6af7f5SFei Shao};
5675e6af7f5SFei Shao
5685e6af7f5SFei Shao&mt6359_vpa_buck_reg {
5695e6af7f5SFei Shao	regulator-max-microvolt = <3100000>;
5705e6af7f5SFei Shao};
5715e6af7f5SFei Shao
5725e6af7f5SFei Shao&mt6359_vproc2_buck_reg {
5735e6af7f5SFei Shao	/*
5745e6af7f5SFei Shao	 * Called "ppvar_dvdd_gpu" in the schematic. Renamed to
5755e6af7f5SFei Shao	 * "ppvar_dvdd_vgpu" here to match mtk-regulator-coupler requirements.
5765e6af7f5SFei Shao	 */
5775e6af7f5SFei Shao	regulator-name = "ppvar_dvdd_vgpu";
5785e6af7f5SFei Shao	regulator-min-microvolt = <550000>;
5795e6af7f5SFei Shao	regulator-max-microvolt = <800000>;
5805e6af7f5SFei Shao	regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>;
5815e6af7f5SFei Shao	regulator-coupled-max-spread = <6250>;
5825e6af7f5SFei Shao};
5835e6af7f5SFei Shao
5845e6af7f5SFei Shao&mt6359_vpu_buck_reg {
5855e6af7f5SFei Shao	regulator-always-on;
5865e6af7f5SFei Shao};
5875e6af7f5SFei Shao
5885e6af7f5SFei Shao&mt6359_vrf12_ldo_reg {
5895e6af7f5SFei Shao	regulator-always-on;
5905e6af7f5SFei Shao};
5915e6af7f5SFei Shao
5925e6af7f5SFei Shao&mt6359_vsram_md_ldo_reg {
5935e6af7f5SFei Shao	regulator-min-microvolt = <800000>;
5945e6af7f5SFei Shao	regulator-max-microvolt = <800000>;
5955e6af7f5SFei Shao};
5965e6af7f5SFei Shao
5975e6af7f5SFei Shao&mt6359_vsram_others_ldo_reg {
5985e6af7f5SFei Shao	regulator-name = "pp0850_dvdd_sram_gpu";
5995e6af7f5SFei Shao	regulator-min-microvolt = <750000>;
6005e6af7f5SFei Shao	regulator-max-microvolt = <800000>;
6015e6af7f5SFei Shao	regulator-coupled-with = <&mt6359_vproc2_buck_reg>;
6025e6af7f5SFei Shao	regulator-coupled-max-spread = <6250>;
6035e6af7f5SFei Shao};
6045e6af7f5SFei Shao
6055e6af7f5SFei Shao&mt6359_vufs_ldo_reg {
6065e6af7f5SFei Shao	regulator-always-on;
6075e6af7f5SFei Shao};
6085e6af7f5SFei Shao
6095e6af7f5SFei Shao&nor_flash {
6105e6af7f5SFei Shao	pinctrl-names = "default";
6115e6af7f5SFei Shao	pinctrl-0 = <&nor_pins>;
6125e6af7f5SFei Shao	status = "okay";
6135e6af7f5SFei Shao
6145e6af7f5SFei Shao	flash@0 {
6155e6af7f5SFei Shao		compatible = "jedec,spi-nor";
6165e6af7f5SFei Shao		reg = <0>;
6175e6af7f5SFei Shao		spi-max-frequency = <52000000>;
6185e6af7f5SFei Shao	};
6195e6af7f5SFei Shao};
6205e6af7f5SFei Shao
621*383c2ac3SAngeloGioacchino Del Regno&ovl0_in {
622*383c2ac3SAngeloGioacchino Del Regno	remote-endpoint = <&vdosys0_ep_main>;
623*383c2ac3SAngeloGioacchino Del Regno};
624*383c2ac3SAngeloGioacchino Del Regno
6255e6af7f5SFei Shao&pcie {
6265e6af7f5SFei Shao	pinctrl-names = "default";
6275e6af7f5SFei Shao	pinctrl-0 = <&pcie_pins>;
6285e6af7f5SFei Shao	status = "okay";
6295e6af7f5SFei Shao};
6305e6af7f5SFei Shao
6315e6af7f5SFei Shao&pciephy {
6325e6af7f5SFei Shao	status = "okay";
6335e6af7f5SFei Shao};
6345e6af7f5SFei Shao
6355e6af7f5SFei Shao&pio {
6365e6af7f5SFei Shao	gpio-line-names =
6375e6af7f5SFei Shao		"gsc_int",
6385e6af7f5SFei Shao		"AP_DISP_BKLTEN",
6395e6af7f5SFei Shao		"",
6405e6af7f5SFei Shao		"EN_PPVAR_MIPI_DISP",
6415e6af7f5SFei Shao		"EN_PPVAR_MIPI_DISP_150MA",
6425e6af7f5SFei Shao		"TCHSCR_RST_1V8_L",
6435e6af7f5SFei Shao		"TCHSRC_REPORT_DISABLE",
6445e6af7f5SFei Shao		"",
6455e6af7f5SFei Shao		"",
6465e6af7f5SFei Shao		"",
6475e6af7f5SFei Shao		"",
6485e6af7f5SFei Shao		"I2S_SPKR_DATAOUT",
6495e6af7f5SFei Shao		"EN_PP3300_WLAN_X",
6505e6af7f5SFei Shao		"WIFI_KILL_1V8_L",
6515e6af7f5SFei Shao		"BT_KILL_1V8_L",
6525e6af7f5SFei Shao		"AP_FLASH_WP_L", /* ... is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */
6535e6af7f5SFei Shao		"",
6545e6af7f5SFei Shao		"EDP_HPD_1V8",
6555e6af7f5SFei Shao		"WCAM_PWDN_L",
6565e6af7f5SFei Shao		"WCAM_RST_L",
6575e6af7f5SFei Shao		"UCAM_PWDM_L",
6585e6af7f5SFei Shao		"UCAM_RST_L",
6595e6af7f5SFei Shao		"WCAM_24M_CLK",
6605e6af7f5SFei Shao		"UCAM_24M_CLK",
6615e6af7f5SFei Shao		"MT6319_INT",
6625e6af7f5SFei Shao		"DISP_RST_1V8_L",
6635e6af7f5SFei Shao		"DSIO_DSI_TE",
6645e6af7f5SFei Shao		"EN_PP3300_EDP_DISP_X",
6655e6af7f5SFei Shao		"TP",
6665e6af7f5SFei Shao		"MIPI_BL_PWM_1V8",
6675e6af7f5SFei Shao		"EDP_BL_PWM_1V8",
6685e6af7f5SFei Shao		"UART_AP_TX_GSC_RX",
6695e6af7f5SFei Shao		"UART_GSC_TX_AP_RX",
6705e6af7f5SFei Shao		"UART_SSPM_TX_DBGCON_RX",
6715e6af7f5SFei Shao		"UART_DBGCON_TX_SSPM_RX",
6725e6af7f5SFei Shao		"UART_ADSP_TX_DBGCON_RX",
6735e6af7f5SFei Shao		"UART_DBGCON_TX_ADSP_RX",
6745e6af7f5SFei Shao		"JTAG_AP_TMS",
6755e6af7f5SFei Shao		"JTAG_AP_TCK",
6765e6af7f5SFei Shao		"JTAG_AP_TDI",
6775e6af7f5SFei Shao		"JTAG_AP_TDO",
6785e6af7f5SFei Shao		"JTAG_AP_TRST",
6795e6af7f5SFei Shao		"AP_KPCOL0",
6805e6af7f5SFei Shao		"TP",
6815e6af7f5SFei Shao		"BEEP_ON_OD",
6825e6af7f5SFei Shao		"TP",
6835e6af7f5SFei Shao		"EC_AP_HPD_OD",
6845e6af7f5SFei Shao		"PCIE_WAKE_1V8_ODL",
6855e6af7f5SFei Shao		"PCIE_RST_1V8_L",
6865e6af7f5SFei Shao		"PCIE_CLKREQ_1V8_ODL",
6875e6af7f5SFei Shao		"",
6885e6af7f5SFei Shao		"",
6895e6af7f5SFei Shao		"",
6905e6af7f5SFei Shao		"",
6915e6af7f5SFei Shao		"",
6925e6af7f5SFei Shao		"AP_I2C_AUD_SCL_1V8",
6935e6af7f5SFei Shao		"AP_I2C_AUD_SDA_1V8",
6945e6af7f5SFei Shao		"AP_I2C_TPM_SCL_1V8",
6955e6af7f5SFei Shao		"AP_I2C_TPM_SDA_1V8",
6965e6af7f5SFei Shao		"AP_I2C_TCHSCR_SCL_1V8",
6975e6af7f5SFei Shao		"AP_I2C_TCHSCR_SDA_1V8",
6985e6af7f5SFei Shao		"AP_I2C_PMIC_SAR_SCL_1V8",
6995e6af7f5SFei Shao		"AP_I2C_PMIC_SAR_SDA_1V8",
7005e6af7f5SFei Shao		"AP_I2C_EC_HID_KB_SCL_1V8",
7015e6af7f5SFei Shao		"AP_I2C_EC_HID_KB_SDA_1V8",
7025e6af7f5SFei Shao		"AP_I2C_UCAM_SCL_1V8",
7035e6af7f5SFei Shao		"AP_I2C_UCAM_SDA_1V8",
7045e6af7f5SFei Shao		"AP_I2C_WCAM_SCL_1V8",
7055e6af7f5SFei Shao		"AP_I2C_WCAM_SDA_1V8",
7065e6af7f5SFei Shao		"SPI_AP_CS_EC_L",
7075e6af7f5SFei Shao		"SPI_AP_CLK_EC",
7085e6af7f5SFei Shao		"SPI_AP_DO_EC_DI",
7095e6af7f5SFei Shao		"SPI_AP_DI_EC_DO",
7105e6af7f5SFei Shao		"TP",
7115e6af7f5SFei Shao		"TP",
7125e6af7f5SFei Shao		"SPI_AP_CS_TCHSCR_L",
7135e6af7f5SFei Shao		"SPI_AP_CLK_TCHSCR",
7145e6af7f5SFei Shao		"SPI_AP_DO_TCHSCR_DI",
7155e6af7f5SFei Shao		"SPI_AP_DI_TCHSCR_DO",
7165e6af7f5SFei Shao		"TP",
7175e6af7f5SFei Shao		"TP",
7185e6af7f5SFei Shao		"TP",
7195e6af7f5SFei Shao		"TP",
7205e6af7f5SFei Shao		"",
7215e6af7f5SFei Shao		"",
7225e6af7f5SFei Shao		"",
7235e6af7f5SFei Shao		"TP",
7245e6af7f5SFei Shao		"",
7255e6af7f5SFei Shao		"SAR_INT_ODL",
7265e6af7f5SFei Shao		"",
7275e6af7f5SFei Shao		"",
7285e6af7f5SFei Shao		"",
7295e6af7f5SFei Shao		"PWRAP_SPI_CS_L",
7305e6af7f5SFei Shao		"PWRAP_SPI_CK",
7315e6af7f5SFei Shao		"PWRAP_SPI_MOSI",
7325e6af7f5SFei Shao		"PWRAP_SPI_MISO",
7335e6af7f5SFei Shao		"SRCLKENA0",
7345e6af7f5SFei Shao		"SRCLKENA1",
7355e6af7f5SFei Shao		"SCP_VREQ_VAO",
7365e6af7f5SFei Shao		"AP_RTC_CLK32K",
7375e6af7f5SFei Shao		"AP_PMIC_WDTRST_L",
7385e6af7f5SFei Shao		"AUD_CLK_MOSI",
7395e6af7f5SFei Shao		"AUD_SYNC_MOSI",
7405e6af7f5SFei Shao		"AUD_DAT_MOSI0",
7415e6af7f5SFei Shao		"AUD_DAT_MOSI1",
7425e6af7f5SFei Shao		"AUD_DAT_MISO0",
7435e6af7f5SFei Shao		"AUD_DAT_MISO1",
7445e6af7f5SFei Shao		"SD_CD_ODL",
7455e6af7f5SFei Shao		"HP_INT_ODL",
7465e6af7f5SFei Shao		"SPKR_INT_ODL",
7475e6af7f5SFei Shao		"I2S_HP_DATAIN",
7485e6af7f5SFei Shao		"EN_SPKR",
7495e6af7f5SFei Shao		"I2S_SPKR_MCLK",
7505e6af7f5SFei Shao		"I2S_SPKR_BCLK",
7515e6af7f5SFei Shao		"I2S_HP_MCLK",
7525e6af7f5SFei Shao		"I2S_HP_BCLK",
7535e6af7f5SFei Shao		"I2S_HP_LRCK",
7545e6af7f5SFei Shao		"I2S_HP_DATAOUT",
7555e6af7f5SFei Shao		"RST_SPKR_L",
7565e6af7f5SFei Shao		"I2S_SPKR_LRCK",
7575e6af7f5SFei Shao		"I2S_SPKR_DATAIN",
7585e6af7f5SFei Shao		"",
7595e6af7f5SFei Shao		"",
7605e6af7f5SFei Shao		"",
7615e6af7f5SFei Shao		"",
7625e6af7f5SFei Shao		"SPI_AP_CLK_ROM",
7635e6af7f5SFei Shao		"SPI_AP_CS_ROM_L",
7645e6af7f5SFei Shao		"SPI_AP_DO_ROM_DI",
7655e6af7f5SFei Shao		"SPI_AP_DI_ROM_DO",
7665e6af7f5SFei Shao		"TP",
7675e6af7f5SFei Shao		"TP",
7685e6af7f5SFei Shao		"",
7695e6af7f5SFei Shao		"",
7705e6af7f5SFei Shao		"",
7715e6af7f5SFei Shao		"",
7725e6af7f5SFei Shao		"",
7735e6af7f5SFei Shao		"",
7745e6af7f5SFei Shao		"",
7755e6af7f5SFei Shao		"",
7765e6af7f5SFei Shao		"EN_PP2800A_UCAM_X",
7775e6af7f5SFei Shao		"EN_PP1200_UCAM_X",
7785e6af7f5SFei Shao		"EN_PP2800A_WCAM_X",
7795e6af7f5SFei Shao		"EN_PP1100_WCAM_X",
7805e6af7f5SFei Shao		"TCHSCR_INT_1V8_L",
7815e6af7f5SFei Shao		"EN_PP3300_MIPI_TCHSCR_X",
7825e6af7f5SFei Shao		"MT7921_PMU_EN_1V8",
7835e6af7f5SFei Shao		"EN_PP3300_EDP_TCHSCR_X",
7845e6af7f5SFei Shao		"AP_EC_WARM_RST_REQ",
7855e6af7f5SFei Shao		"EC_AP_HID_INT_ODL",
7865e6af7f5SFei Shao		"EC_AP_INT_ODL",
7875e6af7f5SFei Shao		"AP_XHCI_INIT_DONE",
7885e6af7f5SFei Shao		"EMMC_DAT7",
7895e6af7f5SFei Shao		"EMMC_DAT6",
7905e6af7f5SFei Shao		"EMMC_DAT5",
7915e6af7f5SFei Shao		"EMMC_DAT4",
7925e6af7f5SFei Shao		"EMMC_RST_L",
7935e6af7f5SFei Shao		"EMMC_CMD",
7945e6af7f5SFei Shao		"EMMC_CLK",
7955e6af7f5SFei Shao		"EMMC_DAT3",
7965e6af7f5SFei Shao		"EMMC_DAT2",
7975e6af7f5SFei Shao		"EMMC_DAT1",
7985e6af7f5SFei Shao		"EMMC_DAT0",
7995e6af7f5SFei Shao		"EMMC_DSL",
8005e6af7f5SFei Shao		"SD_CMD",
8015e6af7f5SFei Shao		"SD_CLK",
8025e6af7f5SFei Shao		"SD_DAT0",
8035e6af7f5SFei Shao		"SD_DAT1",
8045e6af7f5SFei Shao		"SD_DAT2",
8055e6af7f5SFei Shao		"SD_DAT3",
8065e6af7f5SFei Shao		"",
8075e6af7f5SFei Shao		"",
8085e6af7f5SFei Shao		"USB3_HUB_RST_L",
8095e6af7f5SFei Shao		"EC_AP_RSVD0_ODL",
8105e6af7f5SFei Shao		"",
8115e6af7f5SFei Shao		"",
8125e6af7f5SFei Shao		"SPMI_SCL",
8135e6af7f5SFei Shao		"SPMI_SDA";
8145e6af7f5SFei Shao
8155e6af7f5SFei Shao	adsp_uart_pins: adsp-uart-pins {
8165e6af7f5SFei Shao		pins-bus {
8175e6af7f5SFei Shao			pinmux = <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>,
8185e6af7f5SFei Shao				 <PINMUX_GPIO36__FUNC_I1_ADSP_URXD0>;
8195e6af7f5SFei Shao		};
8205e6af7f5SFei Shao	};
8215e6af7f5SFei Shao
8225e6af7f5SFei Shao	aud_etdm_hp_on: aud-etdm-hp-on-pins {
8235e6af7f5SFei Shao		pins-bus {
8245e6af7f5SFei Shao			pinmux = <PINMUX_GPIO110__FUNC_I0_I2SIN_D0>,
8255e6af7f5SFei Shao				 <PINMUX_GPIO115__FUNC_B0_I2SO2_BCK>,
8265e6af7f5SFei Shao				 <PINMUX_GPIO116__FUNC_B0_I2SO2_WS>,
8275e6af7f5SFei Shao				 <PINMUX_GPIO117__FUNC_O_I2SO2_D0>;
8285e6af7f5SFei Shao		};
8295e6af7f5SFei Shao	};
8305e6af7f5SFei Shao
8315e6af7f5SFei Shao	aud_etdm_hp_off: aud-etdm-hp-off-pins {
8325e6af7f5SFei Shao		pins-bus {
8335e6af7f5SFei Shao			pinmux = <PINMUX_GPIO110__FUNC_B_GPIO110>,
8345e6af7f5SFei Shao				 <PINMUX_GPIO115__FUNC_B_GPIO115>,
8355e6af7f5SFei Shao				 <PINMUX_GPIO116__FUNC_B_GPIO116>,
8365e6af7f5SFei Shao				 <PINMUX_GPIO117__FUNC_B_GPIO117>;
8375e6af7f5SFei Shao			bias-pull-down;
8385e6af7f5SFei Shao			input-enable;
8395e6af7f5SFei Shao		};
8405e6af7f5SFei Shao	};
8415e6af7f5SFei Shao
8425e6af7f5SFei Shao	aud_etdm_spk_on: aud-etdm-spk-on-pins {
8435e6af7f5SFei Shao		pins-bus {
8445e6af7f5SFei Shao			pinmux = <PINMUX_GPIO11__FUNC_O_I2SO1_D0>,
8455e6af7f5SFei Shao				 <PINMUX_GPIO113__FUNC_B0_TDMIN_BCK>,
8465e6af7f5SFei Shao				 <PINMUX_GPIO119__FUNC_B0_TDMIN_LRCK>,
8475e6af7f5SFei Shao				 <PINMUX_GPIO120__FUNC_I0_TDMIN_DI>;
8485e6af7f5SFei Shao			drive-strength = <8>;
8495e6af7f5SFei Shao		};
8505e6af7f5SFei Shao	};
8515e6af7f5SFei Shao
8525e6af7f5SFei Shao	aud_etdm_spk_off: aud-etdm-spk-off-pins {
8535e6af7f5SFei Shao		pins-bus {
8545e6af7f5SFei Shao			pinmux = <PINMUX_GPIO11__FUNC_B_GPIO11>,
8555e6af7f5SFei Shao				 <PINMUX_GPIO113__FUNC_B_GPIO113>,
8565e6af7f5SFei Shao				 <PINMUX_GPIO119__FUNC_B_GPIO119>,
8575e6af7f5SFei Shao				 <PINMUX_GPIO120__FUNC_B_GPIO120>;
8585e6af7f5SFei Shao			bias-pull-down;
8595e6af7f5SFei Shao			input-enable;
8605e6af7f5SFei Shao		};
8615e6af7f5SFei Shao	};
8625e6af7f5SFei Shao
8635e6af7f5SFei Shao	aud_mtkaif_on: aud-mtkaif-on-pins {
8645e6af7f5SFei Shao		pins-bus {
8655e6af7f5SFei Shao			pinmux = <PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI>,
8665e6af7f5SFei Shao				 <PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI>,
8675e6af7f5SFei Shao				 <PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0>,
8685e6af7f5SFei Shao				 <PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1>,
8695e6af7f5SFei Shao				 <PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0>,
8705e6af7f5SFei Shao				 <PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1>;
8715e6af7f5SFei Shao		};
8725e6af7f5SFei Shao	};
8735e6af7f5SFei Shao
8745e6af7f5SFei Shao	aud_mtkaif_off: aud-mtkaif-off-pins {
8755e6af7f5SFei Shao		pins-bus {
8765e6af7f5SFei Shao			pinmux = <PINMUX_GPIO101__FUNC_B_GPIO101>,
8775e6af7f5SFei Shao				 <PINMUX_GPIO102__FUNC_B_GPIO102>,
8785e6af7f5SFei Shao				 <PINMUX_GPIO103__FUNC_B_GPIO103>,
8795e6af7f5SFei Shao				 <PINMUX_GPIO104__FUNC_B_GPIO104>,
8805e6af7f5SFei Shao				 <PINMUX_GPIO105__FUNC_B_GPIO105>,
8815e6af7f5SFei Shao				 <PINMUX_GPIO106__FUNC_B_GPIO106>;
8825e6af7f5SFei Shao			bias-pull-down;
8835e6af7f5SFei Shao			input-enable;
8845e6af7f5SFei Shao		};
8855e6af7f5SFei Shao	};
8865e6af7f5SFei Shao
8875e6af7f5SFei Shao	cros_ec_int: cros-ec-int-pins {
8885e6af7f5SFei Shao		pins-ec-ap-int-odl {
8895e6af7f5SFei Shao			pinmux = <PINMUX_GPIO149__FUNC_B_GPIO149>;
8905e6af7f5SFei Shao			input-enable;
8915e6af7f5SFei Shao		};
8925e6af7f5SFei Shao	};
8935e6af7f5SFei Shao
8945e6af7f5SFei Shao	disp_pwm0_pins: disp-pwm0-pins {
8955e6af7f5SFei Shao		pins-disp-pwm0 {
8965e6af7f5SFei Shao			pinmux = <PINMUX_GPIO29__FUNC_O_DISP_PWM0>;
8975e6af7f5SFei Shao			output-high;
8985e6af7f5SFei Shao		};
8995e6af7f5SFei Shao	};
9005e6af7f5SFei Shao
9015e6af7f5SFei Shao	disp_pwm1_pins: disp-pwm1-pins {
9025e6af7f5SFei Shao		pins-disp-pwm1 {
9035e6af7f5SFei Shao			pinmux = <PINMUX_GPIO30__FUNC_O_DISP_PWM1>;
9045e6af7f5SFei Shao			output-high;
9055e6af7f5SFei Shao		};
9065e6af7f5SFei Shao	};
9075e6af7f5SFei Shao
9085e6af7f5SFei Shao	dp_tx_hpd: dp-tx-hpd-pins {
9095e6af7f5SFei Shao		pins-dp-tx-hpd {
9105e6af7f5SFei Shao			pinmux = <PINMUX_GPIO46__FUNC_I0_DP_TX_HPD>;
9115e6af7f5SFei Shao		};
9125e6af7f5SFei Shao	};
9135e6af7f5SFei Shao
9145e6af7f5SFei Shao	gsc_int: gsc-int-pins {
9155e6af7f5SFei Shao		pins-gsc-ap-int-odl {
9165e6af7f5SFei Shao			pinmux = <PINMUX_GPIO0__FUNC_B_GPIO0>;
9175e6af7f5SFei Shao			input-enable;
9185e6af7f5SFei Shao		};
9195e6af7f5SFei Shao	};
9205e6af7f5SFei Shao
9215e6af7f5SFei Shao	i2c0_pins: i2c0-pins {
9225e6af7f5SFei Shao		pins-bus {
9235e6af7f5SFei Shao			pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>,
9245e6af7f5SFei Shao				 <PINMUX_GPIO55__FUNC_B1_SCL0>;
9255e6af7f5SFei Shao		};
9265e6af7f5SFei Shao	};
9275e6af7f5SFei Shao
9285e6af7f5SFei Shao	i2c1_pins: i2c1-pins {
9295e6af7f5SFei Shao		pins-bus {
9305e6af7f5SFei Shao			pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>,
9315e6af7f5SFei Shao				 <PINMUX_GPIO57__FUNC_B1_SCL1>;
9325e6af7f5SFei Shao		};
9335e6af7f5SFei Shao	};
9345e6af7f5SFei Shao
9355e6af7f5SFei Shao	i2c2_pins: i2c2-pins {
9365e6af7f5SFei Shao		pins-bus {
9375e6af7f5SFei Shao			pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>,
9385e6af7f5SFei Shao				 <PINMUX_GPIO59__FUNC_B1_SCL2>;
9395e6af7f5SFei Shao			bias-disable;
9405e6af7f5SFei Shao			drive-strength = <12>;
9415e6af7f5SFei Shao		};
9425e6af7f5SFei Shao	};
9435e6af7f5SFei Shao
9445e6af7f5SFei Shao	i2c3_pins: i2c3-pins {
9455e6af7f5SFei Shao		pins-bus {
9465e6af7f5SFei Shao			pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>,
9475e6af7f5SFei Shao				 <PINMUX_GPIO61__FUNC_B1_SCL3>;
9485e6af7f5SFei Shao		};
9495e6af7f5SFei Shao	};
9505e6af7f5SFei Shao
9515e6af7f5SFei Shao	i2c4_pins: i2c4-pins {
9525e6af7f5SFei Shao		pins-bus {
9535e6af7f5SFei Shao			pinmux = <PINMUX_GPIO64__FUNC_B1_SDA4>,
9545e6af7f5SFei Shao				 <PINMUX_GPIO63__FUNC_B1_SCL4>;
9555e6af7f5SFei Shao		};
9565e6af7f5SFei Shao	};
9575e6af7f5SFei Shao
9585e6af7f5SFei Shao	i2c5_pins: i2c5-pins {
9595e6af7f5SFei Shao		pins-bus {
9605e6af7f5SFei Shao			pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>,
9615e6af7f5SFei Shao				 <PINMUX_GPIO65__FUNC_B1_SCL5>;
9625e6af7f5SFei Shao		};
9635e6af7f5SFei Shao	};
9645e6af7f5SFei Shao
9655e6af7f5SFei Shao	i2c6_pins: i2c6-pins {
9665e6af7f5SFei Shao		pins-bus {
9675e6af7f5SFei Shao			pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>,
9685e6af7f5SFei Shao				 <PINMUX_GPIO67__FUNC_B1_SCL6>;
9695e6af7f5SFei Shao		};
9705e6af7f5SFei Shao	};
9715e6af7f5SFei Shao
9725e6af7f5SFei Shao	mipi_disp_avdd_en: mipi-disp-avdd-en-pins {
9735e6af7f5SFei Shao		pins-en-ppvar-mipi-disp {
9745e6af7f5SFei Shao			pinmux = <PINMUX_GPIO3__FUNC_B_GPIO3>;
9755e6af7f5SFei Shao			output-low;
9765e6af7f5SFei Shao		};
9775e6af7f5SFei Shao	};
9785e6af7f5SFei Shao
9795e6af7f5SFei Shao	mipi_disp_avee_en: mipi-disp-avee-en-pins {
9805e6af7f5SFei Shao		pins-en-ppvar-mipi-disp-150ma {
9815e6af7f5SFei Shao			pinmux = <PINMUX_GPIO4__FUNC_B_GPIO4>;
9825e6af7f5SFei Shao			output-low;
9835e6af7f5SFei Shao		};
9845e6af7f5SFei Shao	};
9855e6af7f5SFei Shao
9865e6af7f5SFei Shao	mipi_dsi_pins: mipi-dsi-pins {
9875e6af7f5SFei Shao		pins-bus {
9885e6af7f5SFei Shao			pinmux = <PINMUX_GPIO1__FUNC_B_GPIO1>,
9895e6af7f5SFei Shao				 <PINMUX_GPIO25__FUNC_B_GPIO25>;
9905e6af7f5SFei Shao			output-low;
9915e6af7f5SFei Shao		};
9925e6af7f5SFei Shao	};
9935e6af7f5SFei Shao
9945e6af7f5SFei Shao	mmc0_pins_default: mmc0-default-pins {
9955e6af7f5SFei Shao		pins-bus {
9965e6af7f5SFei Shao			pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
9975e6af7f5SFei Shao				 <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
9985e6af7f5SFei Shao				 <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
9995e6af7f5SFei Shao				 <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
10005e6af7f5SFei Shao				 <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
10015e6af7f5SFei Shao				 <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
10025e6af7f5SFei Shao				 <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
10035e6af7f5SFei Shao				 <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
10045e6af7f5SFei Shao				 <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
10055e6af7f5SFei Shao			input-enable;
10065e6af7f5SFei Shao			drive-strength = <6>;
10075e6af7f5SFei Shao			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
10085e6af7f5SFei Shao		};
10095e6af7f5SFei Shao
10105e6af7f5SFei Shao		pins-clk {
10115e6af7f5SFei Shao			pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
10125e6af7f5SFei Shao			drive-strength = <6>;
10135e6af7f5SFei Shao			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
10145e6af7f5SFei Shao		};
10155e6af7f5SFei Shao
10165e6af7f5SFei Shao		pins-rst {
10175e6af7f5SFei Shao			pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
10185e6af7f5SFei Shao			drive-strength = <6>;
10195e6af7f5SFei Shao			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
10205e6af7f5SFei Shao		};
10215e6af7f5SFei Shao	};
10225e6af7f5SFei Shao
10235e6af7f5SFei Shao	mmc0_pins_uhs: mmc0-uhs-pins {
10245e6af7f5SFei Shao		pins-bus {
10255e6af7f5SFei Shao			pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
10265e6af7f5SFei Shao				 <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
10275e6af7f5SFei Shao				 <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
10285e6af7f5SFei Shao				 <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
10295e6af7f5SFei Shao				 <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
10305e6af7f5SFei Shao				 <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
10315e6af7f5SFei Shao				 <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
10325e6af7f5SFei Shao				 <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
10335e6af7f5SFei Shao				 <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
10345e6af7f5SFei Shao			input-enable;
10355e6af7f5SFei Shao			drive-strength = <8>;
10365e6af7f5SFei Shao			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
10375e6af7f5SFei Shao		};
10385e6af7f5SFei Shao
10395e6af7f5SFei Shao		pins-clk {
10405e6af7f5SFei Shao			pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
10415e6af7f5SFei Shao			drive-strength = <8>;
10425e6af7f5SFei Shao			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
10435e6af7f5SFei Shao		};
10445e6af7f5SFei Shao
10455e6af7f5SFei Shao		pins-ds {
10465e6af7f5SFei Shao			pinmux = <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>;
10475e6af7f5SFei Shao			drive-strength = <8>;
10485e6af7f5SFei Shao			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
10495e6af7f5SFei Shao		};
10505e6af7f5SFei Shao
10515e6af7f5SFei Shao		pins-rst {
10525e6af7f5SFei Shao			pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
10535e6af7f5SFei Shao			drive-strength = <8>;
10545e6af7f5SFei Shao			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
10555e6af7f5SFei Shao		};
10565e6af7f5SFei Shao	};
10575e6af7f5SFei Shao
10585e6af7f5SFei Shao	nor_pins: nor-default-pins {
10595e6af7f5SFei Shao		pins-clk {
10605e6af7f5SFei Shao			pinmux = <PINMUX_GPIO127__FUNC_B0_SPINOR_IO0>,
10615e6af7f5SFei Shao				 <PINMUX_GPIO125__FUNC_O_SPINOR_CK>,
10625e6af7f5SFei Shao				 <PINMUX_GPIO128__FUNC_B0_SPINOR_IO1>;
10635e6af7f5SFei Shao			bias-pull-down;
10645e6af7f5SFei Shao		};
10655e6af7f5SFei Shao
10665e6af7f5SFei Shao		pins-cs {
10675e6af7f5SFei Shao			pinmux = <PINMUX_GPIO126__FUNC_O_SPINOR_CS>;
10685e6af7f5SFei Shao			bias-pull-up;
10695e6af7f5SFei Shao		};
10705e6af7f5SFei Shao	};
10715e6af7f5SFei Shao
10725e6af7f5SFei Shao	pcie_pins: pcie-default-pins {
10735e6af7f5SFei Shao		pins-bus {
10745e6af7f5SFei Shao			pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>,
10755e6af7f5SFei Shao				 <PINMUX_GPIO48__FUNC_O_PERSTN>,
10765e6af7f5SFei Shao				 <PINMUX_GPIO49__FUNC_B1_CLKREQN>;
10775e6af7f5SFei Shao		};
10785e6af7f5SFei Shao	};
10795e6af7f5SFei Shao
10805e6af7f5SFei Shao	spi0_pins: spi0-pins {
10815e6af7f5SFei Shao		pins-bus {
10825e6af7f5SFei Shao			pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>,
10835e6af7f5SFei Shao				 <PINMUX_GPIO70__FUNC_O_SPIM0_CLK>,
10845e6af7f5SFei Shao				 <PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI>,
10855e6af7f5SFei Shao				 <PINMUX_GPIO72__FUNC_B0_SPIM0_MISO>;
10865e6af7f5SFei Shao			bias-disable;
10875e6af7f5SFei Shao		};
10885e6af7f5SFei Shao	};
10895e6af7f5SFei Shao
10905e6af7f5SFei Shao	spi1_pins_default: spi1-default-pins {
10915e6af7f5SFei Shao		pins-bus {
10925e6af7f5SFei Shao			pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>,
10935e6af7f5SFei Shao				 <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>,
10945e6af7f5SFei Shao				 <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>,
10955e6af7f5SFei Shao				 <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>;
10965e6af7f5SFei Shao			bias-disable;
10975e6af7f5SFei Shao		};
10985e6af7f5SFei Shao	};
10995e6af7f5SFei Shao
11005e6af7f5SFei Shao	spi1_pins_sleep: spi1-sleep-pins {
11015e6af7f5SFei Shao		pins-bus {
11025e6af7f5SFei Shao			pinmux = <PINMUX_GPIO75__FUNC_B_GPIO75>,
11035e6af7f5SFei Shao				 <PINMUX_GPIO76__FUNC_B_GPIO76>,
11045e6af7f5SFei Shao				 <PINMUX_GPIO77__FUNC_B_GPIO77>,
11055e6af7f5SFei Shao				 <PINMUX_GPIO78__FUNC_B_GPIO78>;
11065e6af7f5SFei Shao			bias-pull-down;
11075e6af7f5SFei Shao			input-enable;
11085e6af7f5SFei Shao		};
11095e6af7f5SFei Shao	};
11105e6af7f5SFei Shao
11115e6af7f5SFei Shao	spi2_pins: spi2-pins {
11125e6af7f5SFei Shao		pins-bus {
11135e6af7f5SFei Shao			pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>,
11145e6af7f5SFei Shao				 <PINMUX_GPIO80__FUNC_O_SPIM2_CLK>,
11155e6af7f5SFei Shao				 <PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>,
11165e6af7f5SFei Shao				 <PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>;
11175e6af7f5SFei Shao			bias-disable;
11185e6af7f5SFei Shao		};
11195e6af7f5SFei Shao	};
11205e6af7f5SFei Shao
11215e6af7f5SFei Shao	uart0_pins: uart0-pins {
11225e6af7f5SFei Shao		pins-bus {
11235e6af7f5SFei Shao			pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>,
11245e6af7f5SFei Shao				 <PINMUX_GPIO32__FUNC_I1_URXD0>;
11255e6af7f5SFei Shao			bias-pull-up;
11265e6af7f5SFei Shao		};
11275e6af7f5SFei Shao	};
11285e6af7f5SFei Shao
11295e6af7f5SFei Shao	wlan_en: wlan-en-pins {
11305e6af7f5SFei Shao		pins-en-pp3300-wlan {
11315e6af7f5SFei Shao			pinmux = <PINMUX_GPIO12__FUNC_B_GPIO12>;
11325e6af7f5SFei Shao			output-low;
11335e6af7f5SFei Shao		};
11345e6af7f5SFei Shao	};
11355e6af7f5SFei Shao};
11365e6af7f5SFei Shao
11375e6af7f5SFei Shao&pmic {
11385e6af7f5SFei Shao	interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
11395e6af7f5SFei Shao};
11405e6af7f5SFei Shao
1141*383c2ac3SAngeloGioacchino Del Regno&postmask0_in {
1142*383c2ac3SAngeloGioacchino Del Regno	remote-endpoint = <&gamma0_out>;
1143*383c2ac3SAngeloGioacchino Del Regno};
1144*383c2ac3SAngeloGioacchino Del Regno
1145*383c2ac3SAngeloGioacchino Del Regno&postmask0_out {
1146*383c2ac3SAngeloGioacchino Del Regno	remote-endpoint = <&dither0_in>;
1147*383c2ac3SAngeloGioacchino Del Regno};
1148*383c2ac3SAngeloGioacchino Del Regno
11495e6af7f5SFei Shao&sound {
11505e6af7f5SFei Shao	pinctrl-names = "aud_etdm_hp_on", "aud_etdm_hp_off",
11515e6af7f5SFei Shao			"aud_etdm_spk_on", "aud_etdm_spk_off",
11525e6af7f5SFei Shao			"aud_mtkaif_on", "aud_mtkaif_off";
11535e6af7f5SFei Shao	pinctrl-0 = <&aud_etdm_hp_on>;
11545e6af7f5SFei Shao	pinctrl-1 = <&aud_etdm_hp_off>;
11555e6af7f5SFei Shao	pinctrl-2 = <&aud_etdm_spk_on>;
11565e6af7f5SFei Shao	pinctrl-3 = <&aud_etdm_spk_off>;
11575e6af7f5SFei Shao	pinctrl-4 = <&aud_mtkaif_on>;
11585e6af7f5SFei Shao	pinctrl-5 = <&aud_mtkaif_off>;
11595e6af7f5SFei Shao	mediatek,adsp = <&adsp>;
11605e6af7f5SFei Shao	/* The audio-routing is defined in each board dts */
11615e6af7f5SFei Shao
11625e6af7f5SFei Shao	status = "okay";
11635e6af7f5SFei Shao};
11645e6af7f5SFei Shao
11655e6af7f5SFei Shao&spi0 {
11665e6af7f5SFei Shao	pinctrl-names = "default";
11675e6af7f5SFei Shao	pinctrl-0 = <&spi0_pins>;
11685e6af7f5SFei Shao	status = "okay";
11695e6af7f5SFei Shao
11705e6af7f5SFei Shao	cros_ec: ec@0 {
11715e6af7f5SFei Shao		compatible = "google,cros-ec-spi";
11725e6af7f5SFei Shao		reg = <0>;
11735e6af7f5SFei Shao		interrupts-extended = <&pio 149 IRQ_TYPE_LEVEL_LOW>;
11745e6af7f5SFei Shao		pinctrl-names = "default";
11755e6af7f5SFei Shao		pinctrl-0 = <&cros_ec_int>;
11765e6af7f5SFei Shao		spi-max-frequency = <3000000>;
11775e6af7f5SFei Shao
11785e6af7f5SFei Shao		i2c_tunnel: i2c-tunnel {
11795e6af7f5SFei Shao			compatible = "google,cros-ec-i2c-tunnel";
11805e6af7f5SFei Shao			google,remote-bus = <1>;
11815e6af7f5SFei Shao			#address-cells = <1>;
11825e6af7f5SFei Shao			#size-cells = <0>;
11835e6af7f5SFei Shao		};
11845e6af7f5SFei Shao
11855e6af7f5SFei Shao		cbas {
11865e6af7f5SFei Shao			compatible = "google,cros-cbas";
11875e6af7f5SFei Shao		};
11885e6af7f5SFei Shao	};
11895e6af7f5SFei Shao};
11905e6af7f5SFei Shao
11915e6af7f5SFei Shao&spi1 {
11925e6af7f5SFei Shao	pinctrl-names = "default", "sleep";
11935e6af7f5SFei Shao	pinctrl-0 = <&spi1_pins_default>;
11945e6af7f5SFei Shao	pinctrl-1 = <&spi1_pins_sleep>;
11955e6af7f5SFei Shao	status = "okay";
11965e6af7f5SFei Shao};
11975e6af7f5SFei Shao
11985e6af7f5SFei Shao&spi2 {
11995e6af7f5SFei Shao	pinctrl-names = "default";
12005e6af7f5SFei Shao	pinctrl-0 = <&spi2_pins>;
12015e6af7f5SFei Shao	status = "okay";
12025e6af7f5SFei Shao};
12035e6af7f5SFei Shao
12045e6af7f5SFei Shao&uart0 {
12055e6af7f5SFei Shao	pinctrl-names = "default";
12065e6af7f5SFei Shao	pinctrl-0 = <&uart0_pins>;
12075e6af7f5SFei Shao	status = "okay";
12085e6af7f5SFei Shao};
12095e6af7f5SFei Shao
12105e6af7f5SFei Shao&u3phy0 {
12115e6af7f5SFei Shao	status = "okay";
12125e6af7f5SFei Shao};
12135e6af7f5SFei Shao
12145e6af7f5SFei Shao&u3phy1 {
12155e6af7f5SFei Shao	status = "okay";
12165e6af7f5SFei Shao};
12175e6af7f5SFei Shao
12185e6af7f5SFei Shao&u3phy2 {
12195e6af7f5SFei Shao	status = "okay";
12205e6af7f5SFei Shao};
12215e6af7f5SFei Shao
12225e6af7f5SFei Shao/* USB detachable base */
1223598c4ad8SAngeloGioacchino Del Regno&ssusb0 {
1224598c4ad8SAngeloGioacchino Del Regno	dr_mode = "host";
1225598c4ad8SAngeloGioacchino Del Regno	vusb33-supply = <&pp3300_s3>;
1226598c4ad8SAngeloGioacchino Del Regno	status = "okay";
1227598c4ad8SAngeloGioacchino Del Regno};
1228598c4ad8SAngeloGioacchino Del Regno
12295e6af7f5SFei Shao&xhci0 {
12305e6af7f5SFei Shao	/* controlled by EC */
12315e6af7f5SFei Shao	vbus-supply = <&pp3300_z1>;
12325e6af7f5SFei Shao	status = "okay";
12335e6af7f5SFei Shao};
12345e6af7f5SFei Shao
12355e6af7f5SFei Shao/* USB3 hub */
1236598c4ad8SAngeloGioacchino Del Regno&ssusb1 {
1237598c4ad8SAngeloGioacchino Del Regno	dr_mode = "host";
1238598c4ad8SAngeloGioacchino Del Regno	vusb33-supply = <&pp3300_s3>;
1239598c4ad8SAngeloGioacchino Del Regno	status = "okay";
1240598c4ad8SAngeloGioacchino Del Regno};
1241598c4ad8SAngeloGioacchino Del Regno
12425e6af7f5SFei Shao&xhci1 {
12435e6af7f5SFei Shao	vusb33-supply = <&pp3300_s3>;
12445e6af7f5SFei Shao	vbus-supply = <&pp5000_usb_vbus>;
12455e6af7f5SFei Shao	status = "okay";
12465e6af7f5SFei Shao};
12475e6af7f5SFei Shao
12485e6af7f5SFei Shao/* USB BT */
1249598c4ad8SAngeloGioacchino Del Regno&ssusb2 {
1250598c4ad8SAngeloGioacchino Del Regno	dr_mode = "host";
1251598c4ad8SAngeloGioacchino Del Regno	vusb33-supply = <&pp3300_s3>;
1252598c4ad8SAngeloGioacchino Del Regno	status = "okay";
1253598c4ad8SAngeloGioacchino Del Regno};
1254598c4ad8SAngeloGioacchino Del Regno
1255*383c2ac3SAngeloGioacchino Del Regno&vdosys0 {
1256*383c2ac3SAngeloGioacchino Del Regno	port {
1257*383c2ac3SAngeloGioacchino Del Regno		#address-cells = <1>;
1258*383c2ac3SAngeloGioacchino Del Regno		#size-cells = <0>;
1259*383c2ac3SAngeloGioacchino Del Regno
1260*383c2ac3SAngeloGioacchino Del Regno		vdosys0_ep_main: endpoint@0 {
1261*383c2ac3SAngeloGioacchino Del Regno			reg = <0>;
1262*383c2ac3SAngeloGioacchino Del Regno			remote-endpoint = <&ovl0_in>;
1263*383c2ac3SAngeloGioacchino Del Regno		};
1264*383c2ac3SAngeloGioacchino Del Regno	};
1265*383c2ac3SAngeloGioacchino Del Regno};
1266*383c2ac3SAngeloGioacchino Del Regno
1267*383c2ac3SAngeloGioacchino Del Regno&vdosys1 {
1268*383c2ac3SAngeloGioacchino Del Regno	port {
1269*383c2ac3SAngeloGioacchino Del Regno		#address-cells = <1>;
1270*383c2ac3SAngeloGioacchino Del Regno		#size-cells = <0>;
1271*383c2ac3SAngeloGioacchino Del Regno
1272*383c2ac3SAngeloGioacchino Del Regno		vdosys1_ep_ext: endpoint@1 {
1273*383c2ac3SAngeloGioacchino Del Regno			reg = <1>;
1274*383c2ac3SAngeloGioacchino Del Regno			remote-endpoint = <&ethdr0_in>;
1275*383c2ac3SAngeloGioacchino Del Regno		};
1276*383c2ac3SAngeloGioacchino Del Regno	};
1277*383c2ac3SAngeloGioacchino Del Regno};
1278*383c2ac3SAngeloGioacchino Del Regno
12795e6af7f5SFei Shao&xhci2 {
12805e6af7f5SFei Shao	/* no power supply since MT7921's power is controlled by PCIe */
12815e6af7f5SFei Shao	/* MT7921's USB BT has issues with USB2 LPM */
12825e6af7f5SFei Shao	usb2-lpm-disable;
12835e6af7f5SFei Shao	status = "okay";
12845e6af7f5SFei Shao};
12855e6af7f5SFei Shao
12865e6af7f5SFei Shao#include <arm/cros-ec-keyboard.dtsi>
12875e6af7f5SFei Shao
12885e6af7f5SFei Shao&keyboard_controller {
12895e6af7f5SFei Shao	function-row-physmap = <
12905e6af7f5SFei Shao		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */
12915e6af7f5SFei Shao		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */
12925e6af7f5SFei Shao		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */
12935e6af7f5SFei Shao		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */
12945e6af7f5SFei Shao		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */
12955e6af7f5SFei Shao		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */
12965e6af7f5SFei Shao		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */
12975e6af7f5SFei Shao		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */
12985e6af7f5SFei Shao		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */
12995e6af7f5SFei Shao		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */
13005e6af7f5SFei Shao	>;
13015e6af7f5SFei Shao
13025e6af7f5SFei Shao	linux,keymap = <
13035e6af7f5SFei Shao		MATRIX_KEY(0x00, 0x02, KEY_BACK)
13045e6af7f5SFei Shao		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
13055e6af7f5SFei Shao		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
13065e6af7f5SFei Shao		MATRIX_KEY(0x01, 0x02, KEY_SCALE)
13075e6af7f5SFei Shao		MATRIX_KEY(0x03, 0x04, KEY_BRIGHTNESSDOWN)
13085e6af7f5SFei Shao		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSUP)
13095e6af7f5SFei Shao		MATRIX_KEY(0x01, 0x04, KEY_MICMUTE)
13105e6af7f5SFei Shao		MATRIX_KEY(0x02, 0x09, KEY_MUTE)
13115e6af7f5SFei Shao		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
13125e6af7f5SFei Shao		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
13135e6af7f5SFei Shao		CROS_STD_MAIN_KEYMAP
13145e6af7f5SFei Shao	>;
13155e6af7f5SFei Shao};
1316