1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/gce/mt8186-gce.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/memory/mt8186-memory-port.h> 12#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 13#include <dt-bindings/power/mt8186-power.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/reset/mt8186-resets.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 18 19/ { 20 compatible = "mediatek,mt8186"; 21 interrupt-parent = <&gic>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { 26 ovl0 = &ovl0; 27 ovl-2l0 = &ovl_2l0; 28 rdma0 = &rdma0; 29 rdma1 = &rdma1; 30 }; 31 32 cci: cci { 33 compatible = "mediatek,mt8186-cci"; 34 clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>, 35 <&apmixedsys CLK_APMIXED_MAINPLL>; 36 clock-names = "cci", "intermediate"; 37 operating-points-v2 = <&cci_opp>; 38 }; 39 40 cci_opp: opp-table-cci { 41 compatible = "operating-points-v2"; 42 opp-shared; 43 44 cci_opp_0: opp-500000000 { 45 opp-hz = /bits/ 64 <500000000>; 46 opp-microvolt = <600000>; 47 }; 48 49 cci_opp_1: opp-560000000 { 50 opp-hz = /bits/ 64 <560000000>; 51 opp-microvolt = <675000>; 52 }; 53 54 cci_opp_2: opp-612000000 { 55 opp-hz = /bits/ 64 <612000000>; 56 opp-microvolt = <693750>; 57 }; 58 59 cci_opp_3: opp-682000000 { 60 opp-hz = /bits/ 64 <682000000>; 61 opp-microvolt = <718750>; 62 }; 63 64 cci_opp_4: opp-752000000 { 65 opp-hz = /bits/ 64 <752000000>; 66 opp-microvolt = <743750>; 67 }; 68 69 cci_opp_5: opp-822000000 { 70 opp-hz = /bits/ 64 <822000000>; 71 opp-microvolt = <768750>; 72 }; 73 74 cci_opp_6: opp-875000000 { 75 opp-hz = /bits/ 64 <875000000>; 76 opp-microvolt = <781250>; 77 }; 78 79 cci_opp_7: opp-927000000 { 80 opp-hz = /bits/ 64 <927000000>; 81 opp-microvolt = <800000>; 82 }; 83 84 cci_opp_8: opp-980000000 { 85 opp-hz = /bits/ 64 <980000000>; 86 opp-microvolt = <818750>; 87 }; 88 89 cci_opp_9: opp-1050000000 { 90 opp-hz = /bits/ 64 <1050000000>; 91 opp-microvolt = <843750>; 92 }; 93 94 cci_opp_10: opp-1120000000 { 95 opp-hz = /bits/ 64 <1120000000>; 96 opp-microvolt = <862500>; 97 }; 98 99 cci_opp_11: opp-1155000000 { 100 opp-hz = /bits/ 64 <1155000000>; 101 opp-microvolt = <887500>; 102 }; 103 104 cci_opp_12: opp-1190000000 { 105 opp-hz = /bits/ 64 <1190000000>; 106 opp-microvolt = <906250>; 107 }; 108 109 cci_opp_13: opp-1260000000 { 110 opp-hz = /bits/ 64 <1260000000>; 111 opp-microvolt = <950000>; 112 }; 113 114 cci_opp_14: opp-1330000000 { 115 opp-hz = /bits/ 64 <1330000000>; 116 opp-microvolt = <993750>; 117 }; 118 119 cci_opp_15: opp-1400000000 { 120 opp-hz = /bits/ 64 <1400000000>; 121 opp-microvolt = <1031250>; 122 }; 123 }; 124 125 cluster0_opp: opp-table-cluster0 { 126 compatible = "operating-points-v2"; 127 opp-shared; 128 129 opp-500000000 { 130 opp-hz = /bits/ 64 <500000000>; 131 opp-microvolt = <600000>; 132 required-opps = <&cci_opp_0>; 133 }; 134 135 opp-774000000 { 136 opp-hz = /bits/ 64 <774000000>; 137 opp-microvolt = <675000>; 138 required-opps = <&cci_opp_1>; 139 }; 140 141 opp-875000000 { 142 opp-hz = /bits/ 64 <875000000>; 143 opp-microvolt = <700000>; 144 required-opps = <&cci_opp_2>; 145 }; 146 147 opp-975000000 { 148 opp-hz = /bits/ 64 <975000000>; 149 opp-microvolt = <725000>; 150 required-opps = <&cci_opp_3>; 151 }; 152 153 opp-1075000000 { 154 opp-hz = /bits/ 64 <1075000000>; 155 opp-microvolt = <750000>; 156 required-opps = <&cci_opp_4>; 157 }; 158 159 opp-1175000000 { 160 opp-hz = /bits/ 64 <1175000000>; 161 opp-microvolt = <775000>; 162 required-opps = <&cci_opp_5>; 163 }; 164 165 opp-1275000000 { 166 opp-hz = /bits/ 64 <1275000000>; 167 opp-microvolt = <800000>; 168 required-opps = <&cci_opp_6>; 169 }; 170 171 opp-1375000000 { 172 opp-hz = /bits/ 64 <1375000000>; 173 opp-microvolt = <825000>; 174 required-opps = <&cci_opp_7>; 175 }; 176 177 opp-1500000000 { 178 opp-hz = /bits/ 64 <1500000000>; 179 opp-microvolt = <856250>; 180 required-opps = <&cci_opp_8>; 181 }; 182 183 opp-1618000000 { 184 opp-hz = /bits/ 64 <1618000000>; 185 opp-microvolt = <875000>; 186 required-opps = <&cci_opp_9>; 187 }; 188 189 opp-1666000000 { 190 opp-hz = /bits/ 64 <1666000000>; 191 opp-microvolt = <900000>; 192 required-opps = <&cci_opp_10>; 193 }; 194 195 opp-1733000000 { 196 opp-hz = /bits/ 64 <1733000000>; 197 opp-microvolt = <925000>; 198 required-opps = <&cci_opp_11>; 199 }; 200 201 opp-1800000000 { 202 opp-hz = /bits/ 64 <1800000000>; 203 opp-microvolt = <950000>; 204 required-opps = <&cci_opp_12>; 205 }; 206 207 opp-1866000000 { 208 opp-hz = /bits/ 64 <1866000000>; 209 opp-microvolt = <981250>; 210 required-opps = <&cci_opp_13>; 211 }; 212 213 opp-1933000000 { 214 opp-hz = /bits/ 64 <1933000000>; 215 opp-microvolt = <1006250>; 216 required-opps = <&cci_opp_14>; 217 }; 218 219 opp-2000000000 { 220 opp-hz = /bits/ 64 <2000000000>; 221 opp-microvolt = <1031250>; 222 required-opps = <&cci_opp_15>; 223 }; 224 }; 225 226 cluster1_opp: opp-table-cluster1 { 227 compatible = "operating-points-v2"; 228 opp-shared; 229 230 opp-774000000 { 231 opp-hz = /bits/ 64 <774000000>; 232 opp-microvolt = <675000>; 233 required-opps = <&cci_opp_0>; 234 }; 235 236 opp-835000000 { 237 opp-hz = /bits/ 64 <835000000>; 238 opp-microvolt = <693750>; 239 required-opps = <&cci_opp_1>; 240 }; 241 242 opp-919000000 { 243 opp-hz = /bits/ 64 <919000000>; 244 opp-microvolt = <718750>; 245 required-opps = <&cci_opp_2>; 246 }; 247 248 opp-1002000000 { 249 opp-hz = /bits/ 64 <1002000000>; 250 opp-microvolt = <743750>; 251 required-opps = <&cci_opp_3>; 252 }; 253 254 opp-1085000000 { 255 opp-hz = /bits/ 64 <1085000000>; 256 opp-microvolt = <775000>; 257 required-opps = <&cci_opp_4>; 258 }; 259 260 opp-1169000000 { 261 opp-hz = /bits/ 64 <1169000000>; 262 opp-microvolt = <800000>; 263 required-opps = <&cci_opp_5>; 264 }; 265 266 opp-1308000000 { 267 opp-hz = /bits/ 64 <1308000000>; 268 opp-microvolt = <843750>; 269 required-opps = <&cci_opp_6>; 270 }; 271 272 opp-1419000000 { 273 opp-hz = /bits/ 64 <1419000000>; 274 opp-microvolt = <875000>; 275 required-opps = <&cci_opp_7>; 276 }; 277 278 opp-1530000000 { 279 opp-hz = /bits/ 64 <1530000000>; 280 opp-microvolt = <912500>; 281 required-opps = <&cci_opp_8>; 282 }; 283 284 opp-1670000000 { 285 opp-hz = /bits/ 64 <1670000000>; 286 opp-microvolt = <956250>; 287 required-opps = <&cci_opp_9>; 288 }; 289 290 opp-1733000000 { 291 opp-hz = /bits/ 64 <1733000000>; 292 opp-microvolt = <981250>; 293 required-opps = <&cci_opp_10>; 294 }; 295 296 opp-1796000000 { 297 opp-hz = /bits/ 64 <1796000000>; 298 opp-microvolt = <1012500>; 299 required-opps = <&cci_opp_11>; 300 }; 301 302 opp-1860000000 { 303 opp-hz = /bits/ 64 <1860000000>; 304 opp-microvolt = <1037500>; 305 required-opps = <&cci_opp_12>; 306 }; 307 308 opp-1923000000 { 309 opp-hz = /bits/ 64 <1923000000>; 310 opp-microvolt = <1062500>; 311 required-opps = <&cci_opp_13>; 312 }; 313 314 cluster1_opp_14: opp-1986000000 { 315 opp-hz = /bits/ 64 <1986000000>; 316 opp-microvolt = <1093750>; 317 required-opps = <&cci_opp_14>; 318 }; 319 320 cluster1_opp_15: opp-2050000000 { 321 opp-hz = /bits/ 64 <2050000000>; 322 opp-microvolt = <1118750>; 323 required-opps = <&cci_opp_15>; 324 }; 325 }; 326 327 cpus { 328 #address-cells = <1>; 329 #size-cells = <0>; 330 331 cpu-map { 332 cluster0 { 333 core0 { 334 cpu = <&cpu0>; 335 }; 336 337 core1 { 338 cpu = <&cpu1>; 339 }; 340 341 core2 { 342 cpu = <&cpu2>; 343 }; 344 345 core3 { 346 cpu = <&cpu3>; 347 }; 348 349 core4 { 350 cpu = <&cpu4>; 351 }; 352 353 core5 { 354 cpu = <&cpu5>; 355 }; 356 357 core6 { 358 cpu = <&cpu6>; 359 }; 360 361 core7 { 362 cpu = <&cpu7>; 363 }; 364 }; 365 }; 366 367 cpu0: cpu@0 { 368 device_type = "cpu"; 369 compatible = "arm,cortex-a55"; 370 reg = <0x000>; 371 enable-method = "psci"; 372 clock-frequency = <2000000000>; 373 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 374 <&apmixedsys CLK_APMIXED_MAINPLL>; 375 clock-names = "cpu", "intermediate"; 376 operating-points-v2 = <&cluster0_opp>; 377 dynamic-power-coefficient = <84>; 378 capacity-dmips-mhz = <382>; 379 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 380 i-cache-size = <32768>; 381 i-cache-line-size = <64>; 382 i-cache-sets = <128>; 383 d-cache-size = <32768>; 384 d-cache-line-size = <64>; 385 d-cache-sets = <128>; 386 next-level-cache = <&l2_0>; 387 #cooling-cells = <2>; 388 mediatek,cci = <&cci>; 389 }; 390 391 cpu1: cpu@100 { 392 device_type = "cpu"; 393 compatible = "arm,cortex-a55"; 394 reg = <0x100>; 395 enable-method = "psci"; 396 clock-frequency = <2000000000>; 397 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 398 <&apmixedsys CLK_APMIXED_MAINPLL>; 399 clock-names = "cpu", "intermediate"; 400 operating-points-v2 = <&cluster0_opp>; 401 dynamic-power-coefficient = <84>; 402 capacity-dmips-mhz = <382>; 403 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 404 i-cache-size = <32768>; 405 i-cache-line-size = <64>; 406 i-cache-sets = <128>; 407 d-cache-size = <32768>; 408 d-cache-line-size = <64>; 409 d-cache-sets = <128>; 410 next-level-cache = <&l2_0>; 411 #cooling-cells = <2>; 412 mediatek,cci = <&cci>; 413 }; 414 415 cpu2: cpu@200 { 416 device_type = "cpu"; 417 compatible = "arm,cortex-a55"; 418 reg = <0x200>; 419 enable-method = "psci"; 420 clock-frequency = <2000000000>; 421 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 422 <&apmixedsys CLK_APMIXED_MAINPLL>; 423 clock-names = "cpu", "intermediate"; 424 operating-points-v2 = <&cluster0_opp>; 425 dynamic-power-coefficient = <84>; 426 capacity-dmips-mhz = <382>; 427 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 428 i-cache-size = <32768>; 429 i-cache-line-size = <64>; 430 i-cache-sets = <128>; 431 d-cache-size = <32768>; 432 d-cache-line-size = <64>; 433 d-cache-sets = <128>; 434 next-level-cache = <&l2_0>; 435 #cooling-cells = <2>; 436 mediatek,cci = <&cci>; 437 }; 438 439 cpu3: cpu@300 { 440 device_type = "cpu"; 441 compatible = "arm,cortex-a55"; 442 reg = <0x300>; 443 enable-method = "psci"; 444 clock-frequency = <2000000000>; 445 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 446 <&apmixedsys CLK_APMIXED_MAINPLL>; 447 clock-names = "cpu", "intermediate"; 448 operating-points-v2 = <&cluster0_opp>; 449 dynamic-power-coefficient = <84>; 450 capacity-dmips-mhz = <382>; 451 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 452 i-cache-size = <32768>; 453 i-cache-line-size = <64>; 454 i-cache-sets = <128>; 455 d-cache-size = <32768>; 456 d-cache-line-size = <64>; 457 d-cache-sets = <128>; 458 next-level-cache = <&l2_0>; 459 #cooling-cells = <2>; 460 mediatek,cci = <&cci>; 461 }; 462 463 cpu4: cpu@400 { 464 device_type = "cpu"; 465 compatible = "arm,cortex-a55"; 466 reg = <0x400>; 467 enable-method = "psci"; 468 clock-frequency = <2000000000>; 469 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 470 <&apmixedsys CLK_APMIXED_MAINPLL>; 471 clock-names = "cpu", "intermediate"; 472 operating-points-v2 = <&cluster0_opp>; 473 dynamic-power-coefficient = <84>; 474 capacity-dmips-mhz = <382>; 475 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 476 i-cache-size = <32768>; 477 i-cache-line-size = <64>; 478 i-cache-sets = <128>; 479 d-cache-size = <32768>; 480 d-cache-line-size = <64>; 481 d-cache-sets = <128>; 482 next-level-cache = <&l2_0>; 483 #cooling-cells = <2>; 484 mediatek,cci = <&cci>; 485 }; 486 487 cpu5: cpu@500 { 488 device_type = "cpu"; 489 compatible = "arm,cortex-a55"; 490 reg = <0x500>; 491 enable-method = "psci"; 492 clock-frequency = <2000000000>; 493 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 494 <&apmixedsys CLK_APMIXED_MAINPLL>; 495 clock-names = "cpu", "intermediate"; 496 operating-points-v2 = <&cluster0_opp>; 497 dynamic-power-coefficient = <84>; 498 capacity-dmips-mhz = <382>; 499 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 500 i-cache-size = <32768>; 501 i-cache-line-size = <64>; 502 i-cache-sets = <128>; 503 d-cache-size = <32768>; 504 d-cache-line-size = <64>; 505 d-cache-sets = <128>; 506 next-level-cache = <&l2_0>; 507 #cooling-cells = <2>; 508 mediatek,cci = <&cci>; 509 }; 510 511 cpu6: cpu@600 { 512 device_type = "cpu"; 513 compatible = "arm,cortex-a76"; 514 reg = <0x600>; 515 enable-method = "psci"; 516 clock-frequency = <2050000000>; 517 clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>, 518 <&apmixedsys CLK_APMIXED_MAINPLL>; 519 clock-names = "cpu", "intermediate"; 520 operating-points-v2 = <&cluster1_opp>; 521 dynamic-power-coefficient = <335>; 522 capacity-dmips-mhz = <1024>; 523 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 524 i-cache-size = <65536>; 525 i-cache-line-size = <64>; 526 i-cache-sets = <256>; 527 d-cache-size = <65536>; 528 d-cache-line-size = <64>; 529 d-cache-sets = <256>; 530 next-level-cache = <&l2_1>; 531 #cooling-cells = <2>; 532 mediatek,cci = <&cci>; 533 }; 534 535 cpu7: cpu@700 { 536 device_type = "cpu"; 537 compatible = "arm,cortex-a76"; 538 reg = <0x700>; 539 enable-method = "psci"; 540 clock-frequency = <2050000000>; 541 clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>, 542 <&apmixedsys CLK_APMIXED_MAINPLL>; 543 clock-names = "cpu", "intermediate"; 544 operating-points-v2 = <&cluster1_opp>; 545 dynamic-power-coefficient = <335>; 546 capacity-dmips-mhz = <1024>; 547 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 548 i-cache-size = <65536>; 549 i-cache-line-size = <64>; 550 i-cache-sets = <256>; 551 d-cache-size = <65536>; 552 d-cache-line-size = <64>; 553 d-cache-sets = <256>; 554 next-level-cache = <&l2_1>; 555 #cooling-cells = <2>; 556 mediatek,cci = <&cci>; 557 }; 558 559 idle-states { 560 entry-method = "psci"; 561 562 cpu_ret_l: cpu-retention-l { 563 compatible = "arm,idle-state"; 564 arm,psci-suspend-param = <0x00010001>; 565 local-timer-stop; 566 entry-latency-us = <50>; 567 exit-latency-us = <100>; 568 min-residency-us = <1600>; 569 }; 570 571 cpu_ret_b: cpu-retention-b { 572 compatible = "arm,idle-state"; 573 arm,psci-suspend-param = <0x00010001>; 574 local-timer-stop; 575 entry-latency-us = <50>; 576 exit-latency-us = <100>; 577 min-residency-us = <1400>; 578 }; 579 580 cpu_off_l: cpu-off-l { 581 compatible = "arm,idle-state"; 582 arm,psci-suspend-param = <0x01010001>; 583 local-timer-stop; 584 entry-latency-us = <100>; 585 exit-latency-us = <250>; 586 min-residency-us = <2100>; 587 }; 588 589 cpu_off_b: cpu-off-b { 590 compatible = "arm,idle-state"; 591 arm,psci-suspend-param = <0x01010001>; 592 local-timer-stop; 593 entry-latency-us = <100>; 594 exit-latency-us = <250>; 595 min-residency-us = <1900>; 596 }; 597 }; 598 599 l2_0: l2-cache0 { 600 compatible = "cache"; 601 cache-level = <2>; 602 cache-size = <131072>; 603 cache-line-size = <64>; 604 cache-sets = <512>; 605 next-level-cache = <&l3_0>; 606 cache-unified; 607 }; 608 609 l2_1: l2-cache1 { 610 compatible = "cache"; 611 cache-level = <2>; 612 cache-size = <262144>; 613 cache-line-size = <64>; 614 cache-sets = <512>; 615 next-level-cache = <&l3_0>; 616 cache-unified; 617 }; 618 619 l3_0: l3-cache { 620 compatible = "cache"; 621 cache-level = <3>; 622 cache-size = <1048576>; 623 cache-line-size = <64>; 624 cache-sets = <1024>; 625 cache-unified; 626 }; 627 }; 628 629 clk13m: fixed-factor-clock-13m { 630 compatible = "fixed-factor-clock"; 631 #clock-cells = <0>; 632 clocks = <&clk26m>; 633 clock-div = <2>; 634 clock-mult = <1>; 635 clock-output-names = "clk13m"; 636 }; 637 638 clk26m: oscillator-26m { 639 compatible = "fixed-clock"; 640 #clock-cells = <0>; 641 clock-frequency = <26000000>; 642 clock-output-names = "clk26m"; 643 }; 644 645 clk32k: oscillator-32k { 646 compatible = "fixed-clock"; 647 #clock-cells = <0>; 648 clock-frequency = <32768>; 649 clock-output-names = "clk32k"; 650 }; 651 652 gpu_opp_table: opp-table-gpu { 653 compatible = "operating-points-v2"; 654 655 opp-299000000 { 656 opp-hz = /bits/ 64 <299000000>; 657 opp-microvolt = <612500>; 658 opp-supported-hw = <0xff>; 659 }; 660 661 opp-332000000 { 662 opp-hz = /bits/ 64 <332000000>; 663 opp-microvolt = <625000>; 664 opp-supported-hw = <0xff>; 665 }; 666 667 opp-366000000 { 668 opp-hz = /bits/ 64 <366000000>; 669 opp-microvolt = <637500>; 670 opp-supported-hw = <0xff>; 671 }; 672 673 opp-400000000 { 674 opp-hz = /bits/ 64 <400000000>; 675 opp-microvolt = <643750>; 676 opp-supported-hw = <0xff>; 677 }; 678 679 opp-434000000 { 680 opp-hz = /bits/ 64 <434000000>; 681 opp-microvolt = <656250>; 682 opp-supported-hw = <0xff>; 683 }; 684 685 opp-484000000 { 686 opp-hz = /bits/ 64 <484000000>; 687 opp-microvolt = <668750>; 688 opp-supported-hw = <0xff>; 689 }; 690 691 opp-535000000 { 692 opp-hz = /bits/ 64 <535000000>; 693 opp-microvolt = <687500>; 694 opp-supported-hw = <0xff>; 695 }; 696 697 opp-586000000 { 698 opp-hz = /bits/ 64 <586000000>; 699 opp-microvolt = <700000>; 700 opp-supported-hw = <0xff>; 701 }; 702 703 opp-637000000 { 704 opp-hz = /bits/ 64 <637000000>; 705 opp-microvolt = <712500>; 706 opp-supported-hw = <0xff>; 707 }; 708 709 opp-690000000 { 710 opp-hz = /bits/ 64 <690000000>; 711 opp-microvolt = <737500>; 712 opp-supported-hw = <0xff>; 713 }; 714 715 opp-743000000 { 716 opp-hz = /bits/ 64 <743000000>; 717 opp-microvolt = <756250>; 718 opp-supported-hw = <0xff>; 719 }; 720 721 opp-796000000 { 722 opp-hz = /bits/ 64 <796000000>; 723 opp-microvolt = <781250>; 724 opp-supported-hw = <0xff>; 725 }; 726 727 opp-850000000 { 728 opp-hz = /bits/ 64 <850000000>; 729 opp-microvolt = <800000>; 730 opp-supported-hw = <0xff>; 731 }; 732 733 opp-900000000-3 { 734 opp-hz = /bits/ 64 <900000000>; 735 opp-microvolt = <850000>; 736 opp-supported-hw = <0xcf>; 737 }; 738 739 opp-900000000-4 { 740 opp-hz = /bits/ 64 <900000000>; 741 opp-microvolt = <837500>; 742 opp-supported-hw = <0x10>; 743 }; 744 745 opp-900000000-5 { 746 opp-hz = /bits/ 64 <900000000>; 747 opp-microvolt = <825000>; 748 opp-supported-hw = <0x20>; 749 }; 750 751 opp-950000000-3 { 752 opp-hz = /bits/ 64 <950000000>; 753 opp-microvolt = <900000>; 754 opp-supported-hw = <0xcf>; 755 }; 756 757 opp-950000000-4 { 758 opp-hz = /bits/ 64 <950000000>; 759 opp-microvolt = <875000>; 760 opp-supported-hw = <0x10>; 761 }; 762 763 opp-950000000-5 { 764 opp-hz = /bits/ 64 <950000000>; 765 opp-microvolt = <850000>; 766 opp-supported-hw = <0x20>; 767 }; 768 769 opp-1000000000-3 { 770 opp-hz = /bits/ 64 <1000000000>; 771 opp-microvolt = <950000>; 772 opp-supported-hw = <0xcf>; 773 }; 774 775 opp-1000000000-4 { 776 opp-hz = /bits/ 64 <1000000000>; 777 opp-microvolt = <912500>; 778 opp-supported-hw = <0x10>; 779 }; 780 781 opp-1000000000-5 { 782 opp-hz = /bits/ 64 <1000000000>; 783 opp-microvolt = <875000>; 784 opp-supported-hw = <0x20>; 785 }; 786 }; 787 788 pmu-a55 { 789 compatible = "arm,cortex-a55-pmu"; 790 interrupt-parent = <&gic>; 791 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 792 }; 793 794 pmu-a76 { 795 compatible = "arm,cortex-a76-pmu"; 796 interrupt-parent = <&gic>; 797 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 798 }; 799 800 psci { 801 compatible = "arm,psci-1.0"; 802 method = "smc"; 803 }; 804 805 timer { 806 compatible = "arm,armv8-timer"; 807 interrupt-parent = <&gic>; 808 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 809 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 810 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 811 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 812 }; 813 814 soc { 815 #address-cells = <2>; 816 #size-cells = <2>; 817 compatible = "simple-bus"; 818 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 819 ranges; 820 821 gic: interrupt-controller@c000000 { 822 compatible = "arm,gic-v3"; 823 #interrupt-cells = <4>; 824 #redistributor-regions = <1>; 825 interrupt-parent = <&gic>; 826 interrupt-controller; 827 reg = <0 0x0c000000 0 0x40000>, 828 <0 0x0c040000 0 0x200000>; 829 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 830 831 ppi-partitions { 832 ppi_cluster0: interrupt-partition-0 { 833 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 834 }; 835 836 ppi_cluster1: interrupt-partition-1 { 837 affinity = <&cpu6 &cpu7>; 838 }; 839 }; 840 }; 841 842 mcusys: syscon@c53a000 { 843 compatible = "mediatek,mt8186-mcusys", "syscon"; 844 reg = <0 0xc53a000 0 0x1000>; 845 #clock-cells = <1>; 846 }; 847 848 topckgen: syscon@10000000 { 849 compatible = "mediatek,mt8186-topckgen", "syscon"; 850 reg = <0 0x10000000 0 0x1000>; 851 #clock-cells = <1>; 852 }; 853 854 infracfg_ao: syscon@10001000 { 855 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 856 reg = <0 0x10001000 0 0x1000>; 857 #clock-cells = <1>; 858 #reset-cells = <1>; 859 }; 860 861 pericfg: syscon@10003000 { 862 compatible = "mediatek,mt8186-pericfg", "syscon"; 863 reg = <0 0x10003000 0 0x1000>; 864 }; 865 866 pio: pinctrl@10005000 { 867 compatible = "mediatek,mt8186-pinctrl"; 868 reg = <0 0x10005000 0 0x1000>, 869 <0 0x10002000 0 0x0200>, 870 <0 0x10002200 0 0x0200>, 871 <0 0x10002400 0 0x0200>, 872 <0 0x10002600 0 0x0200>, 873 <0 0x10002a00 0 0x0200>, 874 <0 0x10002c00 0 0x0200>, 875 <0 0x1000b000 0 0x1000>; 876 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 877 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 878 gpio-controller; 879 #gpio-cells = <2>; 880 gpio-ranges = <&pio 0 0 185>; 881 interrupt-controller; 882 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 883 #interrupt-cells = <2>; 884 }; 885 886 scpsys: syscon@10006000 { 887 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 888 reg = <0 0x10006000 0 0x1000>; 889 890 /* System Power Manager */ 891 spm: power-controller { 892 compatible = "mediatek,mt8186-power-controller"; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 #power-domain-cells = <1>; 896 897 /* power domain of the SoC */ 898 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 899 reg = <MT8186_POWER_DOMAIN_MFG0>; 900 clocks = <&topckgen CLK_TOP_MFG>; 901 clock-names = "mfg00"; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 #power-domain-cells = <1>; 905 906 mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 { 907 reg = <MT8186_POWER_DOMAIN_MFG1>; 908 mediatek,infracfg = <&infracfg_ao>; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 #power-domain-cells = <1>; 912 913 power-domain@MT8186_POWER_DOMAIN_MFG2 { 914 reg = <MT8186_POWER_DOMAIN_MFG2>; 915 #power-domain-cells = <0>; 916 }; 917 918 power-domain@MT8186_POWER_DOMAIN_MFG3 { 919 reg = <MT8186_POWER_DOMAIN_MFG3>; 920 #power-domain-cells = <0>; 921 }; 922 }; 923 }; 924 925 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 926 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 927 clocks = <&topckgen CLK_TOP_SENINF>, 928 <&topckgen CLK_TOP_SENINF1>; 929 clock-names = "subsys-csirx-top0", 930 "subsys-csirx-top1"; 931 #power-domain-cells = <0>; 932 }; 933 934 power-domain@MT8186_POWER_DOMAIN_SSUSB { 935 reg = <MT8186_POWER_DOMAIN_SSUSB>; 936 clocks = <&topckgen CLK_TOP_USB_TOP>, 937 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>; 938 clock-names = "sys_ck", "ref_ck"; 939 #power-domain-cells = <0>; 940 }; 941 942 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 943 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 944 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 945 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>; 946 clock-names = "sys_ck", "ref_ck"; 947 #power-domain-cells = <0>; 948 }; 949 950 power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 951 reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 952 clocks = <&topckgen CLK_TOP_AUDIODSP>, 953 <&topckgen CLK_TOP_ADSP_BUS>; 954 clock-names = "audioadsp", 955 "subsys-adsp-bus"; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 #power-domain-cells = <1>; 959 960 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 961 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 #power-domain-cells = <1>; 965 966 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 967 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 968 mediatek,infracfg = <&infracfg_ao>; 969 #power-domain-cells = <0>; 970 }; 971 }; 972 }; 973 974 power-domain@MT8186_POWER_DOMAIN_CONN_ON { 975 reg = <MT8186_POWER_DOMAIN_CONN_ON>; 976 mediatek,infracfg = <&infracfg_ao>; 977 #power-domain-cells = <0>; 978 }; 979 980 power-domain@MT8186_POWER_DOMAIN_DIS { 981 reg = <MT8186_POWER_DOMAIN_DIS>; 982 clocks = <&topckgen CLK_TOP_DISP>, 983 <&topckgen CLK_TOP_MDP>, 984 <&mmsys CLK_MM_SMI_INFRA>, 985 <&mmsys CLK_MM_SMI_COMMON>, 986 <&mmsys CLK_MM_SMI_GALS>, 987 <&mmsys CLK_MM_SMI_IOMMU>; 988 clock-names = "disp", "mdp", 989 "subsys-smi-infra", 990 "subsys-smi-common", 991 "subsys-smi-gals", 992 "subsys-smi-iommu"; 993 mediatek,infracfg = <&infracfg_ao>; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 #power-domain-cells = <1>; 997 998 power-domain@MT8186_POWER_DOMAIN_VDEC { 999 reg = <MT8186_POWER_DOMAIN_VDEC>; 1000 clocks = <&topckgen CLK_TOP_VDEC>, 1001 <&vdecsys CLK_VDEC_LARB1_CKEN>; 1002 clock-names = "vdec0", "larb"; 1003 mediatek,infracfg = <&infracfg_ao>; 1004 #power-domain-cells = <0>; 1005 }; 1006 1007 power-domain@MT8186_POWER_DOMAIN_CAM { 1008 reg = <MT8186_POWER_DOMAIN_CAM>; 1009 clocks = <&topckgen CLK_TOP_SENINF>, 1010 <&topckgen CLK_TOP_SENINF1>, 1011 <&topckgen CLK_TOP_SENINF2>, 1012 <&topckgen CLK_TOP_SENINF3>, 1013 <&camsys CLK_CAM2MM_GALS>, 1014 <&topckgen CLK_TOP_CAMTM>, 1015 <&topckgen CLK_TOP_CAM>; 1016 clock-names = "cam0", "cam1", "cam2", 1017 "cam3", "gals", 1018 "subsys-cam-tm", 1019 "subsys-cam-top"; 1020 mediatek,infracfg = <&infracfg_ao>; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 #power-domain-cells = <1>; 1024 1025 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 1026 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 1027 #power-domain-cells = <0>; 1028 }; 1029 1030 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 1031 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 1032 #power-domain-cells = <0>; 1033 }; 1034 }; 1035 1036 power-domain@MT8186_POWER_DOMAIN_IMG { 1037 reg = <MT8186_POWER_DOMAIN_IMG>; 1038 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1039 <&topckgen CLK_TOP_IMG1>; 1040 clock-names = "gals", "subsys-img-top"; 1041 mediatek,infracfg = <&infracfg_ao>; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 #power-domain-cells = <1>; 1045 1046 power-domain@MT8186_POWER_DOMAIN_IMG2 { 1047 reg = <MT8186_POWER_DOMAIN_IMG2>; 1048 #power-domain-cells = <0>; 1049 }; 1050 }; 1051 1052 power-domain@MT8186_POWER_DOMAIN_IPE { 1053 reg = <MT8186_POWER_DOMAIN_IPE>; 1054 clocks = <&topckgen CLK_TOP_IPE>, 1055 <&ipesys CLK_IPE_LARB19>, 1056 <&ipesys CLK_IPE_LARB20>, 1057 <&ipesys CLK_IPE_SMI_SUBCOM>, 1058 <&ipesys CLK_IPE_GALS_IPE>; 1059 clock-names = "subsys-ipe-top", 1060 "subsys-ipe-larb0", 1061 "subsys-ipe-larb1", 1062 "subsys-ipe-smi", 1063 "subsys-ipe-gals"; 1064 mediatek,infracfg = <&infracfg_ao>; 1065 #power-domain-cells = <0>; 1066 }; 1067 1068 power-domain@MT8186_POWER_DOMAIN_VENC { 1069 reg = <MT8186_POWER_DOMAIN_VENC>; 1070 clocks = <&topckgen CLK_TOP_VENC>, 1071 <&vencsys CLK_VENC_CKE1_VENC>; 1072 clock-names = "venc0", "subsys-larb"; 1073 mediatek,infracfg = <&infracfg_ao>; 1074 #power-domain-cells = <0>; 1075 }; 1076 1077 power-domain@MT8186_POWER_DOMAIN_WPE { 1078 reg = <MT8186_POWER_DOMAIN_WPE>; 1079 clocks = <&topckgen CLK_TOP_WPE>, 1080 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1081 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 1082 clock-names = "wpe0", 1083 "subsys-larb-ck", 1084 "subsys-larb-pclk"; 1085 mediatek,infracfg = <&infracfg_ao>; 1086 #power-domain-cells = <0>; 1087 }; 1088 }; 1089 }; 1090 }; 1091 1092 watchdog: watchdog@10007000 { 1093 compatible = "mediatek,mt8186-wdt"; 1094 mediatek,disable-extrst; 1095 reg = <0 0x10007000 0 0x1000>; 1096 #reset-cells = <1>; 1097 }; 1098 1099 apmixedsys: syscon@1000c000 { 1100 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 1101 reg = <0 0x1000c000 0 0x1000>; 1102 #clock-cells = <1>; 1103 }; 1104 1105 pwrap: pwrap@1000d000 { 1106 compatible = "mediatek,mt8186-pwrap", "syscon"; 1107 reg = <0 0x1000d000 0 0x1000>; 1108 reg-names = "pwrap"; 1109 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1110 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 1111 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 1112 clock-names = "spi", "wrap"; 1113 }; 1114 1115 spmi: spmi@10015000 { 1116 compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; 1117 reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; 1118 reg-names = "pmif", "spmimst"; 1119 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 1120 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 1121 <&topckgen CLK_TOP_SPMI_MST>; 1122 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; 1123 assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>; 1124 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 1125 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>, 1126 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>; 1127 status = "disabled"; 1128 }; 1129 1130 systimer: timer@10017000 { 1131 compatible = "mediatek,mt8186-timer", 1132 "mediatek,mt6765-timer"; 1133 reg = <0 0x10017000 0 0x1000>; 1134 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 1135 clocks = <&clk13m>; 1136 }; 1137 1138 gce: mailbox@1022c000 { 1139 compatible = "mediatek,mt8186-gce"; 1140 reg = <0 0X1022c000 0 0x4000>; 1141 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 1142 clock-names = "gce"; 1143 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 1144 #mbox-cells = <2>; 1145 }; 1146 1147 scp: scp@10500000 { 1148 compatible = "mediatek,mt8186-scp"; 1149 reg = <0 0x10500000 0 0x40000>, 1150 <0 0x105c0000 0 0x19080>; 1151 reg-names = "sram", "cfg"; 1152 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 1153 }; 1154 1155 adsp: adsp@10680000 { 1156 compatible = "mediatek,mt8186-dsp"; 1157 reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, 1158 <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; 1159 reg-names = "cfg", "sram", "sec", "bus"; 1160 clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; 1161 clock-names = "audiodsp", "adsp_bus"; 1162 assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>, 1163 <&topckgen CLK_TOP_ADSP_BUS>; 1164 assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>; 1165 mbox-names = "rx", "tx"; 1166 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 1167 power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>; 1168 status = "disabled"; 1169 }; 1170 1171 adsp_mailbox0: mailbox@10686100 { 1172 compatible = "mediatek,mt8186-adsp-mbox"; 1173 #mbox-cells = <0>; 1174 reg = <0 0x10686100 0 0x1000>; 1175 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; 1176 }; 1177 1178 adsp_mailbox1: mailbox@10687100 { 1179 compatible = "mediatek,mt8186-adsp-mbox"; 1180 #mbox-cells = <0>; 1181 reg = <0 0x10687100 0 0x1000>; 1182 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>; 1183 }; 1184 1185 nor_flash: spi@11000000 { 1186 compatible = "mediatek,mt8186-nor"; 1187 reg = <0 0x11000000 0 0x1000>; 1188 clocks = <&topckgen CLK_TOP_SPINOR>, 1189 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 1190 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 1191 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 1192 clock-names = "spi", "sf", "axi", "axi_s"; 1193 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 1194 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 1195 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 1196 status = "disabled"; 1197 }; 1198 1199 auxadc: adc@11001000 { 1200 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 1201 reg = <0 0x11001000 0 0x1000>; 1202 #io-channel-cells = <1>; 1203 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1204 clock-names = "main"; 1205 }; 1206 1207 uart0: serial@11002000 { 1208 compatible = "mediatek,mt8186-uart", 1209 "mediatek,mt6577-uart"; 1210 reg = <0 0x11002000 0 0x1000>; 1211 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 1212 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1213 clock-names = "baud", "bus"; 1214 status = "disabled"; 1215 }; 1216 1217 uart1: serial@11003000 { 1218 compatible = "mediatek,mt8186-uart", 1219 "mediatek,mt6577-uart"; 1220 reg = <0 0x11003000 0 0x1000>; 1221 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1222 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1223 clock-names = "baud", "bus"; 1224 status = "disabled"; 1225 }; 1226 1227 i2c0: i2c@11007000 { 1228 compatible = "mediatek,mt8186-i2c"; 1229 reg = <0 0x11007000 0 0x1000>, 1230 <0 0x10200100 0 0x100>; 1231 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 1232 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 1233 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1234 clock-names = "main", "dma"; 1235 clock-div = <1>; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 status = "disabled"; 1239 }; 1240 1241 i2c1: i2c@11008000 { 1242 compatible = "mediatek,mt8186-i2c"; 1243 reg = <0 0x11008000 0 0x1000>, 1244 <0 0x10200200 0 0x100>; 1245 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1246 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 1247 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1248 clock-names = "main", "dma"; 1249 clock-div = <1>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 status = "disabled"; 1253 }; 1254 1255 i2c2: i2c@11009000 { 1256 compatible = "mediatek,mt8186-i2c"; 1257 reg = <0 0x11009000 0 0x1000>, 1258 <0 0x10200300 0 0x180>; 1259 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 1260 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 1261 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1262 clock-names = "main", "dma"; 1263 clock-div = <1>; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 status = "disabled"; 1267 }; 1268 1269 i2c3: i2c@1100f000 { 1270 compatible = "mediatek,mt8186-i2c"; 1271 reg = <0 0x1100f000 0 0x1000>, 1272 <0 0x10200480 0 0x100>; 1273 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 1274 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 1275 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1276 clock-names = "main", "dma"; 1277 clock-div = <1>; 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 status = "disabled"; 1281 }; 1282 1283 i2c4: i2c@11011000 { 1284 compatible = "mediatek,mt8186-i2c"; 1285 reg = <0 0x11011000 0 0x1000>, 1286 <0 0x10200580 0 0x180>; 1287 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 1288 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 1289 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1290 clock-names = "main", "dma"; 1291 clock-div = <1>; 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 status = "disabled"; 1295 }; 1296 1297 i2c5: i2c@11016000 { 1298 compatible = "mediatek,mt8186-i2c"; 1299 reg = <0 0x11016000 0 0x1000>, 1300 <0 0x10200700 0 0x100>; 1301 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 1302 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 1303 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1304 clock-names = "main", "dma"; 1305 clock-div = <1>; 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 status = "disabled"; 1309 }; 1310 1311 i2c6: i2c@1100d000 { 1312 compatible = "mediatek,mt8186-i2c"; 1313 reg = <0 0x1100d000 0 0x1000>, 1314 <0 0x10200800 0 0x100>; 1315 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1316 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 1317 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1318 clock-names = "main", "dma"; 1319 clock-div = <1>; 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 status = "disabled"; 1323 }; 1324 1325 i2c7: i2c@11004000 { 1326 compatible = "mediatek,mt8186-i2c"; 1327 reg = <0 0x11004000 0 0x1000>, 1328 <0 0x10200900 0 0x180>; 1329 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 1330 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 1331 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1332 clock-names = "main", "dma"; 1333 clock-div = <1>; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 status = "disabled"; 1337 }; 1338 1339 i2c8: i2c@11005000 { 1340 compatible = "mediatek,mt8186-i2c"; 1341 reg = <0 0x11005000 0 0x1000>, 1342 <0 0x10200A80 0 0x180>; 1343 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1344 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 1345 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1346 clock-names = "main", "dma"; 1347 clock-div = <1>; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 status = "disabled"; 1351 }; 1352 1353 spi0: spi@1100a000 { 1354 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 reg = <0 0x1100a000 0 0x1000>; 1358 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 1359 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1360 <&topckgen CLK_TOP_SPI>, 1361 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1362 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1363 status = "disabled"; 1364 }; 1365 1366 lvts: thermal-sensor@1100b000 { 1367 compatible = "mediatek,mt8186-lvts"; 1368 reg = <0 0x1100b000 0 0x1000>; 1369 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 1370 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1371 resets = <&infracfg_ao MT8186_INFRA_THERMAL_CTRL_RST>; 1372 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1373 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1374 #thermal-sensor-cells = <1>; 1375 }; 1376 1377 svs: svs@1100bc00 { 1378 compatible = "mediatek,mt8186-svs"; 1379 reg = <0 0x1100bc00 0 0x400>; 1380 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 1381 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1382 clock-names = "main"; 1383 nvmem-cells = <&svs_calibration>, <&lvts_efuse_data1>; 1384 nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; 1385 resets = <&infracfg_ao MT8186_INFRA_PTP_CTRL_RST>; 1386 reset-names = "svs_rst"; 1387 }; 1388 1389 pwm0: pwm@1100e000 { 1390 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 1391 reg = <0 0x1100e000 0 0x1000>; 1392 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1393 #pwm-cells = <2>; 1394 clocks = <&topckgen CLK_TOP_DISP_PWM>, 1395 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1396 clock-names = "main", "mm"; 1397 status = "disabled"; 1398 }; 1399 1400 spi1: spi@11010000 { 1401 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 reg = <0 0x11010000 0 0x1000>; 1405 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 1406 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1407 <&topckgen CLK_TOP_SPI>, 1408 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1409 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1410 status = "disabled"; 1411 }; 1412 1413 spi2: spi@11012000 { 1414 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1415 #address-cells = <1>; 1416 #size-cells = <0>; 1417 reg = <0 0x11012000 0 0x1000>; 1418 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 1419 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1420 <&topckgen CLK_TOP_SPI>, 1421 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1422 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1423 status = "disabled"; 1424 }; 1425 1426 spi3: spi@11013000 { 1427 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1428 #address-cells = <1>; 1429 #size-cells = <0>; 1430 reg = <0 0x11013000 0 0x1000>; 1431 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 1432 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1433 <&topckgen CLK_TOP_SPI>, 1434 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1435 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1436 status = "disabled"; 1437 }; 1438 1439 spi4: spi@11014000 { 1440 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 reg = <0 0x11014000 0 0x1000>; 1444 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1445 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1446 <&topckgen CLK_TOP_SPI>, 1447 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1448 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1449 status = "disabled"; 1450 }; 1451 1452 spi5: spi@11015000 { 1453 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1454 #address-cells = <1>; 1455 #size-cells = <0>; 1456 reg = <0 0x11015000 0 0x1000>; 1457 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1458 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1459 <&topckgen CLK_TOP_SPI>, 1460 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1461 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1462 status = "disabled"; 1463 }; 1464 1465 imp_iic_wrap: clock-controller@11017000 { 1466 compatible = "mediatek,mt8186-imp_iic_wrap"; 1467 reg = <0 0x11017000 0 0x1000>; 1468 #clock-cells = <1>; 1469 }; 1470 1471 uart2: serial@11018000 { 1472 compatible = "mediatek,mt8186-uart", 1473 "mediatek,mt6577-uart"; 1474 reg = <0 0x11018000 0 0x1000>; 1475 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 1476 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1477 clock-names = "baud", "bus"; 1478 status = "disabled"; 1479 }; 1480 1481 i2c9: i2c@11019000 { 1482 compatible = "mediatek,mt8186-i2c"; 1483 reg = <0 0x11019000 0 0x1000>, 1484 <0 0x10200c00 0 0x180>; 1485 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1486 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 1487 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1488 clock-names = "main", "dma"; 1489 clock-div = <1>; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 status = "disabled"; 1493 }; 1494 1495 afe: audio-controller@11210000 { 1496 compatible = "mediatek,mt8186-sound"; 1497 reg = <0 0x11210000 0 0x2000>; 1498 clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, 1499 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, 1500 <&topckgen CLK_TOP_AUDIO>, 1501 <&topckgen CLK_TOP_AUD_INTBUS>, 1502 <&topckgen CLK_TOP_MAINPLL_D2_D4>, 1503 <&topckgen CLK_TOP_AUD_1>, 1504 <&apmixedsys CLK_APMIXED_APLL1>, 1505 <&topckgen CLK_TOP_AUD_2>, 1506 <&apmixedsys CLK_APMIXED_APLL2>, 1507 <&topckgen CLK_TOP_AUD_ENGEN1>, 1508 <&topckgen CLK_TOP_APLL1_D8>, 1509 <&topckgen CLK_TOP_AUD_ENGEN2>, 1510 <&topckgen CLK_TOP_APLL2_D8>, 1511 <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, 1512 <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, 1513 <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, 1514 <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, 1515 <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, 1516 <&topckgen CLK_TOP_APLL12_CK_DIV0>, 1517 <&topckgen CLK_TOP_APLL12_CK_DIV1>, 1518 <&topckgen CLK_TOP_APLL12_CK_DIV2>, 1519 <&topckgen CLK_TOP_APLL12_CK_DIV4>, 1520 <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, 1521 <&topckgen CLK_TOP_AUDIO_H>, 1522 <&clk26m>; 1523 clock-names = "aud_infra_clk", 1524 "mtkaif_26m_clk", 1525 "top_mux_audio", 1526 "top_mux_audio_int", 1527 "top_mainpll_d2_d4", 1528 "top_mux_aud_1", 1529 "top_apll1_ck", 1530 "top_mux_aud_2", 1531 "top_apll2_ck", 1532 "top_mux_aud_eng1", 1533 "top_apll1_d8", 1534 "top_mux_aud_eng2", 1535 "top_apll2_d8", 1536 "top_i2s0_m_sel", 1537 "top_i2s1_m_sel", 1538 "top_i2s2_m_sel", 1539 "top_i2s4_m_sel", 1540 "top_tdm_m_sel", 1541 "top_apll12_div0", 1542 "top_apll12_div1", 1543 "top_apll12_div2", 1544 "top_apll12_div4", 1545 "top_apll12_div_tdm", 1546 "top_mux_audio_h", 1547 "top_clk26m_clk"; 1548 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1549 mediatek,apmixedsys = <&apmixedsys>; 1550 mediatek,infracfg = <&infracfg_ao>; 1551 mediatek,topckgen = <&topckgen>; 1552 resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; 1553 reset-names = "audiosys"; 1554 status = "disabled"; 1555 }; 1556 1557 ssusb0: usb@11201000 { 1558 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1559 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1560 reg-names = "mac", "ippc"; 1561 clocks = <&topckgen CLK_TOP_USB_TOP>, 1562 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1563 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1564 <&infracfg_ao CLK_INFRA_AO_ICUSB>, 1565 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; 1566 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1567 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>; 1568 phys = <&u2port0 PHY_TYPE_USB2>; 1569 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; 1570 #address-cells = <2>; 1571 #size-cells = <2>; 1572 ranges; 1573 status = "disabled"; 1574 1575 usb_host0: usb@11200000 { 1576 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1577 reg = <0 0x11200000 0 0x1000>; 1578 reg-names = "mac"; 1579 clocks = <&topckgen CLK_TOP_USB_TOP>, 1580 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1581 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1582 <&infracfg_ao CLK_INFRA_AO_ICUSB>, 1583 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; 1584 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1585 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 1586 mediatek,syscon-wakeup = <&pericfg 0x420 2>; 1587 wakeup-source; 1588 status = "disabled"; 1589 }; 1590 }; 1591 1592 mmc0: mmc@11230000 { 1593 compatible = "mediatek,mt8186-mmc", 1594 "mediatek,mt8183-mmc"; 1595 reg = <0 0x11230000 0 0x10000>, 1596 <0 0x11cd0000 0 0x1000>; 1597 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1598 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1599 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1600 <&infracfg_ao CLK_INFRA_AO_MSDCFDE>; 1601 clock-names = "source", "hclk", "source_cg", "crypto"; 1602 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 1603 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 1604 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 1605 status = "disabled"; 1606 }; 1607 1608 mmc1: mmc@11240000 { 1609 compatible = "mediatek,mt8186-mmc", 1610 "mediatek,mt8183-mmc"; 1611 reg = <0 0x11240000 0 0x1000>, 1612 <0 0x11c90000 0 0x1000>; 1613 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1614 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1615 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1616 clock-names = "source", "hclk", "source_cg"; 1617 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 1618 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1619 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1620 status = "disabled"; 1621 }; 1622 1623 ssusb1: usb@11281000 { 1624 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1625 reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; 1626 reg-names = "mac", "ippc"; 1627 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1628 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1629 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1630 <&clk26m>, 1631 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; 1632 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1633 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 1634 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1635 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; 1636 #address-cells = <2>; 1637 #size-cells = <2>; 1638 ranges; 1639 status = "disabled"; 1640 1641 usb_host1: usb@11280000 { 1642 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1643 reg = <0 0x11280000 0 0x1000>; 1644 reg-names = "mac"; 1645 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1646 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1647 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1648 <&clk26m>, 1649 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; 1650 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; 1651 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 1652 mediatek,syscon-wakeup = <&pericfg 0x424 2>; 1653 wakeup-source; 1654 status = "disabled"; 1655 }; 1656 }; 1657 1658 u3phy0: t-phy@11c80000 { 1659 compatible = "mediatek,mt8186-tphy", 1660 "mediatek,generic-tphy-v2"; 1661 #address-cells = <1>; 1662 #size-cells = <1>; 1663 ranges = <0x0 0x0 0x11c80000 0x1000>; 1664 status = "disabled"; 1665 1666 u2port1: usb-phy@0 { 1667 reg = <0x0 0x700>; 1668 clocks = <&clk26m>; 1669 clock-names = "ref"; 1670 #phy-cells = <1>; 1671 }; 1672 1673 u3port1: usb-phy@700 { 1674 reg = <0x700 0x900>; 1675 clocks = <&clk26m>; 1676 clock-names = "ref"; 1677 #phy-cells = <1>; 1678 }; 1679 }; 1680 1681 u3phy1: t-phy@11ca0000 { 1682 compatible = "mediatek,mt8186-tphy", 1683 "mediatek,generic-tphy-v2"; 1684 #address-cells = <1>; 1685 #size-cells = <1>; 1686 ranges = <0x0 0x0 0x11ca0000 0x1000>; 1687 status = "disabled"; 1688 1689 u2port0: usb-phy@0 { 1690 reg = <0x0 0x700>; 1691 clocks = <&clk26m>; 1692 clock-names = "ref"; 1693 #phy-cells = <1>; 1694 mediatek,discth = <0x8>; 1695 }; 1696 }; 1697 1698 efuse: efuse@11cb0000 { 1699 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 1700 reg = <0 0x11cb0000 0 0x1000>; 1701 #address-cells = <1>; 1702 #size-cells = <1>; 1703 1704 lvts_efuse_data1: lvts1-calib@1cc { 1705 reg = <0x1cc 0x14>; 1706 }; 1707 1708 lvts_efuse_data2: lvts2-calib@2f8 { 1709 reg = <0x2f8 0x14>; 1710 }; 1711 1712 svs_calibration: calib@550 { 1713 reg = <0x550 0x50>; 1714 }; 1715 1716 gpu_speedbin: gpu-speedbin@59c { 1717 reg = <0x59c 0x4>; 1718 bits = <0 3>; 1719 }; 1720 1721 socinfo-data1@7a0 { 1722 reg = <0x7a0 0x4>; 1723 }; 1724 }; 1725 1726 mipi_tx0: dsi-phy@11cc0000 { 1727 compatible = "mediatek,mt8183-mipi-tx"; 1728 reg = <0 0x11cc0000 0 0x1000>; 1729 clocks = <&clk26m>; 1730 #clock-cells = <0>; 1731 #phy-cells = <0>; 1732 clock-output-names = "mipi_tx0_pll"; 1733 status = "disabled"; 1734 }; 1735 1736 mfgsys: clock-controller@13000000 { 1737 compatible = "mediatek,mt8186-mfgsys"; 1738 reg = <0 0x13000000 0 0x1000>; 1739 #clock-cells = <1>; 1740 }; 1741 1742 gpu: gpu@13040000 { 1743 compatible = "mediatek,mt8186-mali", 1744 "arm,mali-bifrost"; 1745 reg = <0 0x13040000 0 0x4000>; 1746 1747 clocks = <&mfgsys CLK_MFG_BG3D>; 1748 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>, 1749 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>, 1750 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 1751 interrupt-names = "job", "mmu", "gpu"; 1752 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>, 1753 <&spm MT8186_POWER_DOMAIN_MFG3>; 1754 power-domain-names = "core0", "core1"; 1755 #cooling-cells = <2>; 1756 nvmem-cells = <&gpu_speedbin>; 1757 nvmem-cell-names = "speed-bin"; 1758 operating-points-v2 = <&gpu_opp_table>; 1759 dynamic-power-coefficient = <4687>; 1760 status = "disabled"; 1761 }; 1762 1763 mmsys: syscon@14000000 { 1764 compatible = "mediatek,mt8186-mmsys", "syscon"; 1765 reg = <0 0x14000000 0 0x1000>; 1766 #clock-cells = <1>; 1767 #reset-cells = <1>; 1768 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1769 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1770 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1771 }; 1772 1773 mutex: mutex@14001000 { 1774 compatible = "mediatek,mt8186-disp-mutex"; 1775 reg = <0 0x14001000 0 0x1000>; 1776 clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1777 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>; 1778 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1779 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1780 <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1781 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1782 }; 1783 1784 smi_common: smi@14002000 { 1785 compatible = "mediatek,mt8186-smi-common"; 1786 reg = <0 0x14002000 0 0x1000>; 1787 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, 1788 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; 1789 clock-names = "apb", "smi", "gals0", "gals1"; 1790 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1791 }; 1792 1793 larb0: smi@14003000 { 1794 compatible = "mediatek,mt8186-smi-larb"; 1795 reg = <0 0x14003000 0 0x1000>; 1796 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1797 <&mmsys CLK_MM_SMI_COMMON>; 1798 clock-names = "apb", "smi"; 1799 mediatek,larb-id = <0>; 1800 mediatek,smi = <&smi_common>; 1801 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1802 }; 1803 1804 larb1: smi@14004000 { 1805 compatible = "mediatek,mt8186-smi-larb"; 1806 reg = <0 0x14004000 0 0x1000>; 1807 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1808 <&mmsys CLK_MM_SMI_COMMON>; 1809 clock-names = "apb", "smi"; 1810 mediatek,larb-id = <1>; 1811 mediatek,smi = <&smi_common>; 1812 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1813 }; 1814 1815 ovl0: ovl@14005000 { 1816 compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl"; 1817 reg = <0 0x14005000 0 0x1000>; 1818 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1819 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>; 1820 iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; 1821 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1822 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1823 }; 1824 1825 ovl_2l0: ovl@14006000 { 1826 compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l"; 1827 reg = <0 0x14006000 0 0x1000>; 1828 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1829 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 1830 iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; 1831 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1832 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1833 }; 1834 1835 rdma0: rdma@14007000 { 1836 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 1837 reg = <0 0x14007000 0 0x1000>; 1838 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1839 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>; 1840 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>; 1841 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1842 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1843 }; 1844 1845 color: color@14009000 { 1846 compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color"; 1847 reg = <0 0x14009000 0 0x1000>; 1848 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1849 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>; 1850 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1851 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1852 }; 1853 1854 dpi: dpi@1400a000 { 1855 compatible = "mediatek,mt8186-dpi"; 1856 reg = <0 0x1400a000 0 0x1000>; 1857 clocks = <&topckgen CLK_TOP_DPI>, 1858 <&mmsys CLK_MM_DISP_DPI>, 1859 <&apmixedsys CLK_APMIXED_TVDPLL>; 1860 clock-names = "pixel", "engine", "pll"; 1861 assigned-clocks = <&topckgen CLK_TOP_DPI>; 1862 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; 1863 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; 1864 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1865 status = "disabled"; 1866 1867 port { 1868 dpi_out: endpoint { }; 1869 }; 1870 }; 1871 1872 ccorr: ccorr@1400b000 { 1873 compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 1874 reg = <0 0x1400b000 0 0x1000>; 1875 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1876 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>; 1877 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1878 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1879 }; 1880 1881 aal: aal@1400c000 { 1882 compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal"; 1883 reg = <0 0x1400c000 0 0x1000>; 1884 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1885 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>; 1886 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1887 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1888 }; 1889 1890 gamma: gamma@1400d000 { 1891 compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma"; 1892 reg = <0 0x1400d000 0 0x1000>; 1893 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1894 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 1895 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1896 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1897 }; 1898 1899 postmask: postmask@1400e000 { 1900 compatible = "mediatek,mt8186-disp-postmask", 1901 "mediatek,mt8192-disp-postmask"; 1902 reg = <0 0x1400e000 0 0x1000>; 1903 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1904 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 1905 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1906 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1907 }; 1908 1909 dither: dither@1400f000 { 1910 compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither"; 1911 reg = <0 0x1400f000 0 0x1000>; 1912 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1913 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>; 1914 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1915 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1916 }; 1917 1918 dsi0: dsi@14013000 { 1919 compatible = "mediatek,mt8186-dsi"; 1920 reg = <0 0x14013000 0 0x1000>; 1921 clocks = <&mmsys CLK_MM_DSI0>, 1922 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, 1923 <&mipi_tx0>; 1924 clock-names = "engine", "digital", "hs"; 1925 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; 1926 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1927 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; 1928 phys = <&mipi_tx0>; 1929 phy-names = "dphy"; 1930 status = "disabled"; 1931 1932 port { 1933 dsi_out: endpoint { }; 1934 }; 1935 }; 1936 1937 iommu_mm: iommu@14016000 { 1938 compatible = "mediatek,mt8186-iommu-mm"; 1939 reg = <0 0x14016000 0 0x1000>; 1940 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1941 clock-names = "bclk"; 1942 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 1943 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 1944 &larb7 &larb8 &larb9 &larb11 1945 &larb13 &larb14 &larb16 &larb17 1946 &larb19 &larb20>; 1947 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1948 #iommu-cells = <1>; 1949 }; 1950 1951 rdma1: rdma@1401f000 { 1952 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 1953 reg = <0 0x1401f000 0 0x1000>; 1954 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1955 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>; 1956 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>; 1957 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>; 1958 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1959 }; 1960 1961 wpesys: clock-controller@14020000 { 1962 compatible = "mediatek,mt8186-wpesys"; 1963 reg = <0 0x14020000 0 0x1000>; 1964 #clock-cells = <1>; 1965 }; 1966 1967 larb8: smi@14023000 { 1968 compatible = "mediatek,mt8186-smi-larb"; 1969 reg = <0 0x14023000 0 0x1000>; 1970 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1971 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; 1972 clock-names = "apb", "smi"; 1973 mediatek,larb-id = <8>; 1974 mediatek,smi = <&smi_common>; 1975 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; 1976 }; 1977 1978 imgsys1: clock-controller@15020000 { 1979 compatible = "mediatek,mt8186-imgsys1"; 1980 reg = <0 0x15020000 0 0x1000>; 1981 #clock-cells = <1>; 1982 }; 1983 1984 larb9: smi@1502e000 { 1985 compatible = "mediatek,mt8186-smi-larb"; 1986 reg = <0 0x1502e000 0 0x1000>; 1987 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1988 <&imgsys1 CLK_IMG1_LARB9_IMG1>; 1989 clock-names = "apb", "smi"; 1990 mediatek,larb-id = <9>; 1991 mediatek,smi = <&smi_common>; 1992 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; 1993 }; 1994 1995 imgsys2: clock-controller@15820000 { 1996 compatible = "mediatek,mt8186-imgsys2"; 1997 reg = <0 0x15820000 0 0x1000>; 1998 #clock-cells = <1>; 1999 }; 2000 2001 larb11: smi@1582e000 { 2002 compatible = "mediatek,mt8186-smi-larb"; 2003 reg = <0 0x1582e000 0 0x1000>; 2004 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, 2005 <&imgsys2 CLK_IMG2_LARB9_IMG2>; 2006 clock-names = "apb", "smi"; 2007 mediatek,larb-id = <11>; 2008 mediatek,smi = <&smi_common>; 2009 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; 2010 }; 2011 2012 video_decoder: video-decoder@16000000 { 2013 compatible = "mediatek,mt8186-vcodec-dec"; 2014 reg = <0 0x16000000 0 0x1000>; 2015 ranges; 2016 #address-cells = <2>; 2017 #size-cells = <2>; 2018 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 2019 iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>; 2020 mediatek,scp = <&scp>; 2021 2022 vcodec_core: video-codec@16025000 { 2023 compatible = "mediatek,mtk-vcodec-core"; 2024 reg = <0 0x16025000 0 0x1000>; 2025 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; 2026 iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>, 2027 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_EXT>, 2028 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PP_EXT>, 2029 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT>, 2030 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT>, 2031 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT>, 2032 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_TILE_EXT>, 2033 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD_EXT>, 2034 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD2_EXT>, 2035 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT>, 2036 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT>, 2037 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT>; 2038 clocks = <&topckgen CLK_TOP_VDEC>, 2039 <&vdecsys CLK_VDEC_CKEN>, 2040 <&vdecsys CLK_VDEC_LARB1_CKEN>, 2041 <&topckgen CLK_TOP_UNIVPLL_D3>; 2042 clock-names = "vdec-sel", "vdec-soc-vdec", "vdec", "vdec-top"; 2043 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2044 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>; 2045 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 2046 }; 2047 }; 2048 2049 larb4: smi@1602e000 { 2050 compatible = "mediatek,mt8186-smi-larb"; 2051 reg = <0 0x1602e000 0 0x1000>; 2052 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, 2053 <&vdecsys CLK_VDEC_LARB1_CKEN>; 2054 clock-names = "apb", "smi"; 2055 mediatek,larb-id = <4>; 2056 mediatek,smi = <&smi_common>; 2057 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 2058 }; 2059 2060 vdecsys: clock-controller@1602f000 { 2061 compatible = "mediatek,mt8186-vdecsys"; 2062 reg = <0 0x1602f000 0 0x1000>; 2063 #clock-cells = <1>; 2064 }; 2065 2066 vencsys: clock-controller@17000000 { 2067 compatible = "mediatek,mt8186-vencsys"; 2068 reg = <0 0x17000000 0 0x1000>; 2069 #clock-cells = <1>; 2070 }; 2071 2072 larb7: smi@17010000 { 2073 compatible = "mediatek,mt8186-smi-larb"; 2074 reg = <0 0x17010000 0 0x1000>; 2075 clocks = <&vencsys CLK_VENC_CKE1_VENC>, 2076 <&vencsys CLK_VENC_CKE1_VENC>; 2077 clock-names = "apb", "smi"; 2078 mediatek,larb-id = <7>; 2079 mediatek,smi = <&smi_common>; 2080 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 2081 }; 2082 2083 venc: video-encoder@17020000 { 2084 compatible = "mediatek,mt8186-vcodec-enc", "mediatek,mt8183-vcodec-enc"; 2085 reg = <0 0x17020000 0 0x2000>; 2086 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 2087 iommus = <&iommu_mm IOMMU_PORT_L7_VENC_RCPU>, 2088 <&iommu_mm IOMMU_PORT_L7_VENC_REC>, 2089 <&iommu_mm IOMMU_PORT_L7_VENC_BSDMA>, 2090 <&iommu_mm IOMMU_PORT_L7_VENC_SV_COMV>, 2091 <&iommu_mm IOMMU_PORT_L7_VENC_RD_COMV>, 2092 <&iommu_mm IOMMU_PORT_L7_VENC_CUR_LUMA>, 2093 <&iommu_mm IOMMU_PORT_L7_VENC_CUR_CHROMA>, 2094 <&iommu_mm IOMMU_PORT_L7_VENC_REF_LUMA>, 2095 <&iommu_mm IOMMU_PORT_L7_VENC_REF_CHROMA>; 2096 clocks = <&vencsys CLK_VENC_CKE1_VENC>; 2097 clock-names = "venc_sel"; 2098 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2099 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>; 2100 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 2101 mediatek,scp = <&scp>; 2102 }; 2103 2104 jpgenc: jpeg-encoder@17030000 { 2105 compatible = "mediatek,mt8186-jpgenc", "mediatek,mtk-jpgenc"; 2106 reg = <0 0x17030000 0 0x10000>; 2107 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>; 2108 clocks = <&vencsys CLK_VENC_CKE2_JPGENC>; 2109 clock-names = "jpgenc"; 2110 iommus = <&iommu_mm IOMMU_PORT_L7_JPGENC_Y_RDMA>, 2111 <&iommu_mm IOMMU_PORT_L7_JPGENC_C_RDMA>, 2112 <&iommu_mm IOMMU_PORT_L7_JPGENC_Q_TABLE>, 2113 <&iommu_mm IOMMU_PORT_L7_JPGENC_BSDMA>; 2114 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 2115 }; 2116 2117 camsys: clock-controller@1a000000 { 2118 compatible = "mediatek,mt8186-camsys"; 2119 reg = <0 0x1a000000 0 0x1000>; 2120 #clock-cells = <1>; 2121 }; 2122 2123 larb13: smi@1a001000 { 2124 compatible = "mediatek,mt8186-smi-larb"; 2125 reg = <0 0x1a001000 0 0x1000>; 2126 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; 2127 clock-names = "apb", "smi"; 2128 mediatek,larb-id = <13>; 2129 mediatek,smi = <&smi_common>; 2130 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 2131 }; 2132 2133 larb14: smi@1a002000 { 2134 compatible = "mediatek,mt8186-smi-larb"; 2135 reg = <0 0x1a002000 0 0x1000>; 2136 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; 2137 clock-names = "apb", "smi"; 2138 mediatek,larb-id = <14>; 2139 mediatek,smi = <&smi_common>; 2140 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 2141 }; 2142 2143 larb16: smi@1a00f000 { 2144 compatible = "mediatek,mt8186-smi-larb"; 2145 reg = <0 0x1a00f000 0 0x1000>; 2146 clocks = <&camsys CLK_CAM_LARB14>, 2147 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; 2148 clock-names = "apb", "smi"; 2149 mediatek,larb-id = <16>; 2150 mediatek,smi = <&smi_common>; 2151 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; 2152 }; 2153 2154 larb17: smi@1a010000 { 2155 compatible = "mediatek,mt8186-smi-larb"; 2156 reg = <0 0x1a010000 0 0x1000>; 2157 clocks = <&camsys CLK_CAM_LARB13>, 2158 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; 2159 clock-names = "apb", "smi"; 2160 mediatek,larb-id = <17>; 2161 mediatek,smi = <&smi_common>; 2162 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; 2163 }; 2164 2165 camsys_rawa: clock-controller@1a04f000 { 2166 compatible = "mediatek,mt8186-camsys_rawa"; 2167 reg = <0 0x1a04f000 0 0x1000>; 2168 #clock-cells = <1>; 2169 }; 2170 2171 camsys_rawb: clock-controller@1a06f000 { 2172 compatible = "mediatek,mt8186-camsys_rawb"; 2173 reg = <0 0x1a06f000 0 0x1000>; 2174 #clock-cells = <1>; 2175 }; 2176 2177 mdpsys: clock-controller@1b000000 { 2178 compatible = "mediatek,mt8186-mdpsys"; 2179 reg = <0 0x1b000000 0 0x1000>; 2180 #clock-cells = <1>; 2181 }; 2182 2183 larb2: smi@1b002000 { 2184 compatible = "mediatek,mt8186-smi-larb"; 2185 reg = <0 0x1b002000 0 0x1000>; 2186 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; 2187 clock-names = "apb", "smi"; 2188 mediatek,larb-id = <2>; 2189 mediatek,smi = <&smi_common>; 2190 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 2191 }; 2192 2193 ipesys: clock-controller@1c000000 { 2194 compatible = "mediatek,mt8186-ipesys"; 2195 reg = <0 0x1c000000 0 0x1000>; 2196 #clock-cells = <1>; 2197 }; 2198 2199 larb20: smi@1c00f000 { 2200 compatible = "mediatek,mt8186-smi-larb"; 2201 reg = <0 0x1c00f000 0 0x1000>; 2202 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; 2203 clock-names = "apb", "smi"; 2204 mediatek,larb-id = <20>; 2205 mediatek,smi = <&smi_common>; 2206 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 2207 }; 2208 2209 larb19: smi@1c10f000 { 2210 compatible = "mediatek,mt8186-smi-larb"; 2211 reg = <0 0x1c10f000 0 0x1000>; 2212 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; 2213 clock-names = "apb", "smi"; 2214 mediatek,larb-id = <19>; 2215 mediatek,smi = <&smi_common>; 2216 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 2217 }; 2218 }; 2219 2220 thermal_zones: thermal-zones { 2221 cpu-little0-thermal { 2222 polling-delay = <1000>; 2223 polling-delay-passive = <150>; 2224 thermal-sensors = <&lvts MT8186_LITTLE_CPU0>; 2225 2226 trips { 2227 cpu_little0_alert0: trip-alert0 { 2228 temperature = <85000>; 2229 hysteresis = <2000>; 2230 type = "passive"; 2231 }; 2232 2233 cpu_little0_alert1: trip-alert1 { 2234 temperature = <95000>; 2235 hysteresis = <2000>; 2236 type = "hot"; 2237 }; 2238 2239 cpu_little0_crit: trip-crit { 2240 temperature = <100000>; 2241 hysteresis = <0>; 2242 type = "critical"; 2243 }; 2244 }; 2245 2246 cooling-maps { 2247 map0 { 2248 trip = <&cpu_little0_alert0>; 2249 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2250 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2251 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2252 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2253 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2254 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2255 }; 2256 }; 2257 }; 2258 2259 cpu-little1-thermal { 2260 polling-delay = <1000>; 2261 polling-delay-passive = <150>; 2262 thermal-sensors = <&lvts MT8186_LITTLE_CPU1>; 2263 2264 trips { 2265 cpu_little1_alert0: trip-alert0 { 2266 temperature = <85000>; 2267 hysteresis = <2000>; 2268 type = "passive"; 2269 }; 2270 2271 cpu_little1_alert1: trip-alert1 { 2272 temperature = <95000>; 2273 hysteresis = <2000>; 2274 type = "hot"; 2275 }; 2276 2277 cpu_little1_crit: trip-crit { 2278 temperature = <100000>; 2279 hysteresis = <0>; 2280 type = "critical"; 2281 }; 2282 }; 2283 2284 cooling-maps { 2285 map0 { 2286 trip = <&cpu_little1_alert0>; 2287 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2288 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2289 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2290 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2291 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2292 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2293 }; 2294 }; 2295 }; 2296 2297 cpu-little2-thermal { 2298 polling-delay = <1000>; 2299 polling-delay-passive = <150>; 2300 thermal-sensors = <&lvts MT8186_LITTLE_CPU2>; 2301 2302 trips { 2303 cpu_little2_alert0: trip-alert0 { 2304 temperature = <85000>; 2305 hysteresis = <2000>; 2306 type = "passive"; 2307 }; 2308 2309 cpu_little2_alert1: trip-alert1 { 2310 temperature = <95000>; 2311 hysteresis = <2000>; 2312 type = "hot"; 2313 }; 2314 2315 cpu_little2_crit: trip-crit { 2316 temperature = <100000>; 2317 hysteresis = <0>; 2318 type = "critical"; 2319 }; 2320 }; 2321 2322 cooling-maps { 2323 map0 { 2324 trip = <&cpu_little2_alert0>; 2325 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2326 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2327 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2328 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2329 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2330 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2331 }; 2332 }; 2333 }; 2334 2335 cam-thermal { 2336 polling-delay = <1000>; 2337 polling-delay-passive = <250>; 2338 thermal-sensors = <&lvts MT8186_CAM>; 2339 2340 trips { 2341 cam_alert0: trip-alert0 { 2342 temperature = <85000>; 2343 hysteresis = <2000>; 2344 type = "passive"; 2345 }; 2346 2347 cam_alert1: trip-alert1 { 2348 temperature = <95000>; 2349 hysteresis = <2000>; 2350 type = "hot"; 2351 }; 2352 2353 cam_crit: trip-crit { 2354 temperature = <100000>; 2355 hysteresis = <0>; 2356 type = "critical"; 2357 }; 2358 }; 2359 }; 2360 2361 nna-thermal { 2362 polling-delay = <1000>; 2363 polling-delay-passive = <250>; 2364 thermal-sensors = <&lvts MT8186_NNA>; 2365 2366 trips { 2367 nna_alert0: trip-alert0 { 2368 temperature = <85000>; 2369 hysteresis = <2000>; 2370 type = "passive"; 2371 }; 2372 2373 nna_alert1: trip-alert1 { 2374 temperature = <95000>; 2375 hysteresis = <2000>; 2376 type = "hot"; 2377 }; 2378 2379 nna_crit: trip-crit { 2380 temperature = <100000>; 2381 hysteresis = <0>; 2382 type = "critical"; 2383 }; 2384 }; 2385 }; 2386 2387 adsp-thermal { 2388 polling-delay = <1000>; 2389 polling-delay-passive = <250>; 2390 thermal-sensors = <&lvts MT8186_ADSP>; 2391 2392 trips { 2393 adsp_alert0: trip-alert0 { 2394 temperature = <85000>; 2395 hysteresis = <2000>; 2396 type = "passive"; 2397 }; 2398 2399 adsp_alert1: trip-alert1 { 2400 temperature = <95000>; 2401 hysteresis = <2000>; 2402 type = "hot"; 2403 }; 2404 2405 adsp_crit: trip-crit { 2406 temperature = <100000>; 2407 hysteresis = <0>; 2408 type = "critical"; 2409 }; 2410 }; 2411 }; 2412 2413 gpu-thermal { 2414 polling-delay = <1000>; 2415 polling-delay-passive = <250>; 2416 thermal-sensors = <&lvts MT8186_GPU>; 2417 2418 trips { 2419 gpu_alert0: trip-alert0 { 2420 temperature = <85000>; 2421 hysteresis = <2000>; 2422 type = "passive"; 2423 }; 2424 2425 gpu_alert1: trip-alert1 { 2426 temperature = <95000>; 2427 hysteresis = <2000>; 2428 type = "hot"; 2429 }; 2430 2431 gpu_crit: trip-crit { 2432 temperature = <100000>; 2433 hysteresis = <0>; 2434 type = "critical"; 2435 }; 2436 }; 2437 2438 cooling-maps { 2439 map0 { 2440 trip = <&gpu_alert0>; 2441 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2442 }; 2443 }; 2444 }; 2445 2446 cpu-big0-thermal { 2447 polling-delay = <1000>; 2448 polling-delay-passive = <100>; 2449 thermal-sensors = <&lvts MT8186_BIG_CPU0>; 2450 2451 trips { 2452 cpu_big0_alert0: trip-alert0 { 2453 temperature = <85000>; 2454 hysteresis = <2000>; 2455 type = "passive"; 2456 }; 2457 2458 cpu_big0_alert1: trip-alert1 { 2459 temperature = <95000>; 2460 hysteresis = <2000>; 2461 type = "hot"; 2462 }; 2463 2464 cpu_big0_crit: trip-crit { 2465 temperature = <100000>; 2466 hysteresis = <0>; 2467 type = "critical"; 2468 }; 2469 }; 2470 2471 cooling-maps { 2472 map0 { 2473 trip = <&cpu_big0_alert0>; 2474 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2475 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2476 }; 2477 }; 2478 }; 2479 2480 cpu-big1-thermal { 2481 polling-delay = <1000>; 2482 polling-delay-passive = <100>; 2483 thermal-sensors = <&lvts MT8186_BIG_CPU1>; 2484 2485 trips { 2486 cpu_big1_alert0: trip-alert0 { 2487 temperature = <85000>; 2488 hysteresis = <2000>; 2489 type = "passive"; 2490 }; 2491 2492 cpu_big1_alert1: trip-alert1 { 2493 temperature = <95000>; 2494 hysteresis = <2000>; 2495 type = "hot"; 2496 }; 2497 2498 cpu_big1_crit: trip-crit { 2499 temperature = <100000>; 2500 hysteresis = <0>; 2501 type = "critical"; 2502 }; 2503 }; 2504 2505 cooling-maps { 2506 map0 { 2507 trip = <&cpu_big1_alert0>; 2508 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2509 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2510 }; 2511 }; 2512 }; 2513 }; 2514}; 2515