1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/gce/mt8186-gce.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/memory/mt8186-memory-port.h> 12#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 13#include <dt-bindings/power/mt8186-power.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/reset/mt8186-resets.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 18 19/ { 20 compatible = "mediatek,mt8186"; 21 interrupt-parent = <&gic>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { 26 ovl0 = &ovl0; 27 ovl-2l0 = &ovl_2l0; 28 rdma0 = &rdma0; 29 rdma1 = &rdma1; 30 }; 31 32 fhctl: fhctl@1000ce00 { 33 compatible = "mediatek,mt8186-fhctl"; 34 clocks = <&apmixedsys CLK_APMIXED_TVDPLL>; 35 reg = <0 0x1000ce00 0 0x200>; 36 status = "disabled"; 37 }; 38 39 cci: cci { 40 compatible = "mediatek,mt8186-cci"; 41 clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>, 42 <&apmixedsys CLK_APMIXED_MAINPLL>; 43 clock-names = "cci", "intermediate"; 44 operating-points-v2 = <&cci_opp>; 45 }; 46 47 cci_opp: opp-table-cci { 48 compatible = "operating-points-v2"; 49 opp-shared; 50 51 cci_opp_0: opp-500000000 { 52 opp-hz = /bits/ 64 <500000000>; 53 opp-microvolt = <600000>; 54 }; 55 56 cci_opp_1: opp-560000000 { 57 opp-hz = /bits/ 64 <560000000>; 58 opp-microvolt = <675000>; 59 }; 60 61 cci_opp_2: opp-612000000 { 62 opp-hz = /bits/ 64 <612000000>; 63 opp-microvolt = <693750>; 64 }; 65 66 cci_opp_3: opp-682000000 { 67 opp-hz = /bits/ 64 <682000000>; 68 opp-microvolt = <718750>; 69 }; 70 71 cci_opp_4: opp-752000000 { 72 opp-hz = /bits/ 64 <752000000>; 73 opp-microvolt = <743750>; 74 }; 75 76 cci_opp_5: opp-822000000 { 77 opp-hz = /bits/ 64 <822000000>; 78 opp-microvolt = <768750>; 79 }; 80 81 cci_opp_6: opp-875000000 { 82 opp-hz = /bits/ 64 <875000000>; 83 opp-microvolt = <781250>; 84 }; 85 86 cci_opp_7: opp-927000000 { 87 opp-hz = /bits/ 64 <927000000>; 88 opp-microvolt = <800000>; 89 }; 90 91 cci_opp_8: opp-980000000 { 92 opp-hz = /bits/ 64 <980000000>; 93 opp-microvolt = <818750>; 94 }; 95 96 cci_opp_9: opp-1050000000 { 97 opp-hz = /bits/ 64 <1050000000>; 98 opp-microvolt = <843750>; 99 }; 100 101 cci_opp_10: opp-1120000000 { 102 opp-hz = /bits/ 64 <1120000000>; 103 opp-microvolt = <862500>; 104 }; 105 106 cci_opp_11: opp-1155000000 { 107 opp-hz = /bits/ 64 <1155000000>; 108 opp-microvolt = <887500>; 109 }; 110 111 cci_opp_12: opp-1190000000 { 112 opp-hz = /bits/ 64 <1190000000>; 113 opp-microvolt = <906250>; 114 }; 115 116 cci_opp_13: opp-1260000000 { 117 opp-hz = /bits/ 64 <1260000000>; 118 opp-microvolt = <950000>; 119 }; 120 121 cci_opp_14: opp-1330000000 { 122 opp-hz = /bits/ 64 <1330000000>; 123 opp-microvolt = <993750>; 124 }; 125 126 cci_opp_15: opp-1400000000 { 127 opp-hz = /bits/ 64 <1400000000>; 128 opp-microvolt = <1031250>; 129 }; 130 }; 131 132 cluster0_opp: opp-table-cluster0 { 133 compatible = "operating-points-v2"; 134 opp-shared; 135 136 opp-500000000 { 137 opp-hz = /bits/ 64 <500000000>; 138 opp-microvolt = <600000>; 139 required-opps = <&cci_opp_0>; 140 }; 141 142 opp-774000000 { 143 opp-hz = /bits/ 64 <774000000>; 144 opp-microvolt = <675000>; 145 required-opps = <&cci_opp_1>; 146 }; 147 148 opp-875000000 { 149 opp-hz = /bits/ 64 <875000000>; 150 opp-microvolt = <700000>; 151 required-opps = <&cci_opp_2>; 152 }; 153 154 opp-975000000 { 155 opp-hz = /bits/ 64 <975000000>; 156 opp-microvolt = <725000>; 157 required-opps = <&cci_opp_3>; 158 }; 159 160 opp-1075000000 { 161 opp-hz = /bits/ 64 <1075000000>; 162 opp-microvolt = <750000>; 163 required-opps = <&cci_opp_4>; 164 }; 165 166 opp-1175000000 { 167 opp-hz = /bits/ 64 <1175000000>; 168 opp-microvolt = <775000>; 169 required-opps = <&cci_opp_5>; 170 }; 171 172 opp-1275000000 { 173 opp-hz = /bits/ 64 <1275000000>; 174 opp-microvolt = <800000>; 175 required-opps = <&cci_opp_6>; 176 }; 177 178 opp-1375000000 { 179 opp-hz = /bits/ 64 <1375000000>; 180 opp-microvolt = <825000>; 181 required-opps = <&cci_opp_7>; 182 }; 183 184 opp-1500000000 { 185 opp-hz = /bits/ 64 <1500000000>; 186 opp-microvolt = <856250>; 187 required-opps = <&cci_opp_8>; 188 }; 189 190 opp-1618000000 { 191 opp-hz = /bits/ 64 <1618000000>; 192 opp-microvolt = <875000>; 193 required-opps = <&cci_opp_9>; 194 }; 195 196 opp-1666000000 { 197 opp-hz = /bits/ 64 <1666000000>; 198 opp-microvolt = <900000>; 199 required-opps = <&cci_opp_10>; 200 }; 201 202 opp-1733000000 { 203 opp-hz = /bits/ 64 <1733000000>; 204 opp-microvolt = <925000>; 205 required-opps = <&cci_opp_11>; 206 }; 207 208 opp-1800000000 { 209 opp-hz = /bits/ 64 <1800000000>; 210 opp-microvolt = <950000>; 211 required-opps = <&cci_opp_12>; 212 }; 213 214 opp-1866000000 { 215 opp-hz = /bits/ 64 <1866000000>; 216 opp-microvolt = <981250>; 217 required-opps = <&cci_opp_13>; 218 }; 219 220 opp-1933000000 { 221 opp-hz = /bits/ 64 <1933000000>; 222 opp-microvolt = <1006250>; 223 required-opps = <&cci_opp_14>; 224 }; 225 226 opp-2000000000 { 227 opp-hz = /bits/ 64 <2000000000>; 228 opp-microvolt = <1031250>; 229 required-opps = <&cci_opp_15>; 230 }; 231 }; 232 233 cluster1_opp: opp-table-cluster1 { 234 compatible = "operating-points-v2"; 235 opp-shared; 236 237 opp-774000000 { 238 opp-hz = /bits/ 64 <774000000>; 239 opp-microvolt = <675000>; 240 required-opps = <&cci_opp_0>; 241 }; 242 243 opp-835000000 { 244 opp-hz = /bits/ 64 <835000000>; 245 opp-microvolt = <693750>; 246 required-opps = <&cci_opp_1>; 247 }; 248 249 opp-919000000 { 250 opp-hz = /bits/ 64 <919000000>; 251 opp-microvolt = <718750>; 252 required-opps = <&cci_opp_2>; 253 }; 254 255 opp-1002000000 { 256 opp-hz = /bits/ 64 <1002000000>; 257 opp-microvolt = <743750>; 258 required-opps = <&cci_opp_3>; 259 }; 260 261 opp-1085000000 { 262 opp-hz = /bits/ 64 <1085000000>; 263 opp-microvolt = <775000>; 264 required-opps = <&cci_opp_4>; 265 }; 266 267 opp-1169000000 { 268 opp-hz = /bits/ 64 <1169000000>; 269 opp-microvolt = <800000>; 270 required-opps = <&cci_opp_5>; 271 }; 272 273 opp-1308000000 { 274 opp-hz = /bits/ 64 <1308000000>; 275 opp-microvolt = <843750>; 276 required-opps = <&cci_opp_6>; 277 }; 278 279 opp-1419000000 { 280 opp-hz = /bits/ 64 <1419000000>; 281 opp-microvolt = <875000>; 282 required-opps = <&cci_opp_7>; 283 }; 284 285 opp-1530000000 { 286 opp-hz = /bits/ 64 <1530000000>; 287 opp-microvolt = <912500>; 288 required-opps = <&cci_opp_8>; 289 }; 290 291 opp-1670000000 { 292 opp-hz = /bits/ 64 <1670000000>; 293 opp-microvolt = <956250>; 294 required-opps = <&cci_opp_9>; 295 }; 296 297 opp-1733000000 { 298 opp-hz = /bits/ 64 <1733000000>; 299 opp-microvolt = <981250>; 300 required-opps = <&cci_opp_10>; 301 }; 302 303 opp-1796000000 { 304 opp-hz = /bits/ 64 <1796000000>; 305 opp-microvolt = <1012500>; 306 required-opps = <&cci_opp_11>; 307 }; 308 309 opp-1860000000 { 310 opp-hz = /bits/ 64 <1860000000>; 311 opp-microvolt = <1037500>; 312 required-opps = <&cci_opp_12>; 313 }; 314 315 opp-1923000000 { 316 opp-hz = /bits/ 64 <1923000000>; 317 opp-microvolt = <1062500>; 318 required-opps = <&cci_opp_13>; 319 }; 320 321 cluster1_opp_14: opp-1986000000 { 322 opp-hz = /bits/ 64 <1986000000>; 323 opp-microvolt = <1093750>; 324 required-opps = <&cci_opp_14>; 325 }; 326 327 cluster1_opp_15: opp-2050000000 { 328 opp-hz = /bits/ 64 <2050000000>; 329 opp-microvolt = <1118750>; 330 required-opps = <&cci_opp_15>; 331 }; 332 }; 333 334 cpus { 335 #address-cells = <1>; 336 #size-cells = <0>; 337 338 cpu-map { 339 cluster0 { 340 core0 { 341 cpu = <&cpu0>; 342 }; 343 344 core1 { 345 cpu = <&cpu1>; 346 }; 347 348 core2 { 349 cpu = <&cpu2>; 350 }; 351 352 core3 { 353 cpu = <&cpu3>; 354 }; 355 356 core4 { 357 cpu = <&cpu4>; 358 }; 359 360 core5 { 361 cpu = <&cpu5>; 362 }; 363 364 core6 { 365 cpu = <&cpu6>; 366 }; 367 368 core7 { 369 cpu = <&cpu7>; 370 }; 371 }; 372 }; 373 374 cpu0: cpu@0 { 375 device_type = "cpu"; 376 compatible = "arm,cortex-a55"; 377 reg = <0x000>; 378 enable-method = "psci"; 379 clock-frequency = <2000000000>; 380 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 381 <&apmixedsys CLK_APMIXED_MAINPLL>; 382 clock-names = "cpu", "intermediate"; 383 operating-points-v2 = <&cluster0_opp>; 384 dynamic-power-coefficient = <84>; 385 capacity-dmips-mhz = <382>; 386 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 387 i-cache-size = <32768>; 388 i-cache-line-size = <64>; 389 i-cache-sets = <128>; 390 d-cache-size = <32768>; 391 d-cache-line-size = <64>; 392 d-cache-sets = <128>; 393 next-level-cache = <&l2_0>; 394 #cooling-cells = <2>; 395 mediatek,cci = <&cci>; 396 }; 397 398 cpu1: cpu@100 { 399 device_type = "cpu"; 400 compatible = "arm,cortex-a55"; 401 reg = <0x100>; 402 enable-method = "psci"; 403 clock-frequency = <2000000000>; 404 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 405 <&apmixedsys CLK_APMIXED_MAINPLL>; 406 clock-names = "cpu", "intermediate"; 407 operating-points-v2 = <&cluster0_opp>; 408 dynamic-power-coefficient = <84>; 409 capacity-dmips-mhz = <382>; 410 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 411 i-cache-size = <32768>; 412 i-cache-line-size = <64>; 413 i-cache-sets = <128>; 414 d-cache-size = <32768>; 415 d-cache-line-size = <64>; 416 d-cache-sets = <128>; 417 next-level-cache = <&l2_0>; 418 #cooling-cells = <2>; 419 mediatek,cci = <&cci>; 420 }; 421 422 cpu2: cpu@200 { 423 device_type = "cpu"; 424 compatible = "arm,cortex-a55"; 425 reg = <0x200>; 426 enable-method = "psci"; 427 clock-frequency = <2000000000>; 428 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 429 <&apmixedsys CLK_APMIXED_MAINPLL>; 430 clock-names = "cpu", "intermediate"; 431 operating-points-v2 = <&cluster0_opp>; 432 dynamic-power-coefficient = <84>; 433 capacity-dmips-mhz = <382>; 434 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 435 i-cache-size = <32768>; 436 i-cache-line-size = <64>; 437 i-cache-sets = <128>; 438 d-cache-size = <32768>; 439 d-cache-line-size = <64>; 440 d-cache-sets = <128>; 441 next-level-cache = <&l2_0>; 442 #cooling-cells = <2>; 443 mediatek,cci = <&cci>; 444 }; 445 446 cpu3: cpu@300 { 447 device_type = "cpu"; 448 compatible = "arm,cortex-a55"; 449 reg = <0x300>; 450 enable-method = "psci"; 451 clock-frequency = <2000000000>; 452 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 453 <&apmixedsys CLK_APMIXED_MAINPLL>; 454 clock-names = "cpu", "intermediate"; 455 operating-points-v2 = <&cluster0_opp>; 456 dynamic-power-coefficient = <84>; 457 capacity-dmips-mhz = <382>; 458 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 459 i-cache-size = <32768>; 460 i-cache-line-size = <64>; 461 i-cache-sets = <128>; 462 d-cache-size = <32768>; 463 d-cache-line-size = <64>; 464 d-cache-sets = <128>; 465 next-level-cache = <&l2_0>; 466 #cooling-cells = <2>; 467 mediatek,cci = <&cci>; 468 }; 469 470 cpu4: cpu@400 { 471 device_type = "cpu"; 472 compatible = "arm,cortex-a55"; 473 reg = <0x400>; 474 enable-method = "psci"; 475 clock-frequency = <2000000000>; 476 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 477 <&apmixedsys CLK_APMIXED_MAINPLL>; 478 clock-names = "cpu", "intermediate"; 479 operating-points-v2 = <&cluster0_opp>; 480 dynamic-power-coefficient = <84>; 481 capacity-dmips-mhz = <382>; 482 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 483 i-cache-size = <32768>; 484 i-cache-line-size = <64>; 485 i-cache-sets = <128>; 486 d-cache-size = <32768>; 487 d-cache-line-size = <64>; 488 d-cache-sets = <128>; 489 next-level-cache = <&l2_0>; 490 #cooling-cells = <2>; 491 mediatek,cci = <&cci>; 492 }; 493 494 cpu5: cpu@500 { 495 device_type = "cpu"; 496 compatible = "arm,cortex-a55"; 497 reg = <0x500>; 498 enable-method = "psci"; 499 clock-frequency = <2000000000>; 500 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 501 <&apmixedsys CLK_APMIXED_MAINPLL>; 502 clock-names = "cpu", "intermediate"; 503 operating-points-v2 = <&cluster0_opp>; 504 dynamic-power-coefficient = <84>; 505 capacity-dmips-mhz = <382>; 506 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 507 i-cache-size = <32768>; 508 i-cache-line-size = <64>; 509 i-cache-sets = <128>; 510 d-cache-size = <32768>; 511 d-cache-line-size = <64>; 512 d-cache-sets = <128>; 513 next-level-cache = <&l2_0>; 514 #cooling-cells = <2>; 515 mediatek,cci = <&cci>; 516 }; 517 518 cpu6: cpu@600 { 519 device_type = "cpu"; 520 compatible = "arm,cortex-a76"; 521 reg = <0x600>; 522 enable-method = "psci"; 523 clock-frequency = <2050000000>; 524 clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>, 525 <&apmixedsys CLK_APMIXED_MAINPLL>; 526 clock-names = "cpu", "intermediate"; 527 operating-points-v2 = <&cluster1_opp>; 528 dynamic-power-coefficient = <335>; 529 capacity-dmips-mhz = <1024>; 530 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 531 i-cache-size = <65536>; 532 i-cache-line-size = <64>; 533 i-cache-sets = <256>; 534 d-cache-size = <65536>; 535 d-cache-line-size = <64>; 536 d-cache-sets = <256>; 537 next-level-cache = <&l2_1>; 538 #cooling-cells = <2>; 539 mediatek,cci = <&cci>; 540 }; 541 542 cpu7: cpu@700 { 543 device_type = "cpu"; 544 compatible = "arm,cortex-a76"; 545 reg = <0x700>; 546 enable-method = "psci"; 547 clock-frequency = <2050000000>; 548 clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>, 549 <&apmixedsys CLK_APMIXED_MAINPLL>; 550 clock-names = "cpu", "intermediate"; 551 operating-points-v2 = <&cluster1_opp>; 552 dynamic-power-coefficient = <335>; 553 capacity-dmips-mhz = <1024>; 554 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 555 i-cache-size = <65536>; 556 i-cache-line-size = <64>; 557 i-cache-sets = <256>; 558 d-cache-size = <65536>; 559 d-cache-line-size = <64>; 560 d-cache-sets = <256>; 561 next-level-cache = <&l2_1>; 562 #cooling-cells = <2>; 563 mediatek,cci = <&cci>; 564 }; 565 566 idle-states { 567 entry-method = "psci"; 568 569 cpu_ret_l: cpu-retention-l { 570 compatible = "arm,idle-state"; 571 arm,psci-suspend-param = <0x00010001>; 572 local-timer-stop; 573 entry-latency-us = <50>; 574 exit-latency-us = <100>; 575 min-residency-us = <1600>; 576 }; 577 578 cpu_ret_b: cpu-retention-b { 579 compatible = "arm,idle-state"; 580 arm,psci-suspend-param = <0x00010001>; 581 local-timer-stop; 582 entry-latency-us = <50>; 583 exit-latency-us = <100>; 584 min-residency-us = <1400>; 585 }; 586 587 cpu_off_l: cpu-off-l { 588 compatible = "arm,idle-state"; 589 arm,psci-suspend-param = <0x01010001>; 590 local-timer-stop; 591 entry-latency-us = <100>; 592 exit-latency-us = <250>; 593 min-residency-us = <2100>; 594 }; 595 596 cpu_off_b: cpu-off-b { 597 compatible = "arm,idle-state"; 598 arm,psci-suspend-param = <0x01010001>; 599 local-timer-stop; 600 entry-latency-us = <100>; 601 exit-latency-us = <250>; 602 min-residency-us = <1900>; 603 }; 604 }; 605 606 l2_0: l2-cache0 { 607 compatible = "cache"; 608 cache-level = <2>; 609 cache-size = <131072>; 610 cache-line-size = <64>; 611 cache-sets = <512>; 612 next-level-cache = <&l3_0>; 613 cache-unified; 614 }; 615 616 l2_1: l2-cache1 { 617 compatible = "cache"; 618 cache-level = <2>; 619 cache-size = <262144>; 620 cache-line-size = <64>; 621 cache-sets = <512>; 622 next-level-cache = <&l3_0>; 623 cache-unified; 624 }; 625 626 l3_0: l3-cache { 627 compatible = "cache"; 628 cache-level = <3>; 629 cache-size = <1048576>; 630 cache-line-size = <64>; 631 cache-sets = <1024>; 632 cache-unified; 633 }; 634 }; 635 636 clk13m: fixed-factor-clock-13m { 637 compatible = "fixed-factor-clock"; 638 #clock-cells = <0>; 639 clocks = <&clk26m>; 640 clock-div = <2>; 641 clock-mult = <1>; 642 clock-output-names = "clk13m"; 643 }; 644 645 clk26m: oscillator-26m { 646 compatible = "fixed-clock"; 647 #clock-cells = <0>; 648 clock-frequency = <26000000>; 649 clock-output-names = "clk26m"; 650 }; 651 652 clk32k: oscillator-32k { 653 compatible = "fixed-clock"; 654 #clock-cells = <0>; 655 clock-frequency = <32768>; 656 clock-output-names = "clk32k"; 657 }; 658 659 gpu_opp_table: opp-table-gpu { 660 compatible = "operating-points-v2"; 661 662 opp-299000000 { 663 opp-hz = /bits/ 64 <299000000>; 664 opp-microvolt = <612500>; 665 opp-supported-hw = <0xff>; 666 }; 667 668 opp-332000000 { 669 opp-hz = /bits/ 64 <332000000>; 670 opp-microvolt = <625000>; 671 opp-supported-hw = <0xff>; 672 }; 673 674 opp-366000000 { 675 opp-hz = /bits/ 64 <366000000>; 676 opp-microvolt = <637500>; 677 opp-supported-hw = <0xff>; 678 }; 679 680 opp-400000000 { 681 opp-hz = /bits/ 64 <400000000>; 682 opp-microvolt = <643750>; 683 opp-supported-hw = <0xff>; 684 }; 685 686 opp-434000000 { 687 opp-hz = /bits/ 64 <434000000>; 688 opp-microvolt = <656250>; 689 opp-supported-hw = <0xff>; 690 }; 691 692 opp-484000000 { 693 opp-hz = /bits/ 64 <484000000>; 694 opp-microvolt = <668750>; 695 opp-supported-hw = <0xff>; 696 }; 697 698 opp-535000000 { 699 opp-hz = /bits/ 64 <535000000>; 700 opp-microvolt = <687500>; 701 opp-supported-hw = <0xff>; 702 }; 703 704 opp-586000000 { 705 opp-hz = /bits/ 64 <586000000>; 706 opp-microvolt = <700000>; 707 opp-supported-hw = <0xff>; 708 }; 709 710 opp-637000000 { 711 opp-hz = /bits/ 64 <637000000>; 712 opp-microvolt = <712500>; 713 opp-supported-hw = <0xff>; 714 }; 715 716 opp-690000000 { 717 opp-hz = /bits/ 64 <690000000>; 718 opp-microvolt = <737500>; 719 opp-supported-hw = <0xff>; 720 }; 721 722 opp-743000000 { 723 opp-hz = /bits/ 64 <743000000>; 724 opp-microvolt = <756250>; 725 opp-supported-hw = <0xff>; 726 }; 727 728 opp-796000000 { 729 opp-hz = /bits/ 64 <796000000>; 730 opp-microvolt = <781250>; 731 opp-supported-hw = <0xff>; 732 }; 733 734 opp-850000000 { 735 opp-hz = /bits/ 64 <850000000>; 736 opp-microvolt = <800000>; 737 opp-supported-hw = <0xff>; 738 }; 739 740 opp-900000000-3 { 741 opp-hz = /bits/ 64 <900000000>; 742 opp-microvolt = <850000>; 743 opp-supported-hw = <0xcf>; 744 }; 745 746 opp-900000000-4 { 747 opp-hz = /bits/ 64 <900000000>; 748 opp-microvolt = <837500>; 749 opp-supported-hw = <0x10>; 750 }; 751 752 opp-900000000-5 { 753 opp-hz = /bits/ 64 <900000000>; 754 opp-microvolt = <825000>; 755 opp-supported-hw = <0x20>; 756 }; 757 758 opp-950000000-3 { 759 opp-hz = /bits/ 64 <950000000>; 760 opp-microvolt = <900000>; 761 opp-supported-hw = <0xcf>; 762 }; 763 764 opp-950000000-4 { 765 opp-hz = /bits/ 64 <950000000>; 766 opp-microvolt = <875000>; 767 opp-supported-hw = <0x10>; 768 }; 769 770 opp-950000000-5 { 771 opp-hz = /bits/ 64 <950000000>; 772 opp-microvolt = <850000>; 773 opp-supported-hw = <0x20>; 774 }; 775 776 opp-1000000000-3 { 777 opp-hz = /bits/ 64 <1000000000>; 778 opp-microvolt = <950000>; 779 opp-supported-hw = <0xcf>; 780 }; 781 782 opp-1000000000-4 { 783 opp-hz = /bits/ 64 <1000000000>; 784 opp-microvolt = <912500>; 785 opp-supported-hw = <0x10>; 786 }; 787 788 opp-1000000000-5 { 789 opp-hz = /bits/ 64 <1000000000>; 790 opp-microvolt = <875000>; 791 opp-supported-hw = <0x20>; 792 }; 793 }; 794 795 pmu-a55 { 796 compatible = "arm,cortex-a55-pmu"; 797 interrupt-parent = <&gic>; 798 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 799 }; 800 801 pmu-a76 { 802 compatible = "arm,cortex-a76-pmu"; 803 interrupt-parent = <&gic>; 804 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 805 }; 806 807 psci { 808 compatible = "arm,psci-1.0"; 809 method = "smc"; 810 }; 811 812 timer { 813 compatible = "arm,armv8-timer"; 814 interrupt-parent = <&gic>; 815 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 816 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 817 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 818 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 819 }; 820 821 soc { 822 #address-cells = <2>; 823 #size-cells = <2>; 824 compatible = "simple-bus"; 825 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 826 ranges; 827 828 gic: interrupt-controller@c000000 { 829 compatible = "arm,gic-v3"; 830 #interrupt-cells = <4>; 831 #redistributor-regions = <1>; 832 interrupt-parent = <&gic>; 833 interrupt-controller; 834 reg = <0 0x0c000000 0 0x40000>, 835 <0 0x0c040000 0 0x200000>; 836 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 837 838 ppi-partitions { 839 ppi_cluster0: interrupt-partition-0 { 840 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 841 }; 842 843 ppi_cluster1: interrupt-partition-1 { 844 affinity = <&cpu6 &cpu7>; 845 }; 846 }; 847 }; 848 849 mcusys: syscon@c53a000 { 850 compatible = "mediatek,mt8186-mcusys", "syscon"; 851 reg = <0 0xc53a000 0 0x1000>; 852 #clock-cells = <1>; 853 }; 854 855 topckgen: syscon@10000000 { 856 compatible = "mediatek,mt8186-topckgen", "syscon"; 857 reg = <0 0x10000000 0 0x1000>; 858 #clock-cells = <1>; 859 }; 860 861 infracfg_ao: syscon@10001000 { 862 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 863 reg = <0 0x10001000 0 0x1000>; 864 #clock-cells = <1>; 865 #reset-cells = <1>; 866 }; 867 868 pericfg: syscon@10003000 { 869 compatible = "mediatek,mt8186-pericfg", "syscon"; 870 reg = <0 0x10003000 0 0x1000>; 871 }; 872 873 pio: pinctrl@10005000 { 874 compatible = "mediatek,mt8186-pinctrl"; 875 reg = <0 0x10005000 0 0x1000>, 876 <0 0x10002000 0 0x0200>, 877 <0 0x10002200 0 0x0200>, 878 <0 0x10002400 0 0x0200>, 879 <0 0x10002600 0 0x0200>, 880 <0 0x10002a00 0 0x0200>, 881 <0 0x10002c00 0 0x0200>, 882 <0 0x1000b000 0 0x1000>; 883 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 884 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 885 gpio-controller; 886 #gpio-cells = <2>; 887 gpio-ranges = <&pio 0 0 185>; 888 interrupt-controller; 889 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 890 #interrupt-cells = <2>; 891 }; 892 893 scpsys: syscon@10006000 { 894 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 895 reg = <0 0x10006000 0 0x1000>; 896 897 /* System Power Manager */ 898 spm: power-controller { 899 compatible = "mediatek,mt8186-power-controller"; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 #power-domain-cells = <1>; 903 904 /* power domain of the SoC */ 905 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 906 reg = <MT8186_POWER_DOMAIN_MFG0>; 907 clocks = <&topckgen CLK_TOP_MFG>; 908 clock-names = "mfg00"; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 #power-domain-cells = <1>; 912 913 mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 { 914 reg = <MT8186_POWER_DOMAIN_MFG1>; 915 mediatek,infracfg = <&infracfg_ao>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 #power-domain-cells = <1>; 919 920 power-domain@MT8186_POWER_DOMAIN_MFG2 { 921 reg = <MT8186_POWER_DOMAIN_MFG2>; 922 #power-domain-cells = <0>; 923 }; 924 925 power-domain@MT8186_POWER_DOMAIN_MFG3 { 926 reg = <MT8186_POWER_DOMAIN_MFG3>; 927 #power-domain-cells = <0>; 928 }; 929 }; 930 }; 931 932 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 933 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 934 clocks = <&topckgen CLK_TOP_SENINF>, 935 <&topckgen CLK_TOP_SENINF1>; 936 clock-names = "subsys-csirx-top0", 937 "subsys-csirx-top1"; 938 #power-domain-cells = <0>; 939 }; 940 941 power-domain@MT8186_POWER_DOMAIN_SSUSB { 942 reg = <MT8186_POWER_DOMAIN_SSUSB>; 943 clocks = <&topckgen CLK_TOP_USB_TOP>, 944 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>; 945 clock-names = "sys_ck", "ref_ck"; 946 #power-domain-cells = <0>; 947 }; 948 949 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 950 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 951 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 952 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>; 953 clock-names = "sys_ck", "ref_ck"; 954 #power-domain-cells = <0>; 955 }; 956 957 power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 958 reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 959 clocks = <&topckgen CLK_TOP_AUDIODSP>, 960 <&topckgen CLK_TOP_ADSP_BUS>; 961 clock-names = "audioadsp", 962 "subsys-adsp-bus"; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 #power-domain-cells = <1>; 966 967 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 968 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 969 #address-cells = <1>; 970 #size-cells = <0>; 971 #power-domain-cells = <1>; 972 973 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 974 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 975 mediatek,infracfg = <&infracfg_ao>; 976 #power-domain-cells = <0>; 977 }; 978 }; 979 }; 980 981 power-domain@MT8186_POWER_DOMAIN_CONN_ON { 982 reg = <MT8186_POWER_DOMAIN_CONN_ON>; 983 mediatek,infracfg = <&infracfg_ao>; 984 #power-domain-cells = <0>; 985 }; 986 987 power-domain@MT8186_POWER_DOMAIN_DIS { 988 reg = <MT8186_POWER_DOMAIN_DIS>; 989 clocks = <&topckgen CLK_TOP_DISP>, 990 <&topckgen CLK_TOP_MDP>, 991 <&mmsys CLK_MM_SMI_INFRA>, 992 <&mmsys CLK_MM_SMI_COMMON>, 993 <&mmsys CLK_MM_SMI_GALS>, 994 <&mmsys CLK_MM_SMI_IOMMU>; 995 clock-names = "disp", "mdp", 996 "subsys-smi-infra", 997 "subsys-smi-common", 998 "subsys-smi-gals", 999 "subsys-smi-iommu"; 1000 mediatek,infracfg = <&infracfg_ao>; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 #power-domain-cells = <1>; 1004 1005 power-domain@MT8186_POWER_DOMAIN_VDEC { 1006 reg = <MT8186_POWER_DOMAIN_VDEC>; 1007 clocks = <&topckgen CLK_TOP_VDEC>, 1008 <&vdecsys CLK_VDEC_LARB1_CKEN>; 1009 clock-names = "vdec0", "larb"; 1010 mediatek,infracfg = <&infracfg_ao>; 1011 #power-domain-cells = <0>; 1012 }; 1013 1014 power-domain@MT8186_POWER_DOMAIN_CAM { 1015 reg = <MT8186_POWER_DOMAIN_CAM>; 1016 clocks = <&topckgen CLK_TOP_SENINF>, 1017 <&topckgen CLK_TOP_SENINF1>, 1018 <&topckgen CLK_TOP_SENINF2>, 1019 <&topckgen CLK_TOP_SENINF3>, 1020 <&camsys CLK_CAM2MM_GALS>, 1021 <&topckgen CLK_TOP_CAMTM>, 1022 <&topckgen CLK_TOP_CAM>; 1023 clock-names = "cam0", "cam1", "cam2", 1024 "cam3", "gals", 1025 "subsys-cam-tm", 1026 "subsys-cam-top"; 1027 mediatek,infracfg = <&infracfg_ao>; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 #power-domain-cells = <1>; 1031 1032 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 1033 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 1034 #power-domain-cells = <0>; 1035 }; 1036 1037 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 1038 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 1039 #power-domain-cells = <0>; 1040 }; 1041 }; 1042 1043 power-domain@MT8186_POWER_DOMAIN_IMG { 1044 reg = <MT8186_POWER_DOMAIN_IMG>; 1045 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1046 <&topckgen CLK_TOP_IMG1>; 1047 clock-names = "gals", "subsys-img-top"; 1048 mediatek,infracfg = <&infracfg_ao>; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 #power-domain-cells = <1>; 1052 1053 power-domain@MT8186_POWER_DOMAIN_IMG2 { 1054 reg = <MT8186_POWER_DOMAIN_IMG2>; 1055 #power-domain-cells = <0>; 1056 }; 1057 }; 1058 1059 power-domain@MT8186_POWER_DOMAIN_IPE { 1060 reg = <MT8186_POWER_DOMAIN_IPE>; 1061 clocks = <&topckgen CLK_TOP_IPE>, 1062 <&ipesys CLK_IPE_LARB19>, 1063 <&ipesys CLK_IPE_LARB20>, 1064 <&ipesys CLK_IPE_SMI_SUBCOM>, 1065 <&ipesys CLK_IPE_GALS_IPE>; 1066 clock-names = "subsys-ipe-top", 1067 "subsys-ipe-larb0", 1068 "subsys-ipe-larb1", 1069 "subsys-ipe-smi", 1070 "subsys-ipe-gals"; 1071 mediatek,infracfg = <&infracfg_ao>; 1072 #power-domain-cells = <0>; 1073 }; 1074 1075 power-domain@MT8186_POWER_DOMAIN_VENC { 1076 reg = <MT8186_POWER_DOMAIN_VENC>; 1077 clocks = <&topckgen CLK_TOP_VENC>, 1078 <&vencsys CLK_VENC_CKE1_VENC>; 1079 clock-names = "venc0", "subsys-larb"; 1080 mediatek,infracfg = <&infracfg_ao>; 1081 #power-domain-cells = <0>; 1082 }; 1083 1084 power-domain@MT8186_POWER_DOMAIN_WPE { 1085 reg = <MT8186_POWER_DOMAIN_WPE>; 1086 clocks = <&topckgen CLK_TOP_WPE>, 1087 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1088 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 1089 clock-names = "wpe0", 1090 "subsys-larb-ck", 1091 "subsys-larb-pclk"; 1092 mediatek,infracfg = <&infracfg_ao>; 1093 #power-domain-cells = <0>; 1094 }; 1095 }; 1096 }; 1097 }; 1098 1099 watchdog: watchdog@10007000 { 1100 compatible = "mediatek,mt8186-wdt"; 1101 mediatek,disable-extrst; 1102 reg = <0 0x10007000 0 0x1000>; 1103 #reset-cells = <1>; 1104 }; 1105 1106 apmixedsys: syscon@1000c000 { 1107 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 1108 reg = <0 0x1000c000 0 0x1000>; 1109 #clock-cells = <1>; 1110 }; 1111 1112 pwrap: pwrap@1000d000 { 1113 compatible = "mediatek,mt8186-pwrap", "syscon"; 1114 reg = <0 0x1000d000 0 0x1000>; 1115 reg-names = "pwrap"; 1116 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1117 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 1118 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 1119 clock-names = "spi", "wrap"; 1120 }; 1121 1122 spmi: spmi@10015000 { 1123 compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; 1124 reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; 1125 reg-names = "pmif", "spmimst"; 1126 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 1127 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 1128 <&topckgen CLK_TOP_SPMI_MST>; 1129 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; 1130 assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>; 1131 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 1132 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>, 1133 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>; 1134 status = "disabled"; 1135 }; 1136 1137 systimer: timer@10017000 { 1138 compatible = "mediatek,mt8186-timer", 1139 "mediatek,mt6765-timer"; 1140 reg = <0 0x10017000 0 0x1000>; 1141 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 1142 clocks = <&clk13m>; 1143 }; 1144 1145 gce: mailbox@1022c000 { 1146 compatible = "mediatek,mt8186-gce"; 1147 reg = <0 0X1022c000 0 0x4000>; 1148 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 1149 clock-names = "gce"; 1150 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 1151 #mbox-cells = <2>; 1152 }; 1153 1154 scp: scp@10500000 { 1155 compatible = "mediatek,mt8186-scp"; 1156 reg = <0 0x10500000 0 0x40000>, 1157 <0 0x105c0000 0 0x19080>; 1158 reg-names = "sram", "cfg"; 1159 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 1160 }; 1161 1162 adsp: adsp@10680000 { 1163 compatible = "mediatek,mt8186-dsp"; 1164 reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, 1165 <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; 1166 reg-names = "cfg", "sram", "sec", "bus"; 1167 clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; 1168 clock-names = "audiodsp", "adsp_bus"; 1169 assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>, 1170 <&topckgen CLK_TOP_ADSP_BUS>; 1171 assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>; 1172 mbox-names = "rx", "tx"; 1173 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 1174 power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>; 1175 status = "disabled"; 1176 }; 1177 1178 adsp_mailbox0: mailbox@10686100 { 1179 compatible = "mediatek,mt8186-adsp-mbox"; 1180 #mbox-cells = <0>; 1181 reg = <0 0x10686100 0 0x1000>; 1182 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; 1183 }; 1184 1185 adsp_mailbox1: mailbox@10687100 { 1186 compatible = "mediatek,mt8186-adsp-mbox"; 1187 #mbox-cells = <0>; 1188 reg = <0 0x10687100 0 0x1000>; 1189 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>; 1190 }; 1191 1192 nor_flash: spi@11000000 { 1193 compatible = "mediatek,mt8186-nor"; 1194 reg = <0 0x11000000 0 0x1000>; 1195 clocks = <&topckgen CLK_TOP_SPINOR>, 1196 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 1197 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 1198 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 1199 clock-names = "spi", "sf", "axi", "axi_s"; 1200 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 1201 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 1202 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 1203 status = "disabled"; 1204 }; 1205 1206 auxadc: adc@11001000 { 1207 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 1208 reg = <0 0x11001000 0 0x1000>; 1209 #io-channel-cells = <1>; 1210 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1211 clock-names = "main"; 1212 }; 1213 1214 uart0: serial@11002000 { 1215 compatible = "mediatek,mt8186-uart", 1216 "mediatek,mt6577-uart"; 1217 reg = <0 0x11002000 0 0x1000>; 1218 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 1219 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1220 clock-names = "baud", "bus"; 1221 status = "disabled"; 1222 }; 1223 1224 uart1: serial@11003000 { 1225 compatible = "mediatek,mt8186-uart", 1226 "mediatek,mt6577-uart"; 1227 reg = <0 0x11003000 0 0x1000>; 1228 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1229 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1230 clock-names = "baud", "bus"; 1231 status = "disabled"; 1232 }; 1233 1234 i2c0: i2c@11007000 { 1235 compatible = "mediatek,mt8186-i2c"; 1236 reg = <0 0x11007000 0 0x1000>, 1237 <0 0x10200100 0 0x100>; 1238 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 1239 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 1240 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1241 clock-names = "main", "dma"; 1242 clock-div = <1>; 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 status = "disabled"; 1246 }; 1247 1248 i2c1: i2c@11008000 { 1249 compatible = "mediatek,mt8186-i2c"; 1250 reg = <0 0x11008000 0 0x1000>, 1251 <0 0x10200200 0 0x100>; 1252 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1253 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 1254 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1255 clock-names = "main", "dma"; 1256 clock-div = <1>; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 status = "disabled"; 1260 }; 1261 1262 i2c2: i2c@11009000 { 1263 compatible = "mediatek,mt8186-i2c"; 1264 reg = <0 0x11009000 0 0x1000>, 1265 <0 0x10200300 0 0x180>; 1266 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 1267 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 1268 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1269 clock-names = "main", "dma"; 1270 clock-div = <1>; 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 status = "disabled"; 1274 }; 1275 1276 i2c3: i2c@1100f000 { 1277 compatible = "mediatek,mt8186-i2c"; 1278 reg = <0 0x1100f000 0 0x1000>, 1279 <0 0x10200480 0 0x100>; 1280 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 1281 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 1282 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1283 clock-names = "main", "dma"; 1284 clock-div = <1>; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 status = "disabled"; 1288 }; 1289 1290 i2c4: i2c@11011000 { 1291 compatible = "mediatek,mt8186-i2c"; 1292 reg = <0 0x11011000 0 0x1000>, 1293 <0 0x10200580 0 0x180>; 1294 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 1295 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 1296 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1297 clock-names = "main", "dma"; 1298 clock-div = <1>; 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 status = "disabled"; 1302 }; 1303 1304 i2c5: i2c@11016000 { 1305 compatible = "mediatek,mt8186-i2c"; 1306 reg = <0 0x11016000 0 0x1000>, 1307 <0 0x10200700 0 0x100>; 1308 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 1309 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 1310 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1311 clock-names = "main", "dma"; 1312 clock-div = <1>; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 status = "disabled"; 1316 }; 1317 1318 i2c6: i2c@1100d000 { 1319 compatible = "mediatek,mt8186-i2c"; 1320 reg = <0 0x1100d000 0 0x1000>, 1321 <0 0x10200800 0 0x100>; 1322 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1323 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 1324 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1325 clock-names = "main", "dma"; 1326 clock-div = <1>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 status = "disabled"; 1330 }; 1331 1332 i2c7: i2c@11004000 { 1333 compatible = "mediatek,mt8186-i2c"; 1334 reg = <0 0x11004000 0 0x1000>, 1335 <0 0x10200900 0 0x180>; 1336 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 1337 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 1338 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1339 clock-names = "main", "dma"; 1340 clock-div = <1>; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 status = "disabled"; 1344 }; 1345 1346 i2c8: i2c@11005000 { 1347 compatible = "mediatek,mt8186-i2c"; 1348 reg = <0 0x11005000 0 0x1000>, 1349 <0 0x10200A80 0 0x180>; 1350 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1351 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 1352 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1353 clock-names = "main", "dma"; 1354 clock-div = <1>; 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 status = "disabled"; 1358 }; 1359 1360 spi0: spi@1100a000 { 1361 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 reg = <0 0x1100a000 0 0x1000>; 1365 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 1366 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1367 <&topckgen CLK_TOP_SPI>, 1368 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1369 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1370 status = "disabled"; 1371 }; 1372 1373 lvts: thermal-sensor@1100b000 { 1374 compatible = "mediatek,mt8186-lvts"; 1375 reg = <0 0x1100b000 0 0x1000>; 1376 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 1377 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1378 resets = <&infracfg_ao MT8186_INFRA_THERMAL_CTRL_RST>; 1379 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1380 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1381 #thermal-sensor-cells = <1>; 1382 }; 1383 1384 svs: svs@1100bc00 { 1385 compatible = "mediatek,mt8186-svs"; 1386 reg = <0 0x1100bc00 0 0x400>; 1387 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 1388 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1389 clock-names = "main"; 1390 nvmem-cells = <&svs_calibration>, <&lvts_efuse_data1>; 1391 nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; 1392 resets = <&infracfg_ao MT8186_INFRA_PTP_CTRL_RST>; 1393 reset-names = "svs_rst"; 1394 }; 1395 1396 pwm0: pwm@1100e000 { 1397 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 1398 reg = <0 0x1100e000 0 0x1000>; 1399 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1400 #pwm-cells = <2>; 1401 clocks = <&topckgen CLK_TOP_DISP_PWM>, 1402 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1403 clock-names = "main", "mm"; 1404 status = "disabled"; 1405 }; 1406 1407 spi1: spi@11010000 { 1408 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 reg = <0 0x11010000 0 0x1000>; 1412 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 1413 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1414 <&topckgen CLK_TOP_SPI>, 1415 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1416 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1417 status = "disabled"; 1418 }; 1419 1420 spi2: spi@11012000 { 1421 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 reg = <0 0x11012000 0 0x1000>; 1425 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 1426 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1427 <&topckgen CLK_TOP_SPI>, 1428 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1429 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1430 status = "disabled"; 1431 }; 1432 1433 spi3: spi@11013000 { 1434 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 reg = <0 0x11013000 0 0x1000>; 1438 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 1439 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1440 <&topckgen CLK_TOP_SPI>, 1441 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1442 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1443 status = "disabled"; 1444 }; 1445 1446 spi4: spi@11014000 { 1447 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1448 #address-cells = <1>; 1449 #size-cells = <0>; 1450 reg = <0 0x11014000 0 0x1000>; 1451 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1452 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1453 <&topckgen CLK_TOP_SPI>, 1454 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1455 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1456 status = "disabled"; 1457 }; 1458 1459 spi5: spi@11015000 { 1460 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 reg = <0 0x11015000 0 0x1000>; 1464 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1465 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1466 <&topckgen CLK_TOP_SPI>, 1467 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1468 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1469 status = "disabled"; 1470 }; 1471 1472 imp_iic_wrap: clock-controller@11017000 { 1473 compatible = "mediatek,mt8186-imp_iic_wrap"; 1474 reg = <0 0x11017000 0 0x1000>; 1475 #clock-cells = <1>; 1476 }; 1477 1478 uart2: serial@11018000 { 1479 compatible = "mediatek,mt8186-uart", 1480 "mediatek,mt6577-uart"; 1481 reg = <0 0x11018000 0 0x1000>; 1482 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 1483 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1484 clock-names = "baud", "bus"; 1485 status = "disabled"; 1486 }; 1487 1488 i2c9: i2c@11019000 { 1489 compatible = "mediatek,mt8186-i2c"; 1490 reg = <0 0x11019000 0 0x1000>, 1491 <0 0x10200c00 0 0x180>; 1492 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1493 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 1494 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1495 clock-names = "main", "dma"; 1496 clock-div = <1>; 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 status = "disabled"; 1500 }; 1501 1502 afe: audio-controller@11210000 { 1503 compatible = "mediatek,mt8186-sound"; 1504 reg = <0 0x11210000 0 0x2000>; 1505 clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, 1506 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, 1507 <&topckgen CLK_TOP_AUDIO>, 1508 <&topckgen CLK_TOP_AUD_INTBUS>, 1509 <&topckgen CLK_TOP_MAINPLL_D2_D4>, 1510 <&topckgen CLK_TOP_AUD_1>, 1511 <&apmixedsys CLK_APMIXED_APLL1>, 1512 <&topckgen CLK_TOP_AUD_2>, 1513 <&apmixedsys CLK_APMIXED_APLL2>, 1514 <&topckgen CLK_TOP_AUD_ENGEN1>, 1515 <&topckgen CLK_TOP_APLL1_D8>, 1516 <&topckgen CLK_TOP_AUD_ENGEN2>, 1517 <&topckgen CLK_TOP_APLL2_D8>, 1518 <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, 1519 <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, 1520 <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, 1521 <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, 1522 <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, 1523 <&topckgen CLK_TOP_APLL12_CK_DIV0>, 1524 <&topckgen CLK_TOP_APLL12_CK_DIV1>, 1525 <&topckgen CLK_TOP_APLL12_CK_DIV2>, 1526 <&topckgen CLK_TOP_APLL12_CK_DIV4>, 1527 <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, 1528 <&topckgen CLK_TOP_AUDIO_H>, 1529 <&clk26m>; 1530 clock-names = "aud_infra_clk", 1531 "mtkaif_26m_clk", 1532 "top_mux_audio", 1533 "top_mux_audio_int", 1534 "top_mainpll_d2_d4", 1535 "top_mux_aud_1", 1536 "top_apll1_ck", 1537 "top_mux_aud_2", 1538 "top_apll2_ck", 1539 "top_mux_aud_eng1", 1540 "top_apll1_d8", 1541 "top_mux_aud_eng2", 1542 "top_apll2_d8", 1543 "top_i2s0_m_sel", 1544 "top_i2s1_m_sel", 1545 "top_i2s2_m_sel", 1546 "top_i2s4_m_sel", 1547 "top_tdm_m_sel", 1548 "top_apll12_div0", 1549 "top_apll12_div1", 1550 "top_apll12_div2", 1551 "top_apll12_div4", 1552 "top_apll12_div_tdm", 1553 "top_mux_audio_h", 1554 "top_clk26m_clk"; 1555 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1556 mediatek,apmixedsys = <&apmixedsys>; 1557 mediatek,infracfg = <&infracfg_ao>; 1558 mediatek,topckgen = <&topckgen>; 1559 resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; 1560 reset-names = "audiosys"; 1561 status = "disabled"; 1562 }; 1563 1564 ssusb0: usb@11201000 { 1565 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1566 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1567 reg-names = "mac", "ippc"; 1568 clocks = <&topckgen CLK_TOP_USB_TOP>, 1569 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1570 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1571 <&infracfg_ao CLK_INFRA_AO_ICUSB>, 1572 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; 1573 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1574 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>; 1575 phys = <&u2port0 PHY_TYPE_USB2>; 1576 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; 1577 #address-cells = <2>; 1578 #size-cells = <2>; 1579 ranges; 1580 status = "disabled"; 1581 1582 usb_host0: usb@11200000 { 1583 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1584 reg = <0 0x11200000 0 0x1000>; 1585 reg-names = "mac"; 1586 clocks = <&topckgen CLK_TOP_USB_TOP>, 1587 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1588 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1589 <&infracfg_ao CLK_INFRA_AO_ICUSB>, 1590 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; 1591 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1592 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 1593 mediatek,syscon-wakeup = <&pericfg 0x420 2>; 1594 wakeup-source; 1595 status = "disabled"; 1596 }; 1597 }; 1598 1599 mmc0: mmc@11230000 { 1600 compatible = "mediatek,mt8186-mmc", 1601 "mediatek,mt8183-mmc"; 1602 reg = <0 0x11230000 0 0x10000>, 1603 <0 0x11cd0000 0 0x1000>; 1604 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1605 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1606 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1607 <&infracfg_ao CLK_INFRA_AO_MSDCFDE>; 1608 clock-names = "source", "hclk", "source_cg", "crypto"; 1609 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 1610 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 1611 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 1612 status = "disabled"; 1613 }; 1614 1615 mmc1: mmc@11240000 { 1616 compatible = "mediatek,mt8186-mmc", 1617 "mediatek,mt8183-mmc"; 1618 reg = <0 0x11240000 0 0x1000>, 1619 <0 0x11c90000 0 0x1000>; 1620 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1621 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1622 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1623 clock-names = "source", "hclk", "source_cg"; 1624 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 1625 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1626 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1627 status = "disabled"; 1628 }; 1629 1630 ssusb1: usb@11281000 { 1631 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1632 reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; 1633 reg-names = "mac", "ippc"; 1634 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1635 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1636 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1637 <&clk26m>, 1638 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; 1639 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1640 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 1641 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1642 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; 1643 #address-cells = <2>; 1644 #size-cells = <2>; 1645 ranges; 1646 status = "disabled"; 1647 1648 usb_host1: usb@11280000 { 1649 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1650 reg = <0 0x11280000 0 0x1000>; 1651 reg-names = "mac"; 1652 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1653 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1654 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1655 <&clk26m>, 1656 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; 1657 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; 1658 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 1659 mediatek,syscon-wakeup = <&pericfg 0x424 2>; 1660 wakeup-source; 1661 status = "disabled"; 1662 }; 1663 }; 1664 1665 u3phy0: t-phy@11c80000 { 1666 compatible = "mediatek,mt8186-tphy", 1667 "mediatek,generic-tphy-v2"; 1668 #address-cells = <1>; 1669 #size-cells = <1>; 1670 ranges = <0x0 0x0 0x11c80000 0x1000>; 1671 status = "disabled"; 1672 1673 u2port1: usb-phy@0 { 1674 reg = <0x0 0x700>; 1675 clocks = <&clk26m>; 1676 clock-names = "ref"; 1677 #phy-cells = <1>; 1678 }; 1679 1680 u3port1: usb-phy@700 { 1681 reg = <0x700 0x900>; 1682 clocks = <&clk26m>; 1683 clock-names = "ref"; 1684 #phy-cells = <1>; 1685 }; 1686 }; 1687 1688 u3phy1: t-phy@11ca0000 { 1689 compatible = "mediatek,mt8186-tphy", 1690 "mediatek,generic-tphy-v2"; 1691 #address-cells = <1>; 1692 #size-cells = <1>; 1693 ranges = <0x0 0x0 0x11ca0000 0x1000>; 1694 status = "disabled"; 1695 1696 u2port0: usb-phy@0 { 1697 reg = <0x0 0x700>; 1698 clocks = <&clk26m>; 1699 clock-names = "ref"; 1700 #phy-cells = <1>; 1701 mediatek,discth = <0x8>; 1702 }; 1703 }; 1704 1705 efuse: efuse@11cb0000 { 1706 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 1707 reg = <0 0x11cb0000 0 0x1000>; 1708 #address-cells = <1>; 1709 #size-cells = <1>; 1710 1711 lvts_efuse_data1: lvts1-calib@1cc { 1712 reg = <0x1cc 0x14>; 1713 }; 1714 1715 lvts_efuse_data2: lvts2-calib@2f8 { 1716 reg = <0x2f8 0x14>; 1717 }; 1718 1719 svs_calibration: calib@550 { 1720 reg = <0x550 0x50>; 1721 }; 1722 1723 gpu_speedbin: gpu-speedbin@59c { 1724 reg = <0x59c 0x4>; 1725 bits = <0 3>; 1726 }; 1727 1728 socinfo-data1@7a0 { 1729 reg = <0x7a0 0x4>; 1730 }; 1731 }; 1732 1733 mipi_tx0: dsi-phy@11cc0000 { 1734 compatible = "mediatek,mt8183-mipi-tx"; 1735 reg = <0 0x11cc0000 0 0x1000>; 1736 clocks = <&clk26m>; 1737 #clock-cells = <0>; 1738 #phy-cells = <0>; 1739 clock-output-names = "mipi_tx0_pll"; 1740 status = "disabled"; 1741 }; 1742 1743 mfgsys: clock-controller@13000000 { 1744 compatible = "mediatek,mt8186-mfgsys"; 1745 reg = <0 0x13000000 0 0x1000>; 1746 #clock-cells = <1>; 1747 }; 1748 1749 gpu: gpu@13040000 { 1750 compatible = "mediatek,mt8186-mali", 1751 "arm,mali-bifrost"; 1752 reg = <0 0x13040000 0 0x4000>; 1753 1754 clocks = <&mfgsys CLK_MFG_BG3D>; 1755 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>, 1756 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>, 1757 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 1758 interrupt-names = "job", "mmu", "gpu"; 1759 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>, 1760 <&spm MT8186_POWER_DOMAIN_MFG3>; 1761 power-domain-names = "core0", "core1"; 1762 #cooling-cells = <2>; 1763 nvmem-cells = <&gpu_speedbin>; 1764 nvmem-cell-names = "speed-bin"; 1765 operating-points-v2 = <&gpu_opp_table>; 1766 dynamic-power-coefficient = <4687>; 1767 status = "disabled"; 1768 }; 1769 1770 mmsys: syscon@14000000 { 1771 compatible = "mediatek,mt8186-mmsys", "syscon"; 1772 reg = <0 0x14000000 0 0x1000>; 1773 #clock-cells = <1>; 1774 #reset-cells = <1>; 1775 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1776 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1777 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1778 }; 1779 1780 mutex: mutex@14001000 { 1781 compatible = "mediatek,mt8186-disp-mutex"; 1782 reg = <0 0x14001000 0 0x1000>; 1783 clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1784 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>; 1785 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1786 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1787 <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1788 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1789 }; 1790 1791 smi_common: smi@14002000 { 1792 compatible = "mediatek,mt8186-smi-common"; 1793 reg = <0 0x14002000 0 0x1000>; 1794 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, 1795 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; 1796 clock-names = "apb", "smi", "gals0", "gals1"; 1797 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1798 }; 1799 1800 larb0: smi@14003000 { 1801 compatible = "mediatek,mt8186-smi-larb"; 1802 reg = <0 0x14003000 0 0x1000>; 1803 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1804 <&mmsys CLK_MM_SMI_COMMON>; 1805 clock-names = "apb", "smi"; 1806 mediatek,larb-id = <0>; 1807 mediatek,smi = <&smi_common>; 1808 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1809 }; 1810 1811 larb1: smi@14004000 { 1812 compatible = "mediatek,mt8186-smi-larb"; 1813 reg = <0 0x14004000 0 0x1000>; 1814 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1815 <&mmsys CLK_MM_SMI_COMMON>; 1816 clock-names = "apb", "smi"; 1817 mediatek,larb-id = <1>; 1818 mediatek,smi = <&smi_common>; 1819 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1820 }; 1821 1822 ovl0: ovl@14005000 { 1823 compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl"; 1824 reg = <0 0x14005000 0 0x1000>; 1825 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1826 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>; 1827 iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; 1828 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1829 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1830 }; 1831 1832 ovl_2l0: ovl@14006000 { 1833 compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l"; 1834 reg = <0 0x14006000 0 0x1000>; 1835 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1836 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 1837 iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; 1838 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1839 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1840 }; 1841 1842 rdma0: rdma@14007000 { 1843 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 1844 reg = <0 0x14007000 0 0x1000>; 1845 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1846 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>; 1847 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>; 1848 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1849 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1850 }; 1851 1852 color: color@14009000 { 1853 compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color"; 1854 reg = <0 0x14009000 0 0x1000>; 1855 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1856 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>; 1857 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1858 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1859 }; 1860 1861 dpi: dpi@1400a000 { 1862 compatible = "mediatek,mt8186-dpi"; 1863 reg = <0 0x1400a000 0 0x1000>; 1864 clocks = <&topckgen CLK_TOP_DPI>, 1865 <&mmsys CLK_MM_DISP_DPI>, 1866 <&apmixedsys CLK_APMIXED_TVDPLL>; 1867 clock-names = "pixel", "engine", "pll"; 1868 assigned-clocks = <&topckgen CLK_TOP_DPI>; 1869 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; 1870 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; 1871 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1872 status = "disabled"; 1873 1874 port { 1875 dpi_out: endpoint { }; 1876 }; 1877 }; 1878 1879 ccorr: ccorr@1400b000 { 1880 compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 1881 reg = <0 0x1400b000 0 0x1000>; 1882 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1883 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>; 1884 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1885 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1886 }; 1887 1888 aal: aal@1400c000 { 1889 compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal"; 1890 reg = <0 0x1400c000 0 0x1000>; 1891 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1892 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>; 1893 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1894 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1895 }; 1896 1897 gamma: gamma@1400d000 { 1898 compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma"; 1899 reg = <0 0x1400d000 0 0x1000>; 1900 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1901 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 1902 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1903 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1904 }; 1905 1906 postmask: postmask@1400e000 { 1907 compatible = "mediatek,mt8186-disp-postmask", 1908 "mediatek,mt8192-disp-postmask"; 1909 reg = <0 0x1400e000 0 0x1000>; 1910 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1911 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 1912 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1913 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1914 }; 1915 1916 dither: dither@1400f000 { 1917 compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither"; 1918 reg = <0 0x1400f000 0 0x1000>; 1919 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1920 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>; 1921 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1922 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1923 }; 1924 1925 dsi0: dsi@14013000 { 1926 compatible = "mediatek,mt8186-dsi"; 1927 reg = <0 0x14013000 0 0x1000>; 1928 clocks = <&mmsys CLK_MM_DSI0>, 1929 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, 1930 <&mipi_tx0>; 1931 clock-names = "engine", "digital", "hs"; 1932 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; 1933 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1934 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; 1935 phys = <&mipi_tx0>; 1936 phy-names = "dphy"; 1937 status = "disabled"; 1938 1939 port { 1940 dsi_out: endpoint { }; 1941 }; 1942 }; 1943 1944 iommu_mm: iommu@14016000 { 1945 compatible = "mediatek,mt8186-iommu-mm"; 1946 reg = <0 0x14016000 0 0x1000>; 1947 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1948 clock-names = "bclk"; 1949 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 1950 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 1951 &larb7 &larb8 &larb9 &larb11 1952 &larb13 &larb14 &larb16 &larb17 1953 &larb19 &larb20>; 1954 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1955 #iommu-cells = <1>; 1956 }; 1957 1958 rdma1: rdma@1401f000 { 1959 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 1960 reg = <0 0x1401f000 0 0x1000>; 1961 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1962 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>; 1963 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>; 1964 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>; 1965 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1966 }; 1967 1968 wpesys: clock-controller@14020000 { 1969 compatible = "mediatek,mt8186-wpesys"; 1970 reg = <0 0x14020000 0 0x1000>; 1971 #clock-cells = <1>; 1972 }; 1973 1974 larb8: smi@14023000 { 1975 compatible = "mediatek,mt8186-smi-larb"; 1976 reg = <0 0x14023000 0 0x1000>; 1977 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1978 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; 1979 clock-names = "apb", "smi"; 1980 mediatek,larb-id = <8>; 1981 mediatek,smi = <&smi_common>; 1982 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; 1983 }; 1984 1985 imgsys1: clock-controller@15020000 { 1986 compatible = "mediatek,mt8186-imgsys1"; 1987 reg = <0 0x15020000 0 0x1000>; 1988 #clock-cells = <1>; 1989 }; 1990 1991 larb9: smi@1502e000 { 1992 compatible = "mediatek,mt8186-smi-larb"; 1993 reg = <0 0x1502e000 0 0x1000>; 1994 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1995 <&imgsys1 CLK_IMG1_LARB9_IMG1>; 1996 clock-names = "apb", "smi"; 1997 mediatek,larb-id = <9>; 1998 mediatek,smi = <&smi_common>; 1999 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; 2000 }; 2001 2002 imgsys2: clock-controller@15820000 { 2003 compatible = "mediatek,mt8186-imgsys2"; 2004 reg = <0 0x15820000 0 0x1000>; 2005 #clock-cells = <1>; 2006 }; 2007 2008 larb11: smi@1582e000 { 2009 compatible = "mediatek,mt8186-smi-larb"; 2010 reg = <0 0x1582e000 0 0x1000>; 2011 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, 2012 <&imgsys2 CLK_IMG2_LARB9_IMG2>; 2013 clock-names = "apb", "smi"; 2014 mediatek,larb-id = <11>; 2015 mediatek,smi = <&smi_common>; 2016 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; 2017 }; 2018 2019 video_decoder: video-decoder@16000000 { 2020 compatible = "mediatek,mt8186-vcodec-dec"; 2021 reg = <0 0x16000000 0 0x1000>; 2022 ranges; 2023 #address-cells = <2>; 2024 #size-cells = <2>; 2025 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; 2026 iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>; 2027 mediatek,scp = <&scp>; 2028 2029 vcodec_core: video-codec@16025000 { 2030 compatible = "mediatek,mtk-vcodec-core"; 2031 reg = <0 0x16025000 0 0x1000>; 2032 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; 2033 iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>, 2034 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_EXT>, 2035 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PP_EXT>, 2036 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT>, 2037 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT>, 2038 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT>, 2039 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_TILE_EXT>, 2040 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD_EXT>, 2041 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD2_EXT>, 2042 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT>, 2043 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT>, 2044 <&iommu_mm IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT>; 2045 clocks = <&topckgen CLK_TOP_VDEC>, 2046 <&vdecsys CLK_VDEC_CKEN>, 2047 <&vdecsys CLK_VDEC_LARB1_CKEN>, 2048 <&topckgen CLK_TOP_UNIVPLL_D3>; 2049 clock-names = "vdec-sel", "vdec-soc-vdec", "vdec", "vdec-top"; 2050 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2051 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>; 2052 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 2053 }; 2054 }; 2055 2056 larb4: smi@1602e000 { 2057 compatible = "mediatek,mt8186-smi-larb"; 2058 reg = <0 0x1602e000 0 0x1000>; 2059 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, 2060 <&vdecsys CLK_VDEC_LARB1_CKEN>; 2061 clock-names = "apb", "smi"; 2062 mediatek,larb-id = <4>; 2063 mediatek,smi = <&smi_common>; 2064 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 2065 }; 2066 2067 vdecsys: clock-controller@1602f000 { 2068 compatible = "mediatek,mt8186-vdecsys"; 2069 reg = <0 0x1602f000 0 0x1000>; 2070 #clock-cells = <1>; 2071 }; 2072 2073 vencsys: clock-controller@17000000 { 2074 compatible = "mediatek,mt8186-vencsys"; 2075 reg = <0 0x17000000 0 0x1000>; 2076 #clock-cells = <1>; 2077 }; 2078 2079 larb7: smi@17010000 { 2080 compatible = "mediatek,mt8186-smi-larb"; 2081 reg = <0 0x17010000 0 0x1000>; 2082 clocks = <&vencsys CLK_VENC_CKE1_VENC>, 2083 <&vencsys CLK_VENC_CKE1_VENC>; 2084 clock-names = "apb", "smi"; 2085 mediatek,larb-id = <7>; 2086 mediatek,smi = <&smi_common>; 2087 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 2088 }; 2089 2090 venc: video-encoder@17020000 { 2091 compatible = "mediatek,mt8186-vcodec-enc", "mediatek,mt8183-vcodec-enc"; 2092 reg = <0 0x17020000 0 0x2000>; 2093 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 2094 iommus = <&iommu_mm IOMMU_PORT_L7_VENC_RCPU>, 2095 <&iommu_mm IOMMU_PORT_L7_VENC_REC>, 2096 <&iommu_mm IOMMU_PORT_L7_VENC_BSDMA>, 2097 <&iommu_mm IOMMU_PORT_L7_VENC_SV_COMV>, 2098 <&iommu_mm IOMMU_PORT_L7_VENC_RD_COMV>, 2099 <&iommu_mm IOMMU_PORT_L7_VENC_CUR_LUMA>, 2100 <&iommu_mm IOMMU_PORT_L7_VENC_CUR_CHROMA>, 2101 <&iommu_mm IOMMU_PORT_L7_VENC_REF_LUMA>, 2102 <&iommu_mm IOMMU_PORT_L7_VENC_REF_CHROMA>; 2103 clocks = <&vencsys CLK_VENC_CKE1_VENC>; 2104 clock-names = "venc_sel"; 2105 assigned-clocks = <&topckgen CLK_TOP_VENC>; 2106 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>; 2107 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 2108 mediatek,scp = <&scp>; 2109 }; 2110 2111 jpgenc: jpeg-encoder@17030000 { 2112 compatible = "mediatek,mt8186-jpgenc", "mediatek,mtk-jpgenc"; 2113 reg = <0 0x17030000 0 0x10000>; 2114 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>; 2115 clocks = <&vencsys CLK_VENC_CKE2_JPGENC>; 2116 clock-names = "jpgenc"; 2117 iommus = <&iommu_mm IOMMU_PORT_L7_JPGENC_Y_RDMA>, 2118 <&iommu_mm IOMMU_PORT_L7_JPGENC_C_RDMA>, 2119 <&iommu_mm IOMMU_PORT_L7_JPGENC_Q_TABLE>, 2120 <&iommu_mm IOMMU_PORT_L7_JPGENC_BSDMA>; 2121 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 2122 }; 2123 2124 camsys: clock-controller@1a000000 { 2125 compatible = "mediatek,mt8186-camsys"; 2126 reg = <0 0x1a000000 0 0x1000>; 2127 #clock-cells = <1>; 2128 }; 2129 2130 larb13: smi@1a001000 { 2131 compatible = "mediatek,mt8186-smi-larb"; 2132 reg = <0 0x1a001000 0 0x1000>; 2133 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; 2134 clock-names = "apb", "smi"; 2135 mediatek,larb-id = <13>; 2136 mediatek,smi = <&smi_common>; 2137 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 2138 }; 2139 2140 larb14: smi@1a002000 { 2141 compatible = "mediatek,mt8186-smi-larb"; 2142 reg = <0 0x1a002000 0 0x1000>; 2143 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; 2144 clock-names = "apb", "smi"; 2145 mediatek,larb-id = <14>; 2146 mediatek,smi = <&smi_common>; 2147 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 2148 }; 2149 2150 larb16: smi@1a00f000 { 2151 compatible = "mediatek,mt8186-smi-larb"; 2152 reg = <0 0x1a00f000 0 0x1000>; 2153 clocks = <&camsys CLK_CAM_LARB14>, 2154 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; 2155 clock-names = "apb", "smi"; 2156 mediatek,larb-id = <16>; 2157 mediatek,smi = <&smi_common>; 2158 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; 2159 }; 2160 2161 larb17: smi@1a010000 { 2162 compatible = "mediatek,mt8186-smi-larb"; 2163 reg = <0 0x1a010000 0 0x1000>; 2164 clocks = <&camsys CLK_CAM_LARB13>, 2165 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; 2166 clock-names = "apb", "smi"; 2167 mediatek,larb-id = <17>; 2168 mediatek,smi = <&smi_common>; 2169 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; 2170 }; 2171 2172 camsys_rawa: clock-controller@1a04f000 { 2173 compatible = "mediatek,mt8186-camsys_rawa"; 2174 reg = <0 0x1a04f000 0 0x1000>; 2175 #clock-cells = <1>; 2176 }; 2177 2178 camsys_rawb: clock-controller@1a06f000 { 2179 compatible = "mediatek,mt8186-camsys_rawb"; 2180 reg = <0 0x1a06f000 0 0x1000>; 2181 #clock-cells = <1>; 2182 }; 2183 2184 mdpsys: clock-controller@1b000000 { 2185 compatible = "mediatek,mt8186-mdpsys"; 2186 reg = <0 0x1b000000 0 0x1000>; 2187 #clock-cells = <1>; 2188 }; 2189 2190 larb2: smi@1b002000 { 2191 compatible = "mediatek,mt8186-smi-larb"; 2192 reg = <0 0x1b002000 0 0x1000>; 2193 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; 2194 clock-names = "apb", "smi"; 2195 mediatek,larb-id = <2>; 2196 mediatek,smi = <&smi_common>; 2197 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 2198 }; 2199 2200 ipesys: clock-controller@1c000000 { 2201 compatible = "mediatek,mt8186-ipesys"; 2202 reg = <0 0x1c000000 0 0x1000>; 2203 #clock-cells = <1>; 2204 }; 2205 2206 larb20: smi@1c00f000 { 2207 compatible = "mediatek,mt8186-smi-larb"; 2208 reg = <0 0x1c00f000 0 0x1000>; 2209 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; 2210 clock-names = "apb", "smi"; 2211 mediatek,larb-id = <20>; 2212 mediatek,smi = <&smi_common>; 2213 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 2214 }; 2215 2216 larb19: smi@1c10f000 { 2217 compatible = "mediatek,mt8186-smi-larb"; 2218 reg = <0 0x1c10f000 0 0x1000>; 2219 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; 2220 clock-names = "apb", "smi"; 2221 mediatek,larb-id = <19>; 2222 mediatek,smi = <&smi_common>; 2223 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 2224 }; 2225 }; 2226 2227 thermal_zones: thermal-zones { 2228 cpu-little0-thermal { 2229 polling-delay = <1000>; 2230 polling-delay-passive = <150>; 2231 thermal-sensors = <&lvts MT8186_LITTLE_CPU0>; 2232 2233 trips { 2234 cpu_little0_alert0: trip-alert0 { 2235 temperature = <85000>; 2236 hysteresis = <2000>; 2237 type = "passive"; 2238 }; 2239 2240 cpu_little0_alert1: trip-alert1 { 2241 temperature = <95000>; 2242 hysteresis = <2000>; 2243 type = "hot"; 2244 }; 2245 2246 cpu_little0_crit: trip-crit { 2247 temperature = <100000>; 2248 hysteresis = <0>; 2249 type = "critical"; 2250 }; 2251 }; 2252 2253 cooling-maps { 2254 map0 { 2255 trip = <&cpu_little0_alert0>; 2256 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2257 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2258 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2259 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2260 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2261 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2262 }; 2263 }; 2264 }; 2265 2266 cpu-little1-thermal { 2267 polling-delay = <1000>; 2268 polling-delay-passive = <150>; 2269 thermal-sensors = <&lvts MT8186_LITTLE_CPU1>; 2270 2271 trips { 2272 cpu_little1_alert0: trip-alert0 { 2273 temperature = <85000>; 2274 hysteresis = <2000>; 2275 type = "passive"; 2276 }; 2277 2278 cpu_little1_alert1: trip-alert1 { 2279 temperature = <95000>; 2280 hysteresis = <2000>; 2281 type = "hot"; 2282 }; 2283 2284 cpu_little1_crit: trip-crit { 2285 temperature = <100000>; 2286 hysteresis = <0>; 2287 type = "critical"; 2288 }; 2289 }; 2290 2291 cooling-maps { 2292 map0 { 2293 trip = <&cpu_little1_alert0>; 2294 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2295 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2296 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2297 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2298 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2299 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2300 }; 2301 }; 2302 }; 2303 2304 cpu-little2-thermal { 2305 polling-delay = <1000>; 2306 polling-delay-passive = <150>; 2307 thermal-sensors = <&lvts MT8186_LITTLE_CPU2>; 2308 2309 trips { 2310 cpu_little2_alert0: trip-alert0 { 2311 temperature = <85000>; 2312 hysteresis = <2000>; 2313 type = "passive"; 2314 }; 2315 2316 cpu_little2_alert1: trip-alert1 { 2317 temperature = <95000>; 2318 hysteresis = <2000>; 2319 type = "hot"; 2320 }; 2321 2322 cpu_little2_crit: trip-crit { 2323 temperature = <100000>; 2324 hysteresis = <0>; 2325 type = "critical"; 2326 }; 2327 }; 2328 2329 cooling-maps { 2330 map0 { 2331 trip = <&cpu_little2_alert0>; 2332 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2333 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2334 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2335 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2336 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2337 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2338 }; 2339 }; 2340 }; 2341 2342 cam-thermal { 2343 polling-delay = <1000>; 2344 polling-delay-passive = <250>; 2345 thermal-sensors = <&lvts MT8186_CAM>; 2346 2347 trips { 2348 cam_alert0: trip-alert0 { 2349 temperature = <85000>; 2350 hysteresis = <2000>; 2351 type = "passive"; 2352 }; 2353 2354 cam_alert1: trip-alert1 { 2355 temperature = <95000>; 2356 hysteresis = <2000>; 2357 type = "hot"; 2358 }; 2359 2360 cam_crit: trip-crit { 2361 temperature = <100000>; 2362 hysteresis = <0>; 2363 type = "critical"; 2364 }; 2365 }; 2366 }; 2367 2368 nna-thermal { 2369 polling-delay = <1000>; 2370 polling-delay-passive = <250>; 2371 thermal-sensors = <&lvts MT8186_NNA>; 2372 2373 trips { 2374 nna_alert0: trip-alert0 { 2375 temperature = <85000>; 2376 hysteresis = <2000>; 2377 type = "passive"; 2378 }; 2379 2380 nna_alert1: trip-alert1 { 2381 temperature = <95000>; 2382 hysteresis = <2000>; 2383 type = "hot"; 2384 }; 2385 2386 nna_crit: trip-crit { 2387 temperature = <100000>; 2388 hysteresis = <0>; 2389 type = "critical"; 2390 }; 2391 }; 2392 }; 2393 2394 adsp-thermal { 2395 polling-delay = <1000>; 2396 polling-delay-passive = <250>; 2397 thermal-sensors = <&lvts MT8186_ADSP>; 2398 2399 trips { 2400 adsp_alert0: trip-alert0 { 2401 temperature = <85000>; 2402 hysteresis = <2000>; 2403 type = "passive"; 2404 }; 2405 2406 adsp_alert1: trip-alert1 { 2407 temperature = <95000>; 2408 hysteresis = <2000>; 2409 type = "hot"; 2410 }; 2411 2412 adsp_crit: trip-crit { 2413 temperature = <100000>; 2414 hysteresis = <0>; 2415 type = "critical"; 2416 }; 2417 }; 2418 }; 2419 2420 gpu-thermal { 2421 polling-delay = <1000>; 2422 polling-delay-passive = <250>; 2423 thermal-sensors = <&lvts MT8186_GPU>; 2424 2425 trips { 2426 gpu_alert0: trip-alert0 { 2427 temperature = <85000>; 2428 hysteresis = <2000>; 2429 type = "passive"; 2430 }; 2431 2432 gpu_alert1: trip-alert1 { 2433 temperature = <95000>; 2434 hysteresis = <2000>; 2435 type = "hot"; 2436 }; 2437 2438 gpu_crit: trip-crit { 2439 temperature = <100000>; 2440 hysteresis = <0>; 2441 type = "critical"; 2442 }; 2443 }; 2444 2445 cooling-maps { 2446 map0 { 2447 trip = <&gpu_alert0>; 2448 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2449 }; 2450 }; 2451 }; 2452 2453 cpu-big0-thermal { 2454 polling-delay = <1000>; 2455 polling-delay-passive = <100>; 2456 thermal-sensors = <&lvts MT8186_BIG_CPU0>; 2457 2458 trips { 2459 cpu_big0_alert0: trip-alert0 { 2460 temperature = <85000>; 2461 hysteresis = <2000>; 2462 type = "passive"; 2463 }; 2464 2465 cpu_big0_alert1: trip-alert1 { 2466 temperature = <95000>; 2467 hysteresis = <2000>; 2468 type = "hot"; 2469 }; 2470 2471 cpu_big0_crit: trip-crit { 2472 temperature = <100000>; 2473 hysteresis = <0>; 2474 type = "critical"; 2475 }; 2476 }; 2477 2478 cooling-maps { 2479 map0 { 2480 trip = <&cpu_big0_alert0>; 2481 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2482 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2483 }; 2484 }; 2485 }; 2486 2487 cpu-big1-thermal { 2488 polling-delay = <1000>; 2489 polling-delay-passive = <100>; 2490 thermal-sensors = <&lvts MT8186_BIG_CPU1>; 2491 2492 trips { 2493 cpu_big1_alert0: trip-alert0 { 2494 temperature = <85000>; 2495 hysteresis = <2000>; 2496 type = "passive"; 2497 }; 2498 2499 cpu_big1_alert1: trip-alert1 { 2500 temperature = <95000>; 2501 hysteresis = <2000>; 2502 type = "hot"; 2503 }; 2504 2505 cpu_big1_crit: trip-crit { 2506 temperature = <100000>; 2507 hysteresis = <0>; 2508 type = "critical"; 2509 }; 2510 }; 2511 2512 cooling-maps { 2513 map0 { 2514 trip = <&cpu_big1_alert0>; 2515 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2516 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2517 }; 2518 }; 2519 }; 2520 }; 2521}; 2522