1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/gce/mt8183-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8183-larb-port.h> 13#include <dt-bindings/power/mt8183-power.h> 14#include <dt-bindings/reset/mt8183-resets.h> 15#include <dt-bindings/phy/phy.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/pinctrl/mt8183-pinfunc.h> 18 19/ { 20 compatible = "mediatek,mt8183"; 21 interrupt-parent = <&sysirq>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 i2c6 = &i2c6; 33 i2c7 = &i2c7; 34 i2c8 = &i2c8; 35 i2c9 = &i2c9; 36 i2c10 = &i2c10; 37 i2c11 = &i2c11; 38 ovl0 = &ovl0; 39 ovl-2l0 = &ovl_2l0; 40 ovl-2l1 = &ovl_2l1; 41 rdma0 = &rdma0; 42 rdma1 = &rdma1; 43 }; 44 45 cluster0_opp: opp-table-cluster0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 opp0-793000000 { 49 opp-hz = /bits/ 64 <793000000>; 50 opp-microvolt = <650000>; 51 required-opps = <&opp2_00>; 52 }; 53 opp0-910000000 { 54 opp-hz = /bits/ 64 <910000000>; 55 opp-microvolt = <687500>; 56 required-opps = <&opp2_01>; 57 }; 58 opp0-1014000000 { 59 opp-hz = /bits/ 64 <1014000000>; 60 opp-microvolt = <718750>; 61 required-opps = <&opp2_02>; 62 }; 63 opp0-1131000000 { 64 opp-hz = /bits/ 64 <1131000000>; 65 opp-microvolt = <756250>; 66 required-opps = <&opp2_03>; 67 }; 68 opp0-1248000000 { 69 opp-hz = /bits/ 64 <1248000000>; 70 opp-microvolt = <800000>; 71 required-opps = <&opp2_04>; 72 }; 73 opp0-1326000000 { 74 opp-hz = /bits/ 64 <1326000000>; 75 opp-microvolt = <818750>; 76 required-opps = <&opp2_05>; 77 }; 78 opp0-1417000000 { 79 opp-hz = /bits/ 64 <1417000000>; 80 opp-microvolt = <850000>; 81 required-opps = <&opp2_06>; 82 }; 83 opp0-1508000000 { 84 opp-hz = /bits/ 64 <1508000000>; 85 opp-microvolt = <868750>; 86 required-opps = <&opp2_07>; 87 }; 88 opp0-1586000000 { 89 opp-hz = /bits/ 64 <1586000000>; 90 opp-microvolt = <893750>; 91 required-opps = <&opp2_08>; 92 }; 93 opp0-1625000000 { 94 opp-hz = /bits/ 64 <1625000000>; 95 opp-microvolt = <906250>; 96 required-opps = <&opp2_09>; 97 }; 98 opp0-1677000000 { 99 opp-hz = /bits/ 64 <1677000000>; 100 opp-microvolt = <931250>; 101 required-opps = <&opp2_10>; 102 }; 103 opp0-1716000000 { 104 opp-hz = /bits/ 64 <1716000000>; 105 opp-microvolt = <943750>; 106 required-opps = <&opp2_11>; 107 }; 108 opp0-1781000000 { 109 opp-hz = /bits/ 64 <1781000000>; 110 opp-microvolt = <975000>; 111 required-opps = <&opp2_12>; 112 }; 113 opp0-1846000000 { 114 opp-hz = /bits/ 64 <1846000000>; 115 opp-microvolt = <1000000>; 116 required-opps = <&opp2_13>; 117 }; 118 opp0-1924000000 { 119 opp-hz = /bits/ 64 <1924000000>; 120 opp-microvolt = <1025000>; 121 required-opps = <&opp2_14>; 122 }; 123 opp0-1989000000 { 124 opp-hz = /bits/ 64 <1989000000>; 125 opp-microvolt = <1050000>; 126 required-opps = <&opp2_15>; 127 }; }; 128 129 cluster1_opp: opp-table-cluster1 { 130 compatible = "operating-points-v2"; 131 opp-shared; 132 opp1-793000000 { 133 opp-hz = /bits/ 64 <793000000>; 134 opp-microvolt = <700000>; 135 required-opps = <&opp2_00>; 136 }; 137 opp1-910000000 { 138 opp-hz = /bits/ 64 <910000000>; 139 opp-microvolt = <725000>; 140 required-opps = <&opp2_01>; 141 }; 142 opp1-1014000000 { 143 opp-hz = /bits/ 64 <1014000000>; 144 opp-microvolt = <750000>; 145 required-opps = <&opp2_02>; 146 }; 147 opp1-1131000000 { 148 opp-hz = /bits/ 64 <1131000000>; 149 opp-microvolt = <775000>; 150 required-opps = <&opp2_03>; 151 }; 152 opp1-1248000000 { 153 opp-hz = /bits/ 64 <1248000000>; 154 opp-microvolt = <800000>; 155 required-opps = <&opp2_04>; 156 }; 157 opp1-1326000000 { 158 opp-hz = /bits/ 64 <1326000000>; 159 opp-microvolt = <825000>; 160 required-opps = <&opp2_05>; 161 }; 162 opp1-1417000000 { 163 opp-hz = /bits/ 64 <1417000000>; 164 opp-microvolt = <850000>; 165 required-opps = <&opp2_06>; 166 }; 167 opp1-1508000000 { 168 opp-hz = /bits/ 64 <1508000000>; 169 opp-microvolt = <875000>; 170 required-opps = <&opp2_07>; 171 }; 172 opp1-1586000000 { 173 opp-hz = /bits/ 64 <1586000000>; 174 opp-microvolt = <900000>; 175 required-opps = <&opp2_08>; 176 }; 177 opp1-1625000000 { 178 opp-hz = /bits/ 64 <1625000000>; 179 opp-microvolt = <912500>; 180 required-opps = <&opp2_09>; 181 }; 182 opp1-1677000000 { 183 opp-hz = /bits/ 64 <1677000000>; 184 opp-microvolt = <931250>; 185 required-opps = <&opp2_10>; 186 }; 187 opp1-1716000000 { 188 opp-hz = /bits/ 64 <1716000000>; 189 opp-microvolt = <950000>; 190 required-opps = <&opp2_11>; 191 }; 192 opp1-1781000000 { 193 opp-hz = /bits/ 64 <1781000000>; 194 opp-microvolt = <975000>; 195 required-opps = <&opp2_12>; 196 }; 197 opp1-1846000000 { 198 opp-hz = /bits/ 64 <1846000000>; 199 opp-microvolt = <1000000>; 200 required-opps = <&opp2_13>; 201 }; 202 opp1-1924000000 { 203 opp-hz = /bits/ 64 <1924000000>; 204 opp-microvolt = <1025000>; 205 required-opps = <&opp2_14>; 206 }; 207 opp1-1989000000 { 208 opp-hz = /bits/ 64 <1989000000>; 209 opp-microvolt = <1050000>; 210 required-opps = <&opp2_15>; 211 }; 212 }; 213 214 cci_opp: opp-table-cci { 215 compatible = "operating-points-v2"; 216 opp-shared; 217 opp2_00: opp-273000000 { 218 opp-hz = /bits/ 64 <273000000>; 219 opp-microvolt = <650000>; 220 }; 221 opp2_01: opp-338000000 { 222 opp-hz = /bits/ 64 <338000000>; 223 opp-microvolt = <687500>; 224 }; 225 opp2_02: opp-403000000 { 226 opp-hz = /bits/ 64 <403000000>; 227 opp-microvolt = <718750>; 228 }; 229 opp2_03: opp-463000000 { 230 opp-hz = /bits/ 64 <463000000>; 231 opp-microvolt = <756250>; 232 }; 233 opp2_04: opp-546000000 { 234 opp-hz = /bits/ 64 <546000000>; 235 opp-microvolt = <800000>; 236 }; 237 opp2_05: opp-624000000 { 238 opp-hz = /bits/ 64 <624000000>; 239 opp-microvolt = <818750>; 240 }; 241 opp2_06: opp-689000000 { 242 opp-hz = /bits/ 64 <689000000>; 243 opp-microvolt = <850000>; 244 }; 245 opp2_07: opp-767000000 { 246 opp-hz = /bits/ 64 <767000000>; 247 opp-microvolt = <868750>; 248 }; 249 opp2_08: opp-845000000 { 250 opp-hz = /bits/ 64 <845000000>; 251 opp-microvolt = <893750>; 252 }; 253 opp2_09: opp-871000000 { 254 opp-hz = /bits/ 64 <871000000>; 255 opp-microvolt = <906250>; 256 }; 257 opp2_10: opp-923000000 { 258 opp-hz = /bits/ 64 <923000000>; 259 opp-microvolt = <931250>; 260 }; 261 opp2_11: opp-962000000 { 262 opp-hz = /bits/ 64 <962000000>; 263 opp-microvolt = <943750>; 264 }; 265 opp2_12: opp-1027000000 { 266 opp-hz = /bits/ 64 <1027000000>; 267 opp-microvolt = <975000>; 268 }; 269 opp2_13: opp-1092000000 { 270 opp-hz = /bits/ 64 <1092000000>; 271 opp-microvolt = <1000000>; 272 }; 273 opp2_14: opp-1144000000 { 274 opp-hz = /bits/ 64 <1144000000>; 275 opp-microvolt = <1025000>; 276 }; 277 opp2_15: opp-1196000000 { 278 opp-hz = /bits/ 64 <1196000000>; 279 opp-microvolt = <1050000>; 280 }; 281 }; 282 283 cci: cci { 284 compatible = "mediatek,mt8183-cci"; 285 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 286 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 287 clock-names = "cci", "intermediate"; 288 operating-points-v2 = <&cci_opp>; 289 }; 290 291 cpus { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 295 cpu-map { 296 cluster0 { 297 core0 { 298 cpu = <&cpu0>; 299 }; 300 core1 { 301 cpu = <&cpu1>; 302 }; 303 core2 { 304 cpu = <&cpu2>; 305 }; 306 core3 { 307 cpu = <&cpu3>; 308 }; 309 }; 310 311 cluster1 { 312 core0 { 313 cpu = <&cpu4>; 314 }; 315 core1 { 316 cpu = <&cpu5>; 317 }; 318 core2 { 319 cpu = <&cpu6>; 320 }; 321 core3 { 322 cpu = <&cpu7>; 323 }; 324 }; 325 }; 326 327 cpu0: cpu@0 { 328 device_type = "cpu"; 329 compatible = "arm,cortex-a53"; 330 reg = <0x000>; 331 enable-method = "psci"; 332 capacity-dmips-mhz = <741>; 333 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 334 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 335 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 336 clock-names = "cpu", "intermediate"; 337 operating-points-v2 = <&cluster0_opp>; 338 dynamic-power-coefficient = <84>; 339 i-cache-size = <32768>; 340 i-cache-line-size = <64>; 341 i-cache-sets = <256>; 342 d-cache-size = <32768>; 343 d-cache-line-size = <64>; 344 d-cache-sets = <128>; 345 next-level-cache = <&l2_0>; 346 #cooling-cells = <2>; 347 mediatek,cci = <&cci>; 348 }; 349 350 cpu1: cpu@1 { 351 device_type = "cpu"; 352 compatible = "arm,cortex-a53"; 353 reg = <0x001>; 354 enable-method = "psci"; 355 capacity-dmips-mhz = <741>; 356 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 357 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 358 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 359 clock-names = "cpu", "intermediate"; 360 operating-points-v2 = <&cluster0_opp>; 361 dynamic-power-coefficient = <84>; 362 i-cache-size = <32768>; 363 i-cache-line-size = <64>; 364 i-cache-sets = <256>; 365 d-cache-size = <32768>; 366 d-cache-line-size = <64>; 367 d-cache-sets = <128>; 368 next-level-cache = <&l2_0>; 369 #cooling-cells = <2>; 370 mediatek,cci = <&cci>; 371 }; 372 373 cpu2: cpu@2 { 374 device_type = "cpu"; 375 compatible = "arm,cortex-a53"; 376 reg = <0x002>; 377 enable-method = "psci"; 378 capacity-dmips-mhz = <741>; 379 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 380 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 381 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 382 clock-names = "cpu", "intermediate"; 383 operating-points-v2 = <&cluster0_opp>; 384 dynamic-power-coefficient = <84>; 385 i-cache-size = <32768>; 386 i-cache-line-size = <64>; 387 i-cache-sets = <256>; 388 d-cache-size = <32768>; 389 d-cache-line-size = <64>; 390 d-cache-sets = <128>; 391 next-level-cache = <&l2_0>; 392 #cooling-cells = <2>; 393 mediatek,cci = <&cci>; 394 }; 395 396 cpu3: cpu@3 { 397 device_type = "cpu"; 398 compatible = "arm,cortex-a53"; 399 reg = <0x003>; 400 enable-method = "psci"; 401 capacity-dmips-mhz = <741>; 402 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 403 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 404 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 405 clock-names = "cpu", "intermediate"; 406 operating-points-v2 = <&cluster0_opp>; 407 dynamic-power-coefficient = <84>; 408 i-cache-size = <32768>; 409 i-cache-line-size = <64>; 410 i-cache-sets = <256>; 411 d-cache-size = <32768>; 412 d-cache-line-size = <64>; 413 d-cache-sets = <128>; 414 next-level-cache = <&l2_0>; 415 #cooling-cells = <2>; 416 mediatek,cci = <&cci>; 417 }; 418 419 cpu4: cpu@100 { 420 device_type = "cpu"; 421 compatible = "arm,cortex-a73"; 422 reg = <0x100>; 423 enable-method = "psci"; 424 capacity-dmips-mhz = <1024>; 425 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 426 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 427 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 428 clock-names = "cpu", "intermediate"; 429 operating-points-v2 = <&cluster1_opp>; 430 dynamic-power-coefficient = <211>; 431 i-cache-size = <65536>; 432 i-cache-line-size = <64>; 433 i-cache-sets = <256>; 434 d-cache-size = <65536>; 435 d-cache-line-size = <64>; 436 d-cache-sets = <256>; 437 next-level-cache = <&l2_1>; 438 #cooling-cells = <2>; 439 mediatek,cci = <&cci>; 440 }; 441 442 cpu5: cpu@101 { 443 device_type = "cpu"; 444 compatible = "arm,cortex-a73"; 445 reg = <0x101>; 446 enable-method = "psci"; 447 capacity-dmips-mhz = <1024>; 448 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 449 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 450 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 451 clock-names = "cpu", "intermediate"; 452 operating-points-v2 = <&cluster1_opp>; 453 dynamic-power-coefficient = <211>; 454 i-cache-size = <65536>; 455 i-cache-line-size = <64>; 456 i-cache-sets = <256>; 457 d-cache-size = <65536>; 458 d-cache-line-size = <64>; 459 d-cache-sets = <256>; 460 next-level-cache = <&l2_1>; 461 #cooling-cells = <2>; 462 mediatek,cci = <&cci>; 463 }; 464 465 cpu6: cpu@102 { 466 device_type = "cpu"; 467 compatible = "arm,cortex-a73"; 468 reg = <0x102>; 469 enable-method = "psci"; 470 capacity-dmips-mhz = <1024>; 471 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 472 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 473 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 474 clock-names = "cpu", "intermediate"; 475 operating-points-v2 = <&cluster1_opp>; 476 dynamic-power-coefficient = <211>; 477 i-cache-size = <65536>; 478 i-cache-line-size = <64>; 479 i-cache-sets = <256>; 480 d-cache-size = <65536>; 481 d-cache-line-size = <64>; 482 d-cache-sets = <256>; 483 next-level-cache = <&l2_1>; 484 #cooling-cells = <2>; 485 mediatek,cci = <&cci>; 486 }; 487 488 cpu7: cpu@103 { 489 device_type = "cpu"; 490 compatible = "arm,cortex-a73"; 491 reg = <0x103>; 492 enable-method = "psci"; 493 capacity-dmips-mhz = <1024>; 494 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 495 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 496 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 497 clock-names = "cpu", "intermediate"; 498 operating-points-v2 = <&cluster1_opp>; 499 dynamic-power-coefficient = <211>; 500 i-cache-size = <65536>; 501 i-cache-line-size = <64>; 502 i-cache-sets = <256>; 503 d-cache-size = <65536>; 504 d-cache-line-size = <64>; 505 d-cache-sets = <256>; 506 next-level-cache = <&l2_1>; 507 #cooling-cells = <2>; 508 mediatek,cci = <&cci>; 509 }; 510 511 idle-states { 512 entry-method = "psci"; 513 514 CPU_SLEEP: cpu-sleep { 515 compatible = "arm,idle-state"; 516 local-timer-stop; 517 arm,psci-suspend-param = <0x00010001>; 518 entry-latency-us = <200>; 519 exit-latency-us = <200>; 520 min-residency-us = <800>; 521 }; 522 523 CLUSTER_SLEEP0: cluster-sleep-0 { 524 compatible = "arm,idle-state"; 525 local-timer-stop; 526 arm,psci-suspend-param = <0x01010001>; 527 entry-latency-us = <250>; 528 exit-latency-us = <400>; 529 min-residency-us = <1000>; 530 }; 531 CLUSTER_SLEEP1: cluster-sleep-1 { 532 compatible = "arm,idle-state"; 533 local-timer-stop; 534 arm,psci-suspend-param = <0x01010001>; 535 entry-latency-us = <250>; 536 exit-latency-us = <400>; 537 min-residency-us = <1300>; 538 }; 539 }; 540 541 l2_0: l2-cache0 { 542 compatible = "cache"; 543 cache-level = <2>; 544 cache-size = <1048576>; 545 cache-line-size = <64>; 546 cache-sets = <1024>; 547 cache-unified; 548 }; 549 550 l2_1: l2-cache1 { 551 compatible = "cache"; 552 cache-level = <2>; 553 cache-size = <1048576>; 554 cache-line-size = <64>; 555 cache-sets = <1024>; 556 cache-unified; 557 }; 558 }; 559 560 gpu_opp_table: opp-table-0 { 561 compatible = "operating-points-v2"; 562 opp-shared; 563 564 opp-300000000 { 565 opp-hz = /bits/ 64 <300000000>; 566 opp-microvolt = <625000>; 567 }; 568 569 opp-320000000 { 570 opp-hz = /bits/ 64 <320000000>; 571 opp-microvolt = <631250>; 572 }; 573 574 opp-340000000 { 575 opp-hz = /bits/ 64 <340000000>; 576 opp-microvolt = <637500>; 577 }; 578 579 opp-360000000 { 580 opp-hz = /bits/ 64 <360000000>; 581 opp-microvolt = <643750>; 582 }; 583 584 opp-380000000 { 585 opp-hz = /bits/ 64 <380000000>; 586 opp-microvolt = <650000>; 587 }; 588 589 opp-400000000 { 590 opp-hz = /bits/ 64 <400000000>; 591 opp-microvolt = <656250>; 592 }; 593 594 opp-420000000 { 595 opp-hz = /bits/ 64 <420000000>; 596 opp-microvolt = <662500>; 597 }; 598 599 opp-460000000 { 600 opp-hz = /bits/ 64 <460000000>; 601 opp-microvolt = <675000>; 602 }; 603 604 opp-500000000 { 605 opp-hz = /bits/ 64 <500000000>; 606 opp-microvolt = <687500>; 607 }; 608 609 opp-540000000 { 610 opp-hz = /bits/ 64 <540000000>; 611 opp-microvolt = <700000>; 612 }; 613 614 opp-580000000 { 615 opp-hz = /bits/ 64 <580000000>; 616 opp-microvolt = <712500>; 617 }; 618 619 opp-620000000 { 620 opp-hz = /bits/ 64 <620000000>; 621 opp-microvolt = <725000>; 622 }; 623 624 opp-653000000 { 625 opp-hz = /bits/ 64 <653000000>; 626 opp-microvolt = <743750>; 627 }; 628 629 opp-698000000 { 630 opp-hz = /bits/ 64 <698000000>; 631 opp-microvolt = <768750>; 632 }; 633 634 opp-743000000 { 635 opp-hz = /bits/ 64 <743000000>; 636 opp-microvolt = <793750>; 637 }; 638 639 opp-800000000 { 640 opp-hz = /bits/ 64 <800000000>; 641 opp-microvolt = <825000>; 642 }; 643 }; 644 645 pmu-a53 { 646 compatible = "arm,cortex-a53-pmu"; 647 interrupt-parent = <&gic>; 648 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 649 }; 650 651 pmu-a73 { 652 compatible = "arm,cortex-a73-pmu"; 653 interrupt-parent = <&gic>; 654 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 655 }; 656 657 psci { 658 compatible = "arm,psci-1.0"; 659 method = "smc"; 660 }; 661 662 clk13m: fixed-factor-clock-13m { 663 compatible = "fixed-factor-clock"; 664 #clock-cells = <0>; 665 clocks = <&clk26m>; 666 clock-div = <2>; 667 clock-mult = <1>; 668 clock-output-names = "clk13m"; 669 }; 670 671 clk26m: oscillator { 672 compatible = "fixed-clock"; 673 #clock-cells = <0>; 674 clock-frequency = <26000000>; 675 clock-output-names = "clk26m"; 676 }; 677 678 timer { 679 compatible = "arm,armv8-timer"; 680 interrupt-parent = <&gic>; 681 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 682 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 683 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 684 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 685 }; 686 687 soc { 688 #address-cells = <2>; 689 #size-cells = <2>; 690 compatible = "simple-bus"; 691 ranges; 692 693 soc_data: efuse@8000000 { 694 compatible = "mediatek,mt8183-efuse", 695 "mediatek,efuse"; 696 reg = <0 0x08000000 0 0x0010>; 697 #address-cells = <1>; 698 #size-cells = <1>; 699 status = "disabled"; 700 }; 701 702 gic: interrupt-controller@c000000 { 703 compatible = "arm,gic-v3"; 704 #interrupt-cells = <4>; 705 interrupt-parent = <&gic>; 706 interrupt-controller; 707 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 708 <0 0x0c100000 0 0x200000>, /* GICR */ 709 <0 0x0c400000 0 0x2000>, /* GICC */ 710 <0 0x0c410000 0 0x1000>, /* GICH */ 711 <0 0x0c420000 0 0x2000>; /* GICV */ 712 713 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 714 ppi-partitions { 715 ppi_cluster0: interrupt-partition-0 { 716 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 717 }; 718 ppi_cluster1: interrupt-partition-1 { 719 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 720 }; 721 }; 722 }; 723 724 mcucfg: syscon@c530000 { 725 compatible = "mediatek,mt8183-mcucfg", "syscon"; 726 reg = <0 0x0c530000 0 0x1000>; 727 #clock-cells = <1>; 728 }; 729 730 sysirq: interrupt-controller@c530a80 { 731 compatible = "mediatek,mt8183-sysirq", 732 "mediatek,mt6577-sysirq"; 733 interrupt-controller; 734 #interrupt-cells = <3>; 735 interrupt-parent = <&gic>; 736 reg = <0 0x0c530a80 0 0x50>; 737 }; 738 739 cpu_debug0: cpu-debug@d410000 { 740 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 741 reg = <0x0 0xd410000 0x0 0x1000>; 742 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 743 clock-names = "apb_pclk"; 744 cpu = <&cpu0>; 745 }; 746 747 cpu_debug1: cpu-debug@d510000 { 748 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 749 reg = <0x0 0xd510000 0x0 0x1000>; 750 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 751 clock-names = "apb_pclk"; 752 cpu = <&cpu1>; 753 }; 754 755 cpu_debug2: cpu-debug@d610000 { 756 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 757 reg = <0x0 0xd610000 0x0 0x1000>; 758 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 759 clock-names = "apb_pclk"; 760 cpu = <&cpu2>; 761 }; 762 763 cpu_debug3: cpu-debug@d710000 { 764 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 765 reg = <0x0 0xd710000 0x0 0x1000>; 766 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 767 clock-names = "apb_pclk"; 768 cpu = <&cpu3>; 769 }; 770 771 cpu_debug4: cpu-debug@d810000 { 772 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 773 reg = <0x0 0xd810000 0x0 0x1000>; 774 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 775 clock-names = "apb_pclk"; 776 cpu = <&cpu4>; 777 }; 778 779 cpu_debug5: cpu-debug@d910000 { 780 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 781 reg = <0x0 0xd910000 0x0 0x1000>; 782 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 783 clock-names = "apb_pclk"; 784 cpu = <&cpu5>; 785 }; 786 787 cpu_debug6: cpu-debug@da10000 { 788 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 789 reg = <0x0 0xda10000 0x0 0x1000>; 790 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 791 clock-names = "apb_pclk"; 792 cpu = <&cpu6>; 793 }; 794 795 cpu_debug7: cpu-debug@db10000 { 796 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 797 reg = <0x0 0xdb10000 0x0 0x1000>; 798 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 799 clock-names = "apb_pclk"; 800 cpu = <&cpu7>; 801 }; 802 803 topckgen: syscon@10000000 { 804 compatible = "mediatek,mt8183-topckgen", "syscon"; 805 reg = <0 0x10000000 0 0x1000>; 806 #clock-cells = <1>; 807 }; 808 809 infracfg: syscon@10001000 { 810 compatible = "mediatek,mt8183-infracfg", "syscon"; 811 reg = <0 0x10001000 0 0x1000>; 812 #clock-cells = <1>; 813 #reset-cells = <1>; 814 }; 815 816 pericfg: syscon@10003000 { 817 compatible = "mediatek,mt8183-pericfg", "syscon"; 818 reg = <0 0x10003000 0 0x1000>; 819 #clock-cells = <1>; 820 }; 821 822 pio: pinctrl@10005000 { 823 compatible = "mediatek,mt8183-pinctrl"; 824 reg = <0 0x10005000 0 0x1000>, 825 <0 0x11f20000 0 0x1000>, 826 <0 0x11e80000 0 0x1000>, 827 <0 0x11e70000 0 0x1000>, 828 <0 0x11e90000 0 0x1000>, 829 <0 0x11d30000 0 0x1000>, 830 <0 0x11d20000 0 0x1000>, 831 <0 0x11c50000 0 0x1000>, 832 <0 0x11f30000 0 0x1000>, 833 <0 0x1000b000 0 0x1000>; 834 reg-names = "iocfg0", "iocfg1", "iocfg2", 835 "iocfg3", "iocfg4", "iocfg5", 836 "iocfg6", "iocfg7", "iocfg8", 837 "eint"; 838 gpio-controller; 839 #gpio-cells = <2>; 840 gpio-ranges = <&pio 0 0 192>; 841 interrupt-controller; 842 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 843 #interrupt-cells = <2>; 844 }; 845 846 scpsys: syscon@10006000 { 847 compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd"; 848 reg = <0 0x10006000 0 0x1000>; 849 850 /* System Power Manager */ 851 spm: power-controller { 852 compatible = "mediatek,mt8183-power-controller"; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 #power-domain-cells = <1>; 856 857 /* power domain of the SoC */ 858 power-domain@MT8183_POWER_DOMAIN_AUDIO { 859 reg = <MT8183_POWER_DOMAIN_AUDIO>; 860 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 861 <&infracfg CLK_INFRA_AUDIO>, 862 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>; 863 clock-names = "audio", "audio1", "audio2"; 864 #power-domain-cells = <0>; 865 }; 866 867 power-domain@MT8183_POWER_DOMAIN_CONN { 868 reg = <MT8183_POWER_DOMAIN_CONN>; 869 mediatek,infracfg = <&infracfg>; 870 #power-domain-cells = <0>; 871 }; 872 873 mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { 874 reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 #power-domain-cells = <1>; 878 879 mfg: power-domain@MT8183_POWER_DOMAIN_MFG { 880 reg = <MT8183_POWER_DOMAIN_MFG>; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 #power-domain-cells = <1>; 884 885 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 { 886 reg = <MT8183_POWER_DOMAIN_MFG_CORE0>; 887 #power-domain-cells = <0>; 888 }; 889 890 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { 891 reg = <MT8183_POWER_DOMAIN_MFG_CORE1>; 892 #power-domain-cells = <0>; 893 }; 894 895 power-domain@MT8183_POWER_DOMAIN_MFG_2D { 896 reg = <MT8183_POWER_DOMAIN_MFG_2D>; 897 mediatek,infracfg = <&infracfg>; 898 #power-domain-cells = <0>; 899 }; 900 }; 901 }; 902 903 power-domain@MT8183_POWER_DOMAIN_DISP { 904 reg = <MT8183_POWER_DOMAIN_DISP>; 905 clocks = <&topckgen CLK_TOP_MUX_MM>, 906 <&mmsys CLK_MM_SMI_COMMON>, 907 <&mmsys CLK_MM_SMI_LARB0>, 908 <&mmsys CLK_MM_SMI_LARB1>, 909 <&mmsys CLK_MM_GALS_COMM0>, 910 <&mmsys CLK_MM_GALS_COMM1>, 911 <&mmsys CLK_MM_GALS_CCU2MM>, 912 <&mmsys CLK_MM_GALS_IPU12MM>, 913 <&mmsys CLK_MM_GALS_IMG2MM>, 914 <&mmsys CLK_MM_GALS_CAM2MM>, 915 <&mmsys CLK_MM_GALS_IPU2MM>; 916 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3", 917 "mm-4", "mm-5", "mm-6", "mm-7", 918 "mm-8", "mm-9"; 919 mediatek,infracfg = <&infracfg>; 920 mediatek,smi = <&smi_common>; 921 #address-cells = <1>; 922 #size-cells = <0>; 923 #power-domain-cells = <1>; 924 925 power-domain@MT8183_POWER_DOMAIN_CAM { 926 reg = <MT8183_POWER_DOMAIN_CAM>; 927 clocks = <&topckgen CLK_TOP_MUX_CAM>, 928 <&camsys CLK_CAM_LARB6>, 929 <&camsys CLK_CAM_LARB3>, 930 <&camsys CLK_CAM_SENINF>, 931 <&camsys CLK_CAM_CAMSV0>, 932 <&camsys CLK_CAM_CAMSV1>, 933 <&camsys CLK_CAM_CAMSV2>, 934 <&camsys CLK_CAM_CCU>; 935 clock-names = "cam", "cam-0", "cam-1", 936 "cam-2", "cam-3", "cam-4", 937 "cam-5", "cam-6"; 938 mediatek,infracfg = <&infracfg>; 939 mediatek,smi = <&smi_common>; 940 #power-domain-cells = <0>; 941 }; 942 943 power-domain@MT8183_POWER_DOMAIN_ISP { 944 reg = <MT8183_POWER_DOMAIN_ISP>; 945 clocks = <&topckgen CLK_TOP_MUX_IMG>, 946 <&imgsys CLK_IMG_LARB5>, 947 <&imgsys CLK_IMG_LARB2>; 948 clock-names = "isp", "isp-0", "isp-1"; 949 mediatek,infracfg = <&infracfg>; 950 mediatek,smi = <&smi_common>; 951 #power-domain-cells = <0>; 952 }; 953 954 power-domain@MT8183_POWER_DOMAIN_VDEC { 955 reg = <MT8183_POWER_DOMAIN_VDEC>; 956 mediatek,smi = <&smi_common>; 957 #power-domain-cells = <0>; 958 }; 959 960 power-domain@MT8183_POWER_DOMAIN_VENC { 961 reg = <MT8183_POWER_DOMAIN_VENC>; 962 mediatek,smi = <&smi_common>; 963 #power-domain-cells = <0>; 964 }; 965 966 power-domain@MT8183_POWER_DOMAIN_VPU_TOP { 967 reg = <MT8183_POWER_DOMAIN_VPU_TOP>; 968 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>, 969 <&topckgen CLK_TOP_MUX_DSP>, 970 <&ipu_conn CLK_IPU_CONN_IPU>, 971 <&ipu_conn CLK_IPU_CONN_AHB>, 972 <&ipu_conn CLK_IPU_CONN_AXI>, 973 <&ipu_conn CLK_IPU_CONN_ISP>, 974 <&ipu_conn CLK_IPU_CONN_CAM_ADL>, 975 <&ipu_conn CLK_IPU_CONN_IMG_ADL>; 976 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1", 977 "vpu-2", "vpu-3", "vpu-4", "vpu-5"; 978 mediatek,infracfg = <&infracfg>; 979 mediatek,smi = <&smi_common>; 980 #address-cells = <1>; 981 #size-cells = <0>; 982 #power-domain-cells = <1>; 983 984 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { 985 reg = <MT8183_POWER_DOMAIN_VPU_CORE0>; 986 clocks = <&topckgen CLK_TOP_MUX_DSP1>; 987 clock-names = "vpu2"; 988 mediatek,infracfg = <&infracfg>; 989 #power-domain-cells = <0>; 990 }; 991 992 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { 993 reg = <MT8183_POWER_DOMAIN_VPU_CORE1>; 994 clocks = <&topckgen CLK_TOP_MUX_DSP2>; 995 clock-names = "vpu3"; 996 mediatek,infracfg = <&infracfg>; 997 #power-domain-cells = <0>; 998 }; 999 }; 1000 }; 1001 }; 1002 }; 1003 1004 watchdog: watchdog@10007000 { 1005 compatible = "mediatek,mt8183-wdt"; 1006 reg = <0 0x10007000 0 0x100>; 1007 #reset-cells = <1>; 1008 }; 1009 1010 apmixedsys: syscon@1000c000 { 1011 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 1012 reg = <0 0x1000c000 0 0x1000>; 1013 #clock-cells = <1>; 1014 }; 1015 1016 pwrap: pwrap@1000d000 { 1017 compatible = "mediatek,mt8183-pwrap"; 1018 reg = <0 0x1000d000 0 0x1000>; 1019 reg-names = "pwrap"; 1020 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 1022 <&infracfg CLK_INFRA_PMIC_AP>; 1023 clock-names = "spi", "wrap"; 1024 }; 1025 1026 keyboard: keyboard@10010000 { 1027 compatible = "mediatek,mt6779-keypad"; 1028 reg = <0 0x10010000 0 0x1000>; 1029 interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_FALLING>; 1030 clocks = <&clk26m>; 1031 clock-names = "kpd"; 1032 status = "disabled"; 1033 }; 1034 1035 scp: scp@10500000 { 1036 compatible = "mediatek,mt8183-scp"; 1037 reg = <0 0x10500000 0 0x80000>, 1038 <0 0x105c0000 0 0x19080>; 1039 reg-names = "sram", "cfg"; 1040 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&infracfg CLK_INFRA_SCPSYS>; 1042 clock-names = "main"; 1043 memory-region = <&scp_mem_reserved>; 1044 status = "disabled"; 1045 }; 1046 1047 systimer: timer@10017000 { 1048 compatible = "mediatek,mt8183-timer", 1049 "mediatek,mt6765-timer"; 1050 reg = <0 0x10017000 0 0x1000>; 1051 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1052 clocks = <&clk13m>; 1053 }; 1054 1055 iommu: iommu@10205000 { 1056 compatible = "mediatek,mt8183-m4u"; 1057 reg = <0 0x10205000 0 0x1000>; 1058 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; 1059 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>, 1060 <&larb4>, <&larb5>, <&larb6>; 1061 #iommu-cells = <1>; 1062 }; 1063 1064 gce: mailbox@10238000 { 1065 compatible = "mediatek,mt8183-gce"; 1066 reg = <0 0x10238000 0 0x4000>; 1067 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 1068 #mbox-cells = <2>; 1069 clocks = <&infracfg CLK_INFRA_GCE>; 1070 clock-names = "gce"; 1071 }; 1072 1073 auxadc: auxadc@11001000 { 1074 compatible = "mediatek,mt8183-auxadc", 1075 "mediatek,mt8173-auxadc"; 1076 reg = <0 0x11001000 0 0x1000>; 1077 clocks = <&infracfg CLK_INFRA_AUXADC>; 1078 clock-names = "main"; 1079 #io-channel-cells = <1>; 1080 status = "disabled"; 1081 }; 1082 1083 uart0: serial@11002000 { 1084 compatible = "mediatek,mt8183-uart", 1085 "mediatek,mt6577-uart"; 1086 reg = <0 0x11002000 0 0x1000>; 1087 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 1088 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 1089 clock-names = "baud", "bus"; 1090 status = "disabled"; 1091 }; 1092 1093 uart1: serial@11003000 { 1094 compatible = "mediatek,mt8183-uart", 1095 "mediatek,mt6577-uart"; 1096 reg = <0 0x11003000 0 0x1000>; 1097 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 1098 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 1099 clock-names = "baud", "bus"; 1100 status = "disabled"; 1101 }; 1102 1103 uart2: serial@11004000 { 1104 compatible = "mediatek,mt8183-uart", 1105 "mediatek,mt6577-uart"; 1106 reg = <0 0x11004000 0 0x1000>; 1107 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 1108 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 1109 clock-names = "baud", "bus"; 1110 status = "disabled"; 1111 }; 1112 1113 i2c6: i2c@11005000 { 1114 compatible = "mediatek,mt8183-i2c"; 1115 reg = <0 0x11005000 0 0x1000>, 1116 <0 0x11000600 0 0x80>; 1117 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 1118 clocks = <&infracfg CLK_INFRA_I2C6>, 1119 <&infracfg CLK_INFRA_AP_DMA>; 1120 clock-names = "main", "dma"; 1121 clock-div = <1>; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 status = "disabled"; 1125 }; 1126 1127 i2c0: i2c@11007000 { 1128 compatible = "mediatek,mt8183-i2c"; 1129 reg = <0 0x11007000 0 0x1000>, 1130 <0 0x11000080 0 0x80>; 1131 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 1132 clocks = <&infracfg CLK_INFRA_I2C0>, 1133 <&infracfg CLK_INFRA_AP_DMA>; 1134 clock-names = "main", "dma"; 1135 clock-div = <1>; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 status = "disabled"; 1139 }; 1140 1141 i2c4: i2c@11008000 { 1142 compatible = "mediatek,mt8183-i2c"; 1143 reg = <0 0x11008000 0 0x1000>, 1144 <0 0x11000100 0 0x80>; 1145 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 1146 clocks = <&infracfg CLK_INFRA_I2C1>, 1147 <&infracfg CLK_INFRA_AP_DMA>, 1148 <&infracfg CLK_INFRA_I2C1_ARBITER>; 1149 clock-names = "main", "dma","arb"; 1150 clock-div = <1>; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 status = "disabled"; 1154 }; 1155 1156 i2c2: i2c@11009000 { 1157 compatible = "mediatek,mt8183-i2c"; 1158 reg = <0 0x11009000 0 0x1000>, 1159 <0 0x11000280 0 0x80>; 1160 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 1161 clocks = <&infracfg CLK_INFRA_I2C2>, 1162 <&infracfg CLK_INFRA_AP_DMA>, 1163 <&infracfg CLK_INFRA_I2C2_ARBITER>; 1164 clock-names = "main", "dma", "arb"; 1165 clock-div = <1>; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 status = "disabled"; 1169 }; 1170 1171 spi0: spi@1100a000 { 1172 compatible = "mediatek,mt8183-spi"; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 reg = <0 0x1100a000 0 0x1000>; 1176 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 1177 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1178 <&topckgen CLK_TOP_MUX_SPI>, 1179 <&infracfg CLK_INFRA_SPI0>; 1180 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1181 status = "disabled"; 1182 }; 1183 1184 thermal: thermal-sensor@1100b000 { 1185 #thermal-sensor-cells = <1>; 1186 compatible = "mediatek,mt8183-thermal"; 1187 reg = <0 0x1100b000 0 0xc00>; 1188 clocks = <&infracfg CLK_INFRA_THERM>, 1189 <&infracfg CLK_INFRA_AUXADC>; 1190 clock-names = "therm", "auxadc"; 1191 resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>; 1192 interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>; 1193 mediatek,auxadc = <&auxadc>; 1194 mediatek,apmixedsys = <&apmixedsys>; 1195 nvmem-cells = <&thermal_calibration>; 1196 nvmem-cell-names = "calibration-data"; 1197 }; 1198 1199 svs: svs@1100bc00 { 1200 compatible = "mediatek,mt8183-svs"; 1201 reg = <0 0x1100bc00 0 0x400>; 1202 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 1203 clocks = <&infracfg CLK_INFRA_THERM>; 1204 clock-names = "main"; 1205 nvmem-cells = <&svs_calibration>, 1206 <&thermal_calibration>; 1207 nvmem-cell-names = "svs-calibration-data", 1208 "t-calibration-data"; 1209 }; 1210 1211 pwm0: pwm@1100e000 { 1212 compatible = "mediatek,mt8183-disp-pwm"; 1213 reg = <0 0x1100e000 0 0x1000>; 1214 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 1215 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1216 #pwm-cells = <2>; 1217 clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, 1218 <&infracfg CLK_INFRA_DISP_PWM>; 1219 clock-names = "main", "mm"; 1220 }; 1221 1222 pwm1: pwm@11006000 { 1223 compatible = "mediatek,mt8183-pwm"; 1224 reg = <0 0x11006000 0 0x1000>; 1225 #pwm-cells = <2>; 1226 clocks = <&infracfg CLK_INFRA_PWM>, 1227 <&infracfg CLK_INFRA_PWM_HCLK>, 1228 <&infracfg CLK_INFRA_PWM1>, 1229 <&infracfg CLK_INFRA_PWM2>, 1230 <&infracfg CLK_INFRA_PWM3>, 1231 <&infracfg CLK_INFRA_PWM4>; 1232 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 1233 "pwm4"; 1234 }; 1235 1236 i2c3: i2c@1100f000 { 1237 compatible = "mediatek,mt8183-i2c"; 1238 reg = <0 0x1100f000 0 0x1000>, 1239 <0 0x11000400 0 0x80>; 1240 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 1241 clocks = <&infracfg CLK_INFRA_I2C3>, 1242 <&infracfg CLK_INFRA_AP_DMA>; 1243 clock-names = "main", "dma"; 1244 clock-div = <1>; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 status = "disabled"; 1248 }; 1249 1250 spi1: spi@11010000 { 1251 compatible = "mediatek,mt8183-spi"; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 reg = <0 0x11010000 0 0x1000>; 1255 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 1256 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1257 <&topckgen CLK_TOP_MUX_SPI>, 1258 <&infracfg CLK_INFRA_SPI1>; 1259 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1260 status = "disabled"; 1261 }; 1262 1263 i2c1: i2c@11011000 { 1264 compatible = "mediatek,mt8183-i2c"; 1265 reg = <0 0x11011000 0 0x1000>, 1266 <0 0x11000480 0 0x80>; 1267 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 1268 clocks = <&infracfg CLK_INFRA_I2C4>, 1269 <&infracfg CLK_INFRA_AP_DMA>; 1270 clock-names = "main", "dma"; 1271 clock-div = <1>; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 status = "disabled"; 1275 }; 1276 1277 spi2: spi@11012000 { 1278 compatible = "mediatek,mt8183-spi"; 1279 #address-cells = <1>; 1280 #size-cells = <0>; 1281 reg = <0 0x11012000 0 0x1000>; 1282 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 1283 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1284 <&topckgen CLK_TOP_MUX_SPI>, 1285 <&infracfg CLK_INFRA_SPI2>; 1286 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1287 status = "disabled"; 1288 }; 1289 1290 spi3: spi@11013000 { 1291 compatible = "mediatek,mt8183-spi"; 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 reg = <0 0x11013000 0 0x1000>; 1295 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 1296 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1297 <&topckgen CLK_TOP_MUX_SPI>, 1298 <&infracfg CLK_INFRA_SPI3>; 1299 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1300 status = "disabled"; 1301 }; 1302 1303 i2c9: i2c@11014000 { 1304 compatible = "mediatek,mt8183-i2c"; 1305 reg = <0 0x11014000 0 0x1000>, 1306 <0 0x11000180 0 0x80>; 1307 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 1308 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 1309 <&infracfg CLK_INFRA_AP_DMA>, 1310 <&infracfg CLK_INFRA_I2C1_ARBITER>; 1311 clock-names = "main", "dma", "arb"; 1312 clock-div = <1>; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 status = "disabled"; 1316 }; 1317 1318 i2c10: i2c@11015000 { 1319 compatible = "mediatek,mt8183-i2c"; 1320 reg = <0 0x11015000 0 0x1000>, 1321 <0 0x11000300 0 0x80>; 1322 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 1323 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 1324 <&infracfg CLK_INFRA_AP_DMA>, 1325 <&infracfg CLK_INFRA_I2C2_ARBITER>; 1326 clock-names = "main", "dma", "arb"; 1327 clock-div = <1>; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 status = "disabled"; 1331 }; 1332 1333 i2c5: i2c@11016000 { 1334 compatible = "mediatek,mt8183-i2c"; 1335 reg = <0 0x11016000 0 0x1000>, 1336 <0 0x11000500 0 0x80>; 1337 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 1338 clocks = <&infracfg CLK_INFRA_I2C5>, 1339 <&infracfg CLK_INFRA_AP_DMA>, 1340 <&infracfg CLK_INFRA_I2C5_ARBITER>; 1341 clock-names = "main", "dma", "arb"; 1342 clock-div = <1>; 1343 #address-cells = <1>; 1344 #size-cells = <0>; 1345 status = "disabled"; 1346 }; 1347 1348 i2c11: i2c@11017000 { 1349 compatible = "mediatek,mt8183-i2c"; 1350 reg = <0 0x11017000 0 0x1000>, 1351 <0 0x11000580 0 0x80>; 1352 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 1353 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 1354 <&infracfg CLK_INFRA_AP_DMA>, 1355 <&infracfg CLK_INFRA_I2C5_ARBITER>; 1356 clock-names = "main", "dma", "arb"; 1357 clock-div = <1>; 1358 #address-cells = <1>; 1359 #size-cells = <0>; 1360 status = "disabled"; 1361 }; 1362 1363 spi4: spi@11018000 { 1364 compatible = "mediatek,mt8183-spi"; 1365 #address-cells = <1>; 1366 #size-cells = <0>; 1367 reg = <0 0x11018000 0 0x1000>; 1368 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 1369 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1370 <&topckgen CLK_TOP_MUX_SPI>, 1371 <&infracfg CLK_INFRA_SPI4>; 1372 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1373 status = "disabled"; 1374 }; 1375 1376 spi5: spi@11019000 { 1377 compatible = "mediatek,mt8183-spi"; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 reg = <0 0x11019000 0 0x1000>; 1381 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 1382 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1383 <&topckgen CLK_TOP_MUX_SPI>, 1384 <&infracfg CLK_INFRA_SPI5>; 1385 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1386 status = "disabled"; 1387 }; 1388 1389 i2c7: i2c@1101a000 { 1390 compatible = "mediatek,mt8183-i2c"; 1391 reg = <0 0x1101a000 0 0x1000>, 1392 <0 0x11000680 0 0x80>; 1393 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 1394 clocks = <&infracfg CLK_INFRA_I2C7>, 1395 <&infracfg CLK_INFRA_AP_DMA>; 1396 clock-names = "main", "dma"; 1397 clock-div = <1>; 1398 #address-cells = <1>; 1399 #size-cells = <0>; 1400 status = "disabled"; 1401 }; 1402 1403 i2c8: i2c@1101b000 { 1404 compatible = "mediatek,mt8183-i2c"; 1405 reg = <0 0x1101b000 0 0x1000>, 1406 <0 0x11000700 0 0x80>; 1407 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 1408 clocks = <&infracfg CLK_INFRA_I2C8>, 1409 <&infracfg CLK_INFRA_AP_DMA>; 1410 clock-names = "main", "dma"; 1411 clock-div = <1>; 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 status = "disabled"; 1415 }; 1416 1417 ssusb: usb@11201000 { 1418 compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3"; 1419 reg = <0 0x11201000 0 0x2e00>, 1420 <0 0x11203e00 0 0x0100>; 1421 reg-names = "mac", "ippc"; 1422 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 1423 phys = <&u2port0 PHY_TYPE_USB2>, 1424 <&u3port0 PHY_TYPE_USB3>; 1425 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1426 <&infracfg CLK_INFRA_USB>; 1427 clock-names = "sys_ck", "ref_ck"; 1428 mediatek,syscon-wakeup = <&pericfg 0x420 101>; 1429 #address-cells = <2>; 1430 #size-cells = <2>; 1431 ranges; 1432 status = "disabled"; 1433 1434 usb_host: usb@11200000 { 1435 compatible = "mediatek,mt8183-xhci", 1436 "mediatek,mtk-xhci"; 1437 reg = <0 0x11200000 0 0x1000>; 1438 reg-names = "mac"; 1439 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 1440 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1441 <&infracfg CLK_INFRA_USB>; 1442 clock-names = "sys_ck", "ref_ck"; 1443 status = "disabled"; 1444 }; 1445 }; 1446 1447 audiosys: audio-controller@11220000 { 1448 compatible = "mediatek,mt8183-audiosys", "syscon"; 1449 reg = <0 0x11220000 0 0x1000>; 1450 #clock-cells = <1>; 1451 afe: mt8183-afe-pcm { 1452 compatible = "mediatek,mt8183-audio"; 1453 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; 1454 resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>; 1455 reset-names = "audiosys"; 1456 power-domains = 1457 <&spm MT8183_POWER_DOMAIN_AUDIO>; 1458 clocks = <&audiosys CLK_AUDIO_AFE>, 1459 <&audiosys CLK_AUDIO_DAC>, 1460 <&audiosys CLK_AUDIO_DAC_PREDIS>, 1461 <&audiosys CLK_AUDIO_ADC>, 1462 <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>, 1463 <&audiosys CLK_AUDIO_22M>, 1464 <&audiosys CLK_AUDIO_24M>, 1465 <&audiosys CLK_AUDIO_APLL_TUNER>, 1466 <&audiosys CLK_AUDIO_APLL2_TUNER>, 1467 <&audiosys CLK_AUDIO_I2S1>, 1468 <&audiosys CLK_AUDIO_I2S2>, 1469 <&audiosys CLK_AUDIO_I2S3>, 1470 <&audiosys CLK_AUDIO_I2S4>, 1471 <&audiosys CLK_AUDIO_TDM>, 1472 <&audiosys CLK_AUDIO_TML>, 1473 <&infracfg CLK_INFRA_AUDIO>, 1474 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, 1475 <&topckgen CLK_TOP_MUX_AUDIO>, 1476 <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 1477 <&topckgen CLK_TOP_SYSPLL_D2_D4>, 1478 <&topckgen CLK_TOP_MUX_AUD_1>, 1479 <&topckgen CLK_TOP_APLL1_CK>, 1480 <&topckgen CLK_TOP_MUX_AUD_2>, 1481 <&topckgen CLK_TOP_APLL2_CK>, 1482 <&topckgen CLK_TOP_MUX_AUD_ENG1>, 1483 <&topckgen CLK_TOP_APLL1_D8>, 1484 <&topckgen CLK_TOP_MUX_AUD_ENG2>, 1485 <&topckgen CLK_TOP_APLL2_D8>, 1486 <&topckgen CLK_TOP_MUX_APLL_I2S0>, 1487 <&topckgen CLK_TOP_MUX_APLL_I2S1>, 1488 <&topckgen CLK_TOP_MUX_APLL_I2S2>, 1489 <&topckgen CLK_TOP_MUX_APLL_I2S3>, 1490 <&topckgen CLK_TOP_MUX_APLL_I2S4>, 1491 <&topckgen CLK_TOP_MUX_APLL_I2S5>, 1492 <&topckgen CLK_TOP_APLL12_DIV0>, 1493 <&topckgen CLK_TOP_APLL12_DIV1>, 1494 <&topckgen CLK_TOP_APLL12_DIV2>, 1495 <&topckgen CLK_TOP_APLL12_DIV3>, 1496 <&topckgen CLK_TOP_APLL12_DIV4>, 1497 <&topckgen CLK_TOP_APLL12_DIVB>, 1498 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/ 1499 <&clk26m>; 1500 clock-names = "aud_afe_clk", 1501 "aud_dac_clk", 1502 "aud_dac_predis_clk", 1503 "aud_adc_clk", 1504 "aud_adc_adda6_clk", 1505 "aud_apll22m_clk", 1506 "aud_apll24m_clk", 1507 "aud_apll1_tuner_clk", 1508 "aud_apll2_tuner_clk", 1509 "aud_i2s1_bclk_sw", 1510 "aud_i2s2_bclk_sw", 1511 "aud_i2s3_bclk_sw", 1512 "aud_i2s4_bclk_sw", 1513 "aud_tdm_clk", 1514 "aud_tml_clk", 1515 "aud_infra_clk", 1516 "mtkaif_26m_clk", 1517 "top_mux_audio", 1518 "top_mux_aud_intbus", 1519 "top_syspll_d2_d4", 1520 "top_mux_aud_1", 1521 "top_apll1_ck", 1522 "top_mux_aud_2", 1523 "top_apll2_ck", 1524 "top_mux_aud_eng1", 1525 "top_apll1_d8", 1526 "top_mux_aud_eng2", 1527 "top_apll2_d8", 1528 "top_i2s0_m_sel", 1529 "top_i2s1_m_sel", 1530 "top_i2s2_m_sel", 1531 "top_i2s3_m_sel", 1532 "top_i2s4_m_sel", 1533 "top_i2s5_m_sel", 1534 "top_apll12_div0", 1535 "top_apll12_div1", 1536 "top_apll12_div2", 1537 "top_apll12_div3", 1538 "top_apll12_div4", 1539 "top_apll12_divb", 1540 /*"top_apll12_div5",*/ 1541 "top_clk26m_clk"; 1542 }; 1543 }; 1544 1545 mmc0: mmc@11230000 { 1546 compatible = "mediatek,mt8183-mmc"; 1547 reg = <0 0x11230000 0 0x1000>, 1548 <0 0x11f50000 0 0x1000>; 1549 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 1550 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 1551 <&infracfg CLK_INFRA_MSDC0>, 1552 <&infracfg CLK_INFRA_MSDC0_SCK>; 1553 clock-names = "source", "hclk", "source_cg"; 1554 status = "disabled"; 1555 }; 1556 1557 mmc1: mmc@11240000 { 1558 compatible = "mediatek,mt8183-mmc"; 1559 reg = <0 0x11240000 0 0x1000>, 1560 <0 0x11e10000 0 0x1000>; 1561 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 1562 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 1563 <&infracfg CLK_INFRA_MSDC1>, 1564 <&infracfg CLK_INFRA_MSDC1_SCK>; 1565 clock-names = "source", "hclk", "source_cg"; 1566 status = "disabled"; 1567 }; 1568 1569 mipi_tx0: dsi-phy@11e50000 { 1570 compatible = "mediatek,mt8183-mipi-tx"; 1571 reg = <0 0x11e50000 0 0x1000>; 1572 clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>; 1573 #clock-cells = <0>; 1574 #phy-cells = <0>; 1575 clock-output-names = "mipi_tx0_pll"; 1576 nvmem-cells = <&mipi_tx_calibration>; 1577 nvmem-cell-names = "calibration-data"; 1578 }; 1579 1580 efuse: efuse@11f10000 { 1581 compatible = "mediatek,mt8183-efuse", 1582 "mediatek,efuse"; 1583 reg = <0 0x11f10000 0 0x1000>; 1584 #address-cells = <1>; 1585 #size-cells = <1>; 1586 1587 socinfo-data1@4c { 1588 reg = <0x04c 0x4>; 1589 }; 1590 1591 socinfo-data2@60 { 1592 reg = <0x060 0x4>; 1593 }; 1594 1595 thermal_calibration: calib@180 { 1596 reg = <0x180 0xc>; 1597 }; 1598 1599 mipi_tx_calibration: calib@190 { 1600 reg = <0x190 0xc>; 1601 }; 1602 1603 svs_calibration: calib@580 { 1604 reg = <0x580 0x64>; 1605 }; 1606 }; 1607 1608 u3phy: t-phy@11f40000 { 1609 compatible = "mediatek,mt8183-tphy", 1610 "mediatek,generic-tphy-v2"; 1611 #address-cells = <1>; 1612 #size-cells = <1>; 1613 ranges = <0 0 0x11f40000 0x1000>; 1614 status = "okay"; 1615 1616 u2port0: usb-phy@0 { 1617 reg = <0x0 0x700>; 1618 clocks = <&clk26m>; 1619 clock-names = "ref"; 1620 #phy-cells = <1>; 1621 mediatek,discth = <15>; 1622 status = "okay"; 1623 }; 1624 1625 u3port0: usb-phy@700 { 1626 reg = <0x0700 0x900>; 1627 clocks = <&clk26m>; 1628 clock-names = "ref"; 1629 #phy-cells = <1>; 1630 status = "okay"; 1631 }; 1632 }; 1633 1634 mfgcfg: syscon@13000000 { 1635 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 1636 reg = <0 0x13000000 0 0x1000>; 1637 #clock-cells = <1>; 1638 power-domains = <&spm MT8183_POWER_DOMAIN_MFG_ASYNC>; 1639 }; 1640 1641 gpu: gpu@13040000 { 1642 compatible = "mediatek,mt8183b-mali", "arm,mali-bifrost"; 1643 reg = <0 0x13040000 0 0x4000>; 1644 interrupts = 1645 <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>, 1646 <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>, 1647 <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>; 1648 interrupt-names = "job", "mmu", "gpu"; 1649 1650 clocks = <&mfgcfg CLK_MFG_BG3D>; 1651 1652 power-domains = 1653 <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, 1654 <&spm MT8183_POWER_DOMAIN_MFG_CORE1>, 1655 <&spm MT8183_POWER_DOMAIN_MFG_2D>; 1656 power-domain-names = "core0", "core1", "core2"; 1657 1658 operating-points-v2 = <&gpu_opp_table>; 1659 }; 1660 1661 mmsys: syscon@14000000 { 1662 compatible = "mediatek,mt8183-mmsys", "syscon"; 1663 reg = <0 0x14000000 0 0x1000>; 1664 #clock-cells = <1>; 1665 #reset-cells = <1>; 1666 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1667 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1668 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1669 }; 1670 1671 dma-controller0@14001000 { 1672 compatible = "mediatek,mt8183-mdp3-rdma"; 1673 reg = <0 0x14001000 0 0x1000>; 1674 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; 1675 mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, 1676 <CMDQ_EVENT_MDP_RDMA0_EOF>; 1677 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1678 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 1679 <&mmsys CLK_MM_MDP_RSZ1>; 1680 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 1681 mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, 1682 <&gce 21 CMDQ_THR_PRIO_LOWEST 0>; 1683 #dma-cells = <1>; 1684 }; 1685 1686 mdp3-rsz0@14003000 { 1687 compatible = "mediatek,mt8183-mdp3-rsz"; 1688 reg = <0 0x14003000 0 0x1000>; 1689 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; 1690 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>, 1691 <CMDQ_EVENT_MDP_RSZ0_EOF>; 1692 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 1693 }; 1694 1695 mdp3-rsz1@14004000 { 1696 compatible = "mediatek,mt8183-mdp3-rsz"; 1697 reg = <0 0x14004000 0 0x1000>; 1698 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; 1699 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>, 1700 <CMDQ_EVENT_MDP_RSZ1_EOF>; 1701 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 1702 }; 1703 1704 dma-controller@14005000 { 1705 compatible = "mediatek,mt8183-mdp3-wrot"; 1706 reg = <0 0x14005000 0 0x1000>; 1707 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1708 mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>, 1709 <CMDQ_EVENT_MDP_WROT0_EOF>; 1710 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1711 clocks = <&mmsys CLK_MM_MDP_WROT0>; 1712 iommus = <&iommu M4U_PORT_MDP_WROT0>; 1713 #dma-cells = <1>; 1714 }; 1715 1716 mdp3-wdma@14006000 { 1717 compatible = "mediatek,mt8183-mdp3-wdma"; 1718 reg = <0 0x14006000 0 0x1000>; 1719 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1720 mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>, 1721 <CMDQ_EVENT_MDP_WDMA0_EOF>; 1722 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1723 clocks = <&mmsys CLK_MM_MDP_WDMA0>; 1724 iommus = <&iommu M4U_PORT_MDP_WDMA0>; 1725 }; 1726 1727 ovl0: ovl@14008000 { 1728 compatible = "mediatek,mt8183-disp-ovl"; 1729 reg = <0 0x14008000 0 0x1000>; 1730 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; 1731 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1732 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1733 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1734 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1735 }; 1736 1737 ovl_2l0: ovl@14009000 { 1738 compatible = "mediatek,mt8183-disp-ovl-2l"; 1739 reg = <0 0x14009000 0 0x1000>; 1740 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; 1741 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1742 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1743 iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; 1744 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1745 }; 1746 1747 ovl_2l1: ovl@1400a000 { 1748 compatible = "mediatek,mt8183-disp-ovl-2l"; 1749 reg = <0 0x1400a000 0 0x1000>; 1750 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; 1751 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1752 clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; 1753 iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; 1754 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1755 }; 1756 1757 rdma0: rdma@1400b000 { 1758 compatible = "mediatek,mt8183-disp-rdma"; 1759 reg = <0 0x1400b000 0 0x1000>; 1760 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; 1761 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1762 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1763 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1764 mediatek,rdma-fifo-size = <5120>; 1765 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1766 }; 1767 1768 rdma1: rdma@1400c000 { 1769 compatible = "mediatek,mt8183-disp-rdma"; 1770 reg = <0 0x1400c000 0 0x1000>; 1771 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 1772 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1773 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1774 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1775 mediatek,rdma-fifo-size = <2048>; 1776 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1777 }; 1778 1779 color0: color@1400e000 { 1780 compatible = "mediatek,mt8183-disp-color", 1781 "mediatek,mt8173-disp-color"; 1782 reg = <0 0x1400e000 0 0x1000>; 1783 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; 1784 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1785 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1786 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1787 }; 1788 1789 ccorr0: ccorr@1400f000 { 1790 compatible = "mediatek,mt8183-disp-ccorr"; 1791 reg = <0 0x1400f000 0 0x1000>; 1792 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; 1793 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1794 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1795 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1796 }; 1797 1798 aal0: aal@14010000 { 1799 compatible = "mediatek,mt8183-disp-aal"; 1800 reg = <0 0x14010000 0 0x1000>; 1801 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; 1802 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1803 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1804 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1805 }; 1806 1807 gamma0: gamma@14011000 { 1808 compatible = "mediatek,mt8183-disp-gamma"; 1809 reg = <0 0x14011000 0 0x1000>; 1810 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; 1811 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1812 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1813 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1814 }; 1815 1816 dither0: dither@14012000 { 1817 compatible = "mediatek,mt8183-disp-dither"; 1818 reg = <0 0x14012000 0 0x1000>; 1819 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; 1820 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1821 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1822 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1823 }; 1824 1825 dsi0: dsi@14014000 { 1826 compatible = "mediatek,mt8183-dsi"; 1827 reg = <0 0x14014000 0 0x1000>; 1828 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; 1829 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1830 clocks = <&mmsys CLK_MM_DSI0_MM>, 1831 <&mmsys CLK_MM_DSI0_IF>, 1832 <&mipi_tx0>; 1833 clock-names = "engine", "digital", "hs"; 1834 resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; 1835 phys = <&mipi_tx0>; 1836 phy-names = "dphy"; 1837 }; 1838 1839 dpi0: dpi@14015000 { 1840 compatible = "mediatek,mt8183-dpi"; 1841 reg = <0 0x14015000 0 0x1000>; 1842 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>; 1843 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1844 clocks = <&mmsys CLK_MM_DPI_IF>, 1845 <&mmsys CLK_MM_DPI_MM>, 1846 <&apmixedsys CLK_APMIXED_TVDPLL>; 1847 clock-names = "pixel", "engine", "pll"; 1848 1849 port { 1850 dpi_out: endpoint { }; 1851 }; 1852 }; 1853 1854 mutex: mutex@14016000 { 1855 compatible = "mediatek,mt8183-disp-mutex"; 1856 reg = <0 0x14016000 0 0x1000>; 1857 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; 1858 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1859 mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>, 1860 <CMDQ_EVENT_MUTEX_STREAM_DONE1>; 1861 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 1862 }; 1863 1864 larb0: larb@14017000 { 1865 compatible = "mediatek,mt8183-smi-larb"; 1866 reg = <0 0x14017000 0 0x1000>; 1867 mediatek,smi = <&smi_common>; 1868 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1869 <&mmsys CLK_MM_SMI_LARB0>; 1870 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1871 clock-names = "apb", "smi"; 1872 }; 1873 1874 smi_common: smi@14019000 { 1875 compatible = "mediatek,mt8183-smi-common"; 1876 reg = <0 0x14019000 0 0x1000>; 1877 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1878 <&mmsys CLK_MM_SMI_COMMON>, 1879 <&mmsys CLK_MM_GALS_COMM0>, 1880 <&mmsys CLK_MM_GALS_COMM1>; 1881 clock-names = "apb", "smi", "gals0", "gals1"; 1882 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1883 }; 1884 1885 mdp3-ccorr@1401c000 { 1886 compatible = "mediatek,mt8183-mdp3-ccorr"; 1887 reg = <0 0x1401c000 0 0x1000>; 1888 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; 1889 mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>, 1890 <CMDQ_EVENT_MDP_CCORR_EOF>; 1891 clocks = <&mmsys CLK_MM_MDP_CCORR>; 1892 }; 1893 1894 imgsys: syscon@15020000 { 1895 compatible = "mediatek,mt8183-imgsys", "syscon"; 1896 reg = <0 0x15020000 0 0x1000>; 1897 #clock-cells = <1>; 1898 }; 1899 1900 larb5: larb@15021000 { 1901 compatible = "mediatek,mt8183-smi-larb"; 1902 reg = <0 0x15021000 0 0x1000>; 1903 mediatek,smi = <&smi_common>; 1904 clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>, 1905 <&mmsys CLK_MM_GALS_IMG2MM>; 1906 clock-names = "apb", "smi", "gals"; 1907 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1908 }; 1909 1910 larb2: larb@1502f000 { 1911 compatible = "mediatek,mt8183-smi-larb"; 1912 reg = <0 0x1502f000 0 0x1000>; 1913 mediatek,smi = <&smi_common>; 1914 clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>, 1915 <&mmsys CLK_MM_GALS_IPU2MM>; 1916 clock-names = "apb", "smi", "gals"; 1917 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1918 }; 1919 1920 vdecsys: syscon@16000000 { 1921 compatible = "mediatek,mt8183-vdecsys", "syscon"; 1922 reg = <0 0x16000000 0 0x1000>; 1923 #clock-cells = <1>; 1924 }; 1925 1926 vcodec_dec: video-codec@16020000 { 1927 compatible = "mediatek,mt8183-vcodec-dec"; 1928 reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 1929 <0 0x16021000 0 0x800>, /* VDEC_VLD */ 1930 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 1931 <0 0x16022000 0 0x1000>, /* VDEC_MC */ 1932 <0 0x16023000 0 0x1000>, /* VDEC_AVCVLD */ 1933 <0 0x16024000 0 0x1000>, /* VDEC_AVCMV */ 1934 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 1935 <0 0x16026800 0 0x800>, /* VP8_VD */ 1936 <0 0x16027000 0 0x800>, /* VP6_VD */ 1937 <0 0x16027800 0 0x800>, /* VP8_VL */ 1938 <0 0x16028400 0 0x400>; /* VP9_VD */ 1939 reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp", 1940 "hwd", "hwq", "hwb", "hwg"; 1941 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_LOW>; 1942 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 1943 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 1944 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 1945 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 1946 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 1947 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 1948 <&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>; 1949 mediatek,scp = <&scp>; 1950 mediatek,vdecsys = <&vdecsys>; 1951 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; 1952 clocks = <&vdecsys CLK_VDEC_VDEC>; 1953 clock-names = "vdec"; 1954 }; 1955 1956 larb1: larb@16010000 { 1957 compatible = "mediatek,mt8183-smi-larb"; 1958 reg = <0 0x16010000 0 0x1000>; 1959 mediatek,smi = <&smi_common>; 1960 clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>; 1961 clock-names = "apb", "smi"; 1962 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; 1963 }; 1964 1965 vencsys: syscon@17000000 { 1966 compatible = "mediatek,mt8183-vencsys", "syscon"; 1967 reg = <0 0x17000000 0 0x1000>; 1968 #clock-cells = <1>; 1969 }; 1970 1971 larb4: larb@17010000 { 1972 compatible = "mediatek,mt8183-smi-larb"; 1973 reg = <0 0x17010000 0 0x1000>; 1974 mediatek,smi = <&smi_common>; 1975 clocks = <&vencsys CLK_VENC_LARB>, 1976 <&vencsys CLK_VENC_LARB>; 1977 clock-names = "apb", "smi"; 1978 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 1979 }; 1980 1981 vcodec_enc: vcodec@17020000 { 1982 compatible = "mediatek,mt8183-vcodec-enc"; 1983 reg = <0 0x17020000 0 0x1000>; 1984 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_LOW>; 1985 iommus = <&iommu M4U_PORT_VENC_REC>, 1986 <&iommu M4U_PORT_VENC_BSDMA>, 1987 <&iommu M4U_PORT_VENC_RD_COMV>, 1988 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1989 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1990 <&iommu M4U_PORT_VENC_REF_LUMA>, 1991 <&iommu M4U_PORT_VENC_REF_CHROMA>; 1992 mediatek,scp = <&scp>; 1993 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 1994 clocks = <&vencsys CLK_VENC_VENC>; 1995 clock-names = "venc_sel"; 1996 }; 1997 1998 venc_jpg: jpeg-encoder@17030000 { 1999 compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; 2000 reg = <0 0x17030000 0 0x1000>; 2001 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; 2002 iommus = <&iommu M4U_PORT_JPGENC_RDMA>, 2003 <&iommu M4U_PORT_JPGENC_BSDMA>; 2004 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 2005 clocks = <&vencsys CLK_VENC_JPGENC>; 2006 clock-names = "jpgenc"; 2007 }; 2008 2009 ipu_conn: syscon@19000000 { 2010 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 2011 reg = <0 0x19000000 0 0x1000>; 2012 #clock-cells = <1>; 2013 }; 2014 2015 ipu_adl: syscon@19010000 { 2016 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 2017 reg = <0 0x19010000 0 0x1000>; 2018 #clock-cells = <1>; 2019 }; 2020 2021 ipu_core0: syscon@19180000 { 2022 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 2023 reg = <0 0x19180000 0 0x1000>; 2024 #clock-cells = <1>; 2025 }; 2026 2027 ipu_core1: syscon@19280000 { 2028 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 2029 reg = <0 0x19280000 0 0x1000>; 2030 #clock-cells = <1>; 2031 }; 2032 2033 camsys: syscon@1a000000 { 2034 compatible = "mediatek,mt8183-camsys", "syscon"; 2035 reg = <0 0x1a000000 0 0x1000>; 2036 #clock-cells = <1>; 2037 }; 2038 2039 larb6: larb@1a001000 { 2040 compatible = "mediatek,mt8183-smi-larb"; 2041 reg = <0 0x1a001000 0 0x1000>; 2042 mediatek,smi = <&smi_common>; 2043 clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>, 2044 <&mmsys CLK_MM_GALS_CAM2MM>; 2045 clock-names = "apb", "smi", "gals"; 2046 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 2047 }; 2048 2049 larb3: larb@1a002000 { 2050 compatible = "mediatek,mt8183-smi-larb"; 2051 reg = <0 0x1a002000 0 0x1000>; 2052 mediatek,smi = <&smi_common>; 2053 clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>, 2054 <&mmsys CLK_MM_GALS_IPU12MM>; 2055 clock-names = "apb", "smi", "gals"; 2056 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 2057 }; 2058 }; 2059 2060 thermal_zones: thermal-zones { 2061 cpu_thermal: cpu-thermal { 2062 polling-delay-passive = <100>; 2063 polling-delay = <500>; 2064 thermal-sensors = <&thermal 0>; 2065 sustainable-power = <5000>; 2066 2067 trips { 2068 threshold: trip-point0 { 2069 temperature = <68000>; 2070 hysteresis = <2000>; 2071 type = "passive"; 2072 }; 2073 2074 target: trip-point1 { 2075 temperature = <80000>; 2076 hysteresis = <2000>; 2077 type = "passive"; 2078 }; 2079 2080 cpu_crit: cpu-crit { 2081 temperature = <115000>; 2082 hysteresis = <2000>; 2083 type = "critical"; 2084 }; 2085 }; 2086 2087 cooling-maps { 2088 map0 { 2089 trip = <&target>; 2090 cooling-device = <&cpu0 2091 THERMAL_NO_LIMIT 2092 THERMAL_NO_LIMIT>, 2093 <&cpu1 2094 THERMAL_NO_LIMIT 2095 THERMAL_NO_LIMIT>, 2096 <&cpu2 2097 THERMAL_NO_LIMIT 2098 THERMAL_NO_LIMIT>, 2099 <&cpu3 2100 THERMAL_NO_LIMIT 2101 THERMAL_NO_LIMIT>; 2102 contribution = <3072>; 2103 }; 2104 map1 { 2105 trip = <&target>; 2106 cooling-device = <&cpu4 2107 THERMAL_NO_LIMIT 2108 THERMAL_NO_LIMIT>, 2109 <&cpu5 2110 THERMAL_NO_LIMIT 2111 THERMAL_NO_LIMIT>, 2112 <&cpu6 2113 THERMAL_NO_LIMIT 2114 THERMAL_NO_LIMIT>, 2115 <&cpu7 2116 THERMAL_NO_LIMIT 2117 THERMAL_NO_LIMIT>; 2118 contribution = <1024>; 2119 }; 2120 }; 2121 }; 2122 2123 tzts1: soc-thermal { 2124 polling-delay = <1000>; 2125 polling-delay-passive = <250>; 2126 thermal-sensors = <&thermal 1>; 2127 sustainable-power = <5000>; 2128 trips { 2129 soc_alert: trip-alert { 2130 temperature = <85000>; 2131 hysteresis = <2000>; 2132 type = "passive"; 2133 }; 2134 2135 soc_crit: trip-crit { 2136 temperature = <100000>; 2137 hysteresis = <2000>; 2138 type = "critical"; 2139 }; 2140 }; 2141 }; 2142 2143 tzts2: gpu-thermal { 2144 polling-delay = <1000>; 2145 polling-delay-passive = <250>; 2146 thermal-sensors = <&thermal 2>; 2147 sustainable-power = <5000>; 2148 2149 trips { 2150 gpu_alert: trip-alert { 2151 temperature = <85000>; 2152 hysteresis = <2000>; 2153 type = "passive"; 2154 }; 2155 2156 gpu_crit: trip-crit { 2157 temperature = <100000>; 2158 hysteresis = <2000>; 2159 type = "critical"; 2160 }; 2161 }; 2162 }; 2163 2164 tzts3: md1-thermal { 2165 polling-delay = <1000>; 2166 polling-delay-passive = <250>; 2167 thermal-sensors = <&thermal 3>; 2168 sustainable-power = <5000>; 2169 2170 trips { 2171 md1_alert: trip-alert { 2172 temperature = <85000>; 2173 hysteresis = <2000>; 2174 type = "passive"; 2175 }; 2176 2177 md1_crit: trip-crit { 2178 temperature = <100000>; 2179 hysteresis = <2000>; 2180 type = "critical"; 2181 }; 2182 }; 2183 }; 2184 2185 tzts4: cpu-little-thermal { 2186 polling-delay = <1000>; 2187 polling-delay-passive = <250>; 2188 thermal-sensors = <&thermal 4>; 2189 sustainable-power = <5000>; 2190 2191 trips { 2192 cpul_alert: trip-alert { 2193 temperature = <85000>; 2194 hysteresis = <2000>; 2195 type = "passive"; 2196 }; 2197 2198 cpul_crit: trip-crit { 2199 temperature = <100000>; 2200 hysteresis = <2000>; 2201 type = "critical"; 2202 }; 2203 }; 2204 }; 2205 2206 tzts5: cpu-big-thermal { 2207 polling-delay = <1000>; 2208 polling-delay-passive = <250>; 2209 thermal-sensors = <&thermal 5>; 2210 sustainable-power = <5000>; 2211 2212 trips { 2213 cpub_alert: trip-alert { 2214 temperature = <85000>; 2215 hysteresis = <2000>; 2216 type = "passive"; 2217 }; 2218 2219 cpub_crit: trip-crit { 2220 temperature = <100000>; 2221 hysteresis = <2000>; 2222 type = "critical"; 2223 }; 2224 }; 2225 }; 2226 2227 tztsABB: tsabb-thermal { 2228 polling-delay = <1000>; 2229 polling-delay-passive = <250>; 2230 thermal-sensors = <&thermal 6>; 2231 sustainable-power = <5000>; 2232 2233 trips { 2234 tsabb_alert: trip-alert { 2235 temperature = <85000>; 2236 hysteresis = <2000>; 2237 type = "passive"; 2238 }; 2239 2240 tsabb_crit: trip-crit { 2241 temperature = <100000>; 2242 hysteresis = <2000>; 2243 type = "critical"; 2244 }; 2245 }; 2246 }; 2247 }; 2248}; 2249